MEMORY SYSTEM AND DATA CORRECTING METHOD - Patent application

Abstract

To provide a memory system using a storage unit for which an error of data cannot be detected from the outside, the memory system being configured to perform scrubbing for correcting the error of the data in the storage unit.SOLUTION: A memory system includes a control unit and a storage unit which enables error correction of data stored therein autonomously. The control unit includes a scrubbing circuit 4 which executes scrubbing of the storage unit. The scrubbing circuit 4 includes an address generation unit 41, an access request unit 42, and a data holding unit 43, to read / write data from / to all data stored in the storage unit within a predetermined period. The scrubbing circuit 4 writes data read from the storage unit back to the same address range where the data has been stored.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a memory system and a data correction method for correcting errors in data stored in a memory by an external control unit. [Background technology]

[0002] Conventionally, memory systems have been known that include dynamic random access memory (DRAM) and a control unit such as a memory controller that manages the data. These systems are capable of correcting bit errors in data stored in the DRAM. When the control unit writes data to the DRAM, it calculates an error-correcting code (ECC) for the data and stores the data and the calculated ECC in the DRAM. When the control unit reads data stored in the DRAM, it reads the data and the ECC, compares them using the ECC, and corrects or detects any errors. For example, when an 8-bit ECC is added to 64-bit data, the control unit corrects 1-bit errors and detects 2-bit errors. The control unit overwrites the read data with the corrected data, thereby correcting the erroneous data stored in the DRAM.

[0003] In the memory system described in Patent Document 1, the control unit reads all data stored in the DRAM within a certain period of time, and if errors are detected and corrected using ECC, it performs a scrubbing process in which the corrected data is written back to the DRAM. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 8,024,638 Summary of the Invention [Problem to be solved by the invention]

[0005] One type of DRAM known is one that generates and stores an ECC code internally and can autonomously perform error correction (hereinafter referred to as "ECC-enabled DRAM"). ECC-enabled DRAM, for example, has a data storage area and an ECC storage area. When a read request is received from an external control unit, the DRAM reads the data and ECC from each area, and if an error is found in the data, the DRAM returns the corrected data to the control unit. Because ECC-enabled DRAM can return correct data to an external control unit even if an error occurs, it is used in applications that require robust error tolerance, such as server memory.

[0006] Let us consider a memory system that includes a controller and an ECC-compatible DRAM. Although ECC-compatible DRAM can return error-corrected data to an external controller, it does not generally overwrite the data stored internally with corrected data, so the erroneous data remains in the data storage area.

[0007] However, in this memory system, the data read from the ECC-compatible DRAM is the data after internal correction, so the external control unit cannot detect whether an error has occurred in the data stored in the ECC-compatible DRAM. Also, in this memory system, even if the ECC is stored separately outside the ECC-compatible DRAM and the above-mentioned scrubbing process is performed, the data error cannot be detected because the data read from the ECC-compatible DRAM by the external control unit is the corrected data.

[0008] In view of the above, an object of the present invention is to enable error correction in a memory system using an ECC-compatible DRAM even when an error occurs in data stored in the ECC-compatible DRAM. [Means for solving the problem]

[0009] In order to achieve the above object, the memory system according to claim 1 comprises a memory unit (3) having a data storage area (31) for storing data, an ECC generation unit (32) for generating an error correction code corresponding to the data, an ECC storage area (33) for storing the error correction code generated by the ECC generation unit, and an error correction unit (34) for correcting an error in the data using the error correction code, and a control unit (2) for reading and writing data stored in the data storage area of ​​the memory unit, wherein the control unit includes a scrubbing processing circuit (4) for executing a scrubbing process for the memory unit. and an arbitration circuit (5) that arbitrates between an access request to the storage unit from the scrubbing processing circuit and an access request to the storage unit from another area different from the control unit, In the scrubbing process, data stored in the memory unit is read and then written back to the memory unit as is. However, if there is a write request from another area to a specified address range in the data storage area of ​​the memory unit between the read request from the scrubbing processing circuit and the next write request, and the specified address range includes at least a part of the address range corresponding to the read request from the scrubbing processing circuit to the memory unit, the arbitration circuit performs a process of suspending the write request from the other area until the write process based on the write request from the scrubbing processing circuit is completed.

[0010] This memory system includes a storage unit capable of internally and autonomously correcting errors, and a control unit that processes reading and writing data stored in a data storage area of ​​the storage unit. The control unit then writes the data read by the control unit back to the storage unit as is. Even if an error occurs in the data read by the control unit, the data is corrected by an error correction unit within the storage unit, and is therefore expected to be error-free and correct. Furthermore, the data with an error stored in the storage unit is written back as is with the corrected data read by the control unit, i.e., the correct data, returning it to its state before the error occurred. Therefore, by using a storage unit that internally and autonomously corrects errors, such as ECC-compatible DRAM, this memory system can correct the data to be correct even if the control unit cannot detect an error in the data stored in the storage unit.

[0011] Claim 4 The data correction method described in the item (1) includes a memory unit (3) having a data storage area (31) for storing data, an ECC generation unit (32) for generating an error correction code corresponding to the data, an ECC storage area (33) for storing the error correction code generated by the ECC generation unit, and an error correction unit (34) for correcting the error using the error correction code when an error occurs in the data. a scrubbing circuit (4) that performs scrubbing of the storage unit; and an arbitration circuit (5) that arbitrates between an access request to the storage unit from the scrubbing circuit and an access request to the storage unit from another area different from the control unit,A data correction method for correcting data errors in a memory system including a control unit (2) that performs processing for reading and writing data stored in a data storage area of ​​a storage unit, the method comprising the steps of: the control unit making read requests and write requests for all data stored in the data storage area of ​​the storage unit at predetermined intervals; in one read request, the control unit reading a portion of the data in the data storage area and holding the portion of the data until the next write request; and in one write request, writing the portion of the data read by the immediately preceding read request directly to the same address in the data storage area where the portion of the data was stored. If a write request from another area to a predetermined address range of the data storage area of ​​the storage unit occurs between a read request from the scrubbing processing circuit and the next write request, and the predetermined address range includes at least a part of the address range corresponding to the read request from the scrubbing processing circuit to the storage unit, the arbitration circuit performs processing to suspend the write request from the other area until the write processing by the write request from the scrubbing processing circuit is completed; Includes.

[0012] This error correction method corrects data in a memory system that includes a storage unit capable of internally and autonomously correcting errors and a control unit that processes reading and writing data stored in a data storage area of ​​the storage unit. In response to a single read request, the control unit reads and stores a portion of the data in the data storage area, and in response to a subsequent write request, writes the portion of the data stored in the previous read request to the same address in the storage unit. Because the storage unit is configured to perform error correction autonomously, the data read by the control unit in response to a single read request is expected to be correct data without errors. By writing this "correct data" as is, the data storage area stores data with the corrected error. This method makes it possible to correct data in the storage unit even in a memory system that uses a storage unit that internally and autonomously corrects errors, such as ECC-compatible DRAM.

[0013] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a block diagram illustrating a memory system according to an embodiment. [Figure 2]FIG. 2 is a block diagram illustrating an example of the configuration of a storage unit used in the memory system. [Figure 3] FIG. 2 is a block diagram illustrating a configuration example of a DRAM controller. [Figure 4] FIG. 2 is a block diagram showing an example of the configuration of a scrubbing processing circuit. [Figure 5] 10 is a flowchart illustrating an example of a scrubbing process according to the embodiment. [Figure 6] 10 is a flowchart illustrating an example of processing in an arbitration circuit. DETAILED DESCRIPTION OF THE INVENTION

[0015] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following embodiments, identical or equivalent parts will be denoted by the same reference numerals.

[0016] (Embodiment) A memory system 1 according to an embodiment will be described with reference to the drawings.

[0017] [Basic configuration] 1, memory system 1 includes control unit 2 and storage unit 3, and is suitable for use in applications requiring robustness against errors, such as data processing for business servers, driving assistance in vehicles, or periphery monitoring in autonomous driving, etc. Memory system 1 is not limited to the above applications, and can also be used in various other applications.

[0018] 1, the control unit 2 includes a plurality of DRAM masters 21, a DRAM controller 22, and a bus 23, and the DRAM controller 22 is capable of exchanging various signals and data with the DRAM masters 21 and the memory unit 3. The control unit 2 is, for example, an SoC, which is an integrated circuit in which various functional circuits such as a processor, CPU, and GPU are integrated on a single semiconductor chip. SoC, CPU, and GPU are abbreviations for "System on a Chip," "Central Processing Unit," and "Graphics Processing Unit," respectively.

[0019] The DRAM master 21 is a processing block that requires memory, such as a processor, a CPU, or a GPU. The DRAM master 21 is connected to the DRAM controller 22 via a bus 23. The number and types of the DRAM masters 21 can be changed as appropriate depending on the application of the memory system 1.

[0020] The DRAM controller 22 is connected to the external storage unit 3 and executes processes of reading and writing various data stored in the storage unit 3. For ease of explanation, the process of the DRAM controller 22 reading data from the storage unit 3 will be referred to as "reading," and the process of writing data to the storage unit 3 will be referred to as "writing." The DRAM controller 22 executes, for example, reading and writing various data from the storage unit 3 that is necessary for the arithmetic processing in the DRAM master 21. Furthermore, as a scrubbing process independent of the above-mentioned reading and writing, the DRAM controller 22 performs a role of reading all data stored in the storage unit 3 at regular intervals and writing the read data directly to the same address in the storage unit 3. Details of the DRAM controller 22 will be described later.

[0021] The certain period of time for one scrubbing process by the control unit 2 is arbitrary and is set appropriately depending on the data capacity of the storage unit 3, the use of the memory system 1, and the like.

[0022] The storage unit 3 is an ECC-compatible DRAM, and is, for example, a recording medium for recording various data used in arithmetic processing in the DRAM master 21. As shown in FIG. 3 , the storage unit 3 includes a data storage area 31, an ECC generation unit 32, an ECC storage area 33, and an error correction unit 34. The ECC generation unit 32 generates an ECC corresponding to the data to be stored in the data storage area 31, and stores the generated ECC in the ECC storage area 33. For example, when the DRAM controller 22 issues a read request for data stored in the data storage area 31, the storage unit 3 reads the ECC corresponding to the data from the ECC storage area 33. When the error correction unit 34 detects an error using the ECC in the data requested to be read by the DRAM controller 22, the storage unit 3 corrects the data and returns the corrected data to the DRAM controller 22. In other words, the storage unit 3 is configured to correct the error when a correctable single-bit error occurs in the data for which a read request has been made and output the corrected data, but is not able to autonomously overwrite the data stored in the data storage area 31 with the error-corrected data. Also, if no error occurs in the data for which a read request has been made, the storage unit 3 outputs the data as is.

[0023] The above is the basic configuration of the memory system 1 according to the embodiment. In the memory system 1, the control unit 2 reads all data stored in the data storage area 31 of the storage unit 3 (ECC-compatible DRAM) within a certain period of time, and then writes the read data directly to the original area. In other words, even if an error occurs in the data stored in the data storage area 31 of the storage unit 3, the memory system 1 is configured so that the corrected data output from the storage unit 3 is written directly to the original area. Therefore, the memory system 1 prevents erroneous data from being stored in the data storage area 31 for a long period of time, and thus prevents an uncorrectable data error of two or more bits from occurring, and has error-resistant characteristics.

[0024] [DRAM Controller] Next, the DRAM controller 22 will be described in detail.

[0025] The DRAM controller 22 includes a scrubbing processing circuit 4, an arbitration circuit 5, and a protocol generation circuit 6, as shown in FIG.

[0026] The scrubbing processing circuit 4 issues read and write requests for all data stored in the memory unit 3 within a certain period of time, and writes the data read from the memory unit 3 directly to the same area. The scrubbing processing circuit 4 includes an address generation unit 41, an access request unit 42, and a data holding unit 43, as shown in FIG.

[0027] The address generation unit 41 sequentially generates address values ​​in the data storage area 31 of the memory unit 3. For example, in the scrubbing process, the address generation unit 41 sequentially generates address values ​​in ascending order at intervals of a value corresponding to the amount of data in one read.

[0028] For ease of explanation, the amount of data read in one scrubbing process will be referred to as the "amount of read data" below.

[0029] Specifically, for example, if the data capacity of the storage unit 3 is 8 GB (gigabytes) and the amount of read data is 512 B (bytes), the address generation unit 41 generates address values ​​in the order of 0, 512, 1024, 1536, 8589934080. In this case, when the address value reaches the value of the data capacity of the storage unit 3, for example, the address generation unit 41 generates the first address value of "0" and repeats the sequential generation of address values ​​in the same manner as above. The address value generated by the address generation unit 41 is output to the access request unit 42, for example, and is used in read requests and write requests by the access request unit 42.

[0030] The amount of read data is a preset fixed value. The data capacity of the storage unit 3 and the amount of data read / written per scrubbing process are not limited to the above examples, and can be changed as appropriate depending on the application of the memory system 1.

[0031] The access request unit 42 outputs to the arbitration circuit 5 an access request to an area of ​​the data storage area 31 of the memory unit 3 that corresponds to the address value generated by the address generation unit 41. The access requests from the access request unit 42 are read and write requests for data stored in the data storage area 31. The access request unit 42 outputs access requests to the memory unit 3 to the arbitration circuit 5 at predetermined intervals so that the DRAM controller 22 can read and write all of the data stored in the data storage area 31 of the memory unit 3 within a certain period of time.

[0032] Hereinafter, the terms "access request," "read request," and "write request" refer to an access request, a read request, and a write request to the storage unit 3 unless otherwise specified.

[0033] For example, consider a case where the data capacity of the storage unit 3 is 8 GB, the amount of read data is 512 B, and it is desired to read and write all data stored in the storage unit 3 in one hour. In this case, the interval between each access request by the access request unit 42 is set to (60 x 60 x 1000 x 1000) / (16 x 1024 x 1024) = 214.6 μsec. Note that the interval between each access request by the access request unit 42 can be changed as appropriate depending on the data capacity of the storage unit 3, the amount of read data, and the fixed period required for one scrubbing process.

[0034] The data holding unit 43 is a read data buffer that temporarily holds data read from the storage unit 3 by the DRAM controller 22 based on a read request from the access request unit 42. The data capacity of the data holding unit 43 is, for example, a capacity corresponding to the amount of read data, i.e., a capacity for one data access in the scrubbing process. When a write request is made from the access request unit 42, the data holding unit 43 outputs the held data as write data. The data holding unit 43 then holds new data read from the storage unit 3 by the DRAM controller 22 in response to a read request from the access request unit 42 for the next address value until the next write request. The write data output from the data holding unit 43 is written by the DRAM controller 22 to the same area of ​​the data storage area 31 of the storage unit 3 where the read data was stored.

[0035] The arbitration circuit 5 performs arbitration when an access request from the bus 23 conflicts with an access request from the scrubbing processing circuit 4. When access requests from the bus 23 and the scrubbing processing circuit 4 to the storage unit 3 conflict, the arbitration circuit 5 outputs one access request to the protocol generation circuit 6 and suspends the other access request until the access request is completed. A conflict in access requests means that the address ranges in the data storage area 31 of the storage unit 3 for two or more access requests at least partially overlap. For example, the arbitration circuit 5 prioritizes the access request from the bus 23 and suspends the access request from the scrubbing processing circuit 4. However, if the address ranges for these access requests do not overlap, the arbitration circuit 5 outputs both access requests to the protocol generation circuit 6. The arbitration circuit 5 issues an access request to the protocol generation circuit 6, returns read data from the storage unit 3 to the access request source, and transmits write data received from the access request source to the storage unit 3.

[0036] For example, when there is a conflict between write requests from the bus 23 and the scrubbing processing circuit 4, and the write request from the bus 23 is between a read request and a write request from the scrubbing processing circuit 4, the arbitration circuit 5 preferably suspends the write request from the bus 23. This is because if data is written from the bus 23 to the same address in the memory unit 3 after a scrubbing processing read, the contents of the data will be rewritten, and if a scrubbing processing write is then performed, the contents of the data will differ from what was intended. The processing operation of the arbitration circuit 5 will be described later.

[0037] The protocol generation circuit 6 receives an access request to the storage unit 3 output from the arbitration circuit 5, converts the access request into a command to be issued to the storage unit 3, and issues the command. The protocol generation circuit 6 is a circuit that generates a protocol for communication with the storage unit 3, which is an ECC-compatible DRAM, and may also be called a DRAM protocol generation circuit.

[0038] The above is the basic configuration of the DRAM controller 22. The DRAM controller 22 executes the scrubbing process by the scrubbing process circuit 4 and the read / write process based on the access request from the DRAM master 21 or the like.

[0039] [Scrubbing process] Next, a description will be given of the scrubbing process of the storage unit 3 by the control unit 2. For ease of explanation, the data stored in the data storage area 31 of the storage unit 3 may be referred to as "stored data" below.

[0040] 5 when a predetermined start condition is satisfied, such as the memory system 1 being powered on. In step S110, the address generation unit 41 in the scrubbing processing circuit 4 generates an address value of the data storage area 31 of the memory unit 3 and outputs the generated address value to the access request unit 42.

[0041] Subsequently, in step S120, the access request unit 42 outputs a read request for the address value generated in step S110 to the arbitration circuit 5. Thereafter, the arbitration circuit 5 outputs the read request output from the access request unit 42 to the protocol generation circuit 6.

[0042] Next, in step S130, the protocol generation circuit 6 receives the read request from the arbitration circuit 5, converts it into a read request command to the storage unit 3, and issues it.

[0043] Then, in step S140, the DRAM controller 22 reads data in a predetermined address range from the address value generated in step S110 in the data storage area 31 of the memory unit 3. The address range at this time can be changed as appropriate depending on the amount of data to be read that is set in advance.

[0044] Subsequently, in step S150, the scrubbing process circuit 4 receives the data read in step S140 and stores it in the data storage unit 43.

[0045] Next, in step S160, the scrubbing processing circuit 4 performs processing similar to steps S110 to S130 to request writing to the same address range of the storage unit 3 as the data read in step S140. Then, in step S150, the DRAM controller 22 outputs the data held by the data holding unit 43 as write data and performs processing to write the write data back to the area of ​​the storage unit 3 where the read data was stored. As a result, if no error has occurred, the data stored in the storage unit 3 is overwritten by the DRAM controller 22 with the original data. On the other hand, if an error has occurred, the data stored in the storage unit 3 is overwritten by the DRAM controller 22 with "correct data" after the error correction unit 34 has corrected the error. In either case, the storage unit 3 maintains error-free stored data, which cannot be detected externally, through the read / write processing by the control unit 2, i.e., the scrubbing processing.

[0046] Then, in step S170, the control unit 2 determines whether the address value generated in step S110 has reached the value for the data capacity of the storage unit 3, that is, the upper limit, and if the determination is affirmative, the process proceeds to step S180. On the other hand, if the determination is negative in step S170, the control unit 2 proceeds to step S190.

[0047] In step S180, the address generating unit 41 generates the first address value (for example, 0). Then, the control unit 2 returns the process to step S120.

[0048] On the other hand, in step S190, the address generation unit 41 generates the next address value by adding the amount of read data to the address value generated in step S110. For example, if the address value generated in step S110 is "0" and the amount of read data is "512B", in step S190 the address generation unit 41 generates an address value of "512". Thereafter, the control unit 2 returns the process to step S120.

[0049] The control unit 2 performs the above process for all data stored in the storage unit 3 within a set predetermined period. As a result, the storage unit 3 reads and writes back all stored data at regular intervals, and even if an error occurs in the stored data for some reason, the corrected data is written back. Therefore, even if the memory system 1 uses a storage unit 3 that cannot be directly error-detected by the external control unit 2, such as an ECC-compatible DRAM, it is possible to prevent data containing uncorrectable errors of two or more bits from being retained.

[0050] [Arbitration circuit] Next, the arbitration process in the arbitration circuit 5 will be described.

[0051] In parallel with the scrubbing process performed by the scrubbing process circuit 4, the arbitration circuit 5 executes, for example, the process shown in FIG.

[0052] In step S210, the arbitration circuit 5 determines whether or not there is a write request from the bus 23, and if the determination is affirmative, the process proceeds to step S220. On the other hand, if the determination is negative in step S210, the arbitration circuit 5 returns the process to step S210.

[0053] In step S220, the arbitration circuit 5 determines whether or not a scrubbing process is occurring between step S120 (read request) and step S160 (data write), and if the determination is affirmative, the process proceeds to step S230. On the other hand, if the determination is negative in step S220, the arbitration circuit 5 proceeds to step S290.

[0054] In step S290, the arbitration circuit 5 executes the write request from the bus 23. After that, the arbitration circuit 5 returns the process to step S210.

[0055] In step S230, the arbitration circuit 5 determines whether the address range of the write request from the bus 23 overlaps with the address range of the write request in the scrubbing process, and if the determination is affirmative, the process proceeds to step S240. On the other hand, if the determination is negative, the arbitration circuit 5 proceeds to step S270.

[0056] In step S240, the arbitration circuit 5 prioritizes the write request in the scrubbing process and performs processing to reserve the write request from the bus 23. Next, in step S250, the arbitration circuit 5 waits until the write request in step S160 in the scrubbing process is issued, and when that write request is issued, executes the write request in the scrubbing process. Then, in step S260 after the write process in the scrubbing process is completed, the arbitration circuit 5 executes the reserved write request from the bus 23 and returns processing to step S210.

[0057] On the other hand, in step S270, the arbitration circuit 5 executes the write request from the bus 23 without suspending it, and the process proceeds to step S280. After that, in step S280, the arbitration circuit 5 executes the write request in the scrubbing process, and the process returns to step S210.

[0058] By performing the above processing, the arbitration circuit 5 puts on hold any write request from the bus 23 whose address range overlaps with that of step S160 between step S140 (data read) and step S160 (data write) in the scrubbing process. This prevents writes from being made from the bus 23 within the overlapping address range between the read and write of stored data in the scrubbing process, making it possible to prevent stored data from being replaced with unintended data due to the scrubbing process.

[0059] The memory system 1 according to the embodiment uses an ECC-compatible DRAM as the storage unit 3, and the control unit 2 reads the data stored in the storage unit 3 within a certain period of time and writes the read data to the same address. The data stored in the storage unit 3 is not overwritten autonomously, but is output to the control unit 2 as is if no error has occurred, and if a correctable single-bit error has occurred, the data is output as corrected using the internal ECC. Since the data read by the control unit 2 from the storage unit 3 is highly likely to be correct data without any errors, the read data can be written back to the same address range as is, thereby reducing the probability of an uncorrectable error of two or more bits occurring.

[0060] Therefore, this memory system 1 is configured to use ECC-compatible DRAM and retain the stored data as error-corrected data through scrubbing processing even if the external control unit 2 cannot directly detect errors in the data stored in the ECC-compatible DRAM. As a result, even though the memory system 1 is configured with an SoC and ECC-compatible DRAM, it is capable of substantial error correction and has error-resistant characteristics.

[0061] (Other embodiments) Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one, or less than one, are also within the scope and spirit of the present disclosure.

[0062] The control unit 2 and the method described herein may be implemented by a special-purpose computer configured by configuring a processor and memory programmed to perform one or more functions embodied in a computer program. Alternatively, the control unit 2 and the method described herein may be implemented by a special-purpose computer configured by configuring a processor with one or more dedicated hardware logic circuits. Alternatively, the control unit 2 and the method described herein may be implemented by one or more special-purpose computers configured by combining a processor and memory programmed to perform one or more functions with a processor configured with one or more hardware logic circuits. Furthermore, the computer program may be stored as instructions executed by a computer on a computer-readable non-transitory tangible storage medium.

[0063] It goes without saying that in each of the above embodiments, the elements constituting the embodiments are not necessarily essential unless they are specifically stated as essential or are clearly considered essential in principle. Furthermore, in each of the above embodiments, when numerical values ​​such as the number, values, amounts, and ranges of the components of the embodiments are mentioned, they are not limited to the specific numbers unless they are specifically stated as essential or are clearly limited to a specific number in principle. Furthermore, in each of the above embodiments, when the shapes, positional relationships, etc. of the components are mentioned, they are not limited to the shapes, positional relationships, etc., unless they are specifically stated or are clearly limited to a specific shape, positional relationship, etc. in principle. [Explanation of symbols]

[0064] 2 control unit, 3 storage unit, 31 data storage area, 32 ECC generation unit 33 ECC storage area, 34 Error correction unit, 4 Scrubbing processing circuit 41: Address generation unit, 42: Address request unit, 43: Data holding unit 5...Arbitration circuit

Claims

1. 1. A memory system comprising: a memory unit (3) having a data storage area (31) for storing data, an ECC generation unit (32) for generating an error correction code corresponding to the data, an ECC storage area (33) for storing the error correction code generated by the ECC generation unit, and an error correction unit (34) for correcting an error in the data using the error correction code; a control unit (2) that performs processing for reading and writing the data stored in the data storage area of ​​the storage unit, The control unit has a scrubbing processing circuit (4) that executes a scrubbing process on the storage unit, and an arbitration circuit (5) that arbitrates between an access request to the storage unit from the scrubbing processing circuit and an access request to the storage unit from another area different from the control unit, and in the scrubbing process, reads the data stored in the storage unit and executes a process of writing the read data back to the storage unit as is, A memory system in which, if a write request from the other area to a specified address range of the data storage area of ​​the memory unit is made between a read request from the scrubbing processing circuit and the next write request, and the specified address range includes at least a portion of the address range corresponding to the read request from the scrubbing processing circuit to the memory unit, the arbitration circuit performs processing to suspend the write request from the other area until the write processing due to the write request from the scrubbing processing circuit is completed.

2. 2. The memory system of claim 1, wherein the scrubbing processing circuit has an address generation unit (41) that sequentially generates address values ​​for the data storage area in the memory unit, an access request unit (42) that makes read and write requests to the area corresponding to the address values, and a data holding unit (43) that holds a portion of the data read from the data storage area in response to one of the read requests, and issues the read and write requests for all data stored in the data storage area at predetermined intervals, and performs a process of writing the portion of the data read from the memory unit to the area in the data storage area corresponding to the same address value where the portion of the data is stored.

3. 3. The memory system of claim 2, wherein the data holding unit holds the portion of data read by the control unit from the memory unit in response to a single read request from the access request unit at least until the next write request, and outputs the portion of data held at the time of the write request as write data.

4. a memory unit (3) having a data storage area (31) for storing data, an ECC generation unit (32) for generating an error correction code corresponding to the data, an ECC storage area (33) for storing the error correction code generated by the ECC generation unit, and an error correction unit (34) for correcting an error using the error correction code when an error occurs in the data; A data correction method for correcting errors in data in a memory system including a scrubbing circuit (4) that performs scrubbing of the storage unit, an arbitration circuit (5) that arbitrates between an access request from the scrubbing circuit to the storage unit and an access request from another area different from the control unit to the storage unit, and a control unit (2) that performs processing for reading and writing the data stored in the data storage area of ​​the storage unit, comprising: the control unit issues a read request and a write request for all data stored in the data storage area of ​​the storage unit at predetermined intervals; In one read request, the control unit reads a portion of the data in the data storage area and holds the portion of the data until the next write request; In one write request, the part of the data read in the immediately preceding read request is written directly to the same address in the data storage area where the part of the data is stored; a data correction method including: if, between a read request from the scrubbing processing circuit and a next write request, there is a write request from the other area to a predetermined address range of the data storage area of ​​the memory unit, and the predetermined address range includes at least a portion of the address range corresponding to the read request from the scrubbing processing circuit to the memory unit, the arbitration circuit performs a process of suspending the write request from the other area until the write process based on the write request from the scrubbing processing circuit is completed.

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