Data conversion to and from selected data types using implicit rounding modes

Abstract

An instruction is obtained to convert data from a source data type to a target data type. The source data type is selected from one or more source data types supported by the instruction, and the target data type is selected from one or more target data types supported by the instruction. A determination of a rounding mode to be used by the instruction is made based on the selected one of the source data type or the target data type. The rounding mode is implicitly set based on the selected data type and assigned to the selected data type. A conversion of the data from the source data type to the target data type is performed. The conversion includes performing a rounding operation using the implicitly set rounding mode. Performing the conversion results in a result in the target data type written to the selected location.

Description

[Technical Field]

[0001] One or more aspects relate generally to facilitating processing within a computing environment, and more particularly to improving such processing. [Background technology]

[0002] Coprocessors, such as artificial intelligence accelerators (also called neural network processors or neural network accelerators), are used to improve processing in data-intensive and / or computationally intensive computing environments. Such accelerators provide large amounts of computing power that are used in performing complex calculations, such as calculations on matrices or tensors.

[0003] As an example, tensor calculus is used in complex processing, including deep learning, which is a subset of machine learning. Deep learning or machine learning, an aspect of artificial intelligence, is used in a variety of technologies, including, but not limited to, design, manufacturing, medical technology, automotive technology, computer processing, etc.

[0004] Performing tensor calculations requires a large amount of time and computational power. Therefore, improvements in facilitating such performance are desired, including providing data in a format that facilitates such calculations. Summary of the Invention

[0005] Shortcomings of the prior art are overcome and additional advantages are provided by providing a computer program product for facilitating processing within a computing environment. The computer program product includes one or more computer-readable storage media and program instructions collectively stored on the one or more computer-readable storage media for performing a method. The method includes obtaining instructions for converting data from a source data type to a target data type. The source data type is selected from one or more source data types supported by the instructions, and the target data type is selected from one or more target data types supported by the instructions. A determination of a rounding mode to use by the instructions is made based on the selected one of the source data type and the target data type. The rounding mode is implicitly set based on the selected data type and assigned to the selected data type. A conversion of the data from the source data type to the target data type is performed. The conversion includes performing a rounding operation using the rounding mode implicitly set based on the selected data type. Performing the conversion results in a result in the target data type. The result is written to the selected location.

[0006] Providing an implicit rounding mode that can be assigned to a particular data type simplifies the conversion process, and restricting the supported rounding modes can improve processing speed. This also makes it easier to write program code that converts data for use on selected processors, such as coprocessors.

[0007] In one example, the selected data type is a target data type specified using the instruction. The target data type is, for example, a machine-specific data type specified using the instruction. The machine-specific data type is, for example, the Neural Network Processing Data Type 1 data type. For example, the rounding mode assigned to the Neural Network Processing Data Type 1 data type is, for example, round to nearest value away from 0. Furthermore, in one example, the source data type is a standard data type specified using the instruction.

[0008] By providing implicitly set rounding modes that are assigned to specific data types, such as machine-specific data types, the conversion process is simplified, and by limiting the rounding modes supported, processing speed can be improved. Efficiency is provided, complexity is reduced, and system performance is improved. Conversion performance is improved, improving system performance and data availability.

[0009] In one example, the selected data type is a source data type specified using the instruction. The source data type is, for example, a machine-specific data type specified using the instruction. The machine-specific data type is, for example, the Neural Network Processing Data Type 1 data type. For example, the rounding mode assigned to the Neural Network Processing Data Type 1 data type is round to nearest value away from 0. Furthermore, in one example, the target data type is a standard data type specified using the instruction.

[0010] By way of example, the data to be converted may include source data in a source data type, the source data including the concatenation of data in one register specified using one field of the instruction and other data in another register specified using another field of the instruction, and performing the conversion may include, for example, rounding the source data based on a rounding mode to provide rounded data, and converting the rounded data to provide a result in the target data type.

[0011] As another example, the data to be converted may include source data in a source data type obtained using the instruction, and performing the conversion may include, for example, rounding the source data based on a rounding mode to provide rounded data with the numeric precision of the target data type, and converting the rounded data to provide a result in the target data type.

[0012] Computer-implemented methods and systems relating to one or more aspects are also described and claimed herein. Additionally, services relating to one or more aspects may also be described and claimed herein.

[0013] Additional features and advantages are realized by the techniques described herein. Other embodiments and aspects are described in detail herein and are considered a part of the claimed aspects.

[0014] One or more aspects are particularly pointed out and distinctly claimed as examples in the claims at the end of this specification. The foregoing, as well as objects, features, and advantages of one or more aspects, will become apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0015] [Figure 1A] FIG. 2 illustrates an example of a binary floating-point format in accordance with one or more aspects of the present invention. [Figure 1B] FIG. 2 illustrates an example of a binary floating-point format in accordance with one or more aspects of the present invention. [Figure 1C] FIG. 2 illustrates an example of a binary floating-point format in accordance with one or more aspects of the present invention. [Figure 1D] FIG. 2 illustrates an example of a binary floating-point format in accordance with one or more aspects of the present invention. [Figure 2]FIG. 1 illustrates an example of a Neural Network Processing (NNP) Data Type 1 data type format in accordance with one or more aspects of the present invention. [Figure 3A] FIG. 1 illustrates an example computing environment for incorporating and using one or more aspects of the present invention. [Figure 3B] FIG. 3B illustrates an example of further details of the memory of FIG. 3A in accordance with one or more aspects of the present invention. [Figure 3C] FIG. 3B illustrates another example of further details of the memory of FIG. 3A in accordance with one or more aspects of the present invention. [Figure 3D] FIG. 3B illustrates further details of the processor of FIG. 3A in accordance with one or more aspects of the present invention. [Figure 4A] FIG. 2 illustrates one example of performing a conversion operation in accordance with one or more aspects of the present invention. [Figure 4B] 4B illustrates further details related to conversion and rounding of the conversion operation of FIG. 4A in accordance with one or more aspects of the present invention. [Figure 5A] FIG. 1 illustrates one example format of a Vector Floating Point Convert and Lengthen From Neural Network Processing High instruction in accordance with one or more aspects of the present invention. [Figure 5B] FIG. 1 illustrates one example format of a Vector Floating Point Convert and Lengthen From Neural Network Processing Low instruction in accordance with one or more aspects of the present invention. [Figure 5C] FIG. 10 illustrates one example of the format of vector floating point conversion and rounding instructions for neural network processing in accordance with one or more aspects of the present invention. [Figure 5D] FIG. 10 illustrates one example of the format of a vector floating point conversion instruction from neural network processing in accordance with one or more aspects of the present invention. [Figure 5E] FIG. 10 illustrates one example of the format of a vector floating point conversion instruction for neural network processing in accordance with one or more aspects of the present invention. [Figure 6A] FIG. 1 illustrates one example of a format for neural network processing assistance instructions used in accordance with one or more aspects of the present invention. [Figure 6B] FIG. 2 illustrates an example of a general-purpose register used by neural network processing assistance instructions in accordance with one or more aspects of the present invention. [Figure 6C] FIG. 10 illustrates example function codes supported by neural network processing assistance instructions in accordance with one or more aspects of the present invention. [Figure 6D] FIG. 10 illustrates one example of another general-purpose register used by neural network processing assistance instructions in accordance with one or more aspects of the present invention. [Figure 6E] FIG. 10 illustrates an example of a parameter block used by a query function of a neural network processing assistance instruction in accordance with one or more aspects of the present invention. [Figure 6F] FIG. 10 illustrates one example of a parameter block used by one or more non-query functions of a neural network processing assistance instruction in accordance with one or more aspects of the present invention. [Figure 6G] FIG. 10 illustrates one example of a tensor descriptor used by neural network processing assistance instructions in accordance with one or more aspects of the present invention. [Figure 7] 1A, 1B, and 1C are diagrams illustrating example input data layouts used by neural network processing assistance instructions in accordance with one or more aspects of the present invention. [Figure 8]7(A), (B), and (C) are diagrams illustrating exemplary outputs corresponding to the input data layouts of FIGS. 7(A)-7(C), in accordance with one or more embodiments of the present invention. [Figure 9A] FIG. 1 illustrates an example that facilitates processing within a computing environment in accordance with one or more aspects of the present invention. [Figure 9B] FIG. 1 illustrates an example that facilitates processing within a computing environment in accordance with one or more aspects of the present invention. [Figure 10] FIG. 1 illustrates another example of a computing environment for incorporating and using one or more aspects of the present invention. [Figure 11A] FIG. 1 illustrates yet another example of a computing environment for incorporating and using one or more aspects of the present invention. [Figure 11B] FIG. 11B illustrates further details of the memory of FIG. 11A in accordance with one or more aspects of the present invention. [Figure 12] FIG. 1 illustrates one embodiment of a cloud computing environment in accordance with one or more aspects of the present invention. [Figure 13] FIG. 2 illustrates an example of an abstract model layer in accordance with one or more aspects of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0016] According to one or more aspects of the present invention, capabilities are provided to facilitate processing within a computing environment. In one aspect, the capabilities include using a coprocessor, such as a neural network processor, of a particular machine model to perform functions including, for example, tensor calculations. A particular model of a machine or processor has specific capabilities. Another model of a machine or processor may have additional, less, or different capabilities, or a combination thereof, or may be a model of a different generation (e.g., a current or future generation) with additional, less, or different capabilities, or a combination thereof. For greater efficiency and to maintain accuracy of a deep learning network, a particular machine model may operate on specific internal or machine-specific data formats / data types used to represent input data / output data (e.g., input tensor data / output tensor data). For example, input data is converted from a standard format to a machine-specific format, and output data is converted back to the standard format. Conversion to and from a machine-specific format may include rounding operations based on a pre-specified rounding mode. In accordance with one or more aspects of the present invention, the rounding mode is not selectable but instead implied based on the machine's native data format. This simplifies the conversion process and can improve processing speed by limiting the rounding modes supported. This also makes it easier to write program code that converts data for use on coprocessors such as neural network processors.

[0017] In one example, the conversion includes using one or more conversion instructions. Each instruction is a single instruction (e.g., a single designed hardware machine instruction at a hardware / software interface) configured to perform at least the conversion function. Each instruction may be part of the instruction set architecture (ISA) of a general-purpose processor, dispatched by a program on a processor such as a general-purpose processor, or may be part of a special-purpose processor, such as a co-processor configured for a specific function that is coupled to or is part of the general-purpose processor. Other variations are possible.

[0018] Each instruction indicates a source data type and a target data type and converts the source data type to the target data type. As an example, one of the data types is a standard data type such as a binary floating-point data type. Binary floating-point data may be represented in a number of different formats, including, for example, a tuple format, a short format, a long format, or an extended format, examples of which are described with reference to FIGS. 1A-1D. Referring to FIG. 1A, a binary floating-point tuple format 100 may include, for example, a sign 102 (e.g., bit 0), an exponent +15 (104) (e.g., bits 1-5), and a fraction 106 (e.g., bits 6-15). 1B, binary floating-point short format 110 includes, for example, sign 112 (e.g., bit 0), exponent +127 (114) (e.g., bits 1-8), and fraction 116 (e.g., bits 9-31). Referring to FIG. 1C, binary floating-point long format 120 includes, for example, sign 122 (e.g., bit 0), exponent +1023 (124) (e.g., bits 1-11), and fraction 126 (e.g., bits 12-63). Furthermore, referring to FIG. 1D, binary floating-point extended format 130 includes, for example, sign 132 (e.g., bit 0), exponent +16383 (134) (e.g., bits 1-15), and fraction 136 (e.g., bits 16-127). Other formats are possible.

[0019] For example, when an operand in binary floating-point short format is read into a floating-point register, it occupies the left half of the register and the right half remains unchanged. When an operand in binary floating-point long format is read into a floating-point register, it occupies the entire register. Operands in binary floating-point extended format occupy a register pair. The sign and biased exponent are in the leftmost 16 bits of the lowest-numbered register of the register pair, followed by the leftmost 48 bits of the fraction. The rightmost 64 bits of the fraction are in the highest-numbered register of the register pair.

[0020] Below, exemplary characteristics of each of the formats are described.

[0021] Characteristics Small amount Short Long Expansion

[0022] Format length (bits) 16 32 64 128

[0023] Biased exponent length (bits) 5 8 11 15

[0024] Fraction length (bits) 10 23 52 112

[0025] Accuracy (p) 11 24 53 113

[0026] Emax 15 127 1023 16383

[0027] Emin -14 -126 -1022 -16382

[0028] LUV bias 15 127 1023 16383

[0029] Nmax (1-2 -11 )×2 16 (1-2 -24 )×2 128 (1-2 -53 )×2 1024 (1-2 -113 )×2 16384

[0030] ≒3.4×10 38 ≒1.8×10 308 ≒1.2 × 10 4932

[0031] Nmin 1.0×2 -14 1.0×2 -126 1.0×2 -1022 1.0×2 -16382

[0032] ≒1.2 × 10 -38 ≒2.2 × 10 -308 ≒3.4×10 -4932

[0033] Dmin 1.0×2 -24 1.0×2 -149 1.0×2 -1074 1.0×2 -16494

[0034] ≒1.4×10 -45 ≒4.9×10 -324 ≒6.5×10 -4966

[0035] where ≒ indicates that the value is approximate, Emax is the largest left-units-view (LUV) exponent, Emin is the smallest left-units-view exponent, Nmax is the largest representable finite number (in magnitude), and Nmin is the smallest representable normal number (in magnitude).

[0036] As an example, above for each format the bias used is shown to allow all exponents to be represented as unsigned numbers.

[0037] In each format, the binary point of a binary floating-point number is considered to be to the left of the leftmost fraction bit. To the left of the binary point is an implied unit bit that is considered to be 1 for normalized numbers and 0 for 0 and subnormalized numbers. The fraction with the implied unit bit added to the left becomes the mantissa of the number.

[0038] The value of a normal binary floating-point number is the product of the mantissa and the unbiased exponent of base 2. The value of a denormal binary floating-point number is the product of the mantissa and the lowest exponent of base 2.

[0039] Below are described example values ​​for various forms of non-zero numbers.

[0040] [Table 1]

[0041] where e is the biased exponent (expressed in decimal) and f is the fraction (in binary).

[0042] Additionally, exemplary floating-point rounding and range operations are described below.

[0043] [Table 2]

[0044] [Table 3]

[0045] Another data type according to an embodiment of the present invention is a machine-specific data type, rather than a standard data type. A machine-specific data type is, for example, a data type optimized for use by a specific processor running on a specific hardware machine. For example, a machine-specific data type may maintain extended precision and / or be easier to implement on the machine. One example of a machine-specific data type is the NNP Data Type 1 data type (also known as the Neural Network Processing Data Type 1 data type). This data type is a 16-bit floating-point format that provides several advantages to deep learning training and inference calculations, for example, including maintaining precision for deep learning networks, eliminating denormalized forms and simplifying rounding modes and corner case handling, automatic rounding to nearest for arithmetic operations, and combining the special entities for infinity and not-a-number (NaN) into a single value (NINF) that is accepted and processed by arithmetic operations. NINF provides better defaults than other formats for exponent overflow and invalid operations (such as division by zero). This allows many programs to continue executing without hiding such errors and without using special exception handlers. Other machine-specific data types are also possible.

[0046] One example of the format of the NNP Data Type 1 data type is shown in Figure 2. As shown in the figure, in one example, NNP Data Type 1 data may be represented in format 200, which may include, for example, a sign 202 (e.g., bit 0), an exponent +31 (204) (e.g., bits 1-6), and a fraction 206 (e.g., bits 7-15).

[0047] Exemplary properties of the NNP Data Type 1 format are shown below.

[0048] Characteristics NNP Data Type 1

[0049] Format length (bits) 16 bits

[0050] Biased exponent length (bits) 6 bits

[0051] Fraction length (bits) 9 bits

[0052] Precision (p) 10 bits

[0053] Maximum left unit exponent (Emax) 32

[0054] Minimum left unit display exponent (Emin) -31

[0055] Left-units-view (LUV) bias 31

[0056] Nmax (1-2 -9 )×2 33 ≒8.6×10 9

[0057] Nmin (1+2 -9 )×2 -31 ≒4.6×10 -10

[0058] Dmin --

[0059] where ≒ indicates that the value is approximate, Nmax is the largest representable finite number (in magnitude), and Nmin is the smallest representable number (in magnitude).

[0060] Another machine-specific data type that may be supported in addition to (or instead of) the NNP Data Type 1 data type is the NNP Data Type 2 data type. Additional, fewer, or other data types, or combinations thereof, may be supported.

[0061] Exemplary properties of the NNP Data Type 2 format are shown below.

[0062] Characteristics NNP Data Type 2

[0063] Format length (bits) 16 bits

[0064] Biased exponent length (bits) 5 bits

[0065] Fraction length (bits) 10 bits

[0066] Precision (p) 11 bits

[0067] Maximum left unit exponent (Emax) 16

[0068] Minimum left unit display exponent (Emin) -15

[0069] Left Unit Display (LUV) Bias 15

[0070] Nmax (1-2 -10 )×-2 16

[0071] Nmin (1+2 -10 )×2 -15

[0072] Dmin ---

[0073] where ≒ indicates that the value is approximate, Nmax is the largest representable finite number (in magnitude), and Nmin is the smallest representable normal number (in magnitude).

[0074] Further details relating to the NNP Data Type 1 and NNP Data Type 2 data types are described below.

[0075] Biased Exponent: Shown above is the bias used to allow the exponent to be represented as an unsigned number. Biased exponents are similar in properties to binary floating-point formats, except that no special meaning is attached to all-zero and all-one biased exponents, as explained below with reference to the NNP Data Type 1 and NNP Data Type 2 data type classes.

[0076] Mantissa: The binary point of NNP data type 1 and NNP data type 2 numbers is considered to be to the left of the leftmost fraction bit. To the left of the binary point there is an implied unit bit that is considered to be 1 for normalized numbers and 0 for 0. The fraction with the implied unit bit added to the left becomes the mantissa of the number.

[0077] A regular NNP datatype 1 or NNP datatype 2 value is the product of the mantissa and a base 2 number raised to an unbiased exponent.

[0078] Non-zero numeric values: Non-zero numeric values ​​are shown below.

[0079] Numeric Class Value

[0080] Normal number ±2 e-31 ×(1.f) where e is the biased exponent in decimal and f is the fraction in binary.

[0081] In one embodiment, there are three classes of NNP datatype1 data and NNP datatype2 data, which contain numeric entities and associated non-numeric entities. Each data item contains a sign, an exponent, and a mantissa. The exponent is biased so that all biased exponents are non-negative unsigned numbers, with the smallest biased exponent being 0. The mantissa contains an explicit fraction and an implicit unit bit to the left of the binary point. The sign bit is 0 for positive and 1 for negative.

[0082] Every allowed finite number other than 0 has a unique NNP data type 1 or NNP data type 2 representation. Numeric values ​​may allow multiple representations of the same value; there are no denormalized numbers, and there are no arithmetic operations on denormalized numbers. The three classes include, for example:

[0083] Class of Data Sign Biased Exponent Unit Bits* Fraction

[0084] 0 ± 0 0 0

[0085] Normal number ± 0 1 not 0

[0086] Normal number ± 1 Not 0, not all 1s Any

[0087] normal number ± all ones - not all ones

[0088] NINF ± all 1 - all 1 where - indicates not applicable, * indicates the unit bit is implicit, and NINF is not a number or infinity.

[0089] Further details regarding each of the classes are provided below.

[0090] 0:0 has a biased exponent of 0 and a fraction of 0. The implicit unit bit is 0.

[0091] Normal Numbers: Normal numbers may contain a biased exponent of any value. If the biased exponent is 0, the fraction will be non-zero. If the biased exponent is all ones, the fraction will not be all ones. Other biased exponent values ​​may have any fraction value. The implicit unit bit for all normal numbers is 1.

[0092] NINF: NINF is represented by a biased exponent of all ones and a fraction of all ones. NINF represents values ​​that can be represented by NNP data type 1 (i.e., 16-bit floating point designed for deep learning (DL), including 6 bits for the exponent and 9 bits for the fraction) or values ​​that are not within the range of NNP data type 2. Typically, NINF is simply propagated during a computation so that it remains visible at the end.

[0093] Although binary floating point data formats, NNP Data Type 1 data types, and NNP Data Type 2 data types are provided as examples, additional, fewer, or other data formats / data types, or combinations thereof, may be used.

[0094] One embodiment of a computing environment for incorporating and using one or more aspects of the present invention is described with reference to FIG. 3A. By way of example, the computing environment of FIG. 3A is based on the z / Architecture® instruction set architecture provided by International Business Machines Corporation (Armonk, New York). One embodiment of the z / Architecture instruction set architecture is described in the publication “z / Architecture Principles of Operation,” IBM Publication No. SA22-7832-12, Thirteenth Edition, September 2019, which is incorporated herein by reference in its entirety. However, the z / Architecture instruction set architecture is only one exemplary architecture, and other architectures or types of computing environments of International Business Machines Corporation or other entities or both may include and / or use one or more aspects of the present invention. z / Architecture and IBM are trademarks or registered trademarks of International Business Machines Corporation in at least one jurisdiction.

[0095] In one example, computing environment 10 includes a central electronics complex (CEC) 11. Central electronics complex 11 includes multiple components, such as memory 12 (also known as system memory, main memory, primary storage, central storage, or storage), coupled to one or more processors, such as one or more general-purpose processors (also known as central processing units (CPUs) 13) and one or more special-purpose processors (e.g., neural network processor 31), and input / output (I / O) subsystem 14.

[0096] By way of example, the one or more special purpose processors may be separate from the one or more general purpose processors, or at least one special purpose processor may be embedded within at least one general purpose processor, or both. Other variations are possible.

[0097] I / O subsystem 14 may be part of or separate from the central electronics complex. I / O subsystem 14 directs the flow of information between main memory 12 and input / output control unit 15 and input / output (I / O) devices 16 coupled to the central electronics complex.

[0098] Many types of I / O devices may be used. One particular type is a data storage device 17. The data storage device 17 may store one or more programs 18, one or more computer-readable program instructions 19, or data, or a combination thereof. The computer-readable program instructions may be configured to perform the functions of embodiments of aspects of the present invention.

[0099] Central electronics complex 11 may include and / or be coupled to removable / non-removable, volatile / non-volatile computer system storage media. For example, central electronics complex 11 may include and / or be coupled to non-removable, non-volatile magnetic media (commonly referred to as "hard drives"), magnetic disk drives for reading from and writing to removable, non-volatile magnetic disks (e.g., "floppy disks"), and / or optical disk drives for reading from or writing to removable, non-volatile optical disks such as CD-ROMs, DVD-ROMs, or other optical media. It should be understood that other hardware and / or software components may be used in conjunction with central electronics complex 11, including, but not limited to, microcode or millicode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archive storage systems.

[0100] Additionally, central electronics complex 11 can operate in numerous other general purpose or special purpose computing system environments or configurations. Examples of well-known computing systems, environments, or configurations, or combinations thereof, that may be suitable for use with central electronics complex 11 include, but are not limited to, personal computer (PC) systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, microcomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of these systems or devices.

[0101] In one or more embodiments, central electronics complex 11 provides support for logical partitioning and / or virtualization. As shown in FIG. 3B, memory 12 includes, for example, one or more logical partitions 20, a hypervisor 21 that manages the logical partitions, and processor firmware 22. One example of hypervisor 21 is the Processor Resource / System Manager (PR / SM™) offered by International Business Machines Corporation (Armonk, New York). As used herein, firmware includes, for example, processor microcode or millicode. Firmware includes, for example, hardware-level instructions and / or data structures used in implementing higher-level machine code. In one embodiment, firmware includes, for example, microcode or millicode containing trusted software, proprietary code that is typically provided as microcode or millicode specific to the underlying hardware and that controls operating system access to the system's hardware. PR / SM is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction.

[0102] Each logical partition 20 can function as a separate system. That is, each logical partition can be reset independently, run a guest operating system 23, such as the z / OS® operating system provided by International Business Machines Corporation (Armonk, New York), or other control code 24, such as coupling facility control code (CFCC), and operate with different programs 25. An operating system or application program running within a logical partition appears to have access to the entire system, but in fact only a portion of it is available. While the z / OS operating system is provided as an example, other operating systems provided by International Business Machines Corporation and / or other companies may be used in accordance with one or more aspects of the present invention. z / OS is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction.

[0103] Memory 12 is coupled to physical processor resources, such as CPU 13 (FIG. 3A), that can be assigned to logical partitions. For example, logical partition 20 may include one or more logical processors, each of which represents all or a portion of physical processor resources 13 that can be dynamically assigned to a logical partition.

[0104] In another embodiment, central electronics complex 11 provides virtualization support (with or without logical partitioning support). As shown in FIG. 3C, memory 12 of central electronics complex 11 includes, for example, one or more virtual machines 26, a virtual machine manager (e.g., hypervisor 27) that manages the virtual machines, and processor firmware 28. One example of hypervisor 27 is the z / VM® hypervisor offered by International Business Machines Corporation (Armonk, New York). A hypervisor may be referred to as a host. z / VM is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction.

[0105] The central electronics complex's virtual machine support provides the ability to operate multiple virtual machines 26, each capable of running a different program 29 and a guest operating system 30, such as the Linux® guest operating system. Each virtual machine 26 can function as a separate system; that is, each virtual machine can be reset independently, run a guest operating system, and operate with different programs. An operating system or application program running within a virtual machine appears to have access to the entire system, but in fact only a portion of it is available. While z / VM and Linux are provided as examples, other virtual machine managers and / or operating systems may be used in accordance with one or more aspects of the present invention. The registered trademark Linux® is used pursuant to a sublicense from the Linux Foundation (an exclusive licensee of Linus Torvalds, owner of the trademark worldwide).

[0106] In one example, a processor (e.g., processor 13 and / or processor 31) includes multiple functional components (or a subset thereof) used to execute instructions. As shown in FIG. 3D , these functional components include, for example, an instruction fetch component 350 for fetching instructions to be executed, an instruction decode unit 352 for decoding the fetched instructions and obtaining operands for the decoded instructions, one or more instruction execution components 354 for executing the decoded instructions, a memory access component 356 for accessing memory to execute the instructions, if necessary, and a writeback component 358 for providing results of the executed instructions. One or more of the components may access and / or use one or more registers 360 in instruction processing. Additionally, one or more of the components may include at least a portion of or have access to one or more other components used in performing, in accordance with one or more aspects of the present invention, e.g., converting, rounding, or processing, or a combination thereof, of one or more transform instructions, and / or neural network processing-assisted processing of, e.g., neural network processing-assisted instructions (or other processing that may employ one or more aspects of the present invention), as described herein. The one or more other components may include, for example, converting and / or rounding component 370 and / or neural network processing-assisted component 372 (or one or more other components or combinations thereof).

[0107] In accordance with an embodiment of the present invention, for greater efficiency, a selected machine of a particular machine model may operate on a specific internal or machine-specific data format / data type used to represent input / output data. In such a case, for example, the input data is converted from a standard format to a machine-specific format, and the output data is converted back to the standard format. Other examples are possible. In accordance with an embodiment of the present invention, conversion to and from a machine-specific format may include rounding. The rounding mode used is not selectable but is implied (also referred to as preselected) based on the machine-specific format used. For example, the rounding mode is assigned to the machine-specific format and is not obtained, for example, from an instruction operand or a control register (such as a floating-point control register) that allows for selectable rounding modes. Instead, in accordance with an embodiment of the present invention, the rounding mode is preselected and assigned to the machine-specific format, such that the machine-specific format uses only that rounding mode. This provides efficiency, reduces complexity, and improves system performance. Conversion performance is improved, improving system performance and data availability.

[0108] In one example, in accordance with aspects of the present invention, a conversion operation is performed, for example, by a general-purpose processor (e.g., processor 13) to enable a selected processor (e.g., neural network processor 31) of a particular machine model to perform a function on data in a machine-specific format. This conversion operation includes performing a conversion as indicated by a selected instruction, and may include rounding using a rounding mode determined based on the data type indicated by the instruction. Further details regarding this process are described with reference to Figures 4A-4B.

[0109] Referring to FIG. 4A, in one example, appropriate conversion instructions are selected and decoded (400). The conversion instructions selected depend, for example, on the source and target data types as well as other operations being performed. Exemplary conversion instructions include, for example, a vector floating-point convert and expand high-order instruction from neural network processing, a vector floating-point convert and expand low-order instruction from neural network processing, a vector floating-point convert and round instruction to neural network processing, a vector floating-point convert instruction from neural network processing, and a vector floating-point convert instruction to neural network processing. Additional conversion instructions, fewer conversion instructions, or other conversion instructions, or a combination thereof, may be used depending, for example, on the data type being converted, etc.

[0110] Decoding includes, for example, obtaining one or more input operands of an instruction (e.g., text information provided in one or more masks) and determining whether and which type of machine-native data type is specified by the one or more input operands. For example, either the source data type input operand or the target data type input operand may specify a machine-native data type. In one example, whether an input operand specifying a machine-native data type is the source data type or the target data type is known from the instruction being decoded (e.g., indicated by an opcode). In another example, an indicator within the operands of the instruction indicates which operands, if any, specify a machine-native data type. This indicator can be part of the operand specifying the data type or can be in a separate operand. In other embodiments, both the source data type and the target data type specify a machine-native data type (e.g., one type and another type). Other examples are possible.

[0111] A determination is made as to whether the instruction specifies a first machine-specific data type, referred to herein as machine-specific data type 1 (e.g., NNP data type 1) (410). If the instruction does not specify a first machine-specific data type, a further determination is made as to whether the instruction specifies a second machine-specific data type, referred to herein as machine-specific data type 2 (e.g., NNP data type 2) (420). If neither the first nor second machine-specific data type is specified, in one example, an unsupported data type exception is specified (430). In this example, two machine-specific data type checks are performed, but other embodiments may include additional or fewer checks for additional or fewer machine-specific data types. Many possibilities exist.

[0112] Returning to inquiry 410, if machine-native data type 1 is specified, the rounding mode is automatically and implicitly set to a first mode, such as round to nearest away from zero. Further, returning to inquiry 420, if machine-native data type 2 is specified, the rounding mode is automatically and implicitly set to a second mode, such as round toward zero. Other examples are possible.

[0113] After setting a pre-specified rounding mode based on the selected machine-specific data type, the instruction is executed, specifically, converting and rounding is performed (440) as described with reference to FIG. 4B.

[0114] Referring to FIG. 4B , in one embodiment, for example, one or more input operands of the instruction containing the data to be converted are obtained (450), if not already obtained. A determination is made (460) of the machine-specific data type specified using the operands of the instruction (assuming a machine-specific data type is specified), and therefore the rounding mode to be used. Rounding is performed (470) based on the rounding mode preselected and assigned to the machine-specific data type. The rounded data is converted (480) from the source data type to the target data type, and a result of the rounding and conversion is provided (490). In one example, the result is an output tensor in the target data type. In one example, the rounding / conversion process is then complete.

[0115] In other embodiments, rounding may be performed after conversion. Additionally, in other embodiments, the rounding mode may be pre-selected and assigned to standard data types rather than machine-native data types. In one or more embodiments, the rounding mode may be implicitly set for one or more selected data types, where the selected data types are standard data types, machine-native data types, and / or other data types. Other examples are possible.

[0116] In one embodiment, each of the transformation instructions is part of, for example, a vector function that provides a fixed-size vector containing, for example, 1 to 16 elements. Each vector contains data that is operated on by the vector instructions defined in that function. In one embodiment, when a vector consists of multiple elements, each element is processed in parallel with the other elements. In one example, completion of the instruction does not occur until processing of all elements is complete. In other embodiments, elements are processed partially in parallel, sequentially, or both.

[0117] In one embodiment, there are 32 vector registers, and other types of registers can be mapped to the vector register quadrants. For example, a register file, which is an array of processor registers within a central processing unit (e.g., processor 13), may contain 32 vector registers, each 128 bits in length. Sixteen floating-point registers, each 64 bits in length, can overlap the vector registers. Thus, as an example, if floating-point register 2 is modified, vector register 2 is also modified. Other mappings of other types of registers are possible.

[0118] For example, vector data may appear in storage in the same left-to-right order as other data formats: bits of the data format numbered 0 through 7 form the byte in the leftmost (lowest numbered) byte position in storage, bits 8 through 15 form the byte in the next consecutive position, etc. In a further example, vector data may appear in storage in another order, such as right-to-left.

[0119] Each of the vector instructions described herein includes multiple fields, which may have a subscript associated with them. A subscript associated with a field of an instruction indicates the operand to which that field applies. For example, a subscript of 1 associated with vector register V1 indicates that the register specified using V1 contains the first operand, and so on. The length of a register operand is one register, e.g., 128 bits.

[0120] Additionally, each vector instruction includes a Register Extension Bits (RXB) field that contains the most significant bits of the operand specified by the vector register. Bits in the register specification not specified by the instruction are reserved and should be set to 0. The most significant bit is concatenated to the left of the 4-bit register specification in the Vector Register field, for example, to create a 5-bit vector register specification.

[0121] In one example, the RXB field includes four bits (eg, bits 0-3), each defined as follows:

[0122] 0 - Most significant bit of the instruction's first vector register specification (e.g., bits 8-11).

[0123] 1 - The most significant bit of the instruction's second vector register designation (e.g., bits 12-15), if present.

[0124] 2 - The most significant bit (e.g., bits 16-19) of the instruction's third vector register designation, if any.

[0125] 3 - The most significant bit of the fourth vector register specification (e.g., bits 32-35) of the instruction, if present.

[0126] Each bit is set to 0 or 1 depending on the register number, e.g., by an assembler. For example, for registers 0-15, the bit is set to 0, for registers 16-31, the bit is set to 1, etc.

[0127] In one embodiment, each RXB bit is an extension bit for a particular position in an instruction containing one or more vector registers. For example, bit 0 of RXB is the extension bit for positions 8-11, assigned to, for example, V1, and so on. Specifically, for vector registers, registers containing operands are specified using a 4-bit field in the register field, for example, with the corresponding register extension bit (RXB) added as the most significant bit. For example, if the 4-bit field is 0110 and the extension bit is 0, then the 5-bit field 00110 indicates register number 6. In a further embodiment, the RXB field includes additional bits, so that two or more bits per vector or position are used as extensions.

[0128] In the descriptions herein of conversion instructions and / or other instructions, specific locations of fields, specific fields, and / or specific sizes of fields, or combinations thereof (e.g., specific bytes and / or bits), may be indicated. However, other locations, fields, and / or sizes, or combinations thereof, may be provided. Furthermore, while the setting of a bit to a particular value (e.g., 1 or 0) may be specified, this is merely an example. The bit, when set, may in other instances be set to a different value, such as the opposite value or another value. Many variations are possible.

[0129] One example of a vector conversion instruction is a vector floating point convert and expand high-level instruction from neural network processing, an example of which is described with reference to Figure 5A. In one embodiment, the vector floating point convert and expand high-level instruction from neural network processing 500 has a VRR format that indicates operands between vector registers along with an extended opcode. The vector floating-point convert and expand high-level instruction 500 from neural network processing includes, for example, operation code (opcode) fields 502a, 502b (e.g., bits 0-7 and 40-47) indicating the conversion to be performed, a first vector register (V1) field 504 (e.g., bits 8-11) used to specify a first vector register, a second vector register (V2) field 506 (e.g., bits 12-15) used to specify a second vector register, a first mask (M4) field 508 (e.g., bits 28-31), a second mask (M3) field 510 (e.g., bits 32-35), and a register extension bit (RXB) field 512 (e.g., bits 36-39), each of which is described herein. In one embodiment, each field is separate and independent of the other, while in other embodiments, two or more fields may be combined. More details regarding these fields are described below.

[0130] In one embodiment, the vector register (V1) field 504 is used to indicate a vector register that stores a first operand. The first operand is the result obtained from the conversion. The second operand is contained in a vector register specified using the vector register (V2) field 506, e.g., the value to be converted. In one example, each of the vector register fields 504, 506 is used in conjunction with the RXB field 512 to specify a vector register. In another embodiment, the vector register field is used to specify one or more vector registers.

[0131] In one example, the M4 field 508 specifies the source data type. Example data types include, for example:

[0132] M4 Source Data Type

[0133] 0 Neural Network Processing Data Types 1

[0134] 1 Neural Network Processing Data Types 2

[0135] 2~15 Reserve

[0136] If a reserved value is specified, the IEEE inexact exception is recognized.

[0137] In one example, the M3 field 510 specifies the target data type. Example data types include, for example:

[0138] M3 target data type

[0139] 0~1 Reserve

[0140] 2 binary floating point short form

[0141] 3~15 Reserve

[0142] If a reserved value is specified, the IEEE inexact exception is recognized.

[0143] In one embodiment, if a combination of values ​​for M3 and M4 other than the spare is not supported by the model (e.g., a selected machine or processor of a particular model), then in one example, an IEEE inexact exception is recognized. For example, an IEEE inexact exception flag (also referred to herein as an indicator) is set, for example, to 1. If the IEEE inexact exception is recognized, then the first operand is, for example, unpredictable. In one example, the first operand is set to a default value (e.g., 0, the value to be converted, or another value). In another embodiment, an IEEE inexact exception is recognized only for a particular invalid data type, such as an invalid machine-specific data type (e.g., NNP data type 1, NNP data type 2), but not for other data types, such as invalid standard data types (e.g., binary floating-point formats). Other examples are possible. Furthermore, in one embodiment, if an IEEE inexact exception is recognized only for a particular invalid data type (e.g., an invalid machine-specific data type) but not for other invalid data types (e.g., invalid standard types), then a specification exception may be recognized for the other invalid data types. Other variations are possible.

[0144] While particular values ​​and formats are provided as examples of source and target data types, additional, fewer, or other values ​​or formats, or combinations thereof, may be used. Additionally, while in this embodiment no rounding is performed with respect to this instruction, in other embodiments rounding is performed in accordance with one or more aspects of the present invention. If rounding is performed, the rounding mode used is, for example, the rounding mode assigned to the machine-specific data type specified by the instruction.

[0145] In executing one embodiment of the Vector Floating-Point Convert and Expand high-level instruction from Neural Network Processing, element values ​​of the source data type specified in the left half of the second operand are converted to the specified target format and placed in corresponding double-width elements in the first operand. The right half of the second operand is ignored. The format of the elements of the second operand is specified by the source data type in the M4 field. The format of the elements of the first operand is specified by the target data type in the M3 field.

[0146] As an example, M4 may specify a neural network processing data type 1 data type, and the value in the second operand, which is in the NNP data type 1 data format, may be converted to the binary floating-point short format specified by M3, and the result may be placed in the first operand.

[0147] Value of the second operand = binary 1.1 x 2 1 = Decimal 3.0

[0148] For NNP data type 1,

[0149] Sign = 0 (if positive)

[0150] Exponent = 31 + 1 (1 is 2 1 exponent in (32) = 32 = 100000

[0151] Mantissa = 1.100000000 (Note that the fractional part of a binary number (e.g., 1) has 9 bits of precision, and the leading "1" is implied and therefore removed when placed into an actual NNP data type 1 format number)

[0152] This gives 0 100000 100000000 in binary.

[0153] 0x4100 (100000100000000 converted to hex)

[0154] In binary floating-point short format,

[0155] Sign = 0 (if positive)

[0156] Index=127+1=128=10000000

[0157] Mantissa = .100000000000000000000000 (23-bit fraction, again, the implied "1" is removed)

[0158] In hexadecimal, it is 0x40400000

[0159] Execution of one embodiment of the instruction leaves the condition code unchanged. Possible IEEE exceptions include invalid operation and inexact.

[0160] An example result of vector floating point convert and expand upper / lower instructions from NNP is shown below:

[0161] [Table 4]

[0162] Another example of a conversion instruction is a vector floating point convert and expand sub-instruction from neural network processing. As shown in Figure 5B, in one embodiment, the vector floating point convert and expand sub-instruction from neural network processing 520 has a VRR format that indicates the vector register to vector register operands along with an extended opcode. The vector floating-point convert and expand sub-instruction 520 from neural network processing includes, for example, operation code (opcode) fields 522a, 522b (e.g., bits 0-7 and 40-47) indicating the conversion to be performed, a first vector register (V1) field 524 (e.g., bits 8-11) used to specify a first vector register, a second vector register (V2) field 526 (e.g., bits 12-15) used to specify a second vector register, a first mask (M4) field 528 (e.g., bits 28-31), a second mask (M3) field 530 (e.g., bits 32-35), and a register extension bit (RXB) field 532 (e.g., bits 36-39), each of which is described herein. In one embodiment, each field is separate and independent of the other, while in other embodiments, two or more fields may be combined. More details regarding these fields are described below.

[0163] In one embodiment, the vector register (V1) field 524 is used to indicate a vector register that stores a first operand. The first operand is the result obtained from the conversion. The second operand is contained in a vector register specified using the vector register (V2) field 526, e.g., contains the value to be converted. In one example, each of the vector register fields 524, 526 is used in conjunction with the RXB field 532 to specify a vector register. In another embodiment, the vector register field is used to specify one or more vector registers.

[0164] In one example, the M4 field 528 specifies the source data type. Example data types include, for example:

[0165] M4 Source Data Type

[0166] 0 Neural Network Processing Data Types 1

[0167] 1 Neural Network Processing Data Types 2

[0168] 2~15 Reserve

[0169] If a reserved value is specified, the IEEE inexact exception is recognized.

[0170] In one example, the M3 field 530 specifies the target data type. Example data types include, for example:

[0171] M3 target data type

[0172] 0~1 Reserve

[0173] 2 binary floating point short form

[0174] 3~15 Reserve

[0175] If a reserved value is specified, the IEEE inexact exception is recognized.

[0176] In one embodiment, if a combination of values ​​for M3 and M4 other than the spare is not supported by the model (e.g., a selected machine or processor of a particular model), then in one example, an IEEE inexact exception is recognized. For example, an IEEE inexact exception flag (also referred to herein as an indicator) is set, for example, to 1. If the IEEE inexact exception is recognized, then the first operand is, for example, unpredictable. In one example, the first operand is set to a default value (e.g., 0, the value to be converted, or another value). In another embodiment, an IEEE inexact exception is recognized only for a particular invalid data type, such as an invalid machine-specific data type (e.g., NNP data type 1, NNP data type 2), but not for other data types, such as invalid standard data types (e.g., binary floating-point formats). Other examples are possible. Furthermore, in one embodiment, if an IEEE inexact exception is recognized only for a particular invalid data type (e.g., an invalid machine-specific data type) but not for other invalid data types (e.g., invalid standard types), then a specification exception may be recognized for the other invalid data types. Other variations are possible.

[0177] While particular values ​​and formats are provided as examples of source and target data types, additional, fewer, or other values ​​or formats, or combinations thereof, may be used. Additionally, while in this embodiment no rounding is performed with respect to this instruction, in other embodiments rounding is performed in accordance with one or more aspects of the present invention. If rounding is performed, the rounding mode used is, for example, the rounding mode assigned to the machine-specific data type specified by the instruction.

[0178] In executing one embodiment of the Vector Floating-Point Convert and Expand sub-instructions from Neural Network Processing, element values ​​of the source data type specified in the right half of the second operand and extended with zeros are converted to the specified target format and placed into corresponding double-wide elements in the first operand. The left half of the second operand is ignored. The format of the elements of the second operand is specified by the source data type in the M4 field. The format of the elements of the first operand is specified by the target data type in the M3 field.

[0179] Execution of one embodiment of the instruction leaves the condition code unchanged. Possible IEEE exceptions include invalid operation and inexact. An exemplary result of the vector floating-point convert and expand sub-instructions from NNP is shown above.

[0180] Another example of a conversion instruction is a vector floating point convert and round instruction for neural network processing. As shown in Figure 5C, in one embodiment, the vector floating point convert and round instruction for neural network processing 540 has a VRR format that indicates the vector register to vector register operands along with an extended opcode. The vector floating-point convert and round instruction 540 for neural network processing may include, for example, operation code (opcode) fields 542a, 542b (e.g., bits 0-7 and 40-47) indicating the conversion and rounding to be performed, a first vector register (V1) field 544 (e.g., bits 8-11) used to specify a first vector register, a second vector register (V2) field 546 (e.g., bits 12-15) used to specify a second vector register, a third vector register (V3) field 548 (e.g., bits 16-19) used to specify a third vector register, a first mask (M5) field 550 (e.g., bits 28-31), a second mask (M4) field 552 (e.g., bits 32-35), and a register extension bit (RXB) field 554 (e.g., bits 36-39), each of which is described herein. In one embodiment, each field is separate and independent of one another, but in other embodiments, two or more fields may be combined. More details regarding these fields are provided below.

[0181] In one embodiment, the vector register (V1) field 544 is used to indicate a vector register that stores a first operand. The first operand is the result obtained from the conversion and rounding. The second operand contained in the vector register specified using the vector register (V2) field 546 and the third operand contained in the vector register specified using the vector register (V3) field 548 are concatenated to create the source vector. In one example, each of the vector register fields 544, 546, and 548 is used in conjunction with the RXB field 554 to specify a vector register. In another embodiment, the vector register fields are used to specify one or more vector registers.

[0182] In one example, the M5 field 550 specifies the source data type. Example data types include, for example:

[0183] M5 Source Data Type

[0184] 0~1 Reserve

[0185] 2 binary floating point short form

[0186] 3~15 Reserve

[0187] If a reserved value is specified, the IEEE inexact exception is recognized.

[0188] In one example, the M4 field 552 specifies the target data type. Example data types include, for example:

[0189] M4 target data type

[0190] 0 Neural Network Processing Data Types 1

[0191] 1 Neural Network Processing Data Types 2

[0192] 2~15 Reserve

[0193] If a reserved value is specified, the IEEE inexact exception is recognized.

[0194] In one embodiment, if a combination of values ​​for M4 and M5 other than the spare is not supported by the model (e.g., a selected machine or processor of a particular model), then in one example, an IEEE inexact exception is recognized. For example, an IEEE inexact exception flag (also referred to herein as an indicator) is set, for example, to 1. If the IEEE inexact exception is recognized, then the first operand is, for example, unpredictable. In one example, the first operand is set to a default value (e.g., 0, the value to be converted, or another value). In another embodiment, an IEEE inexact exception is recognized only for a particular invalid data type, such as an invalid machine-specific data type (e.g., NNP data type 1, NNP data type 2), but not for other data types, such as invalid standard data types (e.g., binary floating-point formats). Other examples are possible. Furthermore, in one embodiment, if an IEEE inexact exception is recognized only for a particular invalid data type (e.g., an invalid machine-specific data type) but not for other invalid data types (e.g., invalid standard types), then a specification exception may be recognized for the other invalid data types. Other variations are possible.

[0195] Although particular values ​​and formats are provided as examples of source and target data types, additional values ​​and / or formats, fewer values ​​and / or formats, or other values ​​and / or formats, or combinations thereof, may be used.

[0196] In one embodiment of the vector floating-point conversion and rounding instruction for neural network processing, a source vector is created from the concatenation of the second operand followed by the third operand. In a left-to-right manner, elements of the source data type of the source vector are converted to the numeric format of the target data type by rounding to the numeric precision of the target data type. Half the size of a numeric value of the target data type is placed in the corresponding element of the first operand specified by the vector register. In accordance with this aspect of the invention, the rounding mode used for rounding is based on the machine-native data type of the target data type. Thus, in one example, the rounding mode is the mode assigned to neural network processing data type 1 because neural network processing data type 1 is the machine-native data type specified by the instruction for use in the conversion. In this example, the rounding mode assigned to neural network processing data type 1 is round to nearest, away from zero.

[0197] In another example, the Neural Network Processing Data Type 2 data type is specified and the rounding mode assigned to the Neural Network Processing Data Type 2 is round towards zero.

[0198] An exemplary conversion of a short format binary floating point number to an NNP data type 2 value is shown below:

[0199] Value of the second operand: +1.0000000001 x 2 in BFP short format -16 (binary).

[0200] Sign = 0 (if positive)

[0201] Exponent = -16 + 127 = 111 (decimal)

[0202] Mantissa = 1.0000000001 (note that the fraction has 10 bits of precision and the leading "1" is implied and therefore removed in BFP short format numbers).

[0203] This gives us 0 01101111 00000000010000000000000 or 0x37802000.

[0204] In NNP data type 2, this number has an exponent value of 2 -15 It cannot be represented directly because it is less than NMin. In fact, this value is exactly half of NMin. If rounding to nearest even is used, this value becomes +0. Therefore, the result is 0x0000.

[0205] Execution of one embodiment of the instruction leaves the condition code unchanged. Possible IEEE exceptions include invalid operation, overflow, underflow, and inexact.

[0206] An example result of vector floating point conversion and rounding instructions on neural network processing is shown below.

[0207] [Table 5]

[0208] Another example of a conversion instruction is a vector floating point conversion instruction from neural network processing. As shown in Figure 5D, in one embodiment, a vector floating point conversion instruction from neural network processing 560 has a VRR format that indicates the vector register to vector register operands along with an extended opcode. A vector floating-point conversion instruction from neural network processing 560 may include, for example, operation code (opcode) fields 562a, 562b (e.g., bits 0-7 and 40-47) indicating the conversion to be performed, a first vector register (V1) field 564 (e.g., bits 8-11) used to specify a first vector register, a second vector register (V2) field 566 (e.g., bits 12-15) used to specify a second vector register, a first mask (M4) field 568 (e.g., bits 28-31), a second mask (M3) field 570 (e.g., bits 32-35), and a register extension bits (RXB) field 572 (e.g., bits 36-39), each of which is described herein. In one embodiment, each field is separate and independent of the other, while in other embodiments, two or more fields may be combined. More details regarding these fields are described below.

[0209] In one embodiment, the vector register (V1) field 564 is used to indicate a vector register that stores a first operand. The first operand is the result obtained from the conversion being performed. The second operand is contained in a vector register specified using the vector register (V2) field 566. In one example, each of the vector register fields 564, 566 is used in conjunction with the RXB field 572 to specify a vector register. In another embodiment, the vector register field is used to specify one or more vector registers.

[0210] In one example, the M4 field 568 specifies the source data type. Example data types include, for example:

[0211] M4 Source Data Type

[0212] 0 Neural Network Processing Data Types 1

[0213] 1 Neural Network Processing Data Types 2

[0214] 2~15 Reserve

[0215] If a reserved value is specified, the IEEE inexact exception is recognized.

[0216] In one example, the M3 field 570 specifies the target data type. Example data types include, for example:

[0217] M3 target data type

[0218] 0 Reserve

[0219] 1 binary floating point small amount format

[0220] 2~15 Reserve

[0221] If a reserved value is specified, the IEEE inexact exception is recognized.

[0222] In one embodiment, if a combination of values ​​for M3 and M4 other than the spare is not supported by the model (e.g., a selected machine or processor of a particular model), then in one example, an IEEE inexact exception is recognized. For example, an IEEE inexact exception flag (also referred to herein as an indicator) is set, for example, to 1. If the IEEE inexact exception is recognized, then the first operand is, for example, unpredictable. In one example, the first operand is set to a default value (e.g., 0, the value to be converted, or another value). In another embodiment, an IEEE inexact exception is recognized only for a particular invalid data type, such as an invalid machine-specific data type (e.g., NNP data type 1, NNP data type 2), but not for other data types, such as invalid standard data types (e.g., binary floating-point formats). Other examples are possible. Furthermore, in one embodiment, if an IEEE inexact exception is recognized only for a particular invalid data type (e.g., an invalid machine-specific data type) but not for other invalid data types (e.g., invalid standard types), then a specification exception may be recognized for the other invalid data types. Other variations are possible.

[0223] Although particular values ​​and formats are provided as examples of source and target data types, additional values ​​and / or formats, fewer values ​​and / or formats, or other values ​​and / or formats, or combinations thereof, may be used.

[0224] In execution of one embodiment of the Neural Network Processing to Vector Floating-Point Conversion instruction, elements of the specified source data type of the second operand are rounded to the numeric precision of the target data type. The result is converted to the specified target data type and placed in the corresponding element of the first operand's position. In accordance with an aspect of the present invention, the rounding mode used for rounding is based on the machine-native data type of the source data type. Thus, in one example, because Neural Network Processing Data Type 1 is the machine-native data type specified by the instruction for use in the conversion, the rounding mode is the mode assigned to Neural Network Processing Data Type 1. If another data type (e.g., NNP Data Type 2 or another data type) is selected, the rounding mode becomes the rounding mode assigned to the other data type.

[0225] Execution of one embodiment of the instruction leaves the condition code unchanged. Possible IEEE exceptions include invalid operation, overflow, underflow, and inexact.

[0226] An example result of vector-floating-point conversion from neural network processing is shown below.

[0227] [Table 6]

[0228] [Table 7]

[0229] Another example of a conversion instruction is a vector floating point to neural network operation conversion instruction. As shown in Figure 5E, in one embodiment, a vector floating point to neural network operation conversion instruction 580 has a VRR format that indicates vector register to vector register operands along with an extended opcode. The vector floating-point conversion instruction 580 for neural network processing includes, for example, operation code (opcode) fields 582a, 582b (e.g., bits 0-7 and 40-47) indicating the conversion to be performed, a first vector register (V1) field 584 (e.g., bits 8-11) used to specify a first vector register, a second vector register (V2) field 586 (e.g., bits 12-15) used to specify a second vector register, a first mask (M4) field 588 (e.g., bits 28-31), a second mask (M3) field 590 (e.g., bits 32-35), and a register extension bits (RXB) field 592 (e.g., bits 36-39), each of which is described herein. In one embodiment, each field is separate and independent of the other, while in other embodiments, two or more fields may be combined. More details regarding these fields are described below.

[0230] In one embodiment, the vector register (V1) field 584 is used to indicate a vector register that stores a first operand. The first operand is the result obtained from the conversion. The second operand is contained in a vector register specified using the vector register (V2) field 586. In one example, each of the vector register fields 584, 586 is used in conjunction with the RXB field 592 to specify a vector register. In another embodiment, the vector register field is used to specify one or more vector registers.

[0231] In one example, the M4 field 588 specifies the source data type. Example data types include, for example:

[0232] M4 Source Data Type

[0233] 0 Reserve

[0234] 1 binary floating point small amount format

[0235] 2~15 Reserve

[0236] If a reserved value is specified, the IEEE inexact exception is recognized.

[0237] In one example, the M3 field 590 specifies the target data type. Example data types include, for example:

[0238] M3 target data type

[0239] 0 Neural Network Processing Data Types 1

[0240] 1 Neural Network Processing Data Types 2

[0241] 2~15 Reserve

[0242] If a reserved value is specified, the IEEE inexact exception is recognized.

[0243] In one embodiment, if a combination of values ​​for M3 and M4 other than the spare is not supported by the model (e.g., a selected machine or processor of a particular model), then in one example, an IEEE inexact exception is recognized. For example, an IEEE inexact exception flag (also referred to herein as an indicator) is set, for example, to 1. If the IEEE inexact exception is recognized, then the first operand is, for example, unpredictable. In one example, the first operand is set to a default value (e.g., 0, the value to be converted, or another value). In another embodiment, an IEEE inexact exception is recognized only for a particular invalid data type, such as an invalid machine-specific data type (e.g., NNP data type 1, NNP data type 2), but not for other data types, such as invalid standard data types (e.g., binary floating-point formats). Other examples are possible. Furthermore, in one embodiment, if an IEEE inexact exception is recognized only for a particular invalid data type (e.g., an invalid machine-specific data type) but not for other invalid data types (e.g., invalid standard types), then a specification exception may be recognized for the other invalid data types. Other variations are possible.

[0244] Although particular values ​​and formats are provided as examples of source and target data types, additional values ​​and / or formats, fewer values ​​and / or formats, or other values ​​and / or formats, or combinations thereof, may be used.

[0245] In execution of one embodiment of the vector floating-point conversion instruction for neural network processing, the binary floating-point elements of the second operand are rounded to the numeric precision of the target data type. The result is converted to the target data type and placed in the corresponding element of the first operand's position. In accordance with an aspect of the present invention, the rounding mode used for rounding is based on the machine-native data type of the target data type. Thus, in one example, the rounding mode is the mode assigned to neural network processing data type 1 because neural network processing data type 1 is the machine-native data type specified for use in the conversion by the instruction. If another data type (e.g., NNP data type 2 or another data type) is selected, the rounding mode becomes the rounding mode assigned to the other data type.

[0246] One execution of one embodiment of the instruction leaves the condition code unchanged. Possible IEEE exceptions include invalid operation, overflow, and inexact.

[0247] An example result of vector floating point conversion to neural network processing is shown below.

[0248] [Table 8]

[0249] One or more of the above conversion instructions may be used, in accordance with one or more aspects of the present invention, to provide data to a processor of a selected machine model, e.g., in a format optimized for that processor / machine model, so that the processor of that machine model can use the data to perform a function. The processor of that machine model provides output in that data type, which may then be converted using one or more of the above conversion instructions to a standard data type or other data type for use by a program or other processor(s), or both.

[0250] In one example, data is converted (and may be rounded) from a standard data type (e.g., binary floating-point format) to a machine-specific data type (e.g., NNP data type 1, NNP data type 2) for a selected processor (e.g., a special-purpose processor) for a particular machine model, e.g., by a general-purpose processor. One or more functions are performed using the converted data by the selected processor. Upon completion of the execution of the one or more functions, the converted data, e.g., in a machine-specific format, is converted back to a standard format, e.g., by the general-purpose processor, for use by the general-purpose processor, another processor, or other processing, or a combination thereof.

[0251] In one example, the selected processor is a coprocessor, such as a neural network processor (e.g., neural network processor 31) used to perform tensor calculations and / or other operations, and the data converted to NNP data type 1 format or NNP data type 2 is provided to the selected processor via instructions, such as neural network processing support instructions, examples of which are described below.

[0252] One example of a neural network processing assistance instruction is described with reference to FIG. 6A. In one example, the instruction is initiated on a general-purpose processor (e.g., processor 13), and the function specified by the instruction is executed on either the general-purpose processor or the specialized processor (e.g., neural network processor 31), or both, depending on the function. The instruction is then completed on the general-purpose processor. In other examples, the instruction is initiated, executed, and completed on one or more general-purpose processors or one or more specialized processors. Other variations are possible. In the descriptions herein, specific locations of fields, specific fields, or specific sizes of fields, or combinations thereof (e.g., specific bytes and / or bits), are indicated. However, other locations, fields, or sizes, or combinations thereof, may be provided. Furthermore, while setting a bit to a particular value (e.g., 1 or 0) may be specified, this is merely an example. When a bit is set, it may be set to a different value, such as the opposite value or another value, in other examples. Many variations are possible.

[0253] In one example, referring to Figure 6A, a neural network processing assistance instruction 600 has an RRE format that indicates registers and register operations along with an extended operation code (opcode). As shown in Figure 6A, in one example, the neural network processing assistance instruction 600 includes an operation code (opcode) field 602 (e.g., bits 0-15) that indicates the neural network processing assistance operation. In one example, bits 16-31 of the instruction are reserved and should contain 0.

[0254] In one example, an instruction uses multiple general purpose registers implicitly specified by the instruction, such as neural network processing assistance instruction 600, which uses implicit registers general purpose register 0 and general purpose register 1, examples of which are described with reference to Figures 6B and 6D, respectively.

[0255] Referring to FIG. 6B, in one example, general register 0 includes a function code field and a status field that may be updated upon completion of the instruction. By way of example, general register 0 includes a response code field 610 (e.g., bits 0-15), an exception flags field 612 (e.g., bits 24-31), and a function code field 614 (e.g., bits 56-63). Additionally, in one example, bits 16-23 and 32-55 of general register 0 are reserved and should contain zeros. One or more fields are used by a particular function performed by the instruction. In one example, not all fields are used by all functions. Each of the fields is described below.

[0256] Response Code (RC) 610: This field (e.g., bit positions 0-15) contains a response code. The response code is stored when execution of a neural network processing support instruction is completed with a condition code of, for example, 1. If an invalid input condition occurs, a non-zero value indicating the cause of the invalid input condition recognized during execution is stored in the response code field, and a selected condition code (e.g., 1) is set. The code stored in the response code field is defined as follows in one example:

[0257] Response Code Meaning

[0258] 0001 The parameter block format specified by the parameter block version number is not supported by the model.

[0259] 0002 The specified feature is not defined or is not installed on the machine.

[0260] 0010 The specified tensor data layout format is not supported.

[0261] 0011 The specified tensor data type is not supported.

[0262] 0012 The dimensions of the specified single tensor are greater than the maximum dimension index size.

[0263] 0013 The specified tensor size is larger than the maximum tensor size.

[0264] 0014 The specified tensor address is not aligned to a 4K byte boundary.

[0265] 0015 The address of the function-specific save area is not aligned to a 4K byte boundary.

[0266] F000-FFFF Function-specific response codes. These response codes are defined for specific functions.

[0267] Exception Flags (EF) 612: This field (e.g., bit positions 24-31) contains exception flags. If an exception condition is detected during the execution of an instruction, the corresponding exception flag control (e.g., bit) is set, e.g., to 1; otherwise, this control remains unchanged. Before the first invocation of an instruction, the exception flags field is initialized to 0. During the execution of the instruction, the reserved flags do not change. In one example, the flags stored in the exception flags field are defined as follows:

[0268] EF (bit) meaning

[0269] 0 Range violation. This flag is set if a non-numeric value is found in an input tensor or stored in an output tensor. This flag is only valid if the instruction completes with, for example, a condition code of 0.

[0270] 1-7 spare.

[0271] Function Code (FC) 614: This field (e.g., bit positions 56-63) contains the function code. Examples of function codes assigned to neural network processing support instructions are shown in Figure 6C. All other function codes are unassigned. If an unassigned or uninstalled function code is specified, a response code of, for example, hexadecimal 0002 and a selected condition code (e.g., 1) are set. This field is not changed during execution.

[0272] In addition to general register 0, as shown, neural network processing support instructions also use general register 1, an example of which is shown in Figure 6D. For example, bits 40 through 63 in 24-bit addressing mode, bits 33 through 63 in 31-bit addressing mode, or bits 0 through 63 in 64-bit addressing mode contain the address 620 of the parameter block. The contents of general register 1 specify, for example, the logical address of the leftmost byte of the parameter block in storage. The parameter block must be specified on a doubleword boundary; otherwise, a specification exception is recognized. For all functions, the contents of general register 1 are unchanged.

[0273] In access register mode, for example, access register 1 specifies the address space containing the parameter block, input tensors, output tensors, and function-specific storage areas.

[0274] In one example, the parameter blocks may have different formats depending on the function specified by the instruction being executed. For example, a query function may include a parameter block of one format, while other functions of the instruction may include a parameter block of another format. In another example, all functions use the same parameter block format. Other variations are possible.

[0275] By way of example, the parameter blocks and / or the information within the parameter blocks may be stored in memory, hardware registers, and / or a combination of memory and / or registers. Other examples are possible.

[0276] One example of a parameter block used by a query function, such as a query for NNPA-available capabilities (QAF) operation, is described with reference to Figure 6E. As shown in the figure, in one example, a query for NNPA-available capabilities parameter block 630 includes, for example:

[0277] Installed Feature Vector 632: This field (e.g., bytes 0-31) of the parameter block contains the installed feature vector. In one example, bits 0-255 of the installed feature vector correspond to function codes 0-255 of the neural network processing assistance instructions, respectively. If a bit is, for example, 1, the corresponding feature is installed; otherwise, the feature is not installed.

[0278] Installed Parameter Block Type Vector 634: This field (e.g., bytes 32-47) of the parameter block contains the installed parameter block type vector. In one example, bits 0-127 of the installed parameter block type vector correspond to parameter block types 0-127 of the non-query function of the neural network processing assistance command. If a bit is, for example, 1, the corresponding parameter block type is installed; otherwise, the parameter block type is not installed.

[0279] Installed Data Types 636: This field of the parameter block (e.g., bytes 48-49) contains an installed data type vector. In one example, bits 0-15 of the installed data type vector correspond to installed data types. If a bit is, for example, 1, the corresponding data type is installed; otherwise, the data type is not installed. Examples of data types include the following (additional, fewer, or other data types, or combinations thereof, are possible):

[0280] Bit Data Type

[0281] 0 NNP data type 1

[0282] 1 NNP data type 2

[0283] 2~15 Reserve

[0284] Installed Data Layout Formats 638: This field (e.g., bytes 52-55) of the parameter block contains an installed data layout format vector. In one example, bits 0-31 of the installed data layout format vector correspond to installed data layout formats. If a bit is, for example, 1, the corresponding data layout format is installed; otherwise, the data layout format is not installed. Examples of data layout formats include the following (additional, fewer, or other data layout formats, or combinations thereof, are possible):

[0285] Bit Data Layout Format

[0286] 0 4D feature tensor

[0287] 1. 4D Kernel Tensor

[0288] 2~31 Reserve

[0289] Maximum Dimension Index Size 640: This field of the parameter block (e.g., bytes 60-63) contains a 32-bit unsigned binary integer that specifies, for example, the maximum number of elements in the specified dimension index size of any specified tensor. In another example, the maximum dimension index size specifies the maximum number of bytes in the specified dimension index size of any specified tensor. Other examples are possible.

[0290] Maximum Tensor Size 642: This field of the parameter block (e.g., bytes 64 through 71) contains a 32-bit unsigned binary integer that specifies the maximum number of bytes in any specified tensor, including any pad bytes required by the tensor format, for example. In another example, the maximum tensor size specifies the maximum number of total elements in any specified tensor, including any padding required by the tensor format. Other examples are possible.

[0291] Installed NNP Data Type 1 Conversion Vector 644: This field of the parameter block (e.g., bytes 72-73) contains the installed NNP Data Type 1 Conversion Vector. In one example, bits 0-15 of the installed NNP Data Type 1 Conversion Vector correspond to installed data type conversions to and from the NNP Data Type 1 format. If a bit is 1, the corresponding conversion is installed; otherwise, the conversion is not installed. Additional conversions, fewer conversions, or other conversions, or a combination thereof, may be specified.

[0292] Bit Data Type

[0293] 0 Reserve

[0294] 1 BFP small quantity format

[0295] 2 BFP short form

[0296] 3~15 Reserve

[0297] In one or more embodiments, an installed NNP data type translation vector is added to the query parameter block for each supported machine-specific data type. For example, in one example, an installed NNP data type 2 translation vector is provided for NNP data type 2. Other variations are possible.

[0298] While one example of a query function parameter block is described with reference to Figure 6E, other formats of the query function parameter block may be used, including query operations for NNPA-enabled functions. The format may depend, in one example, on the type of query function being performed. Furthermore, the parameter block and / or individual fields of the parameter block may contain additional information, less information, other information, or combinations thereof.

[0299] In addition to the parameter block for query functions, in one example, there is a parameter block format for non-query functions, such as the non-query function of a neural network processing assistance instruction. One example of a parameter block used by a non-query function, such as the non-query function of a neural network processing assistance instruction, is described with reference to FIG. 6F.

[0300] As shown in the figure, in one example, a parameter block 650 used by, for example, a non-query function of a neural network processing assistance instruction may include, for example:

[0301] Parameter Block Version Number 652: This field of the parameter block (e.g., bytes 0-1) specifies the version and size of the parameter block. In one example, bits 0-8 of the parameter block version number are reserved and contain 0, and bits 9-15 of the parameter block version number contain an unsigned binary integer that specifies the parameter block format. The query function provides a mechanism to indicate available parameter block formats. If the specified parameter block size or format is not supported by the model, a response code, e.g., hex 0001, is stored in general register 0 and the instruction is completed by setting a condition code (e.g., condition code 1). The parameter block version number is specified by the program and does not change during instruction execution.

[0302] Model Version Number 654: This field (e.g., byte 2) of the parameter block is an unsigned binary integer that identifies the model that executed the command (e.g., a particular non-query function). If the Continue Flag (described below) is 1, the model version number may be input to the operation for the purpose of interpreting the contents of the Continue Status Buffer field (described below) of the parameter block and resuming the operation.

[0303] Continuation flag 656: This field (e.g., bit 63) of the parameter block, when set to 1, indicates that the operation is partially completed and the contents of the continuation state buffer may be used to resume the operation. Programs should initialize the continuation flag to 0 and not change it if instructions are re-executed with the intent of resuming the operation; otherwise, results will be unpredictable.

[0304] If the continue flag is set at the start of the operation and the contents of the parameter block have changed since the initial call, the results will be unpredictable.

[0305] Function-specific save area address 658: This field of the parameter block (e.g., bytes 56-63) contains the logical address of the function-specific save area. In one example, the function-specific save area address should be aligned on a 4K byte boundary; if not, a response code of, for example, hex 0015 is set in general register 0, and the instruction completes with a condition code of, for example, 1. This address is affected by the current addressing mode. The size of the function-specific save area depends on the function code.

[0306] If the entire function-specific save area overlaps with a program event recording (PER) storage area specification, a PER storage change event is recognized, if applicable, for the function-specific save area. If only a portion of the function-specific save area overlaps with a PER storage area specification, which of the following occurs is model-dependent:

[0307] *PER storage alteration events are recognized, where applicable, for the entire function-specific save area.

[0308] *PER storage change events are recognized, where applicable, for some of the saved areas specific to the stored function.

[0309] If an entire parameter block overlaps with a PER storage region specification, a PER storage change event is recognized, if applicable, for the parameter block. If only part of a parameter block overlaps with a PER storage region specification, which of the following occurs is model-dependent:

[0310] *PER storage change events are recognized, if applicable, for the entire parameter block.

[0311] *PER storage change events are recognized, if applicable, for portions of the stored parameter block.

[0312] PER zero address detection events are recognized when applicable for parameter blocks. Zero address detection does not apply to tensor addresses or function-specific storage addresses, for example.

[0313] Output tensor descriptor (e.g., 1-2) 660 / Input tensor descriptor (e.g., 1-3) 665: One example of tensor descriptors is described with reference to Figure 6G. In one example, tensor descriptors 660, 665 include:

[0314] Data Layout Format 682: This field (e.g., byte 0) of the tensor descriptor specifies the data layout format. Valid data layout formats include, for example, the following (additional, fewer, or other data layout formats, or combinations thereof, are possible):

[0315] Format Description Alignment (bytes)

[0316] 0 4D feature tensor 4096

[0317] 1 4D kernel tensor 4096

[0318] 2~255 Reserve --

[0319] If an unsupported or reserved data layout format is specified, a response code, e.g., hex 0010, is stored in general register 0 and the instruction is completed by, e.g., setting condition code 1.

[0320] Data Type 684: This field (e.g., byte 1) specifies the data type of the tensor. Examples of supported data types are described below (additional, fewer, or other data types, or combinations thereof, are possible).

[0321] Value Data Type Data Size (bits)

[0322] 0 NNP data type 1 16

[0323] 1 NNP data type 2 16

[0324] 2~255 Reserve --

[0325] If an unsupported or reserved data type is specified, a response code, for example hex 0011, is stored in general register 0 and the instruction is completed, for example, by setting a condition code of 1.

[0326] Dimension 1-4 Index Size 686: Collectively, dimension index sizes 1-4 specify the shape of a 4D tensor. Each dimension index size should be greater than 0 and less than or equal to the maximum dimension index size (640 in FIG. 6E); if not, a response code, e.g., hex 0012, is stored in general register 0 and the instruction completes, e.g., by setting condition code 1. The total tensor size should be less than or equal to the maximum tensor size (642 in FIG. 6E); if not, a response code, e.g., hex 0013, is stored in general register 0 and the instruction completes, e.g., by setting condition code 1.

[0327] In one example, to determine the number of 4D feature tensors containing elements of NNP data type 1 (i.e., total tensor size), the following is used: dimension index 4 * dimension index 3 * ceil(dimension index 2 / 32) * 32 * ceil(dimension index 1 / 64) * 64 * 2.

[0328] Tensor Address 688: This field of the tensor descriptor (e.g., bytes 24-31) contains the logical address of the leftmost byte of the tensor. This address is affected by the current addressing mode.

[0329] If this address is not aligned to the boundary of the relevant data layout format, a response code, e.g. hex 0014, is stored in general register 0 and the instruction is completed, e.g. by setting condition code 1.

[0330] In access register mode, access register 1 specifies the address space containing all active input and output tensors in storage.

[0331] Returning to Figure 6F, parameter block 650, in one example, further includes function-specific parameters 1-5 (670) that may be used by a particular function. Additionally, parameter block 650, in one example, includes a continuation state buffer field 675, which contains data (or the location of data) to be used if operation of this instruction is resumed.

[0332] As input to an operation, the reserved field of the parameter block should contain 0. When the operation completes, the reserved field may be filled with 0 or may remain unchanged.

[0333] Although one example of a non-query function parameter block is described with reference to FIG. 6F, other formats of the non-query function parameter block may be used, including non-query functions of neural network processing assistance instructions. The format may depend, in one example, on the type of function being performed. Furthermore, although one example of a tensor descriptor is described with reference to FIG. 6G, other formats may be used. Furthermore, different formats for the input tensor and output tensor may be used. Other variations are possible.

[0334] Below, further details regarding one or more functions supported by one embodiment of the neural network processing assistance instructions are provided.

[0335] Function code 0: NNPA-QAF (Query available functions)

[0336] The Neural Network Processing Assist (NNPA) query function provides a mechanism for indicating selected information, such as installed features, installed parameter block formats, installed data types, installed data layout formats, maximum dimension index size, and maximum tensor size availability. This information is retrieved and placed in a selected location, such as a parameter block (e.g., parameter block 630). When an operation terminates, the reserved fields of the parameter block may be filled with zeros or may remain unchanged.

[0337] In one embodiment of the query function, a processor, such as general-purpose processor 13, obtains information related to a particular model of a selected processor, such as a particular model of a neural network processor, such as neural network processor 31. The obtained information is placed in a parameter block (e.g., parameter block 630) or other structure that is accessible by and / or for use by one or more applications that may use the information for further processing. In one example, the parameter block and / or the information in the parameter block are maintained in memory. In other embodiments, the parameter block and / or the information may be maintained in one or more hardware registers. In another example, the query function may be a privileged operation performed by an operating system, which enables an application programming interface to make the information available to applications or non-privileged programs. In a further example, the query function is performed by a dedicated processor, such as neural network processor 31. Other variations are possible.

[0338] This information is obtained, for example, by firmware of the processor executing the query function. The firmware has knowledge of the attributes of the particular model of the particular processor (e.g., neural network processor). This information may be stored, for example, in a control block, register, or memory, or a combination thereof, and / or may be otherwise accessible by the processor executing the query function.

[0339] For example, the retrieved information may include detailed model-dependent information regarding at least one or more data attributes of a particular processor, including, for example, one or more installed or supported data types, one or more installed or supported data layout formats, or one or more installed or supported data sizes, or a combination thereof, of a selected model of the particular processor. This information is model-dependent in that other models (e.g., prior models and / or future models) may not support the same data attributes, such as the same data types, data sizes, or data layout formats, or a combination thereof. Illustratively, condition code 0 is set when execution of a query function (e.g., an NNPA-QAF function) is completed. In one example, condition codes 1, 2, and 3 are not applicable to the query function. Details related to the retrieved information are described below.

[0340] In one example, the query function obtains an indication of the data types installed on the model-dependent processor and places this indication in the parameter block, for example, by setting one or more bits in the installed data types field 636 of the parameter block 630. Exemplary data types that may be installed are the NNP Data Type 1 data type and the NNP Data Type 2 data type, examples of which are described above. Additional, fewer, or other data types, or combinations thereof, may be installed. Supported data types may have one or more assigned bits in the query parameter block (e.g., in the installed data types field 636). For example, machine-specific or non-standard data types supported by a particular processor are indicated in the installed data types field, but standard data types are not. In other embodiments, one or more standard data types are also indicated. Other variations are possible.

[0341] In one particular example, bit 0 of installed data types field 636 is reserved for the NNP Data Type 1 data type, e.g., when set to 1, indicating that the processor supports NNP Data Type 1, and bit 1 is reserved for NNP Data Type 2, e.g., when set to 1, indicating that the processor supports NNP Data Type 2. By way of example, the installed data types bit vector is configured to represent up to 16 data types, with a bit in the bit vector assigned to each data type. However, in other embodiments, the bit vector may support more or fewer data types. Furthermore, vectors may be configured in which one or more bits within are assigned to data types. Many examples are possible, and / or additional, fewer, or other data types, or combinations thereof, may be supported and / or indicated within the vector.

[0342] Additionally, in one example, the query function obtains an indication of an installed data layout format (another data attribute) and places this information in the parameter block, e.g., by setting one or more bits in the installed data layout format field 638. Examples of data layout formats include, for example, a 4D feature tensor layout and a 4D kernel tensor layout. In one example, a 4D feature tensor layout is used by the functions described herein, and in one example, a convolution function uses a 4D kernel tensor layout. These data layout formats arrange tensor data for storage in a manner that improves processing efficiency in the execution of the functions of the neural network processing assistance instructions. For example, to operate efficiently, the neural network processing assistance instructions use input tensors provided in a particular data layout format. While example layouts are provided, additional, fewer, or other layouts, or combinations thereof, may be provided for the functions described herein or other functions.

[0343] The use or availability of layouts for a particular processor model is realized by an installed data layout format vector (e.g., field 638 of parameter block 630). This vector is, for example, an installed data layout format bit vector that allows the CPU to communicate which layouts are supported to an application. For example, bit 0 is reserved for the 4D feature tensor layout and, when set to 1, indicates that the processor supports the 4D feature tensor layout. Bit 1 is reserved for the 4D kernel tensor layout and, when set to 1, indicates that the processor supports the 4D kernel tensor layout. In one example, the installed data layout format bit vector is configured to represent up to 16 data layouts, with a bit in the bit vector assigned to each data layout. However, in other embodiments, the bit vector may support more or fewer data layouts. Furthermore, a vector may be configured in which one or more bits are assigned to a data layout. Many examples are possible. Further details regarding 4D feature tensor layouts and 4D kernel tensor layouts are provided below. Again, other layouts may be used now or in the future to optimize performance.

[0344] In one example, neural network processing assistance instructions operate using 4D tensors (i.e., tensors with four dimensions). These 4D tensors are obtained from the general input tensors described herein, e.g., row-major, i.e., when enumerating tensor elements in increasing memory address order, the inner dimension, called E1, is first incremented by the E1 index size value, starting from 0 to E1 index size 1, then the index of the E2 dimension is incremented, and so on through the E1 dimension. The index of the outer dimension, called E4 dimension, is incremented last.

[0345] A tensor with a fewer number of dimensions (e.g., a 3D tensor or a 1D tensor) is represented as a 4D tensor with one or more dimensions of the 4D tensor beyond the dimensions of the original tensor set to 1.

[0346] The conversion of a row-major general 4D tensor with dimensions E4, E3, E2, E1 to a 4D feature tensor layout (also referred to herein as an NNPA data layout format 0 4D feature tensor) is described herein.

[0347] For example, the resulting tensor can be represented as a 4D tensor, e.g., a 64 element vector, or a 5D tensor with the following dimensions:

[0348] E4,

number

number

number

[0349] The elements [e4][e3][e2][e1] of the general tensor may be mapped to the next elements of the resulting 5D tensor.

[0350]

number

number

number

number

number

[0351] The resulting tensor may be larger than the general tensor. Elements of the resulting tensor that have no corresponding elements in the general tensor are called pad elements.

[0352] Consider an element [fe4][fe1][fe3][fe2][fe0] of a 4D feature tensor in NNPA data layout format 0, which is a 64-element vector, or an equivalent representation as a 5D tensor. This element is a pad element, or the corresponding element in a general 4D tensor with dimensions E4, E3, E2, E1 can be determined using the following formula:

[0353] If fe2 ≥ E2, this element is a pad element of E2 (or page)

[0354] Otherwise, if fe1*64+fe0≧E1, then this element is a pad element for E1 (or row).

[0355] Otherwise, the corresponding elements in a general 4D tensor are:

[0356] [fe4][fe3][fe2][fe1*64+fe0]

[0357] For artificial intelligence models based on convolutional neural networks, the meaning of the four dimensions of a feature tensor can usually be mapped to the following:

[0358] E4:N - minibatch size

[0359] E3: H-3D tensor / image height

[0360] E2:W - 3D tensor / image width

[0361] E1:C - Channel or class of a 3D tensor

[0362] For artificial intelligence models based on machine learning or recurrent neural networks, the meaning of the four dimensions of a 4D feature tensor may usually be mapped to:

[0363] E4:T - number of time steps or models

[0364] E3: Reserved, normally set to 1

[0365] E2:N mb -Minibatch size

[0366] E1:L-Features

[0367] NNPA data layout format 0, for example, provides 2-dimensional data locality with 4k-byte blocks of data (pages) in addition to 4k-byte block data alignment in the outer dimensions of the generated tensors.

[0368] Pad element bytes are ignored for input tensors and unpredictable for output tensors. PER storage changes to pad bytes are unpredictable.

[0369] An example of an input data layout for a 4D feature tensor layout having dimensions E1, E2, E3, and E4 is shown in FIGS. 7(A)-7(C), and an example output of the 4D feature tensor layout is shown in FIGS. 8(A)-8(C). Referring to FIG. 7(A), a 3D tensor 700 is shown having dimensions E1, E2, and E3. In one example, each 3D tensor includes multiple 2D tensors 702. The numbers within each 2D tensor 702 represent the memory offsets where each of the elements resides in memory. These inputs are used to layout the data of the original tensor (e.g., the original 4D tensor of FIGS. 7(A)-7(C)) in memory as shown in FIGS. 8(A)-8(C), which correspond to FIGS. 7(A)-7(C).

[0370] In FIG. 8A, for example, a unit of memory 800 (e.g., a memory page) includes a preselected number (e.g., 32) of rows 802, each identified by, for example, e2_page_idx, and each row includes a preselected number (e.g., 64) of elements 804, each identified by, for example, e1_page_idx. If a row does not include the preselected number of elements, the row is padded (806), referred to as row padding or E1 padding. If the unit of memory does not include the preselected number of rows, the unit of memory is padded (808), referred to as page padding or E2 padding. For example, row padding may be a prespecified value, such as 0, space, or another value, and page padding may be unpredictable data, an existing value, 0, an arbitrary value, etc.

[0371] In one example, output elements for a row are provided in memory (e.g., within a page) based on the element position in the E1 direction of the corresponding input. For example, referring to FIG. 7(A), element positions 0, 1, and 2 (e.g., element positions at the same position within each matrix) of the three illustrated matrices are shown in row 0 of page 0 in FIG. 8(A), etc. In this example, the 4D tensor is small, and all of the elements of each 2D tensor representing the 4D tensor fit on one page. However, this is just one example. A 2D tensor may include one or more pages. If a 2D tensor is created based on reformatting a 4D tensor, the number of pages for the 2D tensor is based on the size of the 4D tensor. In one example, one or more ceil functions are used to determine the number of rows in the 2D tensor and the number of elements in each row, which indicates the number of pages to be used. Other variations are possible.

[0372] In addition to the 4D feature tensor layout, in one example, a neural network processor may support a 4D kernel tensor layout, which rearranges the elements of a 4D tensor to reduce the number of memory accesses and data collection steps when performing certain artificial intelligence (e.g., neural network processing aids) operations such as convolution. By way of example, as described herein, a row-major general 4D tensor with dimensions E4, E3, E2, and E1 is converted to a 4D kernel tensor (4D kernel tensor) in NNPA data layout format 1.

[0373] The resulting tensor can be represented as a 4D tensor, for example a 64 element vector, or as a 5D tensor with the following dimensions:

[0374]

number

number

number

[0375] The elements [e4][e3][e2][e1] of the general tensor may be mapped to the next elements of the resulting 5D tensor.

[0376]

number

number

number

number

number

[0377] The resulting tensor may be larger than the general tensor. Elements of the resulting tensor that have no corresponding elements in the general tensor are called pad elements.

[0378] Consider an element [fe1][fe4][fe3][fe2][fe0] of a 4D feature tensor in NNPA data layout format 1, which is a 64-element vector, or an equivalent representation as a 5D tensor. This element is a pad element, or the corresponding element in a general 4D tensor with dimensions E4, E3, E2, E1 can be determined using the following formula:

[0379] If fe2 ≥ E2, this element is a pad element of E2 (or page)

[0380] Otherwise, if fe1*64+fe0≧E1, then this element is a pad element for E1 (or row).

[0381] Otherwise, the corresponding elements in a general 4D tensor are:

[0382] [fe4][fe3][fe2][fe1*64+fe0]

[0383] For artificial intelligence models based on convolutional neural networks, the meaning of the four dimensions of the kernel tensor can usually be mapped to the following:

[0384] E4: H-3D tensor / image height

[0385] E3:W - 3D tensor / image width

[0386] E2: Number of channels in the C-3D tensor

[0387] E1: K - Number of kernels

[0388] NNPA Data Layout Format 1, for example, provides for parallelism of 2D kernels within 4k-byte blocks of data (pages), in addition to alignment of 4k-byte blocks of data in the outer dimensions of generated tensors for efficient processing.

[0389] Pad bytes are ignored for input tensors. PER storage changes to pad bytes are unpredictable.

[0390] Again, exemplary data layout formats include a 4D feature tensor layout and a 4D kernel tensor layout, although other data layout formats may be supported by a processor (e.g., neural network processor 31). An indication of the supported data layouts is obtained and placed in the query parameter block, for example, by setting one or more bits in field 638.

[0391] The query parameter block also includes other data attribute information, including, for example, information about the supported sizes of data, in accordance with one or more aspects of the present invention. Processors, such as neural network processors, typically have limitations based on internal buffer sizes, processing unit, data bus structure, firmware limitations, etc., that may limit the maximum size of a tensor dimension and / or the overall size of a tensor. Therefore, the query function provides fields for communicating these limitations to an application. For example, the processor may obtain various data sizes, such as the maximum dimension index size (e.g., 65,536 elements) and the maximum tensor size (e.g., 8 GB), based on executing the query function and include this information in fields 640 and 642, respectively, of the parameter block (e.g., parameter block 630). Additional, fewer, or other size information, or combinations thereof, may be supported by a processor (e.g., neural network processor 31) and thus may be obtained and placed in the parameter block (e.g., fields 640, 642, or other fields). In other embodiments, these limits may be smaller or larger, or the sizes may be in other units, such as bytes instead of elements, elements instead of bytes, etc. Additionally, other embodiments allow different maximum sizes for each dimension, rather than the same maximum for all dimensions. Many variations are possible.

[0392] In accordance with one or more aspects of the present invention, a query function is provided that conveys detailed information related to a particular model of a selected processor (e.g., neural network processor 31). The detailed information may include, for example, information dependent on the model associated with the particular processor (a processor may support standard data attributes, such as standard data types, standard data layouts, etc., which are implicit and not necessarily represented by the query function, although in other embodiments, the query function may indicate all or various selected subsets of the data attributes). While exemplary information is provided, other information may be provided in other embodiments. The obtained information, which may vary for different models of a single processor and / or different processors, is used to perform artificial intelligence and / or other processing. The artificial intelligence and / or other processing may use, for example, one or more non-query functions of the neural network processing assistance instructions. The specific non-query functions used in the processing are implemented by executing the neural network processing assistance instructions one or more times and specifying the specific non-query functions.

[0393] As indicated by the query function, exemplary non-query functions supported by the neural network processing support instructions include NNPA-ADD (addition), NNPA-SUB (subtraction), NNPA-MUL (multiplication), NNPA-DIV (division), NNPA-MIN (minimum), NNPA-MAX (maximum), NNPA-LOG (logarithm), NNPA-EXP (exponential), NNPA-RELU (rectified linear unit), NNPA-TANH, NNPA-SIGMOID, NNPA-SOFTMAX, NNPA-BATCH-NORM (batch normalization), NNPA-MAXPOOL2D, NNPA-AVGPOOL2D, NNPA-LSTMACT (long short-term memory activation), NNPA-GRUACT (gated recurrent unit activation), NNPA-CONVOLUTION, NNPA-MATMUL-OP (matrix multiplication operation), and NNPA-MATMUL-OP-BCAST23 (matrix multiplication operation broadcast23). Additional, fewer, or other features, or combinations thereof, may be supported.

[0394] One or more of the functions are performed by a processor, such as neural network processor 31. For example, neural network processing support instructions specifying a particular function to be performed are initiated by a general-purpose processor (e.g., processor 13). If the function specified by the instruction is a non-query function, information is provided by the general-purpose processor to the neural network processor (e.g., neural network processor 31) to enable the neural network processor to perform this function. This information includes, for example, instructions for the function to be performed and / or one or more addresses of input data (e.g., input tensor data) for the function. In one example, the input data has been converted from a standard format, such as binary floating-point format, to a non-standard format, such as a machine-specific format (e.g., NNP data type 1 or NNP data type 2) used by neural network processor 31. The function is performed using the input data to generate output data (e.g., output tensor data) in the machine-specific format. The data (or the location of the data) is then provided to another processor (e.g., general-purpose processor 13) for conversion back to a standard format. The output data in a standard format may then be used in other processes. In other examples, the instructions may be initiated, executed, and completed on one or more general-purpose processors or one or more special-purpose processors. Other variations are possible.

[0395] Further details are provided below regarding exemplary non-query functions supported by the neural network processing instructions and executed, for example, by neural network processor 31 (although in other embodiments additional, fewer, or other functions, or combinations thereof, may be supported).

[0396] Function code 16: NNPA-ADD (addition)

[0397] If the NNPA-ADD function is specified, each element of input tensor 1, described by tensor descriptor 1, is added to the corresponding element of input tensor 2, described by tensor descriptor 2, and the resulting sum is placed in the corresponding element of the output tensor, described by output tensor descriptor.

[0398] In one example, if the data layout specified in any of the specified tensor descriptors does not specify a 4D feature tensor (e.g., data_layout = 0), or if the data type in any of the specified tensor descriptors does not specify an NNP data type 1 (e.g., data_type = 0), a response code (e.g., hex 0010 or hex 0011) is set in general register 0, respectively, and the instruction completes, e.g., with a condition code of 1.

[0399] In one example, the shape, data layout, and data type of input tensor1, input tensor2, and output tensor should be the same; if not, a general operand-data exception is recognized.

[0400] In one example, the output tensor descriptor 2, input tensor descriptor 3, function-specific parameters 1-5, and function-specific storage address fields are ignored.

[0401] The NNPA-ADD function is provided as an example, although other and / or additional functions may be specified as described herein.

[0402] For neural network processing aided instructions, in one embodiment, results become unpredictable if the output tensor overlaps with any of the input tensors or parameter blocks.

[0403] For example, if an attempt is made to execute a neural network processing instruction and the parameter block is not specified on a double-word boundary, for example, a specification exception is recognized.

[0404] When an attempt is made to execute a neural network processing instruction and, for example, there is an inconsistency in the tensor descriptors, a general operand-data exception is recognized.

[0405] Condition codes resulting from neural network processing assistance instructions include, for example, 0 - successful completion, 1 - response code is set, 2 - the amount of processed data determined by the CPU, and 3 - the amount of processed data.

[0406] In one embodiment, the priority of execution of neural network processing assistance instructions includes, for example:

[0407] 1.~7. Exceptions with the same priority as the program interrupt condition for the general case.

[0408] 8.A Condition code 1 caused by specifying a feature code that is not assigned or installed.

[0409] 8.B Specification exception caused by parameter block not being specified on a double-word boundary.

[0410] 9. Access exception regarding access to parameter block.

[0411] 10. Condition code 1 caused by the specified format of the parameter block not being supported by the model.

[0412] 11.A Condition code 1 caused by the specified tensor data layout being unsupported.

[0413] 11.B General operand data exception due to different data layouts between tensor descriptors.

[0414] 12.A Condition Code 1 resulting from conditions other than those contained in Items 8.A, 10, and 11.A above and 12.B.1 below.

[0415] 12.B.1 Condition code 1 due to invalid output tensor data type for NNPA-RELU and NNPA-CONVOLUTION.

[0416] 12.B.2 General Operand Data Exception for invalid values ​​of parameter 1 specific to the NNPA-RELU function and parameter 4 specific to the NNPA-CONVOLUTION function.

[0417] 13.A Access exception on accessing output tensor.

[0418] 13.B Access exception on accessing input tensors.

[0419] 13.C Access Exception for Access to Function-Specific Storage Areas.

[0420] 14. Condition code 0.

[0421] As described herein, in one or more aspects, the ability to perform conversions to and from machine-native data types is provided, where the specific machine-native data types have assigned rounding modes such that the rounding modes are not selectable, facilitating conversion and processing.

[0422] In one example, a machine-specific data type is a data type optimized for use by a particular processor running on a particular hardware machine. For example, a machine-specific data type may be able to maintain extended precision and / or be easier to implement on the machine. Examples of machine-specific data types are the NNP data type 1 and NNP data type 2 data types that may be used by a model of a neural network processor. For example, neural network processing support instructions operate on selected machine-specific data types (also called internal data types) to represent input / output data for greater efficiency. Therefore, the input / output data is converted from a standard format (e.g., IEEE 754 binary floating point) to a selected machine-specific format (e.g., NNP data type 1, NNP data type 2, etc.) that is usable by the machine. Machine-specific data types may vary from machine model to machine model to optimize for new and / or other processor architectures. Therefore, there may be multiple NNP data types (e.g., NNP data type 1 through NNP data type x) and / or other machine-specific data types.

[0423] One or more aspects of the present invention are closely related to computer technology and facilitate processing in computers and improve their performance. In one or more aspects, a transformation operation that facilitates data transformation, including a transformation operation that performs rounding, is provided, improving system performance and reducing system resource usage. The transformed data, rounded data, or both, instructions used to perform the transformation operation, or instructions for using the data, or a combination thereof, may be used in many technical fields, such as computer processing, medical informatics, design, automotive technology, and manufacturing. By implementing optimizations in the transformation and / or rounding of the transformation operation, these technical fields are improved, for example, by reducing execution time.

[0424] Further details of one or more embodiments that facilitate processing within a computing environment as it relates to one or more aspects of the present invention are described with reference to Figures 9A-9B.

[0425] Referring to FIG. 9A, an instruction for converting data from a source data type to a target data type is obtained (900). The source data type is selected from one or more source data types supported by the instruction (902), and the target data type is selected from one or more target data types supported by the instruction (904). A determination of a rounding mode to use by the instruction is made (906) based on the selected one of the source data type and the target data type. The rounding mode is implicitly set (908) based on the selected data type and assigned to the selected data type (910). A conversion of the data from the source data type to the target data type is performed (912). This conversion includes performing a rounding operation using the rounding mode implicitly set based on the selected data type (914). Performing this conversion produces a result in the target data type (916). The result is written to the selected location (918).

[0426] By providing implicit rounding modes assigned to specific data types, the conversion process is simplified, and by limiting the supported rounding modes, processing speed can be improved. This also makes it easier to write program code to convert data for use on selected processors, such as coprocessors. Furthermore, by providing selectable source and / or target data types, a reduced number of conversion instructions can be used, saving opcode space and simplifying instruction decoding and software implementation for execution on accelerators.

[0427] In one example, the selected data type is a target data type specified using an instruction (920). The target data type is, for example, a machine-specific data type specified using an instruction (922). The machine-specific data type is, for example, a neural network processing data type 1 data type (924). For example, the rounding mode assigned to the neural network processing data type 1 data type is, for example, round to nearest value away from zero (926). Further, in one example, the source data type is a standard data type specified using an instruction (928).

[0428] By providing implicitly set rounding modes assigned to specific data types, such as machine-specified data types, the conversion process is simplified, and by limiting the rounding modes supported, processing speed can be improved. Efficiency is gained, complexity is reduced, and system performance is improved. Conversion performance is improved, improving system performance and data availability.

[0429] In another example, referring to FIG. 9B , the selected data type is a source data type specified using an instruction (930). The source data type is, for example, a machine-specific data type specified using an instruction (932). The machine-specific data type, in one example, is a neural network processing data type 1 data type (934). As an example, the rounding mode assigned to the neural network processing data type 1 data type is, for example, round to nearest value away from zero (936). Further, in one example, the target data type is a standard data type specified using an instruction (938).

[0430] For example, the data to be converted includes source data in a source data type (940), which includes a concatenation of data in one register specified using one field of the instruction and other data in another register specified using another field of the instruction (942). Performing the conversion includes, for example, rounding the source data based on a rounding mode to provide rounded data (944), and converting the rounded data to provide a result in the target data type (946).

[0431] As another example, the data to be converted includes source data in a source data type obtained using the instruction 950. Performing the conversion includes, for example, rounding the source data based on a rounding mode to provide rounded data with the numeric precision of the target data type 952, and converting the rounded data to provide a result in the target data type 954.

[0432] Other variations and embodiments are possible.

[0433] Aspects of the present invention may be used with many types of computing environments. Another example of a computing environment for incorporating and using one or more aspects of the present invention is described with reference to FIG. 10. By way of example, the computing environment of FIG. 10 is based on the z / Architecture® instruction set architecture offered by International Business Machines Corporation (Armonk, New York). However, the z / Architecture instruction set architecture is only one exemplary architecture. Additionally, computing environments may be based on other architectures, including, but not limited to, the Intel® x86 architecture, other architectures from International Business Machines Corporation, or other architectures from other companies, or combinations thereof. Intel is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.

[0434] 10, in one example, a computing environment 1000 includes a computer system 1002, shown, for example, in the form of a general-purpose computing device. The computer system 1002 may include, but is not limited to, one or more general-purpose processors or processing units 1004 (e.g., central processing units (CPUs)), at least one special-purpose processor such as a neural network processor 1005, coupled to each other via one or more buses and / or other connections, memory 1006 (e.g., also known as system memory, main memory, primary storage, central storage, or storage), and one or more input / output (I / O) interfaces 1008. For example, the processors 1004, 1005 and memory 1006 are coupled to the I / O interface 1008 via one or more buses 1010, and the processors 1004, 1005 are coupled to each other via one or more buses 1011.

[0435] Bus 1011 may be, for example, a memory or cache coherence bus, and bus 1010 may represent any one or more of several types of bus structures, including, for example, a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures. By way of example, such architectures include, but are not limited to, Industry Standard Architecture (ISA), Micro Channel Architecture (MCA), Enhanced ISA (EISA), Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnects (PCI).

[0436] As an example, one or more special-purpose processors (e.g., neural network processors) may be separate from but coupled to one or more general-purpose processors, or may be incorporated within one or more general-purpose processors, or both. Many variations are possible.

[0437] For example, memory 1006 may include a cache 1012, such as a shared cache, that may be coupled to a local cache 1014 of processor 1004 and / or neural network processor 1005, e.g., via one or more buses 1011. Further, memory 1006 may include one or more programs or applications 1016 and at least one operating system 1018. Exemplary operating systems include the z / OS® operating system offered by International Business Machines Corporation (Armonk, New York). Other operating systems offered by International Business Machines Corporation and / or other entities may also be used. Memory 1006 may include one or more computer-readable program instructions 1020 that may be configured to perform functions of embodiments of aspects of the present invention.

[0438] The computer system 1002 may communicate with one or more external devices 1030, such as a user terminal, a tape drive, a pointing device, a display, and one or more data storage devices 1034, for example, via an I / O interface 1008. The data storage devices 1034 may store one or more programs 1036, one or more computer-readable program instructions 1038, or data, or a combination thereof. The computer-readable program instructions may be configured to perform the functions of embodiments of aspects of the present invention.

[0439] The computer system 1002 may communicate, for example, via the I / O interface 1008, with a network interface 1032 that enables the computer system 1002 to communicate with one or more networks, such as a local area network (LAN), a general wide area network (WAN), or a public network (e.g., the Internet), or a combination thereof, to facilitate communication with other computing devices or systems.

[0440] Computer system 1002 may include and / or be coupled to removable / non-removable, volatile / non-volatile computer system storage media. For example, computer system 1002 may include and / or be coupled to non-removable, non-volatile magnetic media (commonly referred to as a "hard drive"), a magnetic disk drive for reading from and writing to removable, non-volatile magnetic disks (e.g., "floppy disks"), and / or an optical disk drive for reading from and writing to removable, non-volatile optical disks, such as CD-ROMs, DVD-ROMs, or other optical media. It should be understood that other hardware and / or software components may be used with computer system 1002, including, but not limited to, microcode or millicode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archive storage systems.

[0441] Computer system 1002 may operate in numerous other general-purpose or special-purpose computing system environments or configurations. Examples of well-known computing systems, environments, or configurations, or combinations thereof, that may be suitable for use with computer system 1002 include, but are not limited to, personal computer (PC) systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, microcomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of these systems or devices.

[0442] Another embodiment of a computing environment for incorporating and using one or more aspects of the present invention is described with reference to FIG. 11A. In this example, computing environment 36 includes a native central processing unit (CPU) 37, memory 38, and one or more input / output devices and / or interfaces 39, coupled together, for example, via one or more buses 40 or other connections. By way of example, computing environment 36 may include a PowerPC® processor offered by International Business Machines Corporation (Armonk, New York), an HP Superdome with an Intel® Itanium® II processor offered by Hewlett-Packard Company (Palo Alto, California), or other machines based on architectures offered by International Business Machines Corporation, Hewlett-Packard Company, Intel Corporation, Oracle Corporation, or other companies, or combinations thereof. PowerPC is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction. Itanium is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.

[0443] The native central processing unit 37 includes one or more native registers 41, such as one or more general purpose registers and / or one or more special purpose registers used during processing within the environment. These registers contain information that represents the state of the environment at any particular point in time.

[0444] Additionally, native central processing unit 37 executes instructions and code stored in memory 38. In one particular example, central processing unit executes emulator code 42 stored in memory 38. This code enables a computing environment configured with one architecture to emulate another architecture. For example, emulator code 42 enables machines based on architectures other than the z / Architecture instruction set architecture (e.g., PowerPC processors, HP Superdome servers, etc.) to emulate the z / Architecture instruction set architecture and execute software and instructions developed based on the z / Architecture instruction set architecture.

[0445] Further details related to emulator code 42 are described with reference to FIG. 11B . Guest instructions 43 stored in memory 38 include software instructions (e.g., correlated to machine instructions) developed to execute on an architecture other than that of native CPU 37. For example, guest instructions 43 may be designed to execute on a processor based on the z / Architecture instruction set architecture, but are instead emulated on native CPU 37, which may be, for example, an Intel Itanium II processor. In one example, emulator code 42 includes an instruction fetch routine 44 for retrieving one or more guest instructions 43 from memory 38 and, optionally, providing local buffering of the retrieved instructions. Emulator code 42 also includes an instruction conversion routine 45 for determining the type of the retrieved guest instruction and for converting the guest instruction into one or more corresponding native instructions 46. This conversion includes, for example, identifying a function performed by the guest instruction and selecting a native instruction to perform this function.

[0446] Additionally, emulator code 42 includes an emulation control routine 47 for causing execution of native instructions. Emulation control routine 47 may cause native CPU 37 to execute a routine of native instructions that emulates one or more already-fetched guest instructions, and upon completion of such execution, return control to an instruction fetch routine to emulate the fetch of the next guest instruction or group of guest instructions. Execution of native instructions 46 may include reading data from memory 38 into a register, storing data from a register back to memory, or performing some type of arithmetic or logical operation as determined by a translation routine.

[0447] For example, each routine is implemented in software that is stored in memory and executed by native central processing unit 37. In other examples, one or more of the routines or operations are implemented in firmware, hardware, software, or some combination thereof. The emulated processor's registers may be emulated using the native CPU's registers 41 or by using locations in memory 38. In an embodiment, guest instructions 43, native instructions 46, and emulator code 42 may reside in the same memory or may be distributed among different memory devices.

[0448] Exemplary instructions that may be emulated are vector floating point convert and expand high-level instructions from neural network processing, vector floating point convert and expand low-level instructions from neural network processing, vector floating point convert and round instructions to neural network processing, vector floating point convert instructions from neural network processing, vector floating point convert instructions to neural network processing, or neural network processing support instructions, or combinations thereof, as described herein in accordance with one or more aspects of the present invention.

[0449] The aforementioned computing environments are only examples of computing environments that can be used. Other environments may be used, including, but not limited to, non-partitioned, partitioned, cloud, or emulated environments, or combinations thereof, and embodiments are not limited to any one environment. Although various examples of computing environments are described herein, one or more aspects of the present invention may be used with many types of environments. The computing environments provided herein are only examples.

[0450] Each computing environment can be configured to include one or more aspects of the present invention.

[0451] One or more aspects may relate to cloud computing.

[0452] Although this disclosure includes detailed descriptions of cloud computing, it should be understood that implementation of the subject matter recited herein is not limited to cloud computing environments. Embodiments of the invention may be implemented in conjunction with any other type of computing environment now known or later developed.

[0453] Cloud computing is a service delivery model for enabling convenient, on-demand network access to a shared pool of configurable computational resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) and for rapidly provisioning and releasing these resources with minimal administrative effort or interaction with a service provider. This cloud model may include at least five characteristics, at least three service models, and at least four deployment models.

[0454] The features are as follows:

[0455] On-demand self-service: Cloud customers can unilaterally and automatically provision computing power, such as server time and network storage, as needed, without the need for human interaction with the service provider.

[0456] Broad network access: Capabilities are available over the network and can be accessed using standard mechanisms, facilitating use by heterogeneous thin-client or thick-client platforms (e.g., mobile phones, laptops, and PDAs).

[0457] Resource Pool: The provider's computing resources are pooled and offered to multiple consumers using a multi-tenant model, with various physical and virtual resources dynamically allocated and reallocated according to demand. There is a sense of location independence, where consumers typically have no control or knowledge regarding the exact location of the resources offered, although at a higher level of abstraction they may be able to specify a location (e.g., country, state, or data center).

[0458] Rapid Elasticity: Capacity is quickly and elastically provisioned, sometimes automatically, and can be quickly scaled out and quickly released to quickly scale in. Capacity available for provisioning often appears to consumers as unlimited, available for purchase in any quantity at any time.

[0459] Metered Services: Cloud systems leverage metering capabilities to automatically control and optimize resource usage at an abstraction level appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts). Resource usage can be monitored, controlled, and reported, providing transparency to both providers and consumers of the services used.

[0460] The service model is as follows:

[0461] SaaS (Software as a Service): The consumer is provided with the ability to use the provider's applications running on a cloud infrastructure. Those applications can be accessed from a variety of client devices through thin-client interfaces such as web browsers (e.g., web-based email). The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, storage, or individual application features, except for the possibility of setting limited user-specific application configuration settings.

[0462] PaaS (Platform as a Service): The ability offered to a consumer is to deploy applications they create or acquire, written using programming languages ​​and tools supported by the provider, onto a cloud infrastructure. The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, or storage, but does have control over the deployed applications and, in some cases, the configuration of the application hosting environment.

[0463] Infrastructure as a Service (IaaS): The capability provided to a consumer is the provisioning of processing, storage, network, and other basic computing resources, upon which the consumer can deploy and run any software, which may include operating systems and applications. The consumer does not manage or control the underlying cloud infrastructure, but does have control over the operating system, storage, deployed applications, and in some cases, limited control over selected network components (e.g., host firewalls).

[0464] The deployment model is as follows:

[0465] Private Cloud: This cloud infrastructure is operated solely for the organization, can be managed by the organization or a third party, and can reside on-premise or off-premise.

[0466] Community Cloud: This cloud infrastructure is shared by multiple organizations to support a specific community with shared interests (e.g., mission, security requirements, policy, and compliance considerations). It can be managed by these organizations or a third party and can reside on-premises or off-premises.

[0467] Public Cloud: This cloud infrastructure is available for use by the general public or large industry organizations and is owned by an organization that sells cloud services.

[0468] Hybrid cloud: This cloud infrastructure is a combination of two or more clouds (private, community, or public) that remain distinct but are joined together by standardized or proprietary technologies that allow for data and application portability (e.g., cloud bursting to balance load between clouds).

[0469] A cloud computing environment is a service-oriented environment that emphasizes statelessness, low coupling, modularity, and semantic interoperability. At the heart of cloud computing is an infrastructure that contains a network of interconnected nodes.

[0470] Referring now to FIG. 12 , an exemplary cloud computing environment 50 is shown. As shown, the cloud computing environment 50 includes one or more cloud computing nodes 52 with which local computing devices used by cloud consumers (e.g., a personal digital assistant (PDA) or mobile phone 54A, a desktop computer 54B, a laptop computer 54C, and / or an automobile computer system 54N) can communicate. The nodes 52 may communicate with each other. The nodes 52 may be physically or virtually grouped in one or more networks (not shown), such as a private cloud, community cloud, public cloud, or hybrid cloud, or combinations thereof, as previously described herein. This enables the cloud computing environment 50 to provide an infrastructure, platform, and / or SaaS that does not require cloud consumers to maintain resources on their local computing devices. The types of computing devices 54A-N shown in FIG. 12 are intended to be illustrative only, and it is understood that computing node 52 and cloud computing environment 50 can communicate with any type of computer-controlled device via any type of network and / or network-addressable connection (e.g., a connection using a web browser).

[0471] Referring now to Figure 13, a set of functional abstraction layers provided by cloud computing environment 50 (Figure 12) is shown. It should be understood in advance that the components, layers, and functions shown in Figure 13 are intended to be illustrative only, and that embodiments of the present invention are not limited thereto. As shown, the following layers and corresponding functions are provided:

[0472] Hardware and software layer 60 includes hardware and software components. Examples of hardware components include mainframe 61, RISC (Reduced Instruction Set Computer) architecture-based server 62, server 63, blade server 64, storage device 65, and network and network components 66. In some embodiments, software components include network application server software 67 and database software 68.

[0473] The virtualization layer 70 comprises an abstraction layer capable of providing virtual entities such as virtual servers 71 , virtual storage 72 , virtual networks including virtual private networks 73 , virtual applications and operating systems 74 , and virtual clients 75 .

[0474] By way of example, the management layer 80 may provide the following functions: Resource provisioning 81 dynamically procures computing and other resources used to execute tasks within the cloud computing environment; Metering and pricing 82 tracks costs as resources are utilized within the cloud computing environment and sends bills or invoices for the utilization of those resources; by way of example, those resources may include application software licenses; Security verifies the identity of cloud users and tasks and protects data and other resources; User portal 83 provides users and system administrators with access to the cloud computing environment; Service level management 84 allocates and manages cloud computing resources to meet required service levels; and Service Level Agreement (SLA) planning and execution 85 proactively prepares and procures cloud computing resources in accordance with SLAs in anticipation of future demand.

[0475] The Workload Layer 90 illustrates examples of functionality available in a cloud computing environment. Examples of workloads and functionality that may be provided from this layer include mapping and navigation 91, software development and lifecycle management 92, virtual classroom instruction delivery 93, data analytics processing 94, transaction processing 95, and transformation, rounding, and / or neural network processing-assisted processing 96.

[0476] Aspects of the invention may be systems, methods, and / or computer program products, at any possible level of technical detail of integration. The computer program product may include one or more computer-readable storage media containing computer-readable program instructions for causing a processor to perform aspects of the invention.

[0477] A computer-readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device, such as, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media includes portable floppy disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanically encoded devices such as punch cards or ridge-in-groove structures on which instructions are recorded, and any suitable combination thereof. As used herein, computer-readable storage media should not be construed as being ephemeral signals, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses passing through fiber optic cable), or electrical signals transmitted over wires.

[0478] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or storage device over a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network). This network may include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface within each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage on a computer-readable storage medium within each computing / processing device.

[0479] Computer-readable program instructions for carrying out the operations of the present invention may be source or object code written in any combination of one or more programming languages, including assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for integrated circuits, or object-oriented programming languages ​​such as Smalltalk®, C++, and procedural programming languages ​​such as the “C” programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer as a standalone software package, partially on the user's computer and on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, to carry out aspects of the present invention, electronic circuitry including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), may execute computer-readable program instructions to customize the electronic circuitry by utilizing state information of the computer-readable program instructions.

[0480] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0481] These computer-readable program instructions may be provided to a processor of a computer or other programmable data processing apparatus to create a machine, such that the instructions, executed by the processor of the computer or other programmable data processing apparatus, create means for performing the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams. These computer-readable program instructions may be stored on a computer-readable storage medium and capable of directing a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner, such that the computer-readable storage medium on which the instructions are stored comprises an article of manufacture containing instructions for performing aspects of the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0482] Computer-readable program instructions may be loaded into a computer, other programmable data processing apparatus, or other device such that the instructions, which execute on the computer, other programmable apparatus, or other device, perform the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams, thereby causing a series of operable steps to be performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process.

[0483] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, comprising one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions shown in the blocks may occur out of the order shown in the figures. For example, two blocks shown in succession may actually be realized as a single step, executed concurrently, executed substantially concurrently in a partially or fully overlapping manner in time, or executed in the reverse order, depending on the functionality involved. It is also noted that each block in the block diagrams and / or flowchart diagrams, and combinations of blocks included in the block diagrams and / or flowchart diagrams, may be implemented by a special-purpose hardware-based system that performs the specified function or operation or executes a combination of special-purpose hardware and computer instructions.

[0484] In addition to the above, one or more aspects may be provided, offered, deployed, managed, serviced, etc. by a service provider that offers management of a customer's environment. For example, a service provider may create, maintain, support, etc., computer code and / or computer infrastructure that implements one or more aspects for one or more customers. In return, the service provider may receive payments from the customer, for example, pursuant to a subscription and / or fee agreement. Additionally or alternatively, the service provider may receive payments from the sale of advertising content to one or more third parties.

[0485] In one aspect, an application may be deployed to perform one or more embodiments. As one example, deploying an application includes providing a computer infrastructure that functions to perform one or more embodiments.

[0486] As a further aspect, a computing infrastructure may be deployed that includes integrating computer readable code into a computing system, where the code in combination with the computing system is capable of executing one or more embodiments.

[0487] In yet another aspect, a process for integrating a computing infrastructure may be provided, comprising integrating computer-readable code into a computer system, the computer system comprising a computer-readable medium, the computer medium including one or more embodiments, the code in combination with the computer system capable of executing one or more embodiments.

[0488] While various embodiments have been described above, they are merely examples. For example, computing environments of other architectures may be used to incorporate one or more aspects and / or to use one or more aspects. Furthermore, various instructions or operations may be used. Furthermore, different types of registers and / or different registers may be used. Furthermore, other data formats, data layouts, and / or data sizes may be supported. In one or more embodiments, one or more general-purpose processors, one or more special-purpose processors, or a combination of general-purpose and special-purpose processors may be used. Many variations are possible.

[0489] Various embodiments are described herein. Furthermore, many variations are possible without departing from the spirit of the embodiments of the present invention. It should be noted that each embodiment or feature described herein and variations thereof can be combined with any other embodiment or feature unless specifically inconsistent.

[0490] Additionally, other types of computing environments may benefit and be used. By way of example, a data processing system may be used that includes at least two processors coupled directly or indirectly via a system bus to memory elements suitable for storing and / or executing program code. These memory elements may include, for example, local memory used during the actual execution of the program code, bulk storage, and cache memory for temporarily storing at least some program code to reduce the number of times the code must be retrieved from bulk storage during execution.

[0491] Input / output or I / O devices (including but not limited to keyboards, displays, pointing devices, DASDs, tapes, CDs, DVDs, thumb drives, and other storage media) may be coupled to the system either directly or through intervening I / O controllers. Network adapters may also be coupled to the system to enable the data processing system to be coupled to other data processing systems or remote printers or storage devices through intervening private or public networks. Modems, cable modems, and Ethernet cards are just a few of the types of network adapters available.

[0492] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used herein, indicate the presence of stated features, integers, steps, operations, elements, or components, or combinations thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof, or combinations thereof.

[0493] Corresponding structures, materials, acts, and equivalents of all means or steps and functional elements within the scope of the claims below are intended to include any structure, material, or act for performing a function in combination with other claimed elements, if any, when specifically claimed. The description of one or more embodiments has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosed form. Many modifications and variations will be apparent to those skilled in the art. The embodiments have been chosen and described to best explain various aspects and practical applications, and to enable others skilled in the art to appreciate various embodiments with various modifications as may be suited to the particular use contemplated.

Claims

1. A computer program for facilitating processing in a computing environment, the computer comprising: obtaining instructions for converting data from a source data type to a target data type, the source data type being selected from one or more source data types supported by the instructions, and the target data type being selected from one or more target data types supported by the instructions; determining a rounding mode for use by the instruction based on a selected data type of one of the source data type and the target data type, wherein the rounding mode is implicitly set based on the selected data type, and the rounding mode is assigned to the selected data type; performing a conversion of the data from the source data type to the target data type, the conversion including performing a rounding operation using the rounding mode implicitly set based on the selected data type, wherein performing the conversion provides a result in the target data type; and writing said result to a selected location.

2. 2. The computer program product of claim 1, wherein the selected data type is the target data type specified using the instruction, and the target data type comprises a machine-native data type specified using the instruction.

3. 3. The computer program product of claim 2, wherein the machine-native data types include a neural network processing data type 1 data type, and the rounding mode assigned to the neural network processing data type 1 data type is round to nearest value away from zero.

4. 4. A computer program product as claimed in claim 2 or 3, wherein the source data type is a binary floating-point data type specified using the instruction.

5. 2. The computer program product of claim 1, wherein the selected data type is the source data type specified using the instruction, and the source data type comprises a machine-native data type specified using the instruction.

6. 6. The computer program product of claim 5, wherein the machine-native data types include a neural network processing data type 1 data type, and the rounding mode assigned to the neural network processing data type 1 data type is round to nearest value away from zero.

7. 7. A computer program product as claimed in claim 5 or 6, wherein the target data type is a binary floating-point data type specified using the instruction.

8. 2. The computer program product of claim 1, wherein the data to be converted comprises source data in the source data type, the source data comprising a concatenation of data in one register specified using one field of the instruction and other data in another register specified using another field of the instruction.

9. 9. The computer program product of claim 8, wherein the performing the conversion comprises: rounding the source data based on the rounding mode to provide rounded data; and converting the rounded data to provide the result in the target data type.

10. 2. The computer program product of claim 1, wherein the data to be converted comprises source data in the source data type obtained using the instructions, and wherein said performing the conversion comprises rounding the source data based on the rounding mode to provide rounded data with a numeric precision of a target data type, and converting the rounded data to provide the result in the target data type.

11. 1. A computer system for facilitating processing within a computing environment, said computer system comprising: Memory and a processor in communication with the memory, the computer system configured to perform a method, the method comprising: obtaining instructions for converting data from a source data type to a target data type, the source data type being selected from one or more source data types supported by the instructions, and the target data type being selected from one or more target data types supported by the instructions; determining a rounding mode for use by the instruction based on a selected data type of one of the source data type and the target data type, wherein the rounding mode is implicitly set based on the selected data type, and the rounding mode is assigned to the selected data type; performing a conversion of the data from the source data type to the target data type, the conversion including performing a rounding operation using the rounding mode implicitly set based on the selected data type, wherein performing the conversion provides a result in the target data type; and writing said result to a selected location.

12. 12. The computer system of claim 11, wherein the selected data type is the target data type specified using the instruction, and the target data type comprises a machine-native data type specified using the instruction.

13. 13. The computer system of claim 12, wherein the machine-native data types include a neural network processing data type 1 data type, and the rounding mode assigned to the neural network processing data type 1 data type is round to nearest value away from zero.

14. 12. The computer system of claim 11, wherein the selected data type is the source data type specified using the instruction, and the source data type comprises a machine-native data type specified using the instruction.

15. 15. The computer system of claim 14, wherein the machine-native data types include a neural network processing data type 1 data type, and the rounding mode assigned to the neural network processing data type 1 data type is round to nearest value away from zero.

16. 1. A computer-implemented method for facilitating processing in a computing environment, the computer-implemented method comprising: obtaining instructions for converting data from a source data type to a target data type, the source data type being selected from one or more source data types supported by the instructions, and the target data type being selected from one or more target data types supported by the instructions; determining a rounding mode for use by the instruction based on a selected data type of one of the source data type and the target data type, wherein the rounding mode is implicitly set based on the selected data type, and the rounding mode is assigned to the selected data type; performing a conversion of the data from the source data type to the target data type, the conversion including performing a rounding operation using the rounding mode implicitly set based on the selected data type, wherein performing the conversion provides a result in the target data type; and writing the result to a selected location.

17. 17. The computer-implemented method of claim 16, wherein the selected data type is the target data type specified using the instruction, and the target data type comprises a machine-native data type specified using the instruction.

18. 18. The computer-implemented method of claim 17, wherein the machine-native data type comprises a neural network processing data type 1 data type, and the rounding mode assigned to the neural network processing data type 1 data type is round to nearest value away from zero.

19. 17. The computer-implemented method of claim 16, wherein the selected data type is the source data type specified using the instruction, and the source data type comprises a machine-native data type specified using the instruction.

20. 20. The computer-implemented method of claim 19, wherein the machine-native data type comprises a neural network processing data type 1 data type, and the rounding mode assigned to the neural network processing data type 1 data type is round to nearest value away from zero.

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