Josephson wideband multiplexer-demultiplexer circuit

Abstract

The superconducting circuit includes a first port and a plurality of second ports, a plurality of filter poles, each filter pole including an inductor and a capacitor connected in parallel between the first port and a second port of the plurality of second ports, and an admittance inverter including at least one of a coupling capacitor, a coupling inductor, and a Josephson junction, the admittance inverter coupling two consecutive filter poles to each other. When operating as a demultiplexer, the plurality of filter poles and associated admittance inverters define a plurality of current branches such that an input current input through the first port is routed to a selected one of the plurality of second ports by application of a first set of magnetic flux biases.

Description

[Technical Field]

[0001] FIELD OF THE INVENTION The presently claimed embodiments of the invention relate to superconducting circuits, and more particularly to Josephson wideband multiplexer / demultiplexer circuits and quantum mechanical computers employing same. [Background technology]

[0002] The ability to rapidly test quantum computing hardware in a single cooling cycle of a superconducting quantum computer's dilution refrigerator (DR) relies on the ability to multiplex or demultiplex microwave signals to and from different paths. Current techniques for increasing microwave fan-out generally require modifying commercially available hardware to operate in the DR's millikelvin (mK) environment. However, even with these modifications, this commercially available hardware is inherently noisy because it is constructed from non-superconducting materials. In addition, the commonly used mechanical switching between channels introduces significant transient heat loads. This necessarily imposes slow operation, as reheating of the DR mK stage must be achieved after every channel-switching event. Additionally, current techniques utilizing electromechanical microwave relays generally have a large physical footprint and are not suitable for scaling quantum computers to extremely large numbers of qubits.

[0003] It would therefore be desirable to provide a new class of switches that not only solves this and other problems of the prior art by providing a new class of switches with similar or better physical properties than those of state-of-the-art implementations, but also provides switches that are scalable and dissipate negligible amounts of heat. Indeed, quantum computers require, inter alia, high-speed, wide-bandwidth, compact, energy-efficient switches for multiplexing and demultiplexing, especially at low temperature stages (1 K to 10 mK), readout of many channels, a flexible and reconfigurable cryogenic testing infrastructure to allow future integration of cryogenic control and readout electronics, reduced wire counts, heat loads, etc. to enable scaling up the number of qubits in future quantum computers, etc. Summary of the Invention

[0004] One aspect of the present invention provides a superconducting circuit including: a first port and a plurality of second ports; a plurality of filter poles, each filter pole including an inductor and a capacitor connected in parallel between the first port and a second port among the plurality of second ports; and an admittance inverter including at least one of a coupling capacitor, a coupling inductor, and a Josephson junction, the admittance inverter connecting two consecutive filter poles to each other. At least one filter pole among the plurality of filter poles, together with the admittance inverter, defines a current branch (IB). The plurality of filter poles and associated admittance inverters define a plurality of current branches such that, when operating as a demultiplexer, an input current input through a first port is routed to a selected one of the plurality of second ports by application of a first set of flux biases, and, when operating as a multiplexer, an input current input through any one of the plurality of second ports is routed as an output current output through the first port by application of a second set of flux biases.

[0005] In one embodiment, during operation as a demultiplexer, a first set of flux biases is applied to match the current output through a selected one of the plurality of second ports to the current input through the first port, and all remaining unselected ports of the plurality of second ports are mismatched with the first port and have essentially zero transmission.

[0006] In one embodiment, the inductor and capacitor of each filter pole are connected to electrical ground and to the Josephson junction and coupling capacitor of the adjacent admittance inverter. In one embodiment, the coupling capacitor is configured to decouple the two filter poles from direct current (DC). In one embodiment, the current branch includes one pole or two poles.

[0007] In one embodiment, the number of second ports depends on the number of current branches. In one embodiment, the number of second ports is equal to N / 2, where N-1 is the total number of current branches.

[0008] In one embodiment, the number of second ports is two. P / 2 where P is the number of poles in the arm from the first port to a second port of the plurality of second ports, for an even number of P filter poles.

[0009] In one embodiment, the first port is connected to a first current branch having a first filter pole, and each of the plurality of second ports is connected to a corresponding second current branch having a corresponding second pole.

[0010] In one embodiment, the first port is connected to the first current branch via a first capacitor, and each of the plurality of second ports is connected to the second current branch via a corresponding second capacitor.

[0011] In one embodiment, each of the plurality of current branches in the arm from the first port to a second port of the plurality of second ports is configured to operate in a selected frequency range based on selected operating parameters, in one embodiment, the selected frequency range is 4 GHz to 8 GHz.

[0012] In one embodiment, when a current is input through a first port, the current is selectively transmitted to a second port among a plurality of second ports by applying an external magnetic flux bias.

[0013] In one embodiment, the impedance of the plurality of filter poles is determined by the beta-L coefficient (β L ) is chosen to be less than 1, and β L =2π*I c *L / Φ, where L is the geometric inductance of the SQUID and I c is the critical current of the coupled JJ, and Φ is the superconducting magnetic flux quantum. 。

[0014] In one embodiment, the impedance of the first port is matched to the impedance of each of the plurality of second ports. In one embodiment, the impedance of the first port is not matched to the impedance of each of the plurality of second ports.

[0015] One aspect of the present invention provides a superconducting quantum computer. The superconducting quantum computer includes a cooling system having a temperature-controlled enclosure, a quantum processor disposed within the temperature-controlled enclosure, the quantum processor including a plurality of qubits, and a superconducting circuit disposed within the temperature-controlled enclosure. The circuit includes a first port and a plurality of second ports, a plurality of filter poles, each filter pole including an inductor and a capacitor connected in parallel between the first port and a second port of the plurality of second ports, and an admittance inverter including at least one of a coupling capacitor, a coupled inductor, and a Josephson junction, the admittance inverter connecting two consecutive filter poles to each other. At least one filter pole of the plurality of filter poles, together with the admittance inverter, defines a current branch (IB). The plurality of filter poles and associated admittance inverters define a plurality of current branches such that, when operating as a demultiplexer, an input current input through the first port is routed to a selected one of the plurality of second ports by application of a first set of flux biases, and when operating as a multiplexer, an input current input through any one of the plurality of second ports is routed as an output current output through the first port by application of a second set of flux biases, each of the plurality of second ports being connected to a corresponding qubit of the plurality of qubits to control or read out the state of the corresponding qubit.

[0016] In one embodiment, during operation as a demultiplexer, a first set of flux biases is applied to match the current output through a selected one of the plurality of second ports to the current input through the first port, and all remaining unselected ports of the plurality of second ports are mismatched with the first port and have essentially zero transmission.

[0017] In one embodiment, when a current is input through a first port, the current is selectively transmitted to a second port of a plurality of second ports by applying a first set of magnetic flux biases.

[0018] A further aspect of the present invention provides a superconducting network circuit. The superconducting network circuit includes: a first superconducting circuit having a first port and a plurality (N) of second ports for realizing a 1-to-N switch configuration; a plurality of filter poles, each filter pole including an inductor and a capacitor connected in parallel between the first port and a second port of the plurality of second ports; and an admittance inverter including at least one of a coupling capacitor, a coupling inductor, and a Josephson junction, the admittance inverter connecting two consecutive filter poles to each other. At least one filter pole of the plurality of filter poles, together with the admittance inverter, defines a current branch (IB). When operating as a demultiplexer, the plurality of filter poles and the associated admittance inverter define the plurality of current branches such that an input current input through the first port is routed to a selected one of the plurality (N) of second ports by application of a first set of magnetic flux biases. The superconducting network circuit includes a second superconducting circuit having a third port and multiple (M) fourth ports for realizing a 1-to-M switch configuration, a plurality of filter poles, each filter pole including an inductor and a capacitor connected in parallel between the third port and a fourth port of the plurality of fourth ports, and an admittance inverter including at least one of a coupling capacitor, a coupling inductor, and a Josephson junction, the admittance inverter connecting two consecutive filter poles to each other. At least one filter pole of the plurality of filter poles, together with the admittance inverter, defines a current branch (IB).The plurality of filter poles and associated admittance inverters, when operating as a multiplexer, define a plurality of current branches such that an input current input through any one of the plurality of (M) fourth ports is routed as an output current output through the third port upon application of a second set of flux biases. The first port of the first superconducting circuit is connected to the third port of the second superconducting circuit to implement an M-to-N switch matrix.

[0019] The present disclosure, as well as the method of operation and function of the associated elements of construction, and combination of parts and economy of manufacture, will become more apparent from a consideration of the following description and appended claims, taken in conjunction with the accompanying drawings, all of which form a part hereof, and in which like reference numerals indicate corresponding parts in the various views. It is to be expressly understood, however, that the drawings are for the purpose of illustration and description only and are not intended as a definition of the limits of the invention. [Brief explanation of the drawings]

[0020] [Figure 1] FIG. 2 is an electronic circuit diagram of a superconducting circuit, according to one embodiment of the present invention. [Figure 2] FIG. 2 illustrates an expanded portion of the circuit shown in FIG. 1, according to one embodiment of the present invention. [Figure 3A] 3 shows a plot of a simulation of the circuit shown in FIG. 2, in accordance with one embodiment of the present invention. [Figure 3B] 3 shows a plot of a simulation of the circuit shown in FIG. 2, in accordance with one embodiment of the present invention. [Figure 4A] FIG. 10 is a plot of simulation results of scattering parameters versus frequency for a 1:4 circuit, i.e., one first port (e.g., input port) and four second ports (e.g., output ports), in accordance with one embodiment of the present invention. [Figure 4B]FIG. 10 is a plot of simulation results of scattering parameters versus frequency for a 1:4 circuit, i.e., one first port (e.g., input port) and four second ports (e.g., output ports), in accordance with one embodiment of the present invention. [Figure 4C] FIG. 10 is a plot of simulation results of scattering parameters versus frequency for a 1:4 circuit, i.e., one first port (e.g., input port) and four second ports (e.g., output ports), in accordance with one embodiment of the present invention. [Figure 4D] FIG. 10 is a plot of simulation results of scattering parameters versus frequency for a 1:4 circuit, i.e., one first port (e.g., input port) and four second ports (e.g., output ports), in accordance with one embodiment of the present invention. [Figure 5] FIG. 10 is a plot of the results of a simulation of scattering parameters versus frequency for a 1:8 circuit, such as the circuit shown in FIG. 1, i.e., one first port (e.g., input port) and eight second ports (e.g., output ports), in accordance with another embodiment of the present invention. [Figure 6] FIG. 2 is another electronic circuit diagram of a superconducting circuit, according to one embodiment of the present invention. [Figure 7A] FIG. 1 illustrates a superconducting network circuit according to one embodiment of the present invention. [Figure 7B] FIG. 10 illustrates a superconducting network circuit according to another embodiment of the present invention. [Figure 8] 1 is a schematic diagram of a superconducting quantum computer according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0021] FIG. 1 is an electronic circuit diagram of a superconducting circuit according to one embodiment of the present invention. The superconducting circuit 100 includes a first port 102 and a plurality of second ports 104. The superconducting circuit 100 further includes a plurality of filter poles 106. Each filter pole 106 includes an inductor 106A and a capacitor 106B (shown in FIG. 2) connected in parallel between the first port 102 and a second port 104 of the plurality of second ports 104. The circuit 100 further includes an admittance inverter 108. The admittance inverter 108 includes one of a coupling capacitor 108C, a coupling inductor 112A, and a Josephson junction (JJ) 108J (also shown in FIG. 2). The admittance inverter 108 couples two consecutive filter poles 106 to each other. In one embodiment, the admittance inverter is of the "π" type, and the negative shunt reactive component is absorbed in the surrounding pole capacitors and / or inductors.

[0022] FIG. 2 shows an enlarged portion 200 of circuit 100, according to one embodiment of the present invention. As shown in more detail in FIG. 2, each filter pole 106 has an inductor 106A and a capacitor 106B connected in parallel. A Josephson junction 108J couples two consecutive filter poles 106 to each other. A capacitor 108C (C13) couples a filter pole 106 to the input port 102. Capacitors 108C (C16 and C18) couple one filter pole 106 to another filter pole 106 (not shown in FIG. 2).

[0023] 2, the inductor 106A and capacitor 106B of each filter pole 106 are connected to electrical ground and to the Josephson junction 108J and coupling capacitor 108C of the adjacent admittance inverter 108. In one embodiment, the coupling capacitors 108 are provided to decouple the two filter poles from direct current (DC). For example, the coupling capacitor 108C is provided between the first port 102 and the leftmost filter pole 106. Another coupling capacitor 108C can also be provided between two adjacent filter poles 106.

[0024] 1, at least one filter pole 106 of the plurality of filter poles 106, together with the admittance inverter 108, defines a current branch (IB) 110. For example, the current branch 110 directly connected to the input port 102 has one filter pole (first filter pole), while the current branch 110 connected to the first filter pole 106 via a Josephson junction 108J has two filter poles 106.

[0025] The plurality of filter poles 106 and associated admittance inverters 108 define a plurality of current branches 110 such that, when operating as a demultiplexer, an input current input through the first port 102 is routed to a selected one of the plurality of second ports 104 by application of a first set of flux biases, and, when operating as a multiplexer, an input current input through any one of the plurality of second ports 104 is routed as an output current output through the first port 102 by application of a second set of flux biases.

[0026] As shown in FIG. 2, the flux bias is generated by inputting a bias DC current through DC control line 112, which is inductively coupled to inductor 106A of each pole filter 106 via coupled inductor 112A. In one embodiment, controlled operation of the circuit uses a DC flux bias line and a relatively fast (1 GHz bandwidth) control line. The left flux bias control line (I4+L13) sets a DC flux bias offset that pushes current into both JJs 108J. At this point, the circuit is nonfunctional because each JJ is current biased away from its nominal operating point. The user then uses I3, L11, and L12 to push flux into the second half of the circuit, which either cancels the DC offset current in the upper JJ 108J and adds more bias current to the lower JJ, or vice versa, depending on the sign of the current from I3.

[0027] 3A and 3B show plots of a simulation of circuit 200 according to one embodiment of the present invention. The vertical axis represents frequency (in Hz), and the horizontal axis represents the flux bias current (in μA) corresponding to the second flux bias currents (I3, L11, and L12). FIG. 3A shows the scattering parameter S21 in dB as a function of both frequency and flux bias current, and FIG. 3B shows the scattering parameter S31 in dB as a function of both frequency and flux bias current. The simulation predicts that when the current in the AC flux bias line (input) is varied, the amount of separation between the “on” and “off” states of the two channels (outputs) can be controllably changed by at least 20 dB, with the “on” state having a transmission close to unity within a desired frequency band (e.g., between 6 GHz and 7 GHz). The circuits 100, 200 operate reversibly, meaning that the circuits 100, 200 can be used as either a multiplexer or a demultiplexer, depending on the designation of the first and second ports, with approximately the same level of performance in either configuration. That is, the first port 102 can operate as an input port while the second port 104 can operate as an output port, and one of the second ports 104 can also operate as an input port while the first port 102 operates as an output port.

[0028] In one embodiment, during operation as a demultiplexer, a flux bias is applied (via DC induction wire 112). Specifically, during operation, flux bias current I4 sets an offset flux for the circuit, while flux bias current I3 provides flux to reduce the offset flux in one channel and add the offset flux in another channel, depending on the sign of the current provided by flux bias current I3, so that the current output through a selected one of the plurality of second ports 104 matches the current input through first port 102, while all remaining, unselected ports of the plurality of second ports 104 are mismatched with first port 102 and essentially have zero transmission. For example, the top second port (output port) 104 in FIG. 1 can be selected to match first port (input port) 102 to send an output current, while all remaining output ports 104 are mismatched with first port (input port) 102 and therefore essentially have zero transmission and send out zero current.

[0029] In one embodiment, the number of second ports 104 depends on the number of current branches (IB) 110. The number of second ports is equal to N / 2, where N-1 is the total number of current branches. For example, in the embodiment shown in FIG. 1, the total number of current branches is 15, and therefore the number of second ports 104 is 8.

[0030] In one embodiment, the number of second ports 104 may be calculated based on the number of filter poles 106. Specifically, the number of second ports 104 may be 2 P / 2 where P is the number of filter poles 106 in an arm from the first port 102 to a second port 104 of the plurality of second ports 104, for an even number of P filter poles 106. For example, in the embodiment shown in FIG. 1, the number of poles 106 in an arm (e.g., the upper arm) is equal to 6, and therefore the number of second ports (output ports) 104 is equal to 2. 3 , i.e., equal to 8.

[0031] In one embodiment, the first port 102 is connected to a first current branch 110 having a first filter pole 106, and each of the plurality of second ports 104 is connected to a corresponding second current branch 110 having a corresponding second pole 106.

[0032] In one embodiment, the first port 102 is connected to the first current branch 110 via a first capacitor 108C1, and each of the multiple second ports 104 is connected to the second current branch 110 via a corresponding second capacitor 108C2.

[0033] In one embodiment, when a current is input through the first port 102, the current is selectively routed to one of the plurality of second ports 104 by applying a controlled flux bias. The controlled DC offset flux bias is sent through a DC control line 112 that is inductively coupled to the inductor 106A of each pole filter 106 via a coupled inductor 112A. As shown in FIG. 2, the flux bias current, driven by the left current bias I4 through L13, which is coupled to L6, sets the DC offset of the switch. The current driven by I3 through inductors L11 and L12 determines which output the signal is routed to by canceling the DC offset bias in one branch (e.g., the top one) while simultaneously drawing more current through the opposite branch (e.g., the bottom one).

[0034] In one embodiment, each of the multiple current branches 110 in the arm from the first port 102 to a second port 104 of the multiple second ports 104 is configured to operate in a selected frequency range based on selected operating parameters, for example, the selected frequency range is 4 GHz to 8 GHz.

[0035] 4A-4D show plots of simulation results of scattering parameters versus frequency for a 1:4 circuit, i.e., one first port (e.g., input port) and four second ports (e.g., output ports), according to one embodiment of the present invention. The horizontal axis represents frequency in GHz. The vertical axis of each plot represents signal amplitude in dB. Each curve shows the scattering parameters of various ports of the circuit, and SXY represents the ratio of the output signal amplitude at port X to the input signal from port Y, i.e., S11 is the input port voltage reflection coefficient, S31 is the forward voltage gain at port 3, etc. FIG. 4A shows switching or routing of signals from port 1 to port 2 (i.e., S21 is turned ON, while S31, S41, and S51 are turned OFF). FIG. 4B shows switching or routing of signals from port 1 to port 3 (i.e., S31 is turned ON, while S21, S41, and S51 are turned OFF). Figure 4C shows the switching or routing of signals from port 1 to port 4. Figure 4D shows the switching or routing of signals from port 1 to port 5 (i.e., S51 is turned ON while S21, S31, and S41 are turned OFF).

[0036] FIG. 5 shows a plot of the results of a simulation of scattering parameters versus frequency for a 1:8 circuit, i.e., one first port (e.g., input port) and eight second ports (e.g., output ports), according to another embodiment of the present invention. The horizontal axis represents frequency in GHz. The vertical axis represents signal amplitude in dB. In this case, the switch is configured to allow the input signal to be routed primarily toward port 2, resulting in a transmission of nearly unity between 6 and 8 GHz in curve S21, while the reflected signal shown in curve S11 is over 10 dB lower. The remaining outputs are in the off state, as evidenced by the even lower signal response in curves S31, S41, S51, S61, S71, S81, and S91.

[0037] While 1:4 and 1:8 switch circuits are shown herein, it should be appreciated that the number of second ports is not limited to only four or eight ports, but can be any number N of second ports (e.g., output ports) greater than two. For example, 1:16 or greater switch circuits can also be fabricated using a specific number of filter poles, as described in the paragraph above.

[0038] FIG. 6 is another electronic circuit diagram of a superconducting circuit according to one embodiment of the present invention. The superconducting circuit 600 shown in FIG. 6 is similar to the superconducting circuit 100 shown in FIG. 1. However, for clarity, the magnetic flux bias lines shown in FIG. 1 are not shown in FIG. 6 to avoid cluttering the diagram. Both the circuit 100 and the circuit 600 in this example are 1:8 switch circuits, i.e., circuits that can route a signal from a first port 602 (input port) to one of eight second ports 604 (output ports), or circuits that can route a signal from one of eight second ports 604 (input ports) to the first port 602 (output port). As shown in FIG. 6, for example, there are six filter poles in the top arm of the circuit 600 (from the first port 602 to the top second port 604). With six filter poles, eight second ports (e.g., output ports) can be provided, thereby enabling a 1:8 fanout.

[0039] Generally, at larger frequency bandwidths, the beta-L of some SQUIDs (Josephson junctions and inductors) tends to be greater than 1, rendering the circuit unusable. The superconducting quantum interference device (SQUID) loop includes Josephson junctions (JJs) 108J and surrounding shunt-pole inductors 106A. However, the circuit can be configured so that all pairs of resonators have substantially the same impedance, lowering all SQUID beta-L to less than 1. For example, if the impedances are adjusted so that all subsequent pairs of resonators now have the same impedance, a beta-L < 1 can be achieved for each of the SQUID loops, thereby enabling the desired 1-8 fanout. For example, by selecting LC resonators 1, 2, 5, and 6 to have Z = 15 and LC resonators 3 and 4 to have Z = 2, we obtain the following circuit values: "C01": 9.83e-13 F, "C2": 4.86e-13 F, "C3": 1.14e-11 F, "C1": 1.47e-12 F, "C23": 1.19e-12 F, "L12": 1.21e-09 H, "L1": 5.49e-10 H, "L2": 5.49e-10 H, "L34": 1.98e-10 H, "L3": 6.74e-11 H.

[0040] This results in a beta-L of 0.91 for the SQUIDs near the output and input of the circuit, and a beta-L of 0.68 for the SQUID in the center of the circuit. For example, in this calculation, the quoted values ​​L1 and L2 (shown in Figure 6) refer to inductors L6 and L10 shown in Figure 2. Furthermore, the connection between L12 and Josephson junction 108J is made to have a critical current. Then, beta-L is: beta-L = (L6 + L10) / L12 = 2 * π * I cIt can be calculated as (108J)*(L6+L10) / Φ0. In this example, the circuit is symmetrical about the fourth admittance inverter, so that LC poles 1, 2, 5, and 6 are matched in impedance, and LC poles 3 and 4 are matched.

[0041] In one embodiment, the impedance of the plurality of filter poles is determined by the beta-L coefficient (β L ) is chosen to be less than 1, and β L =2π*I c *L / Φ, where L in this equation is the sum of all geometric inductances that make up the SQUID loop. In the example circuit shown in FIG. 2, L=L+L for the top path and L=L+L for the bottom path. Φ is the superconducting flux quantum. In one embodiment, the impedance at the first port 102, 602 (shown in FIGS. 1 and 6, respectively) is matched to the impedance of each of the plurality of second ports 104, 604 (shown in FIGS. 1 and 6, respectively). In another embodiment, the impedance at the first port 102, 602 is not matched to the impedance of each of the plurality of second ports 104, 604.

[0042] Josephson junction-based switches and multiplexer-demultiplexer circuits can have zero internal power consumption, very low insertion loss, relatively wide bandwidth, and can operate quickly, making them potentially impactful for future quantum computers. Simulations of these devices have shown that Josephson junction-based switches can have the following properties: 1. Signal bandwidth 4GHz to 8GHz (although it can be designed for a more specific band by selecting appropriate parameters of the circuit if required for a given application). 2. On / off ratio of at least 20dB. 3. Fast (approximately 20ns) toggling between switch channels. 4.Operates at input signal power of approximately -120dBm. 5. Higher signal power engineering can also be achieved, if desired, by appropriate adjustment of circuit parameters.

[0043] Because the JJ circuit is embedded in an N-pole bandpass filter network, it can be designed to match input and output impedances other than 50 ohms. The impedance matching is achieved by the design of the filter network itself.

[0044] In one embodiment, the SQUID coupler is configured with a β L <1. Additionally, the initial and terminal series capacitances can be chosen to remain limited, which is effective for high-impedance resonators. These two conditions can be met simultaneously by appropriate selection of circuit parameters.

[0045] In one embodiment, the circuits described herein can include coplanar waveguide terminations for proper impedance matching, allowing modular structures of (1 to 2) superconducting switch circuits to be cascaded into larger multi-stage multiplexers. Additionally, DC bias lines can be shared between different stages of the circuit, thereby reducing the number of DC flux lines required to flux bias the circuit.

[0046] FIG. 7A illustrates a superconducting network circuit 700 according to one embodiment of the present invention. The network includes a first superconducting circuit 702 having a first port 702A and a plurality (N) of second ports 702B to implement a 1:N switch configuration. The network 700 further includes a second superconducting circuit 704 having a third port 704A and a plurality (M) of fourth ports 704B to implement a 1:M switch configuration. The first superconducting circuit 702 and the second superconducting circuit 704 are similar to the superconducting circuits 100 and 600 described in detail in the preceding paragraphs. Therefore, a description of the various components of the circuits 702 and 704 will not be repeated. The first port 702A of the first superconducting circuit 702 is connected to the third port 704A of the second superconducting circuit 704 to implement an M:N switch matrix. Although circuits 702 and 704 are shown as having N=8 and M=8 ports, any number of N and M ports (N>2 and M>2) may be provided. Additionally, numbers N and M may be equal or different. For example, an input signal input through one of the fourth ports 704B may be output through the third port 704A of the second superconducting circuit 704 and then input through the coupled first port 702A and routed to any one of the second ports 702B of the first superconducting circuit 702. In this manner, any input signal input through any one of the fourth ports 704B may be routed and output to any one of the second ports 702B as desired by controlling the switching dynamics of superconducting circuits 702 and 704.

[0047] 7B illustrates a superconducting network circuit 701 according to one embodiment of the present invention. The network includes a first superconducting circuit 703 having a first port 703A and a plurality (N) of second ports 703B for implementing a 1:N switch configuration. The network 701 further includes a second superconducting circuit 705 having a third port 705A and a plurality (M) of fourth ports 705B for implementing an M:1 switch configuration. The first superconducting circuit 703 and the second superconducting circuit 705 are similar to the superconducting circuits 100 and 600 described in detail in the preceding paragraphs. Therefore, a description of the various components of the circuits 703 and 705 will not be repeated. The plurality (N) of second ports 703B of the first superconducting circuit 703 and the plurality (M) of fourth ports 705B of the second superconducting circuit 705 are connected to a device under test (DUT) 707. For example, a single first port 703A and a single third port 705A function as input and output ports, respectively. Similar to circuit 700, circuits 703 and 705 are shown as having N=8 and M=8 ports, but any number of N and M ports (N>2 and M>2) may be provided. The DUT may be any cryogenic hardware, including, for example, but not limited to, a qubit, a readout resonator for the qubit, a tunable SQUID-like element, or an on-chip coupler used to tune the qubit.

[0048] 8 is a schematic diagram of a superconducting quantum computer 800 according to one embodiment of the present invention. The superconducting quantum computer 800 includes a cooling system including a temperature-controlled enclosure 802. The superconducting quantum computer 800 further includes a quantum processor 804 disposed within the temperature-controlled enclosure 802. The quantum processor 804 includes a plurality of qubits (X) 806. The superconducting quantum computer 800 further includes a superconducting circuit 100, 600, 700 disposed within the temperature-controlled enclosure 802. The circuit 100, 600, 700 has a first port 102, 602, 702A, 704B and a plurality of second ports 104, 604, 702B. Each of the plurality of second ports 104, 604, and 702B is connected to a corresponding qubit (X) of the plurality of qubits 806 to control or read out the state of the corresponding qubit (X). Generally, the second ports 104, 604, and 702B (e.g., output ports) can also be connected to a qubit, a readout resonator for the qubit, or a tunable SQUID-like element or on-chip coupler for tuning the qubit.

[0049] In one embodiment, these superconducting switch circuits can enable a flexible and reconfigurable cryogenic testing infrastructure that can help increase sample throughput for testing cryogenic hardware. Testing many devices with the cooling of a single dilution refrigerator (temperature-controlled vessel 802) can support efforts to rapidly examine different designs, layouts, signal chains, etc., without warming mK plates or shutting down devices when switching signal lines.

[0050] In some embodiments, the described switch circuit can be used as a replacement for current commercial-off-the-shelf (COTS) switches in modern dilution refrigerator setups. Multiplexing can enable readout of many channels and routing of signals to high-electron-mobility transistor (HEMT) amplifiers. Consequently, this can help reduce the number of wires and heat load, enabling an expansion of the number of qubits in future quantum computers. In addition, the present circuit device can help enable the future integration of cryogenic microwave electronics, ultimately enabling on-chip integration with traveling-wave Josephson parametric amplifiers (TWPAs) or other quantum-limited amplifiers (QLAs). The possibility of dynamically reconfigurable isolation, such as that achieved with the present JJ ​​switch, opens up new possibilities for qubit experiments, such as scheduled readout sequences between different qubit chips sharing a common QLA and readout infrastructure. Finally, cryogenic isolation of the JJ switch at the cryogenic stage (1 K–10 mK) can also help reduce noise from the readout chain based on its influence on spectator qubits, improving multiqubit device performance.

[0051] The description of various embodiments of the present invention has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many variations and modifications will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein have been chosen to best explain the principles of the embodiments, practical applications, or technical improvements to technology found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A superconducting circuit, a first port and a plurality (N) of second ports for implementing a 1:N switch configuration, wherein the number N of second ports is greater than two; a plurality of filter poles, each filter pole of the plurality of filter poles including an inductor and a capacitor connected in parallel between the first port and a second port of the plurality of second ports, one filter pole associated with each of the plurality of second ports; an admittance inverter including at least one of a coupling capacitor, a coupling inductor, and a Josephson junction, the admittance inverter coupling two consecutive filter poles together; and a flux bias is generated by inputting a bias DC current through a DC control line inductively coupled to the inductor of each filter pole via the coupled inductor; at least one filter pole of the plurality of filter poles defines, together with the admittance inverter, a current branch (IB); The plurality of filter poles and associated admittance inverters include: (i) when the plurality of filter poles and associated admittance inverters operate as a demultiplexer, an input current input through the first port is routed to a selected one of the plurality of second ports by application of a flux bias generated by inputting a bias DC current through the DC control line; (ii) when the plurality of filter poles and associated admittance inverters operate as a multiplexer, an input current input through any one of the plurality of second ports is routed as an output current output through the first port by application of the flux bias generated by inputting a bias DC current through the DC control line. A plurality of current branches are defined; the impedances of the plurality of filter poles are selected so that the beta-L factor (β L ) of each superconducting quantum interference device (SQUID) loop including the Josephson junction and inductor is less than 1; β L =2π*I c *L / Φ 0 , where L is the geometrical inductance of the SQUID, I c is the critical current of the coupled JJ, and Φ 0 is the superconducting magnetic flux quantum. Superconducting circuits.

2. 2. The circuit of claim 1, wherein, during operation as the demultiplexer, the flux bias generated during operation as the demultiplexer is applied to match a current output through the selected one of the plurality of second ports to the current input through the first port, and all remaining unselected ports of the plurality of second ports are mismatched with the first port and have essentially zero transmission.

3. 3. The circuit of claim 1, wherein the inductor and capacitor of each filter pole are connected to electrical ground and to the Josephson junction and coupling capacitor of an adjacent admittance inverter.

4. 4. The circuit of claim 3, wherein the coupling capacitor is configured to decouple two filter poles from direct current (DC).

5. 5. The circuit of claim 1, wherein the current branch comprises one pole or two poles.

6. 6. The circuit of claim 1, wherein the number of second ports depends on the number of current branches.

7. 7. The circuit of claim 6, wherein the number of second ports is equal to N / 2, where N-1 is the number of total current branches.

8. The number of the plurality of second ports is two. Ｐ／２ 8. The circuit of claim 1, wherein P is the number of poles in an arm from the first port to a second port of the plurality of second ports, for an even number of P filter poles.

9. 9. The circuit of claim 1, wherein the first port is connected to a first current branch having a first filter pole, and each of the plurality of second ports is connected to a corresponding second current branch, each of the second current branches having a corresponding second pole.

10. 10. The circuit of claim 9, wherein the first port is connected to the first current branch through a first capacitor, and each of the plurality of second ports is connected to the second current branch through a corresponding second capacitor.

11. 11. The circuit of claim 1, wherein each of the plurality of current branches in an arm from the first port to a second port of the plurality of second ports is configured to operate in a selected frequency range based on selected operating parameters.

12. 12. The circuit of claim 11, wherein the selected frequency range is from 4 GHz to 8 GHz.

13. 13. The circuit of claim 1, wherein when a current is input through the first port, the current is selectively transmitted to a second port among the plurality of second ports by applying an external magnetic flux bias.

14. 14. The circuit of claim 1, wherein the impedance of the first port is matched to the impedance of each of the plurality of second ports.

15. 14. The circuit of claim 1, wherein the impedance of the first port is not matched to the impedance of each of the plurality of second ports.

16. A superconducting quantum computer, a cooling system including a temperature-controlled vessel; a quantum processor disposed within the temperature-controlled enclosure, the quantum processor including a plurality of qubits; a superconducting circuit disposed within the temperature-controlled vessel, the superconducting circuit comprising: a first port and a plurality (N) of second ports for implementing a 1:N switch configuration, wherein the number N of second ports is greater than two; a plurality of filter poles, each filter pole of the plurality of filter poles including an inductor and a capacitor connected in parallel between the first port and a second port of the plurality of second ports, one filter pole associated with each of the plurality of second ports; an admittance inverter including at least one of a coupling capacitor, a coupling inductor, and a Josephson junction, the admittance inverter coupling two consecutive filter poles together; and the superconducting circuit comprising: a flux bias is generated by inputting a bias DC current through a DC control line inductively coupled to the inductor of each filter pole via the coupled inductor; at least one filter pole of the plurality of filter poles defines, together with the admittance inverter, a current branch (IB); The plurality of filter poles and associated admittance inverters include: (i) when the plurality of filter poles and associated admittance inverters operate as a demultiplexer, an input current input through the first port is routed to a selected one of the plurality of second ports by application of a flux bias generated by inputting a bias DC current through the DC control line; (ii) when the plurality of filter poles and associated admittance inverters operate as a multiplexer, an input current input through any one of the plurality of second ports is routed as an output current output through the first port by application of the flux bias generated by inputting a bias DC current through the DC control line. defining a plurality of current branches; each of the plurality of second ports is coupled to a corresponding qubit of the plurality of qubits to control or read out the state of the corresponding qubit; the impedances of the plurality of filter poles are selected so that a beta-L factor (β L ) of each superconducting quantum interference device (SQUID) loop including the Josephson junction and inductor is less than 1; β L =2π*I c *L / Φ 0 , where L is the geometrical inductance of the SQUID, I c is the critical current of the coupled JJ, and Φ 0 is the superconducting magnetic flux quantum. Superconducting quantum computer.

17. 17. The superconducting quantum computer of claim 16, wherein, while operating as the demultiplexer, the flux bias generated while operating as the demultiplexer is applied to match a current output through the selected one of the plurality of second ports to the current input through the first port, and all remaining unselected ports of the plurality of second ports are mismatched with the first port and have essentially zero transmission.

18. 18. The superconducting quantum computer of claim 16 or 17, wherein when a current is input through the first port, the current is selectively transmitted to a second port among the plurality of second ports while operating as the demultiplexer by applying the magnetic flux bias generated while operating as the demultiplexer.

19. A superconducting network circuit, a first superconducting circuit; a first port and a plurality (N) of second ports for implementing a 1:N switch configuration, wherein the number N of second ports is greater than two; a plurality of first filter poles, each of which includes a first inductor and a first capacitor connected in parallel between the first port and a second port of the plurality of second ports, with one first filter pole associated with each of the plurality of second ports; a first admittance inverter including at least one of a first coupling capacitor, a first coupling inductor, and a first Josephson junction, wherein the first admittance inverter couples two consecutive first filter poles together; and a flux bias is generated by inputting a bias DC current through a first DC control line inductively coupled to the first inductor of each of the first filter poles via the first coupled inductor; at least one first filter pole of the plurality of first filter poles defines, together with the first admittance inverter, a current branch (IB); The plurality of first filter poles and associated first admittance inverters include: defining a plurality of current branches such that, when the plurality of first filter poles and associated first admittance inverters operate as a first demultiplexer, an input current input through the first port is routed to a selected one of the plurality of second ports by application of a first flux bias generated by inputting a bias DC current through the first DC control line; the first superconducting circuit; a second superconducting circuit; one third port and a plurality (M) of fourth ports for implementing a 1:M switch configuration, wherein the number M of fourth ports is greater than two; a plurality of third filter poles, each of which includes a third inductor and a third capacitor connected in parallel between the third port and a fourth port of the plurality of fourth ports, with one third filter pole associated with each of the plurality of fourth ports; a third admittance inverter including at least one of a third coupling capacitor, a third coupling inductor, and a third Josephson junction, wherein the third admittance inverter couples two consecutive third filter poles together; and a flux bias is generated by inputting a bias DC current through a third DC control line inductively coupled to the third inductor of each of the third filter poles via the third coupled inductor; at least one third filter pole of the plurality of third filter poles defines, together with the third admittance inverter, a current branch (IB); the plurality of third filter poles and associated third admittance inverters comprising: defining a plurality of current branches such that, when the plurality of third filter poles and associated third admittance inverters operate as a third multiplexer, an input current input through any one of the plurality of fourth ports is routed as an output current output through the third port by application of the second flux bias; the second superconducting circuit; Including, the first port of the first superconducting circuit is connected to the third port of the second superconducting circuit to implement an M to N switch matrix; the impedances of the first plurality of filter poles are selected so that a beta-L factor (β L ) of each Superconducting Quantum Interference Device (SQUID) loop including the first Josephson junction and an inductor is less than 1; β L =2π*I c *L / Φ 0 , where L is the geometrical inductance of the SQUID, I c is the critical current of the coupled JJ, and Φ 0 is the superconducting magnetic flux quantum. the impedances of the third plurality of filter poles are selected so that a beta-L factor (β L ) of each Superconducting Quantum Interference Device (SQUID) loop including the third Josephson junction and an inductor is less than 1; β L =2π*I c *L / Φ 0 , where L is the geometrical inductance of the SQUID, I c is the critical current of the coupled JJ, and Φ 0 is the superconducting magnetic flux quantum. Superconducting network circuit.

Images