Precise data tuning method and apparatus for analog neural memories in artificial neural networks

Abstract

To provide a method for programming, verifying and reading a zero value in a differential pair of non-volatile memory cells in a neural network and a vector matrix multiplication (VMM) array.SOLUTION: A tuning correction method performed by an algorithmic controller in a VMM system comprises: erasing an entire VMM array upon receiving a tuning command by a soft erase method or the like; performing a programming operation on all unused cells to obtain a cell current <pA level or an equivalent zero weight; programming all cells in the VMM array to an intermediate value, such as 0.5-1.0 μA, using coarse and / or fine programming cycles; setting a prediction target to the cells used using a function or lookup table; and performing a sector tuning method for each sector of the VMM.SELECTED DRAWING: Figure 35A

Description

[Technical Field]

[0001] (Priority Claim) This application claims priority to U.S. Provisional Patent Application No. 62 / 957,013, filed January 3, 2020, entitled "Precise Data Tuning Method and Apparatus for Analog Neuromorphic Memory in an Artificial Neural Network," which is a continuation-in-part of U.S. Patent Application No. 16 / 829,757, filed March 25, 2020, entitled "Precise Data Tuning Method and Apparatus for Analog Neuromorphic Memory in an Artificial Neural Network," which claims priority to U.S. Provisional Patent Application No. 17 / 185,725, filed February 25, 2021, entitled "Precise Data Tuning Method and Apparatus for Analog Neural Memory in an Artificial Neural Network."

[0002] FIELD OF THE INVENTION Numerous embodiments are disclosed for a precision-tuning method and apparatus for precisely and quickly depositing precise amounts of charge onto the floating gates of non-volatile memory cells in vector-by-matrix multiplication (VMM) arrays within artificial neural networks. [Background technology]

[0003] Artificial neural networks mimic biological neural networks (the central nervous systems of animals, particularly the brain) and are used to estimate or approximate functions that may depend on multiple inputs and are generally unknown. Artificial neural networks generally contain layers of interconnected "neurons" that exchange messages between each other.

[0004] Figure 1 shows an artificial neural network, where circles represent layers of inputs or neurons. Connections (called synapses) are represented by arrows and have numerical weights that can be tuned based on experience. This allows the artificial neural network to adapt to the inputs and learn. Typically, an artificial neural network contains multiple layers of inputs. There are typically one or more hidden layers of neurons, and an output layer of neurons that provide the neural network's output. At each level, neurons make decisions, individually or collectively, based on the data they receive from the synapses.

[0005] One of the major challenges in developing artificial neural networks for high-performance information processing is the lack of suitable hardware technology. In practice, practical artificial neural networks rely on a very large number of synapses, which allows for high connectivity between neurons and therefore a very high degree of parallelization of computation. In principle, such complexity could be achieved using digital supercomputers or dedicated graphic processing unit clusters. However, in addition to high cost, these approaches also suffer from poor energy efficiency compared to biological networks, which primarily perform low-precision analog computations and therefore consume much less energy. While CMOS analog circuits have been used in artificial neural networks, most CMOS-implemented synapses are too bulky given the large number of neurons and synapses.

[0006] The applicant previously disclosed an artificial (analog) neural network utilizing one or more non-volatile memory arrays as synapses in U.S. Patent Application No. 15 / 594,439, published as U.S. Patent Publication No. 2017 / 0337466, which is incorporated by reference. The non-volatile memory array operates as an analog neuromorphic memory. As used herein, the term neuromorphic refers to a circuit that implements a model of a nervous system. The analog neuromorphic memory includes a first plurality of synapses configured to receive a first plurality of inputs and generate a first plurality of outputs therefrom, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, each including spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending therebetween, a floating gate insulated above a first portion of the channel region, and a non-floating gate insulated above a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons in the floating gate. The plurality of memory cells are configured to multiply a first plurality of inputs by the stored weight values ​​to generate a first plurality of outputs. An array of memory cells arranged in this manner may be referred to as a vector matrix multiplication (VMM) array.

[0007] Each non-volatile memory cell used in a VMM array must be erased and programmed to retain a very specific and precise amount of charge, i.e., number of electrons, in its floating gate. For example, each floating gate must retain one of N different values, where N is the number of different weights that can be exhibited by each cell. Examples of N include 16, 32, 64, 128, and 256. One challenge is the ability to program selected cells with the precision and granularity required for different values ​​of N. For example, if a selected cell can contain one of 64 different values, extremely high precision is required in the program operation.

[0008] What is needed is an improved programming system and method suitable for use with VMM arrays in analog neuromorphic memories. Summary of the Invention

[0009] Numerous embodiments are disclosed of precision tuning algorithms and apparatus for precisely and rapidly depositing precise amounts of charge onto the floating gates of non-volatile memory cells in a VMM array in an analog neuromorphic memory system, so that selected cells can be programmed with great precision to hold one of N different values.

[0010] In one embodiment, the neural network includes a vector matrix multiplication array of nonvolatile memory cells, and weight values ​​w are stored as differential pairs w+ and w− of first and second nonvolatile memory cells in the array according to the formula w=(w+)-(w−), where w+ and w− include non-zero offset values.

[0011] In another embodiment, the neural network comprises a vector matrix multiplication array of non-volatile memory cells, the array organized into rows and columns of non-volatile memory cells, and weight values ​​w stored as differential pairs w+ and w− in first and second non-volatile memory cells according to the formula w=(w+)-(w−), where storage of the w+ and w− values ​​is distributed approximately evenly among all columns in the array.

[0012] In another embodiment, a method for programming, verifying, and reading zero values ​​in a differential pair of non-volatile memory cells in a vector matrix multiplication array includes programming a first cell w+ of the differential pair to a first current value, verifying the first cell by applying a voltage equal to a first voltage plus a bias voltage to a control gate terminal of the first cell, programming a second cell w− of the differential pair to the first current value, verifying the second cell by applying a voltage equal to the first voltage plus the bias voltage to the control gate terminal of the second cell, reading the first cell by applying a voltage equal to the first voltage to the control gate terminal of the first cell, reading the second cell by applying a voltage equal to the first voltage to the control gate terminal of the second cell, and calculating a value w according to the formula w=(w+)−(w−). 。

[0013] another In an embodiment, the neural network comprises a vector matrix multiplication array of non-volatile memory cells, the array organized into rows and columns of non-volatile memory cells, and weight values ​​w stored as a differential pair w+ and w− according to the formula w=(w+)-(w−), where w+ is stored as a differential pair of a first non-volatile memory cell and a second non-volatile memory cell in the array and w− is stored as a differential pair of a third non-volatile memory cell and a fourth non-volatile memory cell in the array, and the storage of w+ and w− is offset by a bias value.

[0014] In another embodiment, a neural network comprises a vector matrix multiplication array of non-volatile memory cells, the array organized into rows and columns of non-volatile memory cells, and weight values ​​w stored as differential pairs w+ and w− of first and second non-volatile memory cells according to the formula w=(w+)-(w−), where the value for w+ is selected from a first range of non-zero values ​​and the value for w− is selected from a second range of non-zero values, the first and second ranges not overlapping.

[0015] In another embodiment, a method for reading non-volatile memory cells in a vector matrix multiplication array includes reading a weight stored in a selected cell in the array, the reading step including applying a zero voltage bias to a control gate terminal of the selected cell and sensing a neuron output current comprising a current output from the selected cell.

[0016] In another embodiment, a method of operating non-volatile memory cells in a vector matrix multiplication array includes reading the non-volatile memory cells by applying a first bias voltage to a control gate of the non-volatile memory cell, and reading the non-volatile memory cells by applying the first bias voltage to the control gate of the non-volatile memory cell and applying a second bias voltage to the control gate of the non-volatile memory cell during one or more of a standby operation, a deep power down operation, or a test operation.

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[0070] [Brief explanation of the drawings]

[0071] [Figure 1] FIG. 1 illustrates a prior art artificial neural network. [Figure 2] 1 shows a prior art split-gate flash memory cell. [Figure 3] 1 illustrates another prior art split-gate flash memory cell. [Figure 4] 1 illustrates another prior art split-gate flash memory cell. [Figure 5] 1 illustrates another prior art split-gate flash memory cell. [Figure 6] 1 illustrates another prior art split-gate flash memory cell. [Figure 7] 1 shows a prior art stacked gate flash memory cell. [Figure 8] FIG. 1 illustrates various levels of an exemplary artificial neural network utilizing one or more VMM arrays. [Figure 9] FIG. 1 is a block diagram illustrating a VMM system including a VMM array and other circuits. [Figure 10] FIG. 1 is a block diagram illustrating an example artificial neural network utilizing one or more VMM systems. [Figure 11] 1 illustrates another embodiment of a VMM array. [Figure 12] 1 illustrates another embodiment of a VMM array. [Figure 13] 1 illustrates another embodiment of a VMM array. [Figure 14] 1 illustrates another embodiment of a VMM array. [Figure 15] 1 illustrates another embodiment of a VMM array. [Figure 16] 1 illustrates another embodiment of a VMM array. [Figure 17] 1 illustrates another embodiment of a VMM array. [Figure 18] 1 illustrates another embodiment of a VMM array. [Figure 19] 1 illustrates another embodiment of a VMM array. [Figure 20] 1 illustrates another embodiment of a VMM array. [Figure 21] 1 illustrates another embodiment of a VMM array. [Figure 22] 1 illustrates another embodiment of a VMM array. [Figure 23] 1 illustrates another embodiment of a VMM array. [Figure 24] 1 illustrates another embodiment of a VMM array. [Figure 25] 1 shows a prior art long-term memory system. [Figure 26] An exemplary cell for use in a long-term memory system is shown. [Figure 27] 27 illustrates one embodiment of the exemplary cell of FIG. 26. [Figure 28] 27 illustrates another embodiment of the exemplary cell of FIG. 26. [Figure 29] 1 shows a prior art gated recurrent unit system. [Figure 30] 1 shows an exemplary cell for use in a gated recurrent unit system. [Figure 31] 31 illustrates one embodiment of the exemplary cell of FIG. 30. [Figure 32] 31 illustrates another embodiment of the exemplary cell of FIG. 30. [Figure 33] 1 shows a VMM system. [Figure 34] The tuning correction method is shown. [Figure 35A] The tuning correction method is shown. [Figure 35B] A sector tuning correction method is shown. [Figure 36A] 1 shows the effect of temperature on the value stored in the cell. [Figure 36B] This paper shows the problems caused by data drift during the operation of a VMM system. [Figure 36C] 1 shows a block for compensating for data drift. [Figure 36D] 1 shows a data drift monitor. [Figure 37] 1 shows a bit line compensation circuit. [Figure 38] 1 illustrates another bit line compensation circuit. [Figure 39] 1 illustrates another bit line compensation circuit. [Figure 40] 1 illustrates another bit line compensation circuit. [Figure 41] 1 illustrates another bit line compensation circuit. [Figure 42] 1 illustrates another bit line compensation circuit. [Figure 43] Neuron circuits are shown. [Figure 44] Another neuron circuit is shown. [Figure 45] Another neuron circuit is shown. [Figure 46] Another neuron circuit is shown. [Figure 47] Another neuron circuit is shown. [Figure 48]Another neuron circuit is shown. [Figure 49A] A block diagram of an output circuit is shown. [Figure 49B] 10 shows a block diagram of another output circuit. [Figure 49C] 10 shows a block diagram of another output circuit. DETAILED DESCRIPTION OF THE INVENTION

[0072] The artificial neural network of the present invention utilizes a combination of CMOS technology and non-volatile memory arrays. Non-volatile memory cell

[0073] Digital nonvolatile memories are well known. For example, U.S. Pat. No. 5,029,130 ​​(the "'130 patent"), incorporated herein by reference, discloses an array of split-gate nonvolatile memory cells, a type of flash memory cell. Such a memory cell 210 is shown in FIG. 2. Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 between the source region 14 and the drain region 16. A floating gate 20 is formed over and insulated from a first portion of the channel region 18 (and controls the conductivity of the first portion of the channel region 18) and over a portion of the source region 14. A word line terminal 22 (typically coupled to a word line) has a first portion disposed over and insulated from a second portion of the channel region 18 (and controls the conductivity of the second portion of the channel region 18), and a second portion extending upward above the floating gate 20. The floating gate 20 and word line terminal 22 are insulated from the substrate 12 by a gate oxide. A bit line terminal 24 is coupled to the drain region 16.

[0074] The memory cell 210 is erased (electrons are removed from the floating gate) by applying a high positive voltage to the word line terminal 22, which causes electrons in the floating gate 20 to pass via Fowler-Nordheim tunneling from the floating gate 20 to the word line terminal 22 through the insulator between them.

[0075] The memory cell 210 is programmed (electrons are applied to the floating gate) by applying a positive voltage to the word line terminal 22 and a positive voltage to the source region 14. An electron current flows from the source region 14 (source line terminal) towards the drain region 16. The electrons accelerate and heat up when they reach the gap between the word line terminal 22 and the floating gate 20. Some of the heated electrons are injected into the floating gate 20 through the gate oxide due to electrostatic attraction from the floating gate 20.

[0076] The memory cell 210 is read by applying a positive read voltage to the drain region 16 and word line terminal 22 (turning on the portion of the channel region 18 below the word line terminal). When the floating gate 20 is positively charged (i.e., erased with electrons), the portion of the channel region 18 below the floating gate 20 is also turned on, and current flows through the channel region 18, which is sensed as an erased or "1" state. When the floating gate 20 is negatively charged (i.e., programmed with electrons), the portion of the channel region below the floating gate 20 is mostly or completely off, and no (or very little) current flows through the channel region 18, which is sensed as a programmed or "0" state.

[0077] Table 1 shows typical voltage ranges that may be applied to the terminals of memory cell 110 to perform read, erase, and program operations. Table 1: Operation of flash memory cell 210 of FIG. 2 [Table 1] "Read 1" is a read mode in which the cell current is output to the bit line. "Read 2" is a read mode in which the cell current is output to the source line terminal.

[0078] Figure 3 shows a memory cell 310 similar to memory cell 210 of Figure 2, with the addition of a control gate (CG) terminal 28. The control gate terminal 28 is biased at a high voltage (e.g., 10V) during programming, a low or negative voltage (e.g., 0V / -8V) during erasure, and a low or medium voltage (e.g., 0V / 2.5V) during reading. The other terminals are biased similarly to the terminals of Figure 2.

[0079] FIG. 4 shows a four-gate memory cell 410 comprising a source region 14, a drain region 16, a floating gate 20 above a first portion of a channel region 18, a select gate 22 (typically coupled to a word line, WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Pat. No. 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates, except for the floating gate 20, are non-floating gates, i.e., they are electrically connected or connectable to a voltage source. Programming is performed by heated electrons injecting themselves from the channel region 18 into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0080] Table 2 shows typical voltage ranges that may be applied to the terminals of memory cell 410 to perform read, erase, and program operations. Table 2: Operation of flash memory cell 410 of FIG. 4 [Table 2] "Read 1" is a read mode in which the cell current is output to the bit line. "Read 2" is a read mode in which the cell current is output to the source line terminal.

[0081] 5 shows a memory cell 510 similar to memory cell 410 of FIG. 4, except that memory cell 510 does not include an erase gate EG terminal. Erasing is performed by biasing substrate 18 to a high voltage and control gate CG terminal 28 to a low or negative voltage. Alternatively, erasing is performed by biasing word line terminal 22 to a positive voltage and control gate terminal 28 to a negative voltage. Programming and reading are similar to those of FIG. 4.

[0082] Figure 6 shows another type of flash memory cell, a three-gate memory cell 610. Memory cell 610 is identical to memory cell 410 of Figure 4, except that memory cell 610 does not have a separate control gate terminal. Erase and read operations (erasure occurs through use of the erase gate terminal) are similar to those of Figure 4, except that no control gate bias is applied. Programming operations are also performed without a control gate bias, and as a result, a higher voltage must be applied to the source line terminal during a program operation to compensate for the lack of control gate bias.

[0083] Table 3 shows typical voltage ranges that may be applied to the terminals of memory cell 610 to perform read, erase, and program operations. Table 3: Operation of Flash Memory Cell 610 of FIG. 6 [Table 3] "Read 1" is a read mode in which the cell current is output to the bit line. "Read 2" is a read mode in which the cell current is output to the source line terminal.

[0084] Figure 7 shows another type of flash memory cell, a stacked gate memory cell 710. Memory cell 710 is similar to memory cell 210 of Figure 2, except that the floating gate 20 extends over the entire channel region 18, and a control gate terminal 22 (coupled to a word line) extends above the floating gate 20, separated by an insulating layer (not shown). Erase, programming, and read operations operate in a similar manner to those described above for memory cell 210.

[0085] Table 4 shows typical voltage ranges that may be applied to the terminals of memory cell 710 and substrate 12 to perform read, erase, and program operations. Table 4: Operation of Flash Memory Cell 710 of FIG. 7 [Table 4]

[0086] "Read 1" is a read mode in which the cell current is output to a bit line. "Read 2" is a read mode in which the cell current is output to a source line terminal. Optionally, in an array including rows and columns of memory cells 210, 310, 410, 510, 610, or 710, a source line may be coupled to one row of memory cells or two adjacent rows of memory cells. That is, a source line terminal may be shared by adjacent rows of memory cells.

[0087] In order to utilize a memory array containing one of the types of non-volatile memory cells in the above artificial neural network, two modifications are made. First, as explained further below, the lines are configured so that each memory cell can be individually programmed, erased, and read without adversely affecting the memory state of other memory cells in the array. Second, continuous (analog) programming of the memory cells is provided.

[0088] Specifically, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed continuously from a fully erased state to a fully programmed state, independently and with minimal disturbance to other memory cells. In another embodiment, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed continuously from a fully programmed state to a fully erased state, and vice versa, independently and with minimal disturbance to other memory cells. This means that the cell storage is analog, or at a minimum, capable of storing one of a number of discrete values ​​(such as 16 or 64 different values), making every cell in the memory array very precisely and individually tunable and making the memory array ideal for storage and for fine tuning adjustments to the synaptic weights of neural networks.

[0089] The methods and means described herein can be applied to other non-volatile memory technologies such as, but not limited to, SONOS (silicon-oxide-nitride-oxide-silicon, charge trap in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge trap in nitride), ReRAM (resistive RAM), PCM (phase change memory), MRAM (magnetic RAM), FeRAM (ferroelectric RAM), OTP (bi-level or multi-level one time programmable) and CeRAM (correlated electron RAM). The methods and techniques described herein can be applied to volatile memory technologies used in neural networks, such as, but not limited to, SRAM, DRAM, and other volatile synapse cells. Neural networks using nonvolatile memory cell arrays

[0090] 8 conceptually illustrates a non-limiting example of a neural network utilizing the non-volatile memory array of the present embodiments. This example uses a non-volatile memory array neural network for a face recognition application, although other suitable applications can also be implemented using a non-volatile memory array-based neural network.

[0091] S0 is the input layer, which in this example is a 32x32 pixel RGB image with 5-bit precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, with each pixel having 5-bit precision). Synapse CB1 going from input layer S0 to layer C1 scans the input image with overlapping 3x3 pixel filters (kernels), applying different sets of weights to some instances and shared weights to other instances, and shifts the filters by one pixel (or two or more pixels, depending on the model). Specifically, the values ​​of nine pixels in the 3x3 portion of the image (i.e., referred to as filters or kernels) are provided to synapse CB1, which multiplies these nine input values ​​by the appropriate weights and sums the outputs of the multiplications to determine a single output value, which is provided by the first synapse of CB1 to generate one pixel of the layer of feature map C1. The 3x3 filter is then shifted one pixel to the right in input layer S0 (i.e., adding a column of three pixels to the right and dropping a column of three pixels on the left), so that the nine pixel values ​​of this newly positioned filter are provided to synapse CB1, where they are multiplied by the same weights as above to determine a second single output value by the associated synapse. This process continues until the 3x3 filter has scanned the entire 32x32 pixel image of input layer S0 for all three colors and all bits (precision values). The process is then repeated using different sets of weights to generate different feature maps for C1 until all of the feature maps for layer C1 have been calculated.

[0092] In this example, there are 16 feature maps in layer C1, each having 30x30 pixels. Each pixel is a new feature pixel extracted from the multiplication of the input and the kernel, and therefore each feature map is a two-dimensional array. Thus, in this example, layer C1 comprises 16 layers of two-dimensional arrays. (Note that the layers and arrays referred to herein are logical, not necessarily physical, relationships; i.e., the arrays are not necessarily oriented in a physical two-dimensional array.) Each of the 16 feature maps in layer C1 is generated by one of 16 different sets of synaptic weights applied to the filter scans. The C1 feature maps can all target different aspects of the same image feature, such as boundary identification. For example, a first map (generated using a first set of weights shared by all scans used to generate this first map) can identify circular edges, while a second map (generated using a second set of weights different from the first set of weights) can identify rectangular edges or the aspect ratio of a particular feature, etc.

[0093] Before going from layer C1 to layer S1, an activation function P1 (pooling) is applied, which pools values ​​from non-overlapping, contiguous 2x2 regions within each feature map. The purpose of the pooling function is to average nearby locations (or a max function can be used), e.g., to reduce dependency on edge locations, and to reduce data size before going to the next stage. In layer S1, there are 16 15x15 feature maps (i.e., 16 different arrays of 15x15 pixels each). Synapse CB2 going from layer S1 to layer C2 scans the maps in S1 with a 4x4 filter with a filter shift of 1 pixel. In layer C2, there are 22 12x12 feature maps. Before going from layer C2 to layer S2, an activation function P2 (pooling) is applied, which pools values ​​from non-overlapping, contiguous 2x2 regions within each feature map. In layer S2, there are 22 6x6 feature maps. At synapse CB3 going from layer S2 to layer C3, an activation function (pooling) is applied, where every neuron in layer C3 connects to every map in layer S2 through a respective synapse in CB3. There are 64 neurons in layer C3. Synapse CB4 going from layer C3 to output layer S3 fully connects C3 to S3, i.e., every neuron in layer C3 connects to every neuron in layer S3. The output at S3 includes 10 neurons, where the neuron with the highest output determines the class. This output can indicate, for example, the identification or classification of the content of the original image.

[0094] Each layer of the synapse is implemented using an array or portion of an array of non-volatile memory cells.

[0095] Figure 9 is a block diagram of a system that can be used for this purpose. The VMM system 32 includes non-volatile memory cells and is used to store the synapses (Fig. 81. In particular, the VMM system 32 includes a VMM array 33 having nonvolatile memory cells arranged in rows and columns, an erase gate and word line gate decoder 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37, which decode respective inputs to the nonvolatile memory cell array 33. Inputs to the VMM array 33 can come from the erase gate and word line gate decoder 34 or from the control gate decoder 35. The source line decoder 37 in this example also decodes the output of the VMM array 33. Alternatively, the bit line decoder 36 can decode the output of the VMM array 33.

[0096] The VMM array 33 serves two purposes. First, it stores the weights used by the VMM system 32. Second, it effectively multiplies the inputs by the weights stored in the VMM array 33 and sums them for each output line (source line or bit line) to produce an output, which becomes the input to the next layer or the input to the last layer. By performing multiplication and addition functions, the VMM array 33 eliminates the need for separate multiplication and addition logic and is also power efficient due to in-place memory computation.

[0097] The outputs of the VMM array 33 are fed to a differential summer (such as a summing op-amp or summing current mirror) 38, which sums the outputs of the VMM array 33 to create a single value for the convolution. The differential summer 38 is arranged to perform a summation of both the positive and negative weight inputs to output a single value.

[0098] The summed output values ​​of the differential summer 38 are then provided to an activation function circuit 39, which rectifies the output. The activation function circuit 39 may provide a sigmoid function, a tanh function, a ReLU function, or any other nonlinear function. The rectified output values ​​of the activation function circuit 39 become elements of the feature map of the next layer (e.g., C1 in FIG. 8) and are then applied to the next synapse to generate the next feature map layer or the final layer. Thus, in this example, the VMM array 33 comprises multiple synapses (receiving input from a previous layer of neurons or from an input layer such as an image database), and the summer 38 and activation function circuit 39 comprise multiple neurons.

[0099] The inputs to the VMM system 32 of FIG. 9 (WLx, EGx, CGx, and optionally BLx and SLx) may be analog levels, binary levels, digital pulses (in which case a pulse-to-analog converter PAC may be required to convert the pulses to appropriate input analog levels) or digital bits (in which case a DAC is provided to convert the digital bits to appropriate input analog levels), and the outputs may be analog levels, binary levels, digital pulses, or digital bits (in which case an output ADC is provided to convert the output analog levels to digital bits).

[0100] FIG. 10 is a block diagram illustrating the use of multiple layers of VMM system 32, labeled in the figure as VMM systems 32a, 32b, 32c, 32d, and 32e. As shown in FIG. 10, input (denoted Inputx) is converted from digital to analog by digital-to-analog converter 31 and provided to input VMM system 32a. The converted analog input can be a voltage or current. The first layer of input D / A conversion can be performed by using a function or LUT (look-up table) that maps input Inputx to the appropriate analog level of the matrix multiplier of input VMM system 32a. Input conversion can also be performed by an analog-to-analog (A / A) converter to convert an external analog input to a mapped analog input to input VMM system 32a. Input conversion can also be performed by a digital-to-digital pulse (D / P) converter to convert an external digital input to a mapped digital pulse to input VMM system 32a.

[0101] The output generated by input VMM system 32a is then provided as input to the next VMM system (hidden level 1) 32b, which then generates an output that is provided as input to input VMM system (hidden level 2) 32c, and so on. The various layers of VMM system 32 function as layers of synapses and neurons of a convolutional neural network (CNN). Each VMM system 32a, 32b, 32c, 32d, and 32e can be a standalone physical system with a corresponding non-volatile memory array, or multiple VMM systems can utilize different portions of the same physical non-volatile memory array, or multiple VMM systems can utilize overlapping portions of the same physical non-volatile memory array. Each VMM system 32a, 32b, 32c, 32d, and 32e can also be time-multiplexed to various portions of its array or neurons. The example shown in Figure 10 includes five layers (32a, 32b, 32c, 32d, 32e): one input layer (32a), two hidden layers (32b, 32c), and two fully connected layers (32d, 32e). Those skilled in the art will appreciate that this is merely an example and that the system may alternatively include more than two hidden layers and more than two fully connected layers. VMM Array

[0102] 11 shows a neuron VMM array 1100 that is particularly suited for the memory cells 310 shown in FIG. 3 and that is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 1100 includes a memory array 1101 of non-volatile memory cells and a reference array 1102 of non-volatile reference memory cells (located at the top of the array). Alternatively, a separate reference array can be located at the bottom.

[0103] In VMM array 1100, control gate lines, such as control gate line 1103, run vertically (thus row-oriented reference array 1102 is orthogonal to control gate line 1103), and erase gate lines, such as erase gate line 1104, run horizontally. Here, inputs to VMM array 1100 are provided to control gate lines (CG0, CG1, CG2, CG3), and outputs of VMM array 1100 appear on source lines (SL0, SL1). In one embodiment, only even rows are used, and in another embodiment, only odd rows are used. The current in each source line (SL0, SL1, respectively) is a function of the sum of all currents from memory cells connected to that particular source line.

[0104] As described herein for neural networks, the non-volatile memory cells of VMM array 1100, ie, the flash memory of VMM array 1100, are preferably configured to operate in the sub-threshold region.

[0105] The nonvolatile reference memory cells and nonvolatile memory cells described herein are biased in weak inversion as follows: Ids=Io * e (Vg-Vth) / nVt =w * Io * e (Vg) / nVt In the formula, w=e (-Vth) / nVt and where Ids is the drain-source current, Vg is the gate voltage of the memory cell, Vth is the threshold voltage of the memory cell, and Vt is the thermal voltage = k * where T / q, k is Boltzmann's constant, T is temperature in Kelvin, q is the electron charge, n is the slope coefficient = 1 + (Cdep / Cox), where Cdep = capacitance of the depletion layer, and Cox is the capacitance of the gate oxide layer, Io is the memory cell current at a gate voltage equal to the threshold voltage, and Io is (Wt / L) * u * Cox * (n-1) * Vt 2where u is the carrier mobility, and Wt and L are the width and length of the memory cell, respectively.

[0106] If an IV log converter is used that uses a memory cell (such as a reference memory cell or a peripheral memory cell) or transistor to convert the input current Ids to an input voltage Vg, then Vg is: Vg=n * Vt * log[Ids / wp * Io] where wp is the w of the reference or peripheral memory cell.

[0107] If an IV log converter is used that uses a memory cell (such as a reference memory cell or a peripheral memory cell) or transistor to convert the input current Ids to an input voltage Vg, then Vg is: Vg=n * Vt * log[Ids / wp * Io]

[0108] where wp is the w of the reference or peripheral memory cell.

[0109] For a memory array used as a vector matrix multiplier VMM array, the output current is: Iout=wa * Io * e (Vg) / nVt , i.e. Iout=(wa / wp) * Iin=W * Iin W=e (Vthp-Vtha) / nVt Iin=wp * Io * e (Vg) / nVt where wa=w of each memory cell in the memory array.

[0110] The word line or control gate can be used as the input of the memory cell for the input voltage.

[0111] Alternatively, the non-volatile memory cells of the VMM arrays described herein can be configured to operate in the linear region. Ids=Beta * (Vgs-Vth) * Vds, beta = u * Cox * Wt / L, W ∝ (Vgs-Vth) That is, the weight W in the linear region is proportional to (Vgs-Vth).

[0112] The word line or control gate or bit line or source line can be used as the input of a memory cell operating in the linear region, and the bit line or source line can be used as the output of the memory cell.

[0113] For the IV linear converter, memory cells (such as reference or peripheral memory cells) or transistors operating in the linear region, or resistors can be used to linearly convert input and output currents to input and output voltages.

[0114] Alternatively, the memory cells of the VMM arrays described herein can be configured to operate in the saturation region. Ids= 1 / 2 * beta * (Vgs-Vth) 2 , beta = u * Cox * Wt / L W ∝ (Vgs-Vth) 2 , that is, the weight W is (Vgs-Vth) 2 is proportional to.

[0115] The word line, control gate, or erase gate can be used as the input of a memory cell operating in the saturation region, and the bit line or source line can be used as the output of an output neuron.

[0116] Alternatively, the memory cells of the VMM arrays described herein can be used in all regions or combinations thereof (subthreshold, linear, or saturation).

[0117] Other embodiments for the VMM array 33 of Figure 9 are described in U.S. patent application Ser. No. 15 / 826,345, which is incorporated herein by reference. As described in that application, the source lines or bit lines can be used as neuron outputs (current sum outputs).

[0118] FIG. 12 shows a neuron VMM array 1200 particularly suited for the memory cells 210 shown in FIG. 2 and utilized as synapses between the input layer and the next layer. The VMM array 1200 includes a memory array 1203 of nonvolatile memory cells, a reference array 1201 of first nonvolatile reference memory cells, and a reference array 1202 of second nonvolatile reference memory cells. The reference arrays 1201 and 1202, arranged in columns of the array, function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first and second nonvolatile reference memory cells are diode-connected through multiplexer 1214 (only a portion of which is shown) with current inputs flowing into them. The reference cells are tuned (e.g., programmed) to target reference levels, which are provided by a reference mini-array matrix (not shown).

[0119] Memory array 1203 serves two purposes. First, memory array 1203 stores the weights used by VMM array 1200 in each memory cell. Second, memory array 1203 effectively multiplies the inputs (i.e., the current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which reference arrays 1201 and 1202 convert to input voltages and provide to word lines WL0, WL1, WL2, and WL3) by the weights stored in memory array 1203, and then adds all the results (memory cell currents) to generate outputs for each bit line (BL0-BLN), which serve as inputs to the next layer or the last layer. By performing the multiplication and addition functions, memory array 1203 eliminates the need for separate multiplication and addition logic and is also power efficient. Here, voltage inputs are provided to word lines WL0, WL1, WL2, and WL3, and outputs appear on respective bit lines BL0-BLN during a read (inference) operation. The current in each of the bit lines BL0-BLN performs a function of the sum of the currents from all the non-volatile memory cells connected to that particular bit line.

[0120] Table 5 shows the operating voltages for VMM array 1200. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cell, the bit lines of the unselected cells, the source lines of the selected cell, and the source lines of the unselected cells, and FLT indicates floating, i.e., no voltage is applied. The rows indicate read, erase, and program operations. Table 5: Operation of VMM Array 1200 in Figure 12 [Table 5]

[0121] FIG. 13 shows a neuron VMM array 1300 that is particularly suited for the memory cells 210 shown in FIG. 2 and that is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 1300 includes a memory array 1303 of nonvolatile memory cells, a reference array 1301 of first nonvolatile reference memory cells, and a reference array 1302 of second nonvolatile reference memory cells. The reference arrays 1301 and 1302 extend in the row direction of the VMM array 1300. The VMM array is similar to the VMM 1000, except that word lines extend vertically in the VMM array 1300. Here, inputs are provided to the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3), and outputs appear on the source lines (SL0, SL1) during a read operation. The current in each source line performs a function of the sum of all the currents from the memory cells connected to that particular source line.

[0122] Table 6 shows the operating voltages for VMM array 1300. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cell, the bit lines of the unselected cells, the source lines of the selected cell, and the source lines of the unselected cells. The rows indicate the read, erase, and program operations. Table 6: Operation of VMM Array 1300 in Figure 13 [Table 6]

[0123] 14 shows a neuron VMM array 1400 that is particularly suited for the memory cells 310 shown in FIG. 3 and that is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 1400 includes a memory array 1403 of nonvolatile memory cells, a reference array 1401 of first nonvolatile reference memory cells, and a reference array 1402 of second nonvolatile reference memory cells. The reference arrays 1401 and 1402 function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In effect, the first and second nonvolatile reference memory cells are diode-connected through a multiplexer 1412 (only a portion of which is shown), with the current inputs flowing through BLR0, BLR1, BLR2, and BLR3. Multiplexer 1412 includes a corresponding multiplexer 1405 and cascoding transistor 1404 to ensure a constant voltage on each bit line (e.g., BLR0) of the first and second non-volatile reference memory cells during a read operation, where the reference cells are tuned to a target reference level.

[0124] Memory array 1403 serves two purposes. First, memory array 1203 stores the weights used by VMM array 1400. Second, memory array 1403 effectively multiplies the weights stored in the memory array by the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3; reference arrays 1401 and 1402 convert these current inputs to input voltages provided to control gates (CG0, CG1, CG2, and CG3)), and then adds all the results (cell currents) to generate an output that appears on BL0-BLN and serves as the input to the next layer or the last layer. Having the memory array perform the multiplication and addition functions eliminates the need for separate multiplication and addition logic and is also power efficient. Here, the inputs are provided to the control gate lines (CG0, CG1, CG2, and CG3) and the outputs appear on the bit lines (BL0-BLN) during read operations. The current in each bit line is a function of the sum of all the currents from the memory cells connected to that particular bit line.

[0125] The VMM array 1400 implements one-way tuning of the non-volatile memory cells in the memory array 1403. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. This can be done, for example, using the precision programming techniques described below. If too much charge is added to the floating gate (resulting in an incorrect value being stored in the cell), the cell must be erased and the series of partial programming operations must be redone. As shown, two rows that share the same erase gate (such as EG0 or EG1) must be erased together (known as a page erase), and then each cell is partially programmed until the desired charge on the floating gate is reached.

[0126] Table 7 shows the operating voltages for VMM array 1400. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit line of the selected cell, the bit lines of the unselected cells, the control gate of the selected cell, the control gates of the unselected cells in the same sector as the selected cell, the control gates of the unselected cells in a different sector from the selected cell, the erase gate of the selected cell, the erase gates of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows indicate read, erase, and program operations. Table 7: Operation of the VMM Array 1400 in Figure 14 [Table 7]

[0127] FIG. 15 shows a neuron VMM array 1500 that is particularly suited for the memory cells 310 shown in FIG. 3 and that is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 1500 includes a memory array 1503 of nonvolatile memory cells, a reference array 1501 or first nonvolatile reference memory cells, and a reference array 1502 of second nonvolatile reference memory cells. EG lines EGR0, EG0, EG1, and EGR1 extend vertically, while CG lines CG0, CG1, CG2, and CG3 and SL lines WL0, WL1, WL2, and WL3 extend horizontally. The VMM array 1500 is similar to the VMM array 1400, except that the VMM array 1500 implements bidirectional tuning: each individual cell can be fully erased, partially programmed, and, if necessary, partially erased to reach a desired amount of charge on the floating gate through the use of separate EG lines. As shown, reference arrays 1501 and 1502 convert input currents at terminals BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 (through the action of diode-connected reference cells via multiplexer 1514), which are applied to the memory cells in the row direction. The current outputs (neurons) are in bit lines BL0 through BLN, each bit line summing all the currents from the non-volatile memory cells connected to that particular bit line.

[0128] Table 8 shows the operating voltages for VMM array 1500. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit line of the selected cell, the bit lines of the unselected cells, the control gate of the selected cell, the control gates of the unselected cells in the same sector as the selected cell, the control gates of the unselected cells in a different sector from the selected cell, the erase gate of the selected cell, the erase gates of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows indicate read, erase, and program operations. Table 8: Operation of VMM Array 1500 in Figure 15 [Table 8]

[0129] 16 shows a neuron VMM array 1600 that is particularly suited for the memory cells 210 shown in FIG. 2 and that is used as part of the synapses and neurons between the input layer and the next layer. In the VMM array 1600, inputs INPUT0...., INPUT N are bit lines BL0, ...BL N and outputs OUTPUT1, OUTPUT2, OUTPUT3, and OUTPUT4 are generated on source lines SL0, SL1, SL2, and SL3, respectively.

[0130] 17 shows a neuron VMM array 1700 that is particularly suited for memory cells 210 shown in FIG. 2 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, INPUT1, INPUT2, and INPUT3 are received on source lines SL0, SL1, SL2, and SL3, respectively, and outputs OUTPUT0, ...OUTPUT N are the bit lines BL0, ..., BL N is generated.

[0131] 18 shows a neuron VMM array 1800 that is particularly suited for the memory cells 210 shown in FIG. 2 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0,..., INPUT M are the word lines WL0, ..., WL M OUTPUT0, ...OUTPUT N are the bit lines BL0, ..., BL N is generated.

[0132] 19 shows a neuron VMM array 1900 that is particularly suited for the memory cells 310 shown in FIG. 3 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0,..., INPUT M are the word lines WL0, ..., WL M OUTPUT0, ...OUTPUTN are the bit lines BL0, ..., BL N is generated.

[0133] 20 shows a neuron VMM array 2000 that is particularly suited for the memory cells 410 shown in FIG. 4 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0,..., INPUT n are the vertical control gate lines CG0, ..., CG N and outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0134] 21 shows a neuron VMM array 2100 that is particularly suited for the memory cells 410 shown in FIG. 4 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0,..., INPUT N are the bit lines BL0, ..., BL N , 2901-(N-1) and 2901-N, which are coupled to the source lines SL0 and SL1, respectively. Exemplary outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0135] 22 shows a neuron VMM array 2200 that is particularly suited to memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the word lines WL0, ..., WL M Received and output OUTPUT0, ..., OUTPUT N are the bit lines BL0, ..., BL N are generated respectively.

[0136] 23 shows a neuron VMM array 2300 that is particularly suited to memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the control gate lines CG0, ..., CG M Received by Output OUTPUT0, ..., OUTPUT N are the vertical source lines SL0, ..., SL N are generated on each source line SL i is coupled to the source lines of all memory cells in column i.

[0137] 24 shows a neuron VMM array 2400 that is particularly suited to memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the control gate lines CG0, ..., CG M Received by Output OUTPUT0, ..., OUTPUT N are the vertical bit lines BL0, ..., BL N and each bit line BL i is coupled to the bit lines of all memory cells in column i. Long- and short-term memory

[0138] Prior art includes a concept known as long short-term memory (LSTM). LSTMs are often used in artificial neural networks. LSTMs allow artificial neural networks to remember information for any given period of time and use that information in subsequent operations. A traditional LSTM includes a cell, an input gate, an output gate, and a forget gate. The three gates regulate the flow of information into and out of the cell and the length of time information is stored within the LSTM. VMMs are particularly useful in LSTMs.

[0139] Figure 25 shows an example LSTM 2500. LSTM 2500 in this example includes cells 2501, 2502, 2503, and 2504. Cell 2501 receives input vector x0 and generates output vector h0 and cell state vector c0. Cell 2502 receives input vector x1, output vector (hidden state) h0 from cell 2501, and cell state c0 from cell 2501, and generates output vector h1 and cell state vector c1. Cell 2503 receives input vector x2, output vector (hidden state) h1 from cell 2502, and cell state c1 from cell 2502, and generates output vector h2 and cell state vector c2. Cell 2504 receives input vector x3, output vector (hidden state) h2 from cell 2503, and cell state c2 from cell 2503, and generates output vector h3. Additional cells can be used; an LSTM with four cells is just an example.

[0140] Figure 26 shows an example implementation of an LSTM cell 2600 that can be used for cells 2501, 2502, 2503, and 2504 in Figure 25. LSTM cell 2600 receives an input vector x(t), a cell state vector c(t-1) from a previous cell, and an output vector h(t-1) from a previous cell, and produces a cell state vector c(t) and an output vector h(t).

[0141] LSTM cell 2600 includes sigmoid function devices 2601, 2602, and 2603, each of which applies a number between 0 and 1 to control the degree to which each component of the input vector contributes to the output vector. LSTM cell 2600 also includes tanh devices 2604 and 2605 for applying a hyperbolic tangent function to the input vector, multiplier devices 2606, 2607, and 2608 for multiplying two vectors, and adder device 2609 for adding the two vectors. The output vector h(t) can be provided to the next LSTM cell in the system or can be accessed for other purposes.

[0142] 27 shows LSTM cell 2700, which is an example of one implementation of LSTM cell 2600. For the convenience of the reader, the same numbering scheme from LSTM cell 2600 is used in LSTM cell 2700. Sigmoid function devices 2601, 2602, and 2603 and tanh device 2604 each include multiple VMM arrays 2701 and activation circuit blocks 2702. VMM arrays may therefore prove particularly useful in LSTM cells used in certain neural network systems.

[0143] An alternative example of LSTM cell 2700 (and another example of one implementation of LSTM cell 2600) is shown in Figure 28. In Figure 28, sigmoid function devices 2601, 2602, and 2603 and tanh device 2604 may share the same physical hardware (VMM array 2801 and activation function block 2802) in a time-multiplexed manner. LSTM cell 2800 also includes a multiplier device 2803 for multiplying two vectors, an adder device 2808 for adding two vectors, a tanh device 2605 (including activation circuit block 2802), a register 2807 for storing the value i(t) as it is output from sigmoid function block 2802, and a value f(t). * a register 2804 for storing c(t-1) as its value is output from the multiplier device 2803 via multiplexer 2810; * a register 2805 for storing u(t) as its value is output from the multiplier device 2803 via a multiplexer 2810; and a register 2805 for storing the value o(t) * It includes a register 2806 for storing {tilde over (c)}(t) as its value is output from the multiplier device 2803 via a multiplexer 2810, and a multiplexer 2809.

[0144] While LSTM cell 2700 includes multiple sets of VMM arrays 2701 and respective activation function blocks 2702, LSTM cell 2800 includes only one set of VMM arrays 2801 and activation function blocks 2802, which are used to represent multiple layers in embodiments of LSTM cell 2800. LSTM cell 2800 requires less space than LSTM cell 2700 because LSTM cell 2800 requires one-quarter the space for the VMMs and activation function blocks compared to LSTM cell 2700.

[0145] It can be further appreciated that an LSTM unit typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as adder and activation circuit blocks and high voltage generation blocks. Providing a separate circuit block for each VMM array would require a significant amount of space within a semiconductor device and would be somewhat inefficient. Therefore, the embodiments described below attempt to minimize the circuitry required outside the VMM array itself. Gated Recurrent Unit

[0146] Analog VMM implementations can utilize gated recurrent units (GRUs), which are gating mechanisms within recurrent artificial neural networks. GRUs are similar to LSTMs, except that GRU cells generally contain fewer components than LSTM cells.

[0147] Figure 29 shows an example GRU 2900. GRU 2900 in this example includes cells 2901, 2902, 2903, and 2904. Cell 2901 receives input vector x0 and generates output vector h0. Cell 2902 receives input vector x1 and output vector h0 from cell 2901 and generates output vector h1. Cell 2903 receives input vector x2 and output vector (hidden state) h1 from cell 2902 and generates output vector h2. Cell 2904 receives input vector x3 and output vector (hidden state) h2 from cell 2903 and generates output vector h3. Additional cells can be used; a GRU with four cells is merely an example.

[0148] FIG. 30 shows an example implementation of a GRU cell 3000 that can be used for cells 2901, 2902, 2903, and 2904 of FIG. 29. GRU cell 3000 receives an input vector x(t) and an output vector h(t-1) from a preceding GRU cell and generates an output vector h(t). GRU cell 3000 includes sigmoid function devices 3001 and 3002, each of which applies a number between 0 and 1 to components from the output vector h(t-1) and the input vector x(t). GRU cell 3000 also includes a tanh device 3003 for applying a hyperbolic tangent function to the input vector, multiple multiplier devices 3004, 3005, and 3006 for multiplying two vectors, an adder device 3007 for adding the two vectors, and a complement device 3008 for subtracting the input from 1 to generate the output.

[0149] Figure 31 shows GRU cell 3100, which is an example of one implementation of GRU cell 3000. For the convenience of the reader, the same numbering scheme as GRU cell 3000 is used in GRU cell 3100. As can be seen from Figure 31, sigmoid function devices 3001 and 3002 and tanh device 3003 each include multiple VMM arrays 3101 and activation function blocks 3102. It can therefore be seen that VMM arrays are particularly used in GRU cells used in certain neural network systems.

[0150] An alternative example of GRU cell 3100 (and another example of one implementation of GRU cell 3000) is shown in FIG. 32. In FIG. 32, GRU cell 3200 utilizes VMM array 3201 and activation function block 3202, which, when configured as a sigmoid function, applies a number between 0 and 1 to control the degree to which each component of the input vector contributes to the output vector. In FIG. 32, sigmoid function devices 3001 and 3002 and tanh device 3003 share the same physical hardware (VMM array 3201 and activation function block 3202) in a time-multiplexed manner. GRU cell 3200 also includes multiplier device 3203 for multiplying two vectors, adder device 3205 for adding two vectors, complement device 3209 for subtracting the input from 1 to generate the output, multiplexer 3204, and value h(t-1). * a register 3206 for holding r(t) as its value is output from the multiplier device 3203 via multiplexer 3204; and a value h(t-1) * a register 3207 for holding z(t) as its value is output from the multiplier device 3203 via multiplexer 3204; and a register 3208 for holding the value ĥ(t) * and a register 3208 for holding (1-z((t)) as its value is output from the multiplier device 3203 via multiplexer 3204.

[0151] While GRU cell 3100 includes multiple sets of VMM array 3101 and activation function block 3102, GRU cell 3200 includes only one set of VMM array 3201 and activation function block 3202, which are used to represent multiple layers in embodiments of GRU cell 3200. GRU cell 3200 requires one-third the space for the VMM and activation function block compared to GRU cell 3100, so GRU cell 3200 requires less space than GRU cell 3100.

[0152] It can be further appreciated that a system utilizing a GRU typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as adder and activation circuit blocks and high voltage generation blocks. Providing a separate circuit block for each VMM array would require a significant amount of space within a semiconductor device and would be somewhat inefficient. Therefore, the embodiments described below attempt to minimize the circuitry required outside the VMM array itself.

[0153] The input to the VMM array can be analog levels, binary levels, timing pulses, or digital bits, and the output can be analog levels, binary levels, timing pulses, or digital bits (in this case, an output ADC is required to convert the output analog level current or voltage to digital bits).

[0154] For each memory cell in the VMM array, each weight w can be implemented by a single memory cell, by a differential cell, or by two blended memory cells (an average of two or more cells). In the case of differential cells, two memory cells are required to implement weight w as a differential weight (w = w + - w -). In the case of two blended memory cells, two memory cells are required to implement weight w as an average of two cells. Embodiments for fine tuning of cells in a VMM

[0155] 33 shows a block diagram of a VMM system 3300. The VMM system 3300 includes a VMM array 3301, a row decoder 3302, a high-voltage decoder 3303, a column decoder 3304, a bit line driver 3305, input circuits 3306, output circuits 3307, control logic 3308, and a bias generator 3309. The VMM system 3300 further includes a high-voltage generation block 3310, which includes a charge pump 3311, a charge pump regulator 3312, and a high-voltage level generator 3313. The VMM system 3300 further includes an algorithm controller 3314, analog circuits 3315, control logic 3316, and test control logic 3317. The systems and methods described below can be implemented in the VMM system 3300.

[0156] The input circuit 3306 may include circuits such as a DAC (digital to analog converter) (digital-to-analog converter), a DPC (digital to pulses converter) (digital-to-pulse converter), an AAC (analog to analog converter) (analog-to-analog converter such as a current-to-voltage converter), a PAC (pulse to analog level converter), or any other type of converter. The input circuit 3306 may implement a normalization function, a scaling function, or an arithmetic function. The input circuit 3306 may implement a temperature compensation function for the input. The input circuit 3306 may implement an activation function such as a ReLU or a sigmoid function.

[0157] The output circuit 3307 may include circuits such as an ADC (analog-to-digital converter for converting neuron analog outputs to digital bits), an AAC (analog converter such as a current-to-voltage converter), an APC (analog-to-pulse converter), or any other type of converter. The output circuit 3307 may implement activation functions such as ReLU or sigmoid functions. The output circuit 3307 may implement normalization, scaling, or arithmetic functions for the neuron outputs. The output circuit 3307 may implement temperature compensation functions for the neuron outputs or array outputs (such as bit line outputs), as described below.

[0158] 34 illustrates a tuning (target programming or erasing of memory cells) correction method 3400 that may be performed by algorithm controller 3314 in VMM system 3300. Tuning correction method 3400 generates an adaptive target based on the cell output and a final error resulting from the cell's original target. The method typically begins in response to a tuning command being received (step 3401). An initial current target Itargetv(i) (used in the program / verify algorithm) for a selected cell or group of selected cells is determined using a predictive target model, such as by using a function or lookup table, and a variable DeltaError is set to 0 (step 3402). The target function, if used, will be based on the IV program curve of the selected memory cell or group of cells. The target function also depends on the degree of program anomalies the cell exhibits (depending on the cell address and cell level within the sector, where the cell is subjected to more program time in the inhibit condition if it exhibits relatively more anomalies, where cells with higher currents typically have more anomalies), various variations caused by array characteristics such as cell-to-cell coupling, and various types of array noise. These variations can be characterized on silicon over PVT (process, voltage, temperature). Lookup tables, if used, can be characterized in the same way to emulate IV curves and various variations.

[0159] Next, soft erasure is performed on all cells in the VMM. This soft erasure erases all cells to an intermediate weak erasure level such that each cell draws a current of, for example, about 3 to 5 μA during a read operation (step 3403). The soft erasure is performed, for example, by applying an incremental erasure pulse voltage to the cells until an intermediate cell current is reached. Next, a programming operation (such as deep programming to a target or coarse / fine programming) is performed on all unused cells so as to reach a <pA current level or an equivalent zero weight (step 3404). Then, target adjustment (correction) based on an error result is performed. When DeltaError>0, which means that the cell has received an overshoot during programming, Itargetv(i + 1) is set to Itarget + theta * DeltaError, and theta is, for example, 1, or a number close to 1 (step 3405A).

[0160] Itarget(i + 1) can also be adjusted based on the previous Itarget(i) using an appropriate error target adjustment / correction. When DeltaError<0, it means that the cell has received an undershoot during programming, which means that the cell current has not yet reached the target. Thereafter, Itargetv(i + 1) is set to the previous target Itargetv(i) (step 3405B).

[0161] Next, coarse and / or fine programming and verification operations are performed (step 3406). Before performing the fine (precision) programming step, programming can be accelerated using a plurality of adaptive coarse programming methods, such as targeting a plurality of gradually smaller coarse targets. Adaptive precision programming is performed, for example, with fine (precision) incremental programming voltage pulses or steady programming timing pulses. Examples of systems and methods for performing coarse programming and fine programming are described in U.S. Provisional Patent Application No. 62 / 933,809, entitled "Precise Programming Method and Apparatus for Analog Neural Memory in a Deep Learning Artificial Neural Network," filed on November 11, 2019, by the same assignee as this application, which is incorporated herein by reference.

[0162] Measure Icell at the selected cell (step 3407). For example, the cell current can be measured by a current meter circuit. For example, the cell current can be measured by an ADC (analog-to-digital converter) circuit, in which case the output is represented by digital bits. For example, the cell current can be measured by an I-V (current-voltage converter) circuit, in which case the output is represented by an analog voltage. DeltaError is calculated, which is Icell - Itarget, representing the difference between the actual current (Icell) and the target current (Itarget) in the measured cell. If |DeltaError| < DeltaMargin, the cell has achieved the target current within a specific tolerance (DeltaMargin) and the method ends (step 3410). |DeltaError| = abs(DeltaError) = the absolute value of DeltaError. Otherwise, the method returns to step 3403 and the steps are sequentially executed again (step 3410).

[0163] FIG. 35A and FIG. 35B illustrate a tuning correction method 3500 that can be executed by an algorithm controller 3314 within the VMM system 3300. Referring to FIG. 35A, the method begins (step 3501), which is typically done in response to receiving a tuning command. The entire VMM array is erased, such as by soft erasure (step 3502). A programming operation (such as deep programming to a target or coarse / fine programming) is performed on all unused cells to obtain a cell current <pA level or an equivalent zero weight (step 3503). All cells within the VMM array are programmed to an intermediate value, such as 0.5 to 1.0 μA, using coarse and / or fine programming cycles (step 3504). Examples of systems and methods for performing coarse and fine programming are described in U.S. Patent Application No. 62 / 933,809, titled "Precise Programming Method and Apparatus for Analog Neural Memory in a Deep Learning Artificial Neural Network," filed on November 11, 2019, by the same assignee as this application, which is incorporated herein by reference. The prediction target is set for the cells to be used using a function or look-up table as described above (step 3505). Next, a sector tuning method 3507 is executed for each sector of the VMM (step 3506). A sector typically consists of two or more adjacent rows within the array.

[0164] Figure 35B shows the adaptive target sector tuning method 3507. All cells within the sector are programmed to the final desired value (e.g., 1 nA to 50 nA) using individual or combined program / verify (P / V) methods such as (1) coarse / fine / steady P / V cycles, (2) CG+(only CG increment) or EG+(only EG increment), or complementary CG+ / EG-(CG increment and EG decrement), and (3) the deepest programmed cell first (which means grouping cells into groups, such as progressive grouping where the group has the cell programmed with the lowest current first) (step 3508A). Next, a determination is made as to whether Icell < Itarget. If yes, the method proceeds to step 3509. If no, the method repeats step 3508A. In step 3509, DeltaError equal to the measured Icell - Itarget(i + 1) is measured (step 3509). A determination is made as to whether |DeltaError| < DeltaMargin (step 3510). If yes, the method is complete (step 3511). If no, target adjustment is performed. If DeltaError > 0, which means the cell has received an overshoot during programming, the target is adjusted by setting a new target to Itarget + theta * DeltaError, where theta is typically = 1 (step 3512A). Itarget(i + 1) can also be adjusted based on the previous Itarget(i) using appropriate error target adjustment / correction. If DeltaError < 0, which means the cell has received an undershoot during programming, but this means the cell has not yet reached the target, the target is adjusted by maintaining the previous target, meaning Itargetv(i + 1) = Itargetv(i) (step 3512B). The sector is softly erased (step 3513). All cells within the sector are programmed to an intermediate value (step 3514), and the method returns to step 3509.

[0165] A typical neural network may have positive weights w+ and negative weights w−, with the total weight = w+ - w−, where w+ and w− are each implemented by memory cells (Iw+ and Iw−, respectively), and the total weight (Iw=Iw+ - Iw−, current subtraction) can be performed at the peripheral circuit level (such as by using array bit line output circuits). Thus, a weight tuning embodiment of the total weight is shown in Table 9 In examples such as those shown in Figure 3, tuning operations may include tuning both w+ and w- cells simultaneously, tuning only w+ cells, or tuning only w- cells. Tuning operations are performed using the program / verify and error target adjustment methods described above with respect to Figures 34 / 35A / 35B. Verify operations can be performed on the total weight only (e.g., measuring / reading the total weight current but not measuring / reading the individual positive w+ or w- cell currents), the w+ cell current only, or the w- cell current only.

[0166] For example, for a total Iw of 3 nA, Iw+ could be 3 nA and Iw- could be 0 nA. Alternatively, Iw+ could be 13 nA and Iw- could be 10 nA, meaning that both the positive weight Iw+ and the negative weight Iw- are non-zero (e.g., zero could indicate a deeply programmed cell). This may be preferable in certain operating conditions because both Iw+ and Iw- should be less susceptible to noise. table 9 : Weight tuning method (values ​​are current values ​​in nA) [Table 9]

[0167] Thus, a differential weight mapping according to the formula w=(w+)-(w-) can be used to store tuning values ​​w for use in a neural network. The mapping of w+ and w- can be optimized to address particular problems that arise in VMM arrays within a neural network, for example, by including offset values ​​in w+ and w- where each value is stored.

[0168] In one embodiment, the weight mapping is optimized to reduce RTN noise. For example, if the desired value of w is 0 nA (zero w or unused memory cells), one possible mapping is (w+)=0 nA and (w−)=0 nA, and another possible mapping is (w+)=30 nA and (w−)=30 nA, where 30 nA is an example of a non-zero offset value added to each w+ and w− value before storage. Including such a non-zero offset value ultimately consumes more power and introduces greater inaccuracies during the tuning process, but minimizes the effects of any noise. Similarly, if the desired value of w is 1 nA, one possible mapping is (w+)=1 nA and (w−)=0 nA, and another possible mapping is (w+)=30 nA and (w−)=29 nA. The latter may consume more power and introduce greater inaccuracies during the tuning process, but minimizes the effects of any noise.

[0169] In another embodiment, for a weight w of zero, both w+ and w− can be tuned to be approximately zero, such as by using the bias offset voltage method for verify operations described herein. In this case, both w+ and w− are tuned to, for example, 5 nA with a control gate voltage (VCG) higher than the normal CG voltage used for inference (read). For example, if dVCG / Ir=2 mV / 1 nA and a value of VCG=1.5 V is used in inference, then in the tuning algorithm (program verify algorithm for weight tuning), a value of VCG=1.510 V is used to verify a zero-weight cell that reaches the 5 nA target. Since VCG=1.5 V is used in inference operations, the cell current is shifted down by 2 mV per 1 nA, so that 5 nA in verify operations becomes approximately 0 nA in inference operations.

[0170] In another embodiment, for a zero weight w, both w+ and w− can be tuned to have negative currents, such as by using a negative current tuning method of bias offset voltage for verify operations, as described below. In this case, both w+ and w− are tuned to, for example, −10 nA with a control gate voltage (VCG) higher than the normal CG voltage used for inference (read). For example, if dVCG / Ir=2 mV / 1 nA and a value of VCG=1.5 V is used in inference, then in the tuning algorithm (program verify algorithm for weight tuning), VCG=1.530 V is used to verify a zero weight cell that reaches a target of 5 nA. Since VCG=1.5 V is used in inference operations, the cell current is shifted down by 2 mV per 1 nA, so that 5 nA in verify operations becomes approximately 10 nA in inference operations.

[0171] Similar methods of offset bias conditions or bias (voltage and / or current and / or timing and / or temperature) sequences can be used for test screening purposes to detect abnormal bits, such as cells susceptible to significant noise (such as RTN noise, thermal noise, or any other noise source). Essentially, there are bias conditions or bias sequences that can be used to better detect noise by attenuating the noise from a memory cell more significantly than other bias conditions or bias sequences (noise attenuation testing). For example, for a 20 nA memory cell, it may be advantageous to detect undesirable behavior by modulating the bias conditions for this cell, for example, by changing the control gate bias voltage in test screening, from placing this cell under other conditions. For example, it may be advantageous to detect bits / cells susceptible to noise (such as RTN noise) at higher current levels by modulating the bias conditions due to tester or circuit limitations.

[0172] Another method for screening or verifying noise levels, such as RTN noise screening for memory cells, is to sample the memory cell output (e.g., by measuring the output multiple times, such as 4 / 8 / ... / 1024 times). The screening criteria is such that the value of any sample instance is greater than the average of the samples by a certain amount. Another screening criteria is that the value of one sample is greater than the next sample by a certain amount. These techniques are described in U.S. Provisional Patent Application No. 62 / 933,809, entitled "Precise Programming Method and Apparatus for Analog Neural Memory in a Deep Learning Artificial Neural Network," filed by the applicant on November 11, 2019, which is incorporated herein by reference.

[0173] A method for tuning the weights of memory cells (programming or erasing the cells) incorporating some of the above weight assignments can include soft erasing the cells, then programming the zero weight cells (such as those described above), and then performing coarse and fine and / or ultra-fine tuning algorithms using noise screening as described above. Techniques for coarse, fine, and ultra-fine tuning algorithms were previously disclosed by application in U.S. patent application Ser. No. 16 / 829,757, filed March 25, 2020, and entitled "Precise Data Tuning Method and Apparatus for Analog Neural Memory in an Artificial Neural Network," which is incorporated herein by reference.

[0174] In another embodiment, noise contribution can be reduced by using a read (inference) or verify method that includes bias condition sequencing, for example, a storage condition is performed on the memory cells before a read or verify operation is performed.

[0175] In another embodiment, noise contribution can be reduced by applying a negative voltage range to the control gate. In another embodiment, the background data of the array for zero weight and unused cells can be a specific pattern to reduce fluctuations. For example, a high current level background may be desirable for noise such as RTN noise reduction. For example, a low current level background may be desirable for noise such as data drift. In standby or deep power down, the array is put into the correct state by modulating the control gate voltage, for example, by using a specific voltage level compared to the control gate voltage used during a verify operation, which means that the control gate level can be set to lower current or raise current levels during standby or deep power down operations.

[0176] In another embodiment, the read or verify method is performed by applying 0V, about 0V, or a low bias voltage to the control gate during the read or verify operation. Word lines are used instead of control gate lines to receive row data input (activation values), such as via a pulse width modulated input or an analog voltage applied to the word lines.

[0177] In another embodiment, a "0" value for w (zero w or unused cell) can be defined as <10 nA or another predetermined threshold. That is, if (w+)-(w-)<10 nA, then w is given a value of "0." This provides greater tolerance for when w=0 and is more robust to inaccuracies caused by noise, temperature fluctuations, or other forces.

[0178] In another embodiment, the weight mapping is optimized to reduce temperature variation. For example, if the desired value of w is 5 nA, one possible mapping is (w+)=5 nA and (w−)=0 nA, and another possible mapping is (w+)=30 nA and (w−)=25 nA. The latter consumes more power and may lead to greater inaccuracies during the tuning process, but minimizes temperature variation.

[0179] In another embodiment, the weight mapping is optimized to reduce the total noise or temperature variation of the neurons. For example, the number of w+ and w- values ​​stored per bit line (e.g., for 5 nA, which can be implemented as 30 nA to 25 nA, or 50 nA to 45 nA, or 80 nA to 75 nA) can be mapped to be balanced across all bit lines so that the number of stored values ​​per bit line is approximately the same for all bit lines.

[0180] In another embodiment, the weight mapping is optimized to reduce the total noise of the neuron (bit line). For example, the number of stored w+ and w− values ​​(cells) per bit line can be balanced across all bit lines so that the total noise contribution of all weights (cells) within a neuron (bit line) is optimal (has the least noise). Table 9A: Weight Tuning Methods [Table 9A] Table 9B: Weight Tuning Methods [Table 9B]

[0181] Tables 9A and 9B show exemplary embodiments of 16 levels (states) in nA. That is, a memory cell can have 16 levels as shown. Table 9A shows a situation where w can be one of 16 different positive values, and Table 9B shows a situation where w can be one of 16 different negative values, according to the formula Iw=Iw+-Iw-. The current range shown in the tables is 0 to 80 nA. Table 10A: Weight Tuning Methods [Table 10A] Table 10B: Weight Tuning Methods [Table 10B]

[0182] Tables 10A and 10B show an embodiment that compresses the overall dynamic current range from levels 0-80nA to 40nA-85nA.

[0183] With respect to Tables 10A / 11A / 12A, Iw− can be tuned using coarse, fine, or ultra-fine tuning steps (e.g., program and verify the Iw− cell), and Iw+ can be tuned using fine or ultra-fine steps (e.g., program and verify Iw=(Iw+−Iw−), or simply verify the Iw+ cell). With respect to Tables 10B / 11B / 12B, Iw+ can be tuned using coarse, fine, or ultra-fine tuning steps (e.g., program and verify the Iw+ cell), and Iw− can be tuned using fine or ultra-fine steps (e.g., program and verify Iw=(Iw+−Iw−), or simply verify the Iw cell).

[0184] This is advantageous in that it reduces variations and mismatches due to process, temperature, noise, operating stress, or operating conditions, similar to the concept shown in FIGS.

[0185] As shown in Tables 10A and 10B, the values ​​in the bottom half of the table are shifted up by a positive amount (offset bias) so that the full range of values ​​is approximately the same as the top half of the table. The offset is approximately equal to half the maximum current (level). Table 11A: Weight Tuning Methods [Table 11A] Table 11B: Weight Tuning Methods [Table 11B]

[0186] Tables 11A and 11B have zero weight (w=0) equal to the offset bias value. table 10A and 10B show an embodiment similar to that of 10A and 10B, showing, by way of example, one range of weight values ​​for one offset bias value, and two sub-ranges of weights for two offset values. Table 12A: Weight Tuning Methods [Table 12A] Table 12B: Weight Tuning Methods [Table 12B] Table 13: Weight Tuning Methods [Table 13] Table 13 shows an embodiment using variable offsets for positive and negative weights. Table 14: Weight Tuning Methods [Table 14] Table 14 shows an embodiment that uses a common offset for positive and negative weights. Table 15: Weight Tuning Methods [Table 15] Table 15 shows an embodiment that uses increasing offsets to the weights. Table 16: Weight Tuning Methods [Table 16] Table 16 shows an embodiment that uses decreasing offsets for the weights. It also shows a constant offset for Iw+. It also shows a maximum constant value for Iw+, essentially shifting all weights toward the maximum value.

[0187] Tables 12A and 12B show an embodiment similar to that of Figures 10A and 10B, where each w+ or w+ value is implemented by two memory cells, further reducing the total dynamic range by approximately half.

[0188] It should be understood that the values ​​for w+ and w- provided in the above embodiments are merely examples, and that other values ​​may be used in accordance with the disclosed concepts. For example, the offset bias value may be any value that shifts the value of each level, or may be a fixed value for all levels. In practice, each w is implemented as a differential cell, which may be effective to minimize variations or mismatches from process, temperature, noise (such as RTN or power supply noise), stress, or operating conditions.

[0189] FIG. 36A shows data behavior (IV curves) over temperature (in the subthreshold region as an example), FIG. 36B shows the problems caused by data drift during operation of a VMM system, and FIGS. 36C and 36D show blocks for compensating for data drift, with FIG. 36C showing blocks for compensating for temperature changes.

[0190] FIG. 36A illustrates a known characteristic of a VMM system, where as the operating temperature increases, the sense current in any given selected non-volatile memory cell in the VMM array increases in the subthreshold region, decreases in the saturation region, or decreases generally in the linear region.

[0191] Figure 36B shows the array current distribution over time usage (data drift), which shows that the aggregate output from the VMM array (which is the sum of the currents from all bitlines in the VMM array) shifts to the right (or left, depending on the technology used) over operational time usage, meaning that the total aggregate output drifts over the lifetime usage of the VMM system. This phenomenon is known as data drift, when data drifts due to usage conditions and degradation due to environmental factors.

[0192] FIG. 36C shows a compensation current i at the output of the bit line output circuit 3610 to compensate for data drift. COMP36 shows a bitline compensation circuit 3600 that may include injecting a . The bitline compensation circuit 3600 may include scaling the output up or down with a scaler circuit based on a resistor or capacitor network. The bitline compensation circuit 3600 may include shifting or offsetting the output with a shift circuit based on the resistor or capacitor network.

[0193] Figure 36D shows a data drift monitor 3620 that detects the amount of data drift. That information is then used as an input to the bit line compensation circuit 3600, resulting in i COMP An appropriate level of may be selected.

[0194] Figure 37 shows a bit line compensation circuit 3700, which is one embodiment of the bit line compensation circuit 3600 of Figure 36. The bit line compensation circuit 3700 comprises an adjustable current source 3701 and an adjustable current source 3702, which together provide an adjustable current source i COMP Generate i COMP is the current generated by the adjustable current source 3701, 2 is equal to the current minus the current generated by

[0195] Figure 38 shows a bit line compensation circuit 3700, which is one embodiment of the bit line compensation circuit 3600 of Figure 36. The bit line compensation circuit 3800 comprises an operational amplifier 3801, an adjustable resistor 3802, and an adjustable resistor 3803. The operational amplifier 3801 receives a reference voltage VREF on its non-inverting terminal and VREF on its inverting terminal. INPUT where V INPUT is the voltage received from the bit line output circuit 3610 of FIG. 36C, and V OUTPUT produces an output of where V OUTPUT is the V to compensate for data drift based on the ratio of resistor 3803 to resistor 3802. INPUT By configuring the values ​​of resistors 3803 and / or 3802, V OUTPUT can be scaled up or down.

[0196] Figure 39 shows a bitline compensation circuit 3900, which is one embodiment of the bitline compensation circuit 3600 of Figure 36. The bitline compensation circuit 3900 comprises an operational amplifier 3901, a current source 3902, a switch 3904, and an adjustable integrating output capacitor 3903. Here, current source 3902 is actually the output current of a single bitline or a collection of bitlines (such as one for summing the positive weights w+ and one for summing the negative weights w-) in a VMM array. The operational amplifier 3901 receives a reference voltage VREF on its non-inverting terminal and VREF on its inverting terminal. INPUT where V INPUT is the voltage received from the bit line output circuit 3610 of FIG. 36C. The bit line compensation circuit 3900 integrates the current I neu across the capacitor 3903 over an adjustable integration time to produce an output voltage V OUTPUT where V OUTPUT =Ineu * Integral time / C 3903 where C 3903 is the value of capacitor 3903. Therefore, the output voltage V OUTPUT is proportional to the (bit line) output current Ineu, proportional to the integration time, and inversely proportional to the capacitance of the capacitor 3903. The bit line compensation circuit 3900 OUTPUT produces an output of where V OUTPUT The value of is scaled based on the configuration value of capacitor 3903 and / or integration time to compensate for data drift.

[0197] 40 shows a bit line compensation circuit 4000, which is one embodiment of the bit line compensation circuit 3600 of FIG. 36. The bit line compensation circuit 4000 comprises a current mirror 4010 with an M:N ratio, which is COMP =(M / N) * i input The current mirror 4010 is a current i INPUT , mirroring the current and optionally scaling the current to i COMP Therefore, by configuring M and / or N parameters, iCOMP can be scaled up or down.

[0198] Figure 41 shows a bit line compensation circuit 4100, which is one embodiment of the bit line compensation circuit 3600 of Figure 36. The bit line compensation circuit 4100 comprises an operational amplifier 4101, an adjustable scaling resistor 4102, an adjustable shifting resistor 4103, and an adjustable resistor 4104. The operational amplifier 4101 couples a reference voltage V REF receives V on its inverting terminal IN Receive V IN is V INPUT and Vshft, where V INPUT is the voltage received from the bit line output circuit 3610 of FIG. 36C, and Vshft is V INPUT and V OUTPUT This is the voltage intended to implement a shift between Therefore, V OUTPUT is the V INPUT is a scaled and shifted version of

[0199] Figure 42 shows a bitline compensation circuit 4200, which is one embodiment of the bitline compensation circuit 3600 of Figure 36. The bitline compensation circuit 4200 comprises an operational amplifier 4201, an input current source Ineu 4202, a current shifter 4203, switches 4205 and 4206, and an adjustable integrating output capacitor 4204, where current source 4202 is actually the output current Ineu on one or more bitlines in the VMM array. The operational amplifier 4201 receives a reference voltage VREF on its non-inverting terminal and Ineu on its inverting terminal. IN receiving a signal from the receiving device, IN is the sum of Ineu and the current output by the current shifter 4203, and V OUTPUT where V OUTPUT is scaled (based on capacitor 4204) and shifted (based on Ishifter 4203) to compensate for data drift.

[0200] 43-48 illustrate various circuits that may be used to provide the W value to be programmed or read for each selected cell during a programming or read operation.

[0201] FIG. 43 shows a neuron output circuit 4300 comprising an adjustable current source 4301 and an adjustable current source 4302, which together provide I OUT Generates I OUT is the current I generated by the adjustable current source 4301. W+ , the current I generated by the adjustable current source 4302 W- The adjustable current Iw+ 4301 is a scaled version of the cell or neuron current (e.g., bit line current) to implement positive weights. The adjustable current Iw- 4302 is a scaled version of the cell or neuron current (e.g., bit line current) to implement negative weights. Current scaling is achieved by using an M:N ratio current mirror circuit, Iout=(M / N) * This is done by Iain et al.

[0202] FIG. 44 shows an adjustable capacitor 4401, a control transistor 4405, a switch 4402, a switch 4403, and a BiM :N is a scaled output current of the cell current or (bit line) neuron current by a current mirror circuit or the like. 4 shows a neuron output circuit 4400 with an adjustable current source 4404 that generates a current Iw+. Transistor 4405 is used, for example, to impose a fixed bias voltage on current 4404. Circuit 4404 is connected to V OUT where V OUT is inversely proportional to the capacitor 4401 and proportional to the adjustable integration time (the time that switch 4403 is closed and switch 4402 is open), and is the current I generated by the adjustable current source 4404 W+ is proportional to V OUT is V+-((Iw+ * integration time) / C 4401 ), where C 4401is the value of capacitor 4401. The positive terminal V+ of capacitor 4401 is connected to the positive supply voltage and the negative terminal V- of capacitor 4401 is connected to the output voltage V OUT is connected to.

[0203] FIG. 45 shows the capacitor 4401 and BiM :N current mirror circuit etc. Therefore Scaled current of cell current or (bit line) neuron current 45 shows a neuron circuit 4500 with an adjustable current source 4502 that generates Iw−. Circuit 4500 is V OUT where V OUT is inversely proportional to the capacitor 4401 and proportional to the adjustable integration time (the time that switch 4501 is open), and is the current I generated by the adjustable current source 4502 Wi After the capacitor 4401 has completed its operation of integrating the current Iw+, it is reused from the neuron output circuit 44. The positive and negative terminals (V+ and V−) are then swapped in the neuron output circuit 45, where the positive terminal is proportional to the output voltage V OUT , which is de-integrated by a current Iw-. The negative terminal is held at its previous voltage value by a clamp circuit (not shown). In practice, output circuit 44 is used for positive weight implementations and circuit 45 is used for negative weight implementations, with the final charge on capacitor 4401 effectively representing the total weight (Qw=Qw+-Qw-).

[0204] Figure 46 shows a neuron circuit 4600 comprising an adjustable capacitor 4601, a switch 4602, a control transistor 4604, and an adjustable current source 4603. The circuit 4600 is OUT where V OUT is inversely proportional to the capacitor 4601 and proportional to the adjustable integration time (the time that switch 4602 was open), and is the current I generated by the adjustable current source 4603 W-The negative terminal V− of capacitor 4601 is, for example, equal to ground. The positive terminal V+ of capacitor 4601 is, for example, first precharged to a positive voltage before integrating current Iw−. Neuron circuit 4600 can be used in place of neuron circuit 4500 along with neuron circuit 4400 to implement the sum weight (Qw=Qw+−Qw−).

[0205] 47 shows a neuron circuit 4700 comprising operational amplifiers 4703 and 4706, adjustable current sources Iw+ 4701 and Iw− 4702, and adjustable resistors 4704, 4705, and 4707. The neuron circuit 4700 is OUT which generates R 4707 * The adjustable resistor 4707 implements the scaling of the output. The adjustable current sources Iw+ 4701 and Iw- 4702 also implement an M:N ratio current mirror circuit (Iout=(M / N) * Implement output scaling by, for example, Iin.

[0206] 48 shows a neuron circuit 4800 that includes operational amplifiers 4803 and 4806, switches 4808 and 4809, adjustable current sources Iw− 4802 and Iw+ 4801, and adjustable capacitors 4804, 4805, and 4807. The neuron circuit 4800 includes an operational amplifier 4803 and an operational amplifier 4806, switches 4808 and 4809, adjustable current sources Iw− 4802 and Iw+ 4801, and adjustable capacitors 4804, 4805, and 4807. OUT , which is proportional to (Iw+ - Iw-), proportional to the integration time (the time that switches 4808 and 4809 are open), and inversely proportional to the capacitance of capacitor 4807. Adjustable capacitor 4807 implements the scaling of the output. Adjustable current sources Iw+ 4801 and Iw- 4802 also implement an M:N ratio current mirror circuit (Iout = (M / N) * Implements scaling of the output by, for example, Iin. The integral time can also adjust the output scaling.

[0207] 49A, 49B, and 49C show block diagrams of output circuits such as output circuit 3307 of FIG.

[0208] In FIG. 49A, output circuit 4901 includes ADC circuit 4911, which is used to directly digitize analog neuron outputs 4910 to provide digital output bits 4912.

[0209] In Figure 49B, output circuit 4902 comprises neuron output circuit 4921 and ADC 4911. Neuron output circuit 4921 receives neuron output 4920, shapes it, and then digitizes it by ADC circuit 4911 to produce output 4912. Neuron output circuit 4921 can be used for normalization, scaling, shifting, mapping, arithmetic operations, activation, and / or temperature compensation as described above. The ADC circuit can be a serial (slope or ramp or count) ADC, a SAR ADC, a pipeline ADC, a sigma-delta ADC, or any type of ADC.

[0210] In FIG. 49C , the output circuit includes a neuron output circuit 4921 that receives a neuron output 4930, and a converter circuit 4931 for converting the output from the neuron output circuit 4921 to an output 4932. The converter 4931 can include an ADC, an AAC (analog-to-analog converter such as a current-to-voltage converter), an APC (analog-to-pulse converter), or any other type of converter. The ADC 4911 or the converter 4931 can be used to implement an activation function, for example, by bit mapping (e.g., quantization) or clipping (e.g., clipped ReLU). The ADC 4911 and the converter 4931 can be configurable for lower or higher precision (e.g., lower or higher number of bits), lower or higher performance (e.g., slower or faster speed), etc.

[0211] Another embodiment for scaling and shifting is by configuring an ADC (analog-to-digital) conversion circuit (such as a serial ADC, SAR ADC, pipeline ADC, slope ADC, etc.) that is used to convert the array (bit line) output into digital bits, such as those with fewer or more bits of precision, and then manipulate the digital output bits by normalizing (e.g., 12 bits to 8 bits), shifting, or remapping, etc., according to a particular function (e.g., linear or nonlinear, compression, nonlinear activation, etc.). An example of an ADC conversion circuit is described in U.S. Provisional Patent Application No. 62 / 933,809, entitled "Precise Programming Method and Apparatus for Analog Neural Memory in a Deep Learning Artificial Neural Network," filed November 11, 2019, by the same assignee as the present application, which is incorporated herein by reference.

[0212] table 17 shows an alternative approach for performing read, erase, and program operations. table 17 : Operation of flash memory cells [Table 17] The read and erase operations are similar to the previous table, however the two methods for programming are implemented by the Fowler-Nordheim (FN) tunneling mechanism.

[0213] An embodiment for scaling the input can be by allowing a certain number of rows of the VMM at a time, then fully combining the results, and so on.

[0214] Another embodiment is to scale the input voltage and rescale the output appropriately for normalization.

[0215] Another embodiment for scaling a pulse width modulated input is by modulating the timing of the pulse width. An example of this technique is described in U.S. Patent Application No. 16 / 449,201, entitled "Configurable Input Blocks and Output Blocks and Physical Layout for Analog Neural Memory in Deep Learning Artificial Neural Network," filed June 21, 2019, by the same assignee as the present application, and which is incorporated herein by reference.

[0216] Another embodiment for scaling inputs is, for example, for an 8-bit input IN7:0, by allowing one input binary bit at a time, evaluating each IN0, IN1, ..., IN7 in turn, and then combining the output result with the appropriate binary bit weighting. An example of this technique is described in U.S. Patent Application No. 16 / 449,201, entitled "Configurable Input Blocks and Output Blocks and Physical Layout for Analog Neural Memory in Deep Learning Artificial Neural Network," filed June 21, 2019 by the same assignee as the present application, which is incorporated herein by reference.

[0217] Optionally, in the above embodiments, measuring the cell current for purposes of verifying or reading the current may be, for example, taking an average or multiple measurements, 8 to 32 times, to reduce the effects of noise (RTN or any random noise) and / or to detect any outlier bits that are defective and need to be replaced by redundant bits.

[0218] It should be noted that, as used herein, both the terms "over" and "on" are inclusive of "directly" (with no intermediate material, element, or gap disposed therebetween) and "indirectly" (with an intermediate material, element, or gap disposed therebetween). Similarly, the term "adjacent" includes "directly adjacent" (with no intermediate material, element, or gap disposed therebetween) and "indirectly adjacent" (with an intermediate material, element, or gap disposed therebetween); "attached" includes "directly attached" (with no intermediate material, element, or gap disposed therebetween) and "indirectly attached" (with an intermediate material, element, or gap disposed therebetween); and "electrically coupled" includes "directly electrically coupled" (with no intermediate material or element disposed therebetween that electrically connects the elements together) and "indirectly electrically coupled" (with an intermediate material or element disposed therebetween that electrically connects the elements together). For example, forming an element "over a substrate" can include forming the element directly on the substrate with no intermediate materials / elements therebetween, and forming the element indirectly on the substrate with one or more intermediate materials / elements therebetween.

Claims

1. 1. A method for programming, verifying, and reading zero values ​​in differential pairs of non-volatile memory cells in a vector matrix multiplication array, the method comprising: programming a first cell w+ in the differential pair; verifying the first cell based on a first current value by applying a voltage equal to a first voltage plus a bias voltage to a control gate terminal of the first cell; programming a second cell w− in the differential pair; verifying the second cell based on the first current value by applying a voltage equal to the first voltage plus the bias voltage to a control gate terminal of the second cell; reading the first cell by applying a voltage equal to the first voltage to the control gate terminal of the first cell; reading the second cell by applying a voltage equal to the first voltage to the control gate terminal of the second cell; calculating a value w according to the formula w=(w+)-(w-); the first current value is a current value that flows when a voltage equal to the first voltage plus the bias voltage is applied to the control gate terminal of the first cell or the second cell, when a current value that flows when a voltage equal to the first voltage is applied to the control gate terminal of the first cell or the second cell is the zero value.

2. 10. The method of claim 1, wherein the first cell is tuned by one or more of a coarse, fine, or ultra-fine tuning algorithm, and the second cell is tuned by one or more of a fine or ultra-fine tuning algorithm.

3. The method of claim 1 , wherein the first current value is a positive value.

4. 10. The method of claim 1, wherein the first cell is tuned to w+ by one or more of a coarse, fine, or ultra-fine tuning algorithm, and the second cell is tuned to w− by one or more of a fine or ultra-fine tuning algorithm.

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