Semiconductor device and method for manufacturing a semiconductor device

Abstract

To provide a technique of being able to form easily an upper element and a structure to relieve the impact of wire bonding on an electrode pad corresponding to an end part of the upper element.SOLUTION: A semiconductor device 100 includes a substrate 1, a breakdown voltage holding insulating film 4, an element part having a lower element 3 and an upper element 5, an extraction wire 7, a first electrode pad 8, a second electrode pad 10 corresponding to an end part of the upper element 5, and an uppermost protection film 6 that covers the upper element 5 so as to expose the second electrode pad 10 from a second contact hole 12. The breakdown voltage holding insulating film 4 and the uppermost protection film 6 are provided up to a region outside the first electrode pad 8 in a direction where the extraction wire 7 extends. On an upper surface of the second electrode pad 10, a pad double stack part 13 with conductivity is provided. The uppermost protection film 6 covers a peripheral part of the pad double stack part 13.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

Background Art

[0002] As a conventional structure, for example, in Patent Document 1, there is disclosed a signal transmission device including a pressure-resistant holding insulating film provided on the upper surface side of a substrate, a lower element in a spiral shape in a top view provided in the pressure-resistant holding insulating film, an upper element in a spiral shape in a top view provided on the upper surface of the pressure-resistant holding insulating film, and a lead-out wiring having one end connected to one end of the lower element. In this signal transmission device, the pressure-resistant holding insulating film is provided in a region inside the lead-out wiring in the extending direction of the lead-out wiring.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Since the signal transmission device described in Patent Document 1 has a structure in which the pressure-resistant holding insulating film is formed only in the region where the lower element is provided, a step of several tens of μm occurs at the boundary between the region where the pressure-resistant holding insulating film is formed and the region where it is not formed. Since it is necessary to consider the step in processes such as photolithography or etching for forming the upper element after forming the pressure-resistant holding insulating film, it has been difficult to carry out this process.

[0005] Furthermore, wire bonding is performed on the electrode pad, which is one end of the upper element. During this process, a downward load and lateral vibration are applied to the electrode pad to improve the adhesion between the wire and the electrode pad. If the electrode pad is thin, the impact of such wire bonding is not mitigated, raising concerns that cracks may occur in the electrode pad and the insulating film beneath it.

[0006] Therefore, the present disclosure aims to provide a technology that makes it possible to easily form an upper element and a structure for mitigating the impact of wire bonding on an electrode pad which is one end of the upper element. [Means for solving the problem]

[0007] The semiconductor device according to this disclosure comprises a substrate, a dielectric film for withstanding loads provided on the upper surface of the substrate, an element portion having a spiral-shaped lower element in a top view provided within the dielectric film for withstanding loads and an upper element in a spiral shape in a top view provided above the lower element within the dielectric film for withstanding loads, a lead wire with one end connected to one end of the lower element, a first electrode pad connected to the other end of the lead wire, a second electrode pad provided at a position opposite to one end of the lower element and being one end of the upper element, and an uppermost protective film having an opening above the second electrode pad and covering the upper element such that the second electrode pad is exposed through the opening, wherein the dielectric film for withstanding loads and the uppermost protective film are provided in the direction of extension of the lead wire to an area outside the first electrode pad, a conductive double-stacked pad portion is provided on the upper surface of the second electrode pad, and the uppermost protective film covers the peripheral edge of the double-stacked pad portion. [Effects of the Invention]

[0008] According to this disclosure, since the dielectric dielectric film for withstand voltage is provided in the region extending beyond the first electrode pad in the direction of extension of the lead wiring, no step is generated in the region where the upper element is formed in the dielectric dielectric film and in the surrounding region. As a result, it is not necessary to consider the step in the process of forming the upper element, and the upper element can be easily formed.

[0009] Furthermore, since a double-layer pad section is provided on the upper surface of the second electrode pad, there is no need to change the thickness of the upper element, making it easy to form a structure to mitigate the impact of wire bonding on the second electrode pad, which is one end of the upper element. [Brief explanation of the drawing]

[0010] [Figure 1] This is a top view of a semiconductor device according to Embodiment 1. [Figure 2] This is a cross-sectional view along line AA in Figure 1. [Figure 3] This is a flowchart showing the method for manufacturing a semiconductor device according to Embodiment 1. [Figure 4] This is a cross-sectional view illustrating the manufacturing method of a semiconductor device according to Embodiment 1. [Figure 5] This is a cross-sectional view illustrating the manufacturing method of a semiconductor device according to Embodiment 1. [Figure 6] This is a cross-sectional view illustrating the manufacturing method of a semiconductor device according to Embodiment 1. [Figure 7] This is a cross-sectional view illustrating the manufacturing method of a semiconductor device according to Embodiment 1. [Figure 8] This is a cross-sectional view illustrating the manufacturing method of a semiconductor device according to Embodiment 1. [Figure 9] This is a cross-sectional view illustrating the manufacturing method of a semiconductor device according to Embodiment 1. [Figure 10] This is a cross-sectional view illustrating the manufacturing method of a semiconductor device according to Embodiment 1. [Figure 11] This is a cross-sectional view illustrating the manufacturing method of a semiconductor device according to Embodiment 1. [Figure 12] It is a top view of the semiconductor device according to Embodiment 2. [Figure 13] It is a cross-sectional view taken along line B-B of FIG. 12.

Embodiments for Carrying Out the Invention

[0011] <Embodiment 1> <Structure of the Semiconductor Device> Embodiment 1 will be described below with reference to the drawings. FIG. 1 is a top view of a semiconductor device 100 according to Embodiment 1. FIG. 2 is a cross-sectional view taken along line A-A of FIG. 1.

[0012] As shown in FIGS. 1 and 2, the semiconductor device 100 includes a substrate 1, an insulating film 2, a lead wiring 7, a lower element 3, a first electrode pad 8, a breakdown voltage holding insulating film 4, an upper element 5, a second electrode pad 10, a pad stacking portion 13, and an uppermost layer protective film 6.

[0013] The substrate 1 may be a semiconductor substrate such as Si, SiC, or GaN, or an insulating substrate such as glass or ceramics.

[0014] The insulating film 2 is provided over the entire upper surface of the substrate 1. The insulating film 2 is an oxide film or a nitride film, which are common semiconductor materials.

[0015] The breakdown voltage holding insulating film 4 is provided over the entire upper surface of the insulating film 2 on the upper surface side of the substrate 1. The breakdown voltage holding insulating film 4 is a silicon oxide film, a silicon nitride film, or a polyimide film made of an organic material.

[0016] The lower element 3 is a lower coil element formed in a spiral shape in a top view, and is provided on the upper surface of the insulating film 2 within the breakdown voltage holding insulating film 4. Also, the lower element 3 is provided in the right region within the breakdown voltage holding insulating film 4 in FIGS. 1 and 2.

[0017] The spiral-shaped central portion of the lower element 3 (one end of the lower element 3) is connected to one end of the lead wire 7. The lead wire 7 extends to the left from the spiral-shaped central portion of the lower element 3 in Figures 1 and 2. The other end of the lead wire 7 is connected to the first electrode pad 8.

[0018] Furthermore, the other end of the spiral shape in the lower element 3 is connected to one end of another lead wire 7. The other lead wire 7 extends to the left from the other end of the spiral shape in the lower element 3 in Figures 1 and 2. The other end of the other lead wire 7 is connected to another first electrode pad 8.

[0019] A protective film 9 made of a different material from the dielectric strength-holding insulating film 4 may be provided on the upper surface of the lower element 3, the first electrode pad 8, and the insulating film 2 in order to improve the dielectric strength. The protective film 9 is a silicon oxide film or a silicon nitride film.

[0020] A spiral groove 4a is formed on the upper surface of the pressure-resistant insulating film 4 when viewed from above, and an upper element 5, which is a spiral-shaped upper coil element when viewed from above, is provided inside the groove 4a. In other words, the upper element 5 is located above the lower element 3 within the pressure-resistant insulating film 4.

[0021] Signal transmission occurs through magnetic coupling between the lower element 3 and the upper element 5, and a high voltage is applied between them. By adjusting the thickness of the dielectric film 4 for maintaining the dielectric strength, it is possible to obtain the desired dielectric strength in the dielectric film 4. In this way, the lower element 3 and the upper element 5 constitute a coil element as an element part.

[0022] Second electrode pads 10 are formed at both ends of the upper element 5. A conductive double-layer pad section 13 is provided on the upper surface of the second electrode pad 10. Wire bonding is performed on the second electrode pad 10, and during this process, a downward load and lateral vibration are applied to the second electrode pad 10 to improve the adhesion between the wire and the second electrode pad 10. If the thickness of the second electrode pad 10 is thin, the impact of such wire bonding will not be mitigated, raising concerns that cracks may occur in the second electrode pad 10 and the pressure-resistant insulating film 4 below it. The double-layer pad section 13 is provided to mitigate the impact of wire bonding.

[0023] Furthermore, it is conceivable to thicken the second electrode pad 10 without providing the double-layer pad section 13, but this would affect the device characteristics. Therefore, it is necessary to thicken the second electrode pad 10 without changing the thickness of the parts of the upper element 5 other than the second electrode pad 10. For this reason, thickening the second electrode pad 10 was difficult. By providing the double-layer pad section 13, it becomes possible to mitigate the impact of wire bonding without changing the thickness of the upper element 5.

[0024] Here, the top view contour of the double-stacked pad portion 13 may be formed to be larger than the top view contour of the second electrode pad 10. In this structure, by forming the uppermost protective film 6, described later, to cover the periphery of the double-stacked pad portion 13, the double-stacked pad portion 13 becomes less likely to peel off during wire bonding.

[0025] Furthermore, as described above, the upper element 5 is provided inside the groove 4a of the pressure-resistant insulating film 4. That is, since the upper element 5 is embedded in the groove 4a of the pressure-resistant insulating film 4, the upper surface of the pressure-resistant insulating film 4 and the upper surface of the upper element 5 are at the same height within the range of manufacturing tolerances. Because both are at the same height, the upper surface of the double-stacked pad portion 13 is flat, and the top view contour of the double-stacked pad portion 13 can be made larger than the top view contour of the second electrode pad 10.

[0026] An upper protective film 6, which constitutes the uppermost part of the semiconductor device 100, is provided on the upper surface of the upper element 5 and the dielectric insulating film 4 for withstanding the pressure. The upper protective film 6 is a silicon nitride film or a polyimide film.

[0027] A first contact hole 11 is formed above the first electrode pad 8 in the uppermost protective film 6 and the pressure-resistant insulating film 4. Furthermore, a second contact hole 12 (opening) is formed above the second electrode pad 10 in the uppermost protective film 6, that is, at a position corresponding to the double-stacked pad portion 13 in the uppermost protective film 6. In this case, the top view contour of the second contact hole 12 is formed to be smaller than the top view contour of the double-stacked pad portion 13.

[0028] <Manufacturing method for semiconductor devices> Next, the manufacturing method of the semiconductor device 100 will be explained using Figures 3 to 11. Figure 3 is a flowchart showing the manufacturing method of the semiconductor device 100 according to Embodiment 1, and specifically, it is a flowchart showing the process from the formation of the dielectric film 4 for withstand voltage retention to the formation of the second contact hole 12. Figures 4 to 11 are cross-sectional views illustrating the manufacturing method of the semiconductor device 100 according to Embodiment 1.

[0029] First, as shown in Figure 4, an insulating film 2 is formed on the substrate 1 by CVD or SOG method, and then lead wires 7 extending from the lower element 3 are formed by sputtering or vapor deposition, photolithography, or etching.

[0030] After forming the insulating film 2 again and creating the first electrode pad 8, which will be connected to the lead wiring 7, in the insulating film 2 by etching, the lower element 3 is formed. The lower element 3 is formed by sputtering or vapor deposition to create a metal film, photogravure, or etching. Subsequently, a protective film 9 is formed on the upper side of the lower element 3 by CVD or SOG.

[0031] Next, as shown in Figure 5, a pressure-resistant insulating film 4 is formed to cover the lower element 3 and extend in the direction of the lead wire 7 to an area outside the first electrode pad 8 (step S1). If the pressure-resistant insulating film 4 is a silicon oxide film or a silicon nitride film, it is formed by the CVD method or SOG method. If the pressure-resistant insulating film 4 is a polyimide film, it is formed by a manufacturing method such as rotary coating or spray coating.

[0032] Next, grooves 4a are formed in the dielectric film 4 for maintaining the load-bearing capacity using the damascene method, and the upper element 5 is formed in the grooves 4a. This will be explained. First, as shown in Figure 6, grooves 4a with the same shape as the upper element 5 are formed on the upper surface of the dielectric film 4 by etching (step S2). Subsequently, as shown in Figure 7, a metal film that will become the upper element 5 is formed on the upper surface of the dielectric film 4 by sputtering and vapor deposition. As shown in Figure 8, the surface of the metal film is further flattened by the CMP method or the etch-back method, thereby forming the upper element 5 inside the grooves 4a of the dielectric film 4 (step S3).

[0033] Next, as shown in Figure 9, a metal film that will become the double-stacked pad portion 13 is formed on the upper surface of the pressure-resistant insulating film 4 by sputtering and vapor deposition. As shown in Figure 10, the double-stacked pad portion 13 is formed on the upper surface of the second electrode pad 10, which is part of the upper element 5, by photolithography or etching (step S4).

[0034] Next, as shown in Figure 11, an uppermost protective film 6 is formed to cover the upper element 5 (step S5). If the uppermost protective film 6 is a silicon nitride film, it is formed by the CVD method or the SOG method. If the uppermost protective film 6 is polyimide, it is formed by rotary coating or spray coating.

[0035] Finally, a first contact hole 11 is formed in the uppermost protective film 6 at a position corresponding to the first electrode pad 8, and a second contact hole 12 is formed in the uppermost protective film 6 at a position corresponding to the double-stacked pad portion 13 (step S6). Specifically, the first contact hole 11 and the second contact hole 12 are opened by etching, and the final structure of the semiconductor device 100 shown in Figure 2 is obtained.

[0036] <Effects> As described above, the semiconductor device 100 according to Embodiment 1 comprises a substrate 1, a pressure-resistant insulating film 4 provided on the upper surface of the substrate 1, an element portion having a spiral-shaped lower element 3 provided within the pressure-resistant insulating film 4 and a spiral-shaped upper element 5 provided above the lower element 3 within the pressure-resistant insulating film 4, a lead wire 7 with one end connected to one end of the lower element 3, a first electrode pad 8 connected to the other end of the lead wire 7, a second electrode pad 10 provided at a position opposite to one end of the lower element 3 and being one end of the upper element 5, and an uppermost protective film 6 covering the upper element 5 with a second contact hole 12 above the second electrode pad 10 and the second electrode pad 10 exposed through the second contact hole 12. The pressure-resistant insulating film 4 and the uppermost protective film 6 are provided in the direction of extension of the lead wire 7 to an area outside the first electrode pad 8. A conductive double-stacked pad portion 13 is provided on the upper surface of the second electrode pad 10. The uppermost protective film 6 covers the peripheral edge of the double-layered pad section 13.

[0037] Therefore, since the dielectric strength insulating film 4 is provided in the direction of extension of the lead wire 7, extending beyond the region outside the first electrode pad 8, no step is generated in the region of the dielectric strength insulating film 4 where the upper element 5 is formed and in the surrounding region. As a result, there is no need to consider the step in the process of forming the upper element 5, and the upper element 5 can be easily formed.

[0038] Furthermore, since a double-stacked pad portion 13 is provided on the upper surface of the second electrode pad 10, there is no need to change the thickness of the upper element 5, and therefore a structure for mitigating the impact of wire bonding can be easily formed on the second electrode pad 10, which is one end of the upper element 5.

[0039] Furthermore, the manufacturing method for the semiconductor device 100 according to Embodiment 1 includes the steps of: forming lead wires 7 on the upper surface side of a substrate 1; forming a spiral-shaped lower element 3 in a top view, having one end connected to one end of the lead wire 7; forming a first electrode pad 8 connected to the other end of the lead wire 7; forming a pressure-resistant insulating film 4 that covers the lower element 3 and extends to an area outside the first electrode pad 8 in the direction of extension of the lead wire 7; forming a spiral-shaped groove 4a in a top view on the upper surface of the pressure-resistant insulating film 4; forming a spiral-shaped upper element 5 in a top view in the groove 4a of the pressure-resistant insulating film 4; forming a double-stacked pad portion 13 on the upper surface of a second electrode pad 10 which is part of the upper element 5; forming an uppermost protective film 6 so as to cover the upper element 5; and forming a second contact hole 12 in the uppermost protective film 6 at a position corresponding to the double-stacked pad portion 13.

[0040] Therefore, by forming the upper element 5 in the groove 4a of the pressure-resistant insulating film 4, the upper surfaces of the pressure-resistant insulating film 4 and the upper element 5 become flat, and the double-stacked pad portion 13 can be easily formed.

[0041] Furthermore, since the top view contour of the double-stacked pad portion 13 is larger than the top view contour of the second electrode pad 10, the contact area between the double-stacked pad portion 13 and the pressure-resistant insulating film 4 surrounding the second electrode pad 10 can be increased. This further improves the effect of mitigating the impact of wire bonding.

[0042] <Embodiment 2> Next, a semiconductor device 100A according to Embodiment 2 will be described. Figure 12 is a top view of the semiconductor device 100A according to Embodiment 2. Figure 13 is a cross-sectional view taken along line BB of Figure 12. In Embodiment 2, the same reference numerals are used for components that are the same as those described in Embodiment 1, and their descriptions are omitted.

[0043] In Embodiment 1, both the upper element 5 and the lower element 3 were spiral-shaped coil elements when viewed from above. However, as shown in Figures 12 and 13, in Embodiment 2, both the upper element 5 and the lower element 3 are circular flat plates when viewed from above. The lower element 3 and the upper element 5 constitute a flat plate capacitor as the element part. Furthermore, the groove 4a of the dielectric insulation film 4 for maintaining withstand voltage is formed in a circular shape when viewed from above, and the second electrode pad 10 and the double-stacked pad portion 13 are formed only in the central part of the upper element 5, which differs from Embodiment 1.

[0044] The method for manufacturing the semiconductor device 100A according to Embodiment 2 is the same as that of Embodiment 1, so a description will be omitted.

[0045] As described above, the semiconductor device 100A according to Embodiment 2 comprises a substrate 1, a dielectric film 4 for withstand voltage retention provided on the upper surface of the substrate 1, an element portion having a lower element 3 that is circular in a top view and provided within the dielectric film 4, and an upper element 5 that is circular in a top view and provided above the lower element 3 within the dielectric film 4, a lead wire 7 with one end connected to the central part of the lower element 3, a first electrode pad 8 connected to the other end of the lead wire 7, a second electrode pad 10 provided at a position opposite to the central part of the lower element 3 and being the central part of the upper element 5, and an uppermost protective film 6 that covers the upper element 5 and has a second contact hole 12 above the second electrode pad 10, with the second electrode pad 10 exposed through the second contact hole 12. The dielectric film 4 for withstand voltage retention and the uppermost protective film 6 are provided in the direction of extension of the lead wire 7 to an area outside the first electrode pad 8. A conductive double-layer pad section 13 is provided on the upper surface of the second electrode pad 10. The uppermost protective film 6 covers the periphery of the double-layer pad section 13.

[0046] Furthermore, the manufacturing method for the semiconductor device 100A according to Embodiment 2 includes the steps of: forming lead wires 7 on the upper surface side of a substrate 1; forming a lower element 3 that is circular in top view and has a central part connected to one end of the lead wires 7; forming a pressure-resistant insulating film 4 that covers the lower element 3 and extends to an area outside the first electrode pad 8 in the direction of extension of the lead wires 7; forming a circular groove 4a in top view on the upper surface of the pressure-resistant insulating film 4; forming a circular upper element 5 in top view in the groove 4a of the pressure-resistant insulating film 4; forming a double-stacked pad portion 13 on the upper surface of a second electrode pad 10 which is part of the upper element 5; forming an uppermost protective film 6 that covers the upper element 5; and forming a second contact hole 12 in the uppermost protective film 6 at a position corresponding to the double-stacked pad portion 13.

[0047] Therefore, the same effects as in Embodiment 1 can be obtained.

[0048] Furthermore, it is possible to freely combine each embodiment, or to modify or omit each embodiment as appropriate.

[0049] The various aspects of this disclosure are summarized below as an appendix.

[0050] (Note 1) circuit board and A pressure-resistant insulating film provided on the upper surface side of the substrate, An element portion having a lower element that is spiral-shaped when viewed from above and provided within the pressure-resistant insulating film, and an upper element that is spiral-shaped when viewed from above and provided above the lower element within the pressure-resistant insulating film, A lead wire, one end of which is connected to one end of the lower element, A first electrode pad connected to the other end of the aforementioned lead wire, A second electrode pad is provided at a position opposite to one end of the lower element, and is one end of the upper element. The uppermost protective film covers the upper element, having an opening above the second electrode pad, and exposing the second electrode pad through the opening. The dielectric film for withstanding the pressure and the uppermost protective film are provided in the direction of extension of the lead wiring, extending to a region outside the first electrode pad. A conductive pad double-stack portion is provided on the upper surface of the second electrode pad. The aforementioned uppermost protective film covers the peripheral edge of the double-stacked pad portion, in a semiconductor device.

[0051] (Note 2) circuit board and A pressure-resistant insulating film provided on the upper surface side of the substrate, An element portion having a lower element that is circular in shape when viewed from above and provided within the insulating film for maintaining the pressure, and an upper element that is circular in shape when viewed from above and provided above the lower element within the insulating film for maintaining the pressure, A lead wire, one end of which is connected to the central part of the lower element, A first electrode pad connected to the other end of the aforementioned lead wire, A second electrode pad is provided at a position opposite to the central part of the lower element, and is located at the central part of the upper element. The uppermost protective film covers the upper element, having an opening above the second electrode pad, and exposing the second electrode pad through the opening. The dielectric film for withstanding the pressure and the uppermost protective film are provided in the direction of extension of the lead wiring, extending to a region outside the first electrode pad. A conductive pad double-stack portion is provided on the upper surface of the second electrode pad. The aforementioned uppermost protective film covers the peripheral edge of the double-stacked pad portion, in a semiconductor device.

[0052] (Note 3) The semiconductor device according to Appendix 1 or Appendix 2, wherein the top view contour of the double-stacked pad portion is larger than the top view contour of the second electrode pad.

[0053] (Note 4) The process involves forming lead wires on the upper surface of the substrate, then forming a spiral-shaped lower element in a top view, having one end connected to one end of the lead wire, and a first electrode pad connected to the other end of the lead wire. A step of forming a dielectric film for withstand voltage that covers the lower element and extends to a region outside the first electrode pad in the direction of extension of the lead wiring, The process involves forming spiral grooves on the upper surface of the pressure-resistant insulating film when viewed from above, A step of forming a spiral-shaped upper element in the groove of the pressure-resistant insulating film when viewed from above, The process of forming a double-stacked portion on the upper surface of the second electrode pad, which is part of the upper element, A step of forming an uppermost protective film so as to cover the upper element, A step of forming an opening in the uppermost protective film at a position corresponding to the double-layered portion, A method for manufacturing a semiconductor device, comprising the features described above.

[0054] (Note 5) The process involves forming lead wires on the upper surface of the substrate, then forming a circular lower element in a top view having a central portion connected to one end of the lead wire, and a first electrode pad connected to the other end of the lead wire, A step of forming a dielectric film for withstand voltage that covers the lower element and extends to a region outside the first electrode pad in the direction of extension of the lead wiring, The process involves forming a circular groove on the upper surface of the pressure-resistant insulating film when viewed from above, A step of forming a circular upper element in the groove of the pressure-resistant insulating film when viewed from above, The process of forming a double-stacked portion on the upper surface of the second electrode pad, which is part of the upper element, A step of forming an uppermost protective film so as to cover the upper element, A step of forming an opening in the uppermost protective film at a position corresponding to the double-layered portion, A method for manufacturing a semiconductor device, comprising the features described above. [Explanation of Symbols]

[0055] 1 Substrate, 4 Insulating film for withstand voltage retention, 4a Groove, 3 Lower element, 5 Upper element, 6 Top protective film, 7 Lead wire, 8 First electrode pad, 10 Second electrode pad, 12 Second contact hole, 13 Double pad stacking section, 100, 100A Semiconductor device.

Claims

1. circuit board and A pressure-resistant insulating film provided on the upper surface side of the substrate, An element portion having a lower element that is spiral-shaped when viewed from above and provided within the pressure-resistant insulating film, and an upper element that is spiral-shaped when viewed from above and provided above the lower element within the pressure-resistant insulating film, A lead wire, one end of which is connected to one end of the lower element, A first electrode pad connected to the other end of the aforementioned lead wiring, A second electrode pad is provided at a position opposite to one end of the lower element, and is one end of the upper element. The uppermost protective film covers the upper element, having an opening above the second electrode pad, and exposing the second electrode pad through the opening. The dielectric film for maintaining withstand voltage and the uppermost protective film are provided in the direction of extension of the lead wiring, extending to a region outside the first electrode pad. A conductive pad double-stack portion is provided on the upper surface of the second electrode pad. The aforementioned uppermost protective film covers the peripheral edge of the double-stacked pad portion, in a semiconductor device.

2. circuit board and A pressure-resistant insulating film provided on the upper surface side of the substrate, An element portion having a lower element that is circular in shape when viewed from above and provided within the insulating film for maintaining the pressure, and an upper element that is circular in shape when viewed from above and provided above the lower element within the insulating film for maintaining the pressure, A lead wire, one end of which is connected to the central part of the lower element, A first electrode pad connected to the other end of the aforementioned lead wiring, A second electrode pad is provided at a position opposite to the central part of the lower element, and is located at the central part of the upper element. The uppermost protective film covers the upper element, having an opening above the second electrode pad, and exposing the second electrode pad through the opening. The dielectric film for maintaining withstand voltage and the uppermost protective film are provided in the direction of extension of the lead wiring, extending to a region outside the first electrode pad. A conductive pad double-stack portion is provided on the upper surface of the second electrode pad. The aforementioned uppermost protective film covers the peripheral edge of the double-stacked pad portion, in a semiconductor device.

3. The semiconductor device according to claim 1 or claim 2, wherein the top view contour of the double-stacked pad portion is larger than the top view contour of the second electrode pad.

4. The process involves forming lead wires on the upper surface of the substrate, then forming a spiral-shaped lower element in a top view, having one end connected to one end of the lead wire, and a first electrode pad connected to the other end of the lead wire. A step of forming a dielectric film for withstand voltage that covers the lower element and extends to a region outside the first electrode pad in the direction of extension of the lead wiring, The process involves forming spiral grooves on the upper surface of the pressure-resistant insulating film when viewed from above, A step of forming a spiral-shaped upper element in the groove of the pressure-resistant insulating film when viewed from above, The process of forming a double-stacked portion on the upper surface of the second electrode pad, which is part of the upper element, A step of forming an uppermost protective film so as to cover the upper element, A step of forming an opening in the uppermost protective film at a position corresponding to the double-layered portion, A method for manufacturing a semiconductor device, comprising the features described above.

5. The process involves forming lead wires on the upper surface of the substrate, then forming a circular lower element in a top view having a central portion connected to one end of the lead wire, and a first electrode pad connected to the other end of the lead wire, A step of forming a dielectric film for withstand voltage that covers the lower element and extends to a region outside the first electrode pad in the direction of extension of the lead wiring, The process involves forming a circular groove on the upper surface of the pressure-resistant insulating film when viewed from above, A step of forming a circular upper element in the groove of the pressure-resistant insulating film when viewed from above, The process of forming a double-stacked portion on the upper surface of the second electrode pad, which is part of the upper element, A step of forming an uppermost protective film so as to cover the upper element, A step of forming an opening in the uppermost protective film at a position corresponding to the double-layered portion, A method for manufacturing a semiconductor device, comprising the features described above.

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