Semiconductor equipment

Abstract

To provide a semiconductor device that is miniaturized, is reduced in power consumption, and increases an arithmetic processing speed.SOLUTION: In a semiconductor device 10, a computation block 20 includes multiple memory circuits 30, a switching circuit 41, a product-sum operation circuit 42, and a dedicated operation circuit comprising an activation function operation circuit 43, a quantization operation circuit 44, and a pre-pooling operation circuit 45. Each of the multiple memory circuits has a function of holding weight data. The switching circuit has a function of switching a conductive state of one of the memory circuits and the product-sum operation circuit. The sum product-sum operation circuit outputs a first output signal based on product-sum operation processing of input data, and weight data selected by the switching circuit to the dedicated operation circuit. A layer having multiple memory circuits is provided while being laminated on a layer having the switching circuit, the product-sum operation circuit, and the dedicated operation circuit.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This specification describes semiconductor devices and the like.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention disclosed herein include semiconductor devices, imaging devices, display devices, light-emitting devices, energy storage devices, memory devices, display systems, electronic devices, lighting devices, input devices, input / output devices, methods for driving them, or methods for manufacturing them. [Background technology]

[0003] Electronic devices containing semiconductor devices, including CPUs (Central Processing Units), are becoming widespread. To process large amounts of data at high speed in such devices, technological development to improve the performance of semiconductor devices is active. One technology that achieves high performance is the so-called SoC (System on Chip), which tightly couples an accelerator such as a GPU (Graphics Processing Unit) with the CPU. However, with SoC-based high-performance semiconductor devices, increased heat generation and power consumption become problematic.

[0004] In AI (Artificial Intelligence) technology, the computational load increases due to the enormous amount of computation and the large number of parameters. This increase in computational load leads to increased heat generation and power consumption, so architectures to reduce computational load are being actively proposed. Representative architectures include Binary Neural Networks (BNNs) and Ternary Neural Networks (TNNs), which are particularly effective in reducing circuit size and power consumption (see, for example, Patent Document 1). [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] International Publication No. 2019 / 078924 [Overview of the project] [Problems that the invention aims to solve]

[0006] AI technology involves performing sum-of-accumulate operations using weight data and input data an enormous number of times, requiring memory cell arrays to store large amounts of weight data and intermediate data. Furthermore, AI technology typically involves operations other than sum-of-accumulate, such as activation operations and pooling operations. Therefore, when implementing AI-based calculations using integrated circuits, there is a risk of a significant increase in the circuit area required for memory cell arrays and dedicated calculation circuits.

[0007] Furthermore, AI technology requires faster computation. When AI-based computations are implemented using integrated circuits, memory cell arrays read weight data and intermediate data to the arithmetic circuit via bit lines. The frequency of reading weight data and intermediate data on bit lines increases. As a result, the charging and discharging energy of the bit lines increases, which may lead to increased power consumption.

[0008] To reduce the charging and discharging energy of bit lines, shortening the bit lines is effective. However, this would require arranging arithmetic circuits and memory cell arrays alternately, which could significantly increase the area of ​​the peripheral circuits.

[0009] One aspect of the present invention aims to provide a miniaturized semiconductor device. Alternatively, one aspect of the present invention aims to provide a semiconductor device with reduced power consumption. Alternatively, one aspect of the present invention aims to provide a semiconductor device with improved processing speed. Alternatively, one aspect of the present invention aims to provide a semiconductor device with a novel configuration.

[0010] Note that one aspect of the present invention does not necessarily need to solve all of the above problems, and it is sufficient if it can solve at least one problem. Also, the description of the above problems does not prevent the existence of other problems. Other problems will become apparent from the descriptions in the specification, claims, drawings, etc., and it is possible to extract these other problems from the descriptions in the specification, claims, drawings, etc.

Means for Solving the Problems

[0011] One aspect of the present invention includes a plurality of memory circuits, a switching circuit, a first arithmetic circuit, and a second arithmetic circuit. Each of the plurality of memory circuits has a function of holding weight data. The switching circuit has a function of switching the conduction state between any one of the plurality of memory circuits and the first arithmetic circuit. The first arithmetic circuit outputs a first output signal based on the product-sum operation processing of input data and the weight data selected by the switching circuit to the second arithmetic circuit. The plurality of memory circuits are semiconductor devices provided in a layer laminated on a layer having the switching circuit, the first arithmetic circuit, and the second arithmetic circuit.

[0012] One aspect of the present invention includes a plurality of memory circuits, a switching circuit, a first arithmetic circuit, and a second arithmetic circuit. Each of the plurality of memory circuits has a function of holding weight data. The switching circuit has a function of switching the conduction state between any one of the plurality of memory circuits and the first arithmetic circuit. The first arithmetic circuit outputs a first output signal based on the product-sum operation processing of input data and the weight data selected by the switching circuit to the second arithmetic circuit. The second arithmetic circuit has a function of performing activation function operation processing, quantization operation processing, and first pooling operation processing. The plurality of memory circuits are semiconductor devices provided in a layer laminated on a layer having the switching circuit, the first arithmetic circuit, and the second arithmetic circuit.

[0013] One aspect of the present invention includes a plurality of memory circuits, a switching circuit, a first arithmetic circuit, a second arithmetic circuit, and a third arithmetic circuit. Each of the plurality of memory circuits has a function of holding weight data. The switching circuit has a function of switching the conduction state between any one of the plurality of memory circuits and the first arithmetic circuit. The first arithmetic circuit outputs a first output signal based on a sum-of-products operation process of input data and the weight data selected by the switching circuit to the second arithmetic circuit. The second arithmetic circuit has a function of performing an activation function operation process, a quantization operation process, and a first pooling operation process. The third arithmetic circuit has a function of performing a second pooling operation process on the second output signal output by the second arithmetic circuit. The plurality of memory circuits are preferably provided in a layer stacked on a layer having the switching circuit, the first arithmetic circuit, and the second arithmetic circuit, in a semiconductor device.

[0014] In one aspect of the present invention, the memory circuit preferably has a first transistor, and the first transistor has a semiconductor layer having a metal oxide in a channel formation region, in a semiconductor device.

[0015] In one aspect of the present invention, the metal oxide contains In, Ga, and Zn, in a semiconductor device.

[0016] In one aspect of the present invention, the switching circuit, the first arithmetic circuit, and the second arithmetic circuit preferably have a second transistor, and the second transistor has a semiconductor layer having silicon in a channel formation region, in a semiconductor device.

[0017] For other aspects of the present invention, they are described in the embodiments described below and in the drawings.

Advantages of the Invention

[0018] One aspect of the present invention can provide a miniaturized semiconductor device. Or, one aspect of the present invention can provide a semiconductor device with reduced power consumption. Or, one aspect of the present invention can provide a semiconductor device with improved arithmetic processing speed. Or, a semiconductor device with a novel configuration can be provided.

[0019] The description of multiple effects does not preclude the existence of other effects. Furthermore, one embodiment of the present invention does not necessarily have to possess all of the exemplified effects. In addition, any problems, effects, and novel features of one embodiment of the present invention other than those described above will become clear from the description and drawings of this specification. [Brief explanation of the drawing]

[0020] [Figure 1] Figures 1A and 1B illustrate an example of the configuration of a semiconductor device. [Figure 2] Figure 2 illustrates an example of a semiconductor device configuration. [Figure 3] Figure 3 illustrates an example of a semiconductor device configuration. [Figure 4] Figures 4A and 4B illustrate an example of the configuration of a semiconductor device. [Figure 5] Figures 5A and 5B illustrate an example of the configuration of a semiconductor device. [Figure 6] Figures 6A, 6B, and 6C illustrate an example of a semiconductor device configuration. [Figure 7] Figures 7A and 7B illustrate an example of the configuration of a semiconductor device. [Figure 8] Figure 8 illustrates an example of a semiconductor device configuration. [Figure 9] Figures 9A and 9B illustrate an example of the configuration of a semiconductor device. [Figure 10] Figure 10 is a diagram illustrating an example of a semiconductor device configuration. [Figure 11] Figure 11 is a diagram illustrating an example of a semiconductor device configuration. [Figure 12] Figure 12 illustrates an example of a semiconductor device configuration. [Figure 13] Figures 13A and 13B illustrate an example of a semiconductor device configuration. [Figure 14] Figures 14A and 14B illustrate an example of the configuration of a semiconductor device. [Figure 15]Figure 15 is a diagram illustrating an example of a semiconductor device configuration. [Figure 16] Figures 16A and 16B illustrate an example of a semiconductor device configuration. [Figure 17] Figure 17 illustrates an example of the configuration of a computing system. [Figure 18] Figure 18 is a diagram illustrating an example of a CPU configuration. [Figure 19] Figures 19A and 19B illustrate an example of a CPU configuration. [Figure 20] Figure 20 shows an example of a CPU configuration. [Figure 21] Figure 21 shows an example of a transistor configuration. [Figure 22] Figures 22A and 22B show examples of transistor configurations. [Figure 23] Figures 23A and 23B illustrate an example of an integrated circuit configuration. [Figure 24] Figures 24A and 24B illustrate examples of applications for integrated circuits. [Figure 25] Figures 25A and 25B illustrate examples of applications for integrated circuits. [Figure 26] Figures 26A, 26B, and 26C illustrate examples of applications for integrated circuits. [Figure 27] Figure 27 illustrates an example of an integrated circuit application. [Modes for carrying out the invention]

[0021] Embodiments of the present invention are described below. However, it will be readily apparent to those skilled in the art that an embodiment of the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, an embodiment of the present invention is not to be interpreted as being limited to the contents of the embodiments shown below.

[0022] In this specification, the ordinal numbers "1st," "2nd," and "3rd" are used to avoid confusion of constituent elements. Therefore, they do not limit the number of constituent elements, nor do they limit the order of the constituent elements. For example, a constituent element referred to as "1st" in one embodiment of this specification may be referred to as "2nd" in another embodiment or in the claims. For example, a constituent element referred to as "1st" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0023] In drawings, identical elements, elements with similar functions, elements of the same material, or elements formed simultaneously may be denoted by the same reference numeral, and repeated explanations may be omitted.

[0024] In this specification, for example, the power supply potential VDD may be abbreviated as potential VDD, VDD, etc. This also applies to other components (e.g., signals, voltages, circuits, elements, electrodes, wiring, etc.).

[0025] Furthermore, when the same designation is used for multiple elements, especially when it is necessary to distinguish them, identification designations such as "_1", "_2", "[n]", and "[m,n]" may be added to the designation. For example, the second wiring GL is written as wiring GL[2].

[0026] (Embodiment 1) The configuration and operation of a semiconductor device according to one aspect of the present invention will be described.

[0027] In this specification, the term "semiconductor device" refers to any device that can function by utilizing semiconductor properties. Semiconductor elements such as transistors, as well as semiconductor circuits, computing devices, and memory devices, are all forms of semiconductor devices. Display devices (such as liquid crystal displays and light-emitting displays), projection devices, lighting devices, electro-optical devices, energy storage devices, memory devices, semiconductor circuits, imaging devices, and electronic devices may also be considered to have semiconductor devices.

[0028] Figure 1A is a diagram illustrating a semiconductor device 10 according to one aspect of the present invention. Figure 1B is a diagram illustrating an example of the configuration of an arithmetic block in the semiconductor device 10.

[0029] The semiconductor device 10 functions as an accelerator, executing a program (also called a kernel or kernel program) called from a host program. The semiconductor device 10 can perform, for example, parallel processing of matrix operations in graphics processing, parallel processing of multiply-accumulate operations in neural networks, and parallel processing of floating-point operations in scientific and technical calculations.

[0030] As shown in Figure 1A, the semiconductor device 10 has a plurality of arithmetic blocks 20. Each arithmetic block 20 includes a memory circuit section 30 (also called a memory cell array) and an arithmetic circuit section 40. As shown in Figures 1A and 1B, the memory circuit section 30 and the arithmetic circuit section 40 are arranged on different layers in a direction approximately perpendicular to the xy plane in the figures (the z direction in Figure 1A). In other words, the memory circuit section 30 and the arithmetic circuit section 40 are stacked.

[0031] "Approximately perpendicular" refers to a state where the elements are positioned at an angle of 85 degrees or more and 95 degrees or less. In this specification, the X, Y, and Z directions shown in Figure 1B, etc., are mutually orthogonal or intersecting directions. Furthermore, the X and Y directions are parallel or approximately parallel to the substrate surface, and the Z direction is perpendicular or approximately perpendicular to the substrate surface.

[0032] The memory circuit section 30 has a plurality of circuit blocks 31. Each circuit block 31 has a plurality of memory circuits 32. Writing and reading data to and from the memory circuits 32 is controlled by drive circuits 12 and 13. Drive circuits 12 and 13 are also called data control circuits.

[0033] The data stored in the memory circuit 32 is data corresponding to the weight parameters used in the sum-of-accumulate operation of the neural network (weight data). By using digital data for the weight data, a semiconductor device that is resistant to noise and capable of high-speed calculations can be created. Alternatively, the weight data may also be analog data.

[0034] In the layer having the memory circuit section 30, the memory circuit 32 of the circuit block 31 is connected to the switching circuit 41 of the arithmetic circuit section 40 via wiring LBL_1 to LBL_4 (also called local bit lines or read bit lines), as shown as an example. The memory circuit 32 of the memory circuit section 30 has an oxide semiconductor transistor (OS transistor) in the channel formation region.

[0035] The layer having the arithmetic circuit section 40 includes a switching circuit 41, a multiply-accumulate circuit 42, a dedicated activation function circuit 43, a quantization circuit 44, and a pre-pooling circuit 45. The control and processing of data input and output in the arithmetic circuit section 40 are controlled by a control circuit 14 and a processing circuit 15. The control circuit 14 and the processing circuit 15 are also called the arithmetic control circuit, arithmetic processing circuit, or arithmetic circuit.

[0036] The switching circuit 41 has the function of selecting the potential of the wirings LBL_1 to LBL_4 extending from each of the multiple circuit blocks 31 and transmitting it to the wiring GBL (also called the global bit line). The switching circuit 41 can use, for example, a three-state buffer whose output potential state is controlled by a control signal. Preferably, the switching circuit 41 is composed of a transistor (Si transistor) having silicon in the channel formation region. This configuration allows for high-speed switching of the connection state.

[0037] Wiring LBL_1 to LBL_4 (wiring LBL) is used to transmit weight data from the memory circuit section 30 to the arithmetic circuit section 40. In order to read weight data from the memory circuit section 30 to the wiring LBL at high speed, it is preferable to make the wiring LBL short. It is also preferable to make the wiring LBL short in order to reduce the energy consumption associated with charging and discharging. In other words, it is preferable to configure the switching circuit 41 to be positioned close to the wiring LBL (arrows extending in the z direction in the figure) that are provided extending in the z direction. By bringing the physical distance between the arithmetic circuit section 40 and the memory circuit section 30 closer, for example by stacking the circuits to shorten the wiring distance, parasitic capacitance occurring in the signal lines can be reduced, thus enabling lower power consumption.

[0038] The multiply-accumulate circuit 42 has the function of performing arithmetic operations such as multiply-accumulate operations. The multiply-accumulate circuit 42 may also be simply called the arithmetic circuit or the first arithmetic circuit. The multiply-accumulate circuit 42 performs a multiply-accumulate operation on the input data input from the control circuit 14 and the weight data given to the wiring GBL. The input data and weight data are preferably digital data. Digital data is less susceptible to noise. Therefore, the multiply-accumulate circuit 42 is suitable for performing arithmetic operations that require highly accurate calculation results. It is preferable that the multiply-accumulate circuit 42 is composed of Si transistors.

[0039] The activation function calculation circuit 43 has the function of processing data obtained by the sum-of-products operation based on an activation function. Examples of activation functions that can be used include the sigmoid function, tanh function, softmax function, ReLU (Rectified Linear Unit) function, and threshold function. The ReLU function outputs "0" if the input value is negative, and outputs the input value as is if the input value is "0" or greater. It is preferable that the activation function calculation circuit 43 is composed of Si transistors.

[0040] The quantization arithmetic circuit 44 has the function of performing quantization arithmetic operations to reduce the bit width of the input data in order to reduce the amount of computation in subsequent operations. In multiply-accumulate operations, the bit width increases due to repeated operations. Therefore, the quantization arithmetic circuit 44 reduces the bit width by bit-shifting the input data and rounding the data at the decimal point. It is preferable that the quantization arithmetic circuit 44 is composed of Si transistors.

[0041] The pre-pooling arithmetic circuit 45 has the function of performing a part of the pooling arithmetic process. For example, in the case of 3x3 pooling, performing an arithmetic operation using only some of the values ​​in the 3x3 region, rather than using all of them, is sometimes called pre-pooling, pre-pooling arithmetic processing, or first pooling arithmetic processing. Alternatively, since pre-pooling arithmetic processing is an arithmetic process that performs a part of the pooling arithmetic process, it may be called partial pooling arithmetic processing or first partial pooling arithmetic processing. In max pooling, for example, the pre-pooling arithmetic circuit 45 corresponds to a circuit that extracts the maximum value of data in a part of the region, for example, one-dimensional data, as the output data of the pre-pooling arithmetic circuit 45. It is preferable that the pre-pooling arithmetic circuit 45 is composed of Si transistors.

[0042] Furthermore, the output data obtained from the pre-pooling calculation circuit 45 is output to the processing circuit 15. For example, by performing calculations in the post-pooling calculation circuit within the processing circuit 15, the data can be made to have calculations equivalent to those performed in the pooling calculation. For example, in the case of 3x3 pooling, performing pre-pooling calculations using the numerical values ​​in a 3x1 region and then performing pooling calculations equivalent to 3x3 pooling using the data obtained from the pre-pooling calculation is sometimes called post-pooling, post-pooling calculation, or second-stage pooling calculation. Alternatively, since post-pooling calculation is an calculation that performs a part of the pooling calculation, it may be called partial pooling calculation or second-stage partial pooling calculation. A processing circuit having a post-pooling calculation circuit may be called an calculation circuit or a third-stage calculation circuit. Specific examples of calculations in the pre-pooling calculation circuit and post-pooling calculation circuit will be described later.

[0043] The switching circuit 41, the multiply-accumulate circuit 42, the dedicated activation function circuit 43, the quantization circuit 44, and the pre-pooling circuit 45 can be made of Si transistors and therefore stacked with OS transistors. In other words, the memory circuit section 30, which is composed of OS transistors, can be stacked with the arithmetic circuit section 40, which can be composed of Si transistors. As a result, the area on which the memory circuit section 30 can be placed can be increased without increasing the circuit area. By placing the area on which the memory circuit section 30 is provided on the same substrate as the arithmetic circuit section 40, the memory capacity required for arithmetic processing in the semiconductor device 10, which functions as an accelerator, can be increased compared to the case where the memory circuit section 30 and the arithmetic circuit section 40 are placed on the same layer. By increasing the memory capacity, the number of data transfers required for arithmetic processing from the external storage device to the semiconductor device can be reduced, thereby lowering power consumption.

[0044] The memory circuit 32 in the memory circuit section 30 can be configured as a NOSRAM. "NOSRAM (registered trademark)" is an abbreviation for "Nonvolatile Oxide Semiconductor RAM". NOSRAM is a memory in which the memory cell is a 2-transistor type (2T) or 3-transistor type (3T) gain cell and the access transistor is an OS transistor.

[0045] OS transistors have extremely low leakage current, or current flowing between the source and drain, when they are off. NOSRAM can be used as non-volatile memory by utilizing this extremely low leakage current characteristic to hold charge corresponding to the data within the memory circuit. In particular, NOSRAM can read data without destroying it (non-destructive read), making it suitable for parallel processing of multiply-accumulate operations in neural networks, which involve repeating data read operations a large number of times.

[0046] The memory circuit 32 is preferably a memory having an OS transistor, such as NOSRAM or DOSRAM (hereinafter also referred to as OS memory). Since the band gap of the metal oxide that functions as an oxide semiconductor is 2.5 eV or more, the OS transistor has an extremely small off current. As an example, with a source-drain voltage of 3.5 V and at room temperature (25°C), the off current per 1 μm of channel width is 1 × 10⁻¹⁶. -20 Less than A, 1 × 10 -22 Less than A, or 1 × 10 -24 It can be less than A. Therefore, the amount of charge leaking from the holding node via the OS transistor in the OS memory is extremely small. Consequently, the OS memory can function as a non-volatile memory circuit, enabling power gating of the semiconductor device 10.

[0047] Semiconductor devices with high-density transistor integration can generate heat due to circuit operation. This heat can raise the temperature of the transistors, altering their characteristics and potentially causing changes in field-effect mobility and a decrease in operating frequency. OS transistors have higher thermal resistance than Si transistors, making them less susceptible to changes in field-effect mobility due to temperature fluctuations, and also less prone to a decrease in operating frequency. Furthermore, OS transistors tend to maintain the characteristic of exponentially increasing drain current with respect to gate-source voltage even at high temperatures. Therefore, using OS transistors enables stable operation in high-temperature environments.

[0048] Metal oxides applicable to OS transistors include Zn oxide, Zn-Sn oxide, Ga-Sn oxide, In-Ga oxide, In-Zn oxide, and In-M-Zn oxide (where M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf). In particular, metal oxides using Ga as M are preferred for OS transistors because adjusting the elemental ratios can result in transistors with excellent electrical properties such as field-effect mobility. Furthermore, oxides containing indium and zinc may also contain one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and others.

[0049] To improve the reliability and electrical characteristics of OS transistors, the metal oxide applied to the semiconductor layer is preferably a metal oxide having a crystalline portion, such as CAAC-OS, CAC-OS, or nc-OS. CAAC-OS is an abbreviation for c-axis-aligned crystalline oxide semiconductor. CAC-OS is an abbreviation for Cloud-Aligned Composite oxide semiconductor. nc-OS is an abbreviation for nanocrystalline oxide semiconductor.

[0050] CAAC-OS has a c-axis orientation and a crystal structure in which multiple nanocrystals are linked in the ab-plane direction, resulting in a strained structure. Strain refers to the area where the orientation of the lattice arrangement changes between regions with aligned lattice arrangements and other regions with aligned lattice arrangements, within the region where multiple nanocrystals are linked.

[0051] CAC-OS has the function of allowing electrons (or holes) to flow as carriers and the function of not allowing electrons to flow as carriers. By separating the function of allowing electrons to flow from the function of not allowing electrons to flow, both functions can be maximized. In other words, by using CAC-OS in the channel formation region of an OS transistor, both high on-current and extremely low off-current can be achieved.

[0052] Because metal oxides have a large band gap, electrons are not easily excited, and the effective mass of holes is large, OS transistors are less prone to avalanche decay compared to general Si transistors. Therefore, for example, hot carrier degradation caused by avalanche decay can be suppressed. By suppressing hot carrier degradation, OS transistors can be driven at high drain voltages.

[0053] OS transistors are storage-type transistors that use electrons as majority carriers. Therefore, compared to inverting transistors with pn junctions (typically Si transistors), they are less affected by DIBL (Drain-Induced Barrier Lowering), one of the short-channel effects. In other words, OS transistors have higher resistance to short-channel effects than Si transistors.

[0054] OS transistors have high resistance to short-channel effects, allowing for a reduction in channel length without degrading the reliability of the OS transistor. Therefore, using OS transistors can increase the integration density of circuits. As the channel length is reduced, the drain field strength increases, but as mentioned above, OS transistors are less prone to avalanche decay than Si transistors.

[0055] Furthermore, because OS transistors have high resistance to short-channel effects, it is possible to use thicker gate insulators than Si transistors. For example, even in fine transistors with channel length and channel width of 50 nm or less, it may be possible to provide a gate insulator about 10 nm thick. By increasing the thickness of the gate insulator, parasitic capacitance can be reduced, thereby improving the operating speed of the circuit. In addition, by increasing the thickness of the gate insulator, leakage current through the gate insulator is reduced, leading to a reduction in static current consumption.

[0056] As described above, the semiconductor device 10 has a memory circuit 32 which is an OS memory, so it can retain data even when the power supply voltage is interrupted. Therefore, power gating of the semiconductor device 10 becomes possible, and power consumption can be significantly reduced.

[0057] Next, Figure 2 describes a block diagram showing the entire arithmetic processing system 100, including a semiconductor device 10 that functions as an AI accelerator.

[0058] Figure 2 illustrates the accelerator unit 130, which has multiple semiconductor devices 10 as described in Figures 1A and 1B, as well as the CPU 110 and bus 120. The CPU 110 has a CPU core 200 and a backup circuit 222. In addition to the multiple semiconductor devices 10, the accelerator unit 130 has a control unit 131 for controlling the input and output of data between the semiconductor devices 10.

[0059] The CPU 110 has functions for general-purpose processing, such as executing the operating system, controlling data, and executing various calculations and programs. The CPU 110 has a CPU core 200. The CPU core 200 corresponds to one or more CPU cores. The CPU 110 also has a backup circuit 222 that can retain data in the CPU core 200 even if the power supply voltage is interrupted. The power supply voltage can be controlled by electrical disconnection from the power domain using a power switch or the like. Note that the power supply voltage is sometimes called the drive voltage. As the backup circuit 222, for example, an OS memory having an OS transistor is preferred.

[0060] The backup circuit 222, which is composed of OS transistors, can be stacked with the CPU core 200, which can be composed of Si transistors. Since the area of ​​the backup circuit 222 is smaller than the area of ​​the CPU core 200, the backup circuit 222 can be placed on the CPU core 200 without increasing the circuit area. The backup circuit 222 has the function of holding the data of the registers of the CPU core 200. The backup circuit 222 is also called a data holding circuit. Further details of the configuration of the CPU core 200 equipped with the backup circuit 222 having OS transistors will be explained in Embodiment 3.

[0061] The control unit 131 has an internal memory circuit such as SRAM. The control unit 131 stores the output data obtained from multiple semiconductor devices 10 in the memory circuit. The configuration is such that it outputs the output data MAC stored in the memory circuit to the multiple semiconductor devices. This configuration enables parallel computing with a high degree of parallelism using multiple semiconductor devices.

[0062] Bus 120 electrically connects the CPU 110 and the accelerator unit 130. In other words, data can be transmitted between the CPU 110 and the semiconductor device 10 via bus 120.

[0063] Figure 3 is a diagram illustrating suitable transistors for the memory circuit section 30 and the arithmetic circuit section 40 in the arithmetic block 20 shown in Figure 1B.

[0064] The memory circuit section 30 has a memory circuit 32. The memory circuit 32 has a transistor 21. By making the semiconductor layer 22 of the transistor 21 an oxide semiconductor (metal oxide), the memory circuit 32 can be composed of the OS transistor described above.

[0065] The arithmetic circuit section 40 includes a switching circuit 41, a multiply-accumulate circuit 42, a dedicated activation function circuit 43, a quantization circuit 44, and a pre-pooling circuit 45. Each circuit in the arithmetic circuit section 40 has a transistor 23. By making the semiconductor layer 24 of the transistor 23 out of silicon, each circuit in the arithmetic circuit section 40 can be composed of the Si transistors described above.

[0066] By placing the memory circuit section 30 on the same substrate as the arithmetic circuit section 40, the memory capacity required for arithmetic processing in the semiconductor device 10, which functions as an accelerator, can be increased, compared to the case where the memory circuit section 30 and the arithmetic circuit section 40 are arranged on the same layer. This increases the memory capacity, which reduces the number of data transfers required for arithmetic processing from the external storage device to the semiconductor device, thereby reducing power consumption.

[0067] Figure 4A is a block diagram illustrating the data input and output of each circuit in a semiconductor device 10 according to one embodiment of the present invention. Figure 4A shows a switching circuit 41, a multiply-accumulate circuit 42, a dedicated activation function circuit 43, a quantization circuit 44, and a pre-pooling circuit 45.

[0068] The switching circuit 41 has the function of switching the conduction state between one of the memory circuits 32 and the sum-of-accumulate circuit 42. For example, the switching circuit 41 outputs weight data W1 to W from the data held in the memory circuit 32 in the circuit block 31 of the memory circuit section 30 to the wiring GBL. N (N is a natural number greater than or equal to 2) is selected. Then the switching circuit 41 selects the weight data W from the selected weight data. SEL The output is then sent to the multiply-accumulate circuit 42 via wiring GBL.

[0069] The sum-of-products circuit 42 outputs data (output signal) based on the sum-of-products operation of the input data and the weight data selected by the switching circuit 41 to the dedicated calculation circuit 46. For example, the sum-of-products circuit 42 outputs the weight data W SEL And input data A is input from control circuit 14. IN A sum-of-products operation is performed based on this. The data MAC obtained by this sum-of-products operation is output to the activation function operation circuit 43 in the dedicated operation circuit 46.

[0070] The dedicated arithmetic circuit 46 is a circuit for performing operations such as multiply-accumulate operations in the neural network used for convolution, such as operations based on activation functions, operations for quantization, operations for pooling operations, or operations for normalization. The dedicated arithmetic circuit 46 may also be called an arithmetic circuit or a second arithmetic circuit. As an example, the diagram shows a configuration in which the dedicated arithmetic circuit 46 has an activation function arithmetic circuit 43, a quantization arithmetic circuit 44, and a pre-pooling arithmetic circuit 45, but it may have other configurations.

[0071] The activation function arithmetic circuit 43 is a circuit that performs arithmetic processing based on the activation function on the input data MAC and outputs it as data FUNC obtained from the arithmetic processing based on the activation function. The data FUNC is output to the quantization arithmetic circuit 44 in the dedicated arithmetic circuit 46.

[0072] The quantization arithmetic circuit 44 is a circuit that performs quantization operations on the input data FUNC and outputs it as data QUA. The quantization operations adjust the bit width of the input data by bit shifting the input data and rounding the data at the decimal point. Data QUA is output to the pre-pooling arithmetic circuit 45 in the dedicated arithmetic circuit 46.

[0073] The pre-pooling calculation circuit 45 is a circuit that performs a part of the pooling calculation on the input data QUA and outputs data PPD that has undergone pre-pooling calculation. By having the pre-pooling calculation circuit 45, the dedicated calculation circuit 46 can perform a part of the pooling calculation. As shown in Figure 4B, the data PPD is output to the post-pooling calculation circuit 47 of the processing circuit 15. The processing circuit 15 having the post-pooling calculation circuit 47 may be called the calculation circuit or the third calculation circuit.

[0074] The post-pooling calculation circuit 47 is a circuit that performs calculations on the input data PPD and outputs data PD which has undergone pooling calculation on data QUA. By having the post-pooling calculation circuit 47, the processing circuit 15 can be made more compact compared to when all the calculations for the pooling calculation are performed by the processing circuit 14. Data PD is input data A IN It is used as such.

[0075] Figure 5A illustrates an example of a circuit configuration applicable to a circuit block 31 in a memory circuit section 30 of the semiconductor device 10 of the present invention. Figure 5A shows write word lines WWL_1 to WWL_M, read word lines RWL_1 to RWL_M, write bit lines WBL_1 to WBL_N, and wiring LBL_1 to LBL_N arranged in an M x N matrix direction (M and N are natural numbers of 2 or more). A memory circuit 32 connected to each word line and bit line is also shown.

[0076] Figure 5B illustrates an example of a circuit configuration applicable to the memory circuit 32. The memory circuit 32 includes transistors 61, 62, 63, and a capacitive element 64 (also called a capacitor).

[0077] One of the sources or drains of transistor 61 is connected to the write bit line WBL. The gate of transistor 61 is connected to the write word line WWL. The other of the sources or drains of transistor 61 is connected to one electrode of the capacitive element 64 and the gate of transistor 62. One of the sources or drains of transistor 62 and the other electrode of the capacitive element 64 are connected to a wire that provides a fixed potential, such as ground potential. The other of the sources or drains of transistor 62 is connected to one of the sources or drains of transistor 63. The gate of transistor 63 is connected to the read word line RWL. The other of the sources or drains of transistor 63 is connected to the wire LBL. The wire LBL is connected to the wire GBL via the switching circuit 41. The wire LBL is connected to the switching circuit 41 via a wire that extends in a direction approximately perpendicular to the substrate surface on which the Si transistors of the arithmetic circuit section 40 are provided.

[0078] The circuit configuration of the memory circuit 32 shown in Figure 5B corresponds to a 3-transistor (3T) gain cell NOSRAM. Transistors 61 to 63 are OS transistors. OS transistors have an extremely small current flowing between their source and drain when off, i.e., a leakage current. NOSRAM can be used as a non-volatile memory by using this extremely low leakage current characteristic to hold a charge corresponding to the data within the memory circuit.

[0079] The circuit configuration applicable to the memory circuit 32 in Figure 5A is not limited to the 3T type NOSRAM in Figure 5B. For example, a circuit equivalent to the DOSRAM shown in Figure 6A may also be used. Figure 6A illustrates a memory circuit 32A having a transistor 61A and a capacitive element 64A. Transistor 61A is an OS transistor. The memory circuit 32A is shown as an example connected to the bit line BL, word line WL, and back gate line BGL.

[0080] The circuit configuration applicable to the memory circuit 32 in Figure 5A may also be a circuit corresponding to the 2T type NOSRAM shown in Figure 6B. Figure 6B illustrates a memory circuit 32B having transistors 61B, 62B and capacitive elements 64B. Transistors 61B and 62B are OS transistors. Transistors 61B and 62B may be OS transistors with semiconductor layers arranged on different layers, or OS transistors with semiconductor layers arranged on the same layer. The memory circuit 32B is illustrated as an example connected to a write bit line WBL, a wiring LBL that functions as a read bit line, a write word line WWL, a read word line RWL, a source line SL and a back gate line BGL.

[0081] The circuit configuration applicable to the memory circuit 32 in FIG. 5A may also be a circuit combining the 3T-type NOSRAM illustrated in FIG. 6C. FIG. 6C illustrates a memory circuit 32C having a memory circuit 32_P capable of holding different logical data and a memory circuit 32_N. In FIG. 6C, a memory circuit 32_P having a transistor 61_P, a transistor 62_P, a transistor 63_P, and a capacitor element 64_P, and a memory circuit 32_N having a transistor 61_N, a transistor 62_N, a transistor 63_N, and a capacitor element 64_N are illustrated. Each transistor included in the memory circuit 32_P and the memory circuit 32_N is an OS transistor. Each transistor included in the memory circuit 32_P and the memory circuit 32_N may be an OS transistor in which semiconductor layers are disposed in different layers, or may be an OS transistor in which semiconductor layers are disposed in the same layer. FIG. 6C illustrates an example in which the memory circuit 32C is connected to a write bit line WBL_P, a wiring LBL_P, a write bit line WBL_N, a wiring LBL_N, a write word line WWL, and a read word line RWL. The memory circuit 32C can hold different logical data and read different logical data to the wirings LBL_P and LBL_N.

[0082] In the configuration of FIG. 6C, an exclusive OR circuit (XOR circuit) may be provided so that data corresponding to the multiplication of the data held in the memory circuit 32_P and the memory circuit 32_N is output to the wiring LBL. With this configuration, the operation corresponding to the multiplication in the product-sum operation circuit 42 can be omitted, and thus power consumption can be reduced.

[0083] FIG. 7A is a diagram for explaining the switching circuit 41. In FIG. 7A, it is described that weight data W1 to W6 are read from the memory circuit 32 in the circuit block 31 to the wirings LBL_1 to LBL_6. Further, the weight data selected from the weight data W1 to W6 by the switching circuit 41 and given to the wiring GBL is described as weight data W SEL . Input data A IN is given to the product-sum operation circuit 42, and it is described that data MAC corresponding to the product-sum operation data is obtained.

[0084] Vertical wiring LBLs connecting the upper and lower layers in wiring LBL_1 to LBL_6. P These wires are shorter than horizontally extending wires. Therefore, the parasitic capacitance of wires LBL_1 to LBL_6 can be reduced, the charge required for charging and discharging the wires can be reduced, and power consumption can be lowered and computational efficiency can be improved. In addition, reading from the memory circuit 32 to wires LBL_1 to LBL_6 can be done at high speed.

[0085] Through the wiring GBL, the weight data W is processed in the sum-of-products operation circuit 42. SEL It is possible to perform calculations using the weight data W. SEL This configuration can be used to supply power to multiple multiply-accumulate circuits 42 via a wiring GBL. This configuration is suitable for the computational processing of a convolutional neural network that performs computational processing using the same weight data.

[0086] Figure 7B shows an example of a circuit configuration applicable to the switching circuit 41 shown in Figure 7A. The three-state buffer shown in Figure 7B has the function of amplifying and transmitting the potential of wiring LBL to wiring GBL according to the control signal EN. The switching circuit 41 can be considered a multiplexer. It has the function of selecting one from multiple input signals.

[0087] In Figure 7A, the switching circuit 41 selects one wiring from multiple wiring LBLs and generates weight data W. SEL Although the diagram illustrates a configuration for providing data to the wiring GBL, other configurations are also possible. For example, a configuration with multiple switching circuits may be used as the switching circuit. Also, in Figure 7A, the configuration was described in which each memory circuit 32 holds 1 bit of data (i.e., data of '1' or '0') and performs arithmetic processing using this data, but one aspect of the present invention is also applicable to configurations that perform arithmetic processing using multi-bit data. In the case of multi-bit data (for example, n bits), a configuration can be used in which switching circuits 41 connected to wiring LBL_1 to LBL_n in a number corresponding to the number of bits are used to select the multi-bit weight data to be provided to the wiring GBL.

[0088] When the memory circuit section 30 and the arithmetic circuit section 40 are on separate chips, the bus width is limited according to the number of pins on the chip. On the other hand, in a configuration in which the memory circuit section 30 and the arithmetic circuit section 40 are stacked, as in one embodiment of the present invention, the number of parallel data required for arithmetic processing can be increased according to the openings in which wiring LBLs are provided, thereby enabling efficient arithmetic processing.

[0089] Figure 8 shows a timing chart illustrating the operation of each configuration described in Figure 7A. The multiply-accumulate circuit 42 performs calculations in accordance with the toggle operation of the clock signal CLK (for example, from time T0 to T6). By increasing the frequency of the clock signal CLK, the calculation speed can be increased.

[0090] Input Data A IN When switching rapidly in response to a clock signal CLK, it is necessary to rapidly switch the data of the wiring GBL that provides the weight data.

[0091] In one embodiment of the present invention, the weight data selected from wiring LBL to wiring GBL by the switching circuit 41 is pre-read into wiring LBL_1 to LBL_6, thereby enabling high-speed switching of the data of wiring GBL to which the weight data is provided. For example, weight data W1 can be read into wiring LBL_1 at time T0, and the switching circuit 41 can be switched at time T1 to output weight data W1 from wiring LBL_1 to wiring GBL. At times T1 to T6, the reading of weight data W1 to W6 into wiring LBL and the reading of weight data W in wiring GBL are also performed. SEL By selecting and varying the time of, weight data W corresponding to the clock signal CLK is generated. SEL The configuration can be set up to allow switching between these two states.

[0092] Figure 9A shows a specific configuration example of the multiply-accumulate circuit 42. Figure 9A illustrates a configuration example of the multiply-accumulate circuit 42 that can perform multiply-accumulate operations on 8-bit weight data and 8-bit input data. Figure 9A shows the multiplier circuit 51, the adder circuit 52, and the register 53. The 16-bit data multiplied by the multiplier circuit 51 is input to the adder circuit 52. The output of the adder circuit 52 is held in the register 53, and the data multiplied by the multiplier circuit 51 and the adder circuit 52 are added together to perform the multiply-accumulate operation. The register 53 is controlled by the clock signal CLK and the reset signal reset_B. In the figure, "α" in "17+α" indicates the carry-over that occurs when multiplying data is added. This configuration allows the weight data W SEL and input data A IN This allows you to obtain data MAC equivalent to a sum-of-products operation.

[0093] Furthermore, although Figure 9A describes a configuration that performs arithmetic processing using 8 bits of data, one aspect of the present invention is also applicable to a configuration that uses 1 bit of data. This configuration is illustrated in Figure 9B, similar to Figure 9A. In the case of 1 bit of data, arithmetic processing should be performed according to the number of bits, as shown in Figure 9B.

[0094] Figure 10 shows an example of the configuration of the activation function calculation circuit 43 described above. The activation function calculation circuit 43 shown in Figure 10 is a circuit that has the function of performing activation function calculations based on the ReLU function, as an example.

[0095] The activation function arithmetic circuit 43 shown in Figure 10 has multiple multiplexers 54. For example, 8-bit data MAC[0] to MAC[7] are input to the multiplexer 54. Data 0 is also input to the multiplexer 54. The multiplexer 54 outputs either data MAC[0] to MAC[7] or data 0 as data FUNC[0] to FUNC[7], depending on the most significant bit of the data MAC, which is data MAC[7]. If the data MAC is a signed integer, a 0 in the most significant bit of the data MAC represents a positive value, and a 1 represents a negative value, so the activation function arithmetic circuit 43 can perform activation function calculations based on the ReLU function.

[0096] Figure 11 shows an example of the configuration of the pre-pooling calculation circuit 45 described above. The pre-pooling calculation circuit 45 shown in Figure 11 is a circuit that has the function of performing pre-pooling calculations based on max pooling, as an example.

[0097] The pre-pooling arithmetic circuit 45 shown in Figure 11 has a comparison circuit 55 and a register 56. The comparison circuit 55 receives data that will be the initial value, or data input from register 56, and data QUA output from the quantization arithmetic circuit 44. The comparison circuit 55 compares the two input data and outputs the data with the larger value as data QUA[C] to register 56. Data QUA[C] is held in register 56. The held data QUA[C] becomes data PPD, which is the output signal of the pre-pooling arithmetic circuit 45, or data QUA[MAX], which is input to the comparison circuit 55.

[0098] The operation of the pre-pooling arithmetic circuit 45 will be explained with reference to Figure 12. In Figure 12, it is assumed that data QUA[1], data QUA[2] to data QUA[N] are successively input as data QUA output from the quantization arithmetic circuit 44 in accordance with the change in the clock signal CLK. The comparison circuit 55 takes the data input as the initial value as data QUA[0].

[0099] During period P1, data QUA[0] and data QUA[1] are input to the comparator circuit 55. If data QUA[1] is greater than data QUA[0], data QUA[1] is held in register 56 as the output data of the comparator circuit 55, i.e., data QUA[C].

[0100] Next, during period P2, data QUA[2] is input to the comparator circuit 55 in accordance with the change in the clock signal CLK. The comparator circuit 55 also receives data QUA[1], which was held in register 56 during period P1. If data QUA[2] is greater than data QUA[1], data QUA[2] is held in register 56 as the output data of the comparator circuit 55, i.e., data QUA[C].

[0101] In the comparison circuit 55, the magnitudes of the input data QUA values ​​are compared sequentially, and the larger data is stored in register 56. As a result, register 56 holds the largest data QUA[MAX] among the input data QUA. During period PN, data QUA[N] is input to the comparison circuit 55. The comparison circuit 55 also receives the data QUA[MAX] that has been stored in register 56 up to period P(N-1). If data QUA[MAX] is larger than data QUA[N], data QUA[MAX] is stored in register 56 as the output data of the comparison circuit 55, i.e., data QUA[C]. Then, the data QUA[MAX] stored in register 56 is output as data PPD.

[0102] By performing the operation described in Figure 12 using multiple dedicated arithmetic circuits and comparing the resulting data PPD again, data PD obtained through pooling arithmetic processing can be acquired.

[0103] For example, let's consider a configuration example as shown in Figure 13A, which includes dedicated arithmetic circuits 46_1 to 46_3 and performs 3x3 pooling arithmetic processing. Dedicated arithmetic circuits 46_1 to 46_3 divide and process data QUA[1] to [9] from the quantization arithmetic circuit 44, and the pre-pooling arithmetic circuit 45 can obtain data PPD[1] to [3]. In other words, the pre-pooling arithmetic circuit 45 can extract the maximum value of the one-dimensional data as the data PPD output from the pre-pooling arithmetic circuit 45. The data PPD[1] to [3] are compared in the post-pooling arithmetic circuit 47 in the processing circuit 15 to obtain data PD. The post-pooling arithmetic circuit 47 has the function of a comparison circuit that compares the magnitude of the input data PPD values. In other words, the post-pooling arithmetic circuit 47 can extract the maximum value of the two-dimensional data that becomes 3x3, that is, the data PD which becomes 3x3 max pooling, as output data.

[0104] In the example shown in Figure 13A, the data QUA[1] to [9] are divided and processed by the operation illustrated in Figure 13B, and the data PPD[1] to [3] can be obtained by the pre-pooling arithmetic circuit 45. For example, dedicated arithmetic circuit 46_1 compares data QUA[1] to [3] to obtain data PPD[1]. Dedicated arithmetic circuit 46_2 compares data QUA[4] to [6] to obtain data PPD[2]. Dedicated arithmetic circuit 46_3 compares data QUA[7] to [9] to obtain data PPD[3]. With this configuration, data PPD can be obtained with a small number of clock cycles because different dedicated arithmetic circuits are used to obtain the data PPD.

[0105] For example, as shown in Figure 14A, if data PD is obtained by outputting data QUA[1] to [9] from multiple quantization circuits 44_1 to 44_9 to the post-pooling circuit 47 without obtaining data PPD in the pre-pooling circuit 45, the number of wires transmitting the data increases. As a result, it may become difficult to miniaturize and reduce the power consumption of the semiconductor device 10.

[0106] Furthermore, as illustrated in Figure 14B, when data PD is obtained by comparing data QUA[1] to [9] input to a single pre-pooling arithmetic circuit 45, it takes time to obtain data PD depending on the number of data QUA, which can make it difficult to speed up the arithmetic processing in the semiconductor device 10.

[0107] In the configuration of the semiconductor device 10 in this embodiment, when each arithmetic operation in the neural network is performed by a dedicated arithmetic circuit, a configuration that performs arithmetic operations using multiple data, such as pooling operations, can be implemented with distributed arithmetic operations. Furthermore, since the wiring connecting the dedicated arithmetic circuit and the multiply-accumulate operation circuit can be shortened, the increase in the area required for arranging the dedicated arithmetic circuit can be suppressed. In addition, since multiple memory circuits can be arranged in the dedicated arithmetic circuit, the area available for arranging memory circuits can be increased. As a result, a huge amount of weight data can be held in the memory circuit section, and the number of times weight data is transferred from external memory circuits can be reduced, thus enabling lower power consumption.

[0108] Figure 15 illustrates an example of the configuration of the memory circuit section 30, which is stacked on the arithmetic circuit section 40 as described in Figures 1A and 1B, and its peripheral circuits. Specifically, Figure 15 shows the drive circuit 12, drive circuit 13, control circuit 14, processing circuit 15, switching circuit 41, multiply-accumulate circuit 42, activation function arithmetic circuit 43, quantization arithmetic circuit 44, and pre-pooling arithmetic circuit 45. Figure 15 also shows the post-pooling arithmetic circuit 47 located within the processing circuit 15.

[0109] Although not shown in Figure 15, each circuit in Figure 15 is configured to have control signals, input data, and output data for controlling each circuit connected to and from external circuits.

[0110] Figure 16A is a diagram showing the blocks that control the memory circuit section 30 for each configuration shown in Figure 15. In Figure 16A, in addition to the memory circuit 32 of the circuit block 31 in the memory circuit section 30, the drive circuit 12 and drive circuit 13 are also shown separately.

[0111] The drive circuits 12 and 13 process external input signals to generate signals for writing weight data to the memory circuit and signals for reading weight data from the memory circuit. The generated signals are supplied to the memory circuit via wiring.

[0112] Figure 16B is a diagram showing the blocks that control the arithmetic circuit section 40 for each configuration shown in Figure 15. In Figure 16B, in addition to the switching circuit 41, multiply-accumulate circuit 42, activation function circuit 43, quantization circuit 44, and pre-pooling circuit 45 of the arithmetic circuit section 40, the control circuit 14, processing circuit 15, and post-pooling circuit 47 within the processing circuit 15 are also shown.

[0113] The control circuit 14 receives input data A IN It generates and outputs to the sum-of-accumulate circuit 42. The control circuit 14 outputs a control signal to control the switching circuit 41. The switching circuit 41 selects the weight data read from the memory circuit 32 and outputs the weight data W SEL The data is output to the multiply-accumulate circuit 42. The dedicated arithmetic circuits, the activation function arithmetic circuit 43, the quantization arithmetic circuit 44, and the pre-pooling arithmetic circuit 45, perform arithmetic processing on the data MAC generated by the multiply-accumulate circuit 42, and output the pre-pooling processed data PPD to the post-pooling arithmetic circuit 47 in the processing circuit 15. The post-pooling arithmetic circuit 47 in the processing circuit 15 outputs the pooling processed data PD to the control circuit 14, and the control circuit 14 processes the input data A IN The following is generated. The generated data is re-input to the arithmetic circuit unit 40.

[0114] In the semiconductor device 10, the control circuit 14 can output the processed data as input data to the arithmetic circuit unit 40. Therefore, arithmetic processing can be performed without reading the data during the calculation to a main memory or other external memory outside the semiconductor device 10. In addition, in the semiconductor device 10, the electrical connection between the memory circuit unit and the arithmetic circuit unit can be made via wiring through openings provided in an insulating film, etc., so the number of parallel connections can be increased by increasing the number of wires. As a result, the semiconductor device 10 can perform parallel calculations with a number of bits exceeding the data bus width of the CPU 110. Furthermore, in addition to the multiply-accumulate operation circuit, a circuit that performs dedicated arithmetic processing such as activation function operation processing is stacked with the memory circuit, which increases the area on which the memory circuit can be arranged. As a result, a huge amount of weight data can be held in the memory circuit unit, and the number of times weight data is transferred from an external memory circuit can be reduced, thus reducing power consumption.

[0115] In one embodiment of the present invention, a configuration in which a single arithmetic operation is distributed across multiple locations, such as pooling arithmetic operations, allows for shorter wiring connections between the dedicated arithmetic circuit and the multiply-accumulate arithmetic circuit. Therefore, a configuration in which arithmetic operations are distributed across multiple locations is effective in suppressing the increase in area required for arranging the dedicated arithmetic circuit. This configuration is also effective in configurations where the memory circuit section and the arithmetic circuit section are not stacked, such as the configurations shown in Figures 15, 16A, and 16B, where the memory circuit section 30, the arithmetic circuit section 40, and peripheral circuits such as the drive circuit 12, the drive circuit 13, the control circuit 14, and the processing circuit 15 are made of Si transistors, and the memory circuit section 30 and the arithmetic circuit section 40 are not stacked.

[0116] As described above, one aspect of the present invention can provide a semiconductor device that functions as an accelerator and is miniaturized. Alternatively, one aspect of the present invention can provide a semiconductor device that functions as an accelerator and has reduced power consumption. Alternatively, one can provide a semiconductor device that functions as an accelerator with a novel configuration.

[0117] (Embodiment 2) In this embodiment, an example of operation is described in which a part of the calculations of the program executed by the CPU 110 described in the above embodiment is executed by the accelerator described as the semiconductor device 10.

[0118] Figure 17 illustrates an example of operation when a portion of the calculations in a program executed on the CPU are performed on an accelerator.

[0119] The host program is executed on the CPU (host program execution; step S1).

[0120] When the CPU confirms an instruction to allocate a data area in the memory circuit section that is required when performing calculations using the accelerator (memory allocation instruction; step S2), it allocates the data area in the memory circuit section (memory allocation; step S3).

[0121] Next, the CPU transmits weight data, which is input data, from the main memory or external storage device to the memory circuit unit (data transmission; step S4). The memory circuit unit receives the weight data and stores it in the area reserved in step S3 (data reception; step S5).

[0122] When the CPU confirms the instruction to start the kernel program (starting the kernel program; step S6), the accelerator starts executing the kernel program (starting the calculation; step S7).

[0123] Immediately after the accelerator starts executing the kernel program, the CPU may be switched from the computation state to the PG (power gating) state (PG state transition; step S8). In that case, just before the accelerator finishes executing the kernel program, the CPU is switched from the PG state back to the computation state (PG state termination; step S9). By keeping the CPU in the PG state from step S8 to step S9, power consumption and heat generation can be suppressed for the entire computing system.

[0124] When the accelerator finishes executing the kernel program, the output data is stored in the memory unit that holds the calculation results within the accelerator (completion complete; step S10).

[0125] After the kernel program has finished executing, if the CPU confirms an instruction to send the output data stored in the memory unit to main memory or an external storage device (data transmission request; step S11), the output data is sent to main memory or an external storage device and stored in main memory or an external storage device (data transmission; step S12).

[0126] By repeating the operations from step S1 to step S12 described above, it is possible to suppress the power consumption and heat generation of the CPU and accelerator while performing a portion of the calculations performed by the CPU on the accelerator. One embodiment of the present invention is a semiconductor device having a non-von Neumann architecture, which can perform calculations with extremely low power consumption compared to a von Neumann architecture, where power consumption increases with increasing processing speed.

[0127] This embodiment can be appropriately combined with descriptions of other embodiments.

[0128] (Embodiment 3) This embodiment describes an example of a CPU having CPU cores capable of power gating.

[0129] Figure 18 shows an example configuration of the CPU 110. The CPU 110 includes a CPU core 200, an L1 (level 1) cache memory device 202, an L2 cache memory device 203, a bus interface unit 205, power switches 210-212, and a level shifter (LS) 214. The CPU core 200 has a flip-flop 220.

[0130] The bus interface unit 205 interconnects the CPU core 200, the L1 cache memory device 202, and the L2 cache memory device 203.

[0131] In response to externally input interrupt signals and signals such as SLEEP1 issued by the CPU 110, the PMU 193 generates the clock signal GCLK1 and various PG (power gating) control signals. The clock signal GCLK1 and PG control signals are input to the CPU 110. The PG control signals control the power switches 210-212 and the flip-flop 220.

[0132] Power switches 210 and 211 control the supply of voltages VDDD and VDD1 to the virtual power line V_VDD (hereinafter referred to as the V_VDD line), respectively. Power switch 212 controls the supply of voltage VDDH to the level shifter (LS) 214. Voltage VSSS is input to the CPU 110 and PMU 193 without going through the power switches. Voltage VDDD is input to the PMU 193 without going through the power switches.

[0133] Voltages VDDD and VDD1 are drive voltages for CMOS circuits. Voltage VDD1 is lower than voltage VDDD and is the drive voltage in sleep mode. Voltage VDDH is the drive voltage for OS transistors and is higher than voltage VDDD.

[0134] Each of the L1 cache memory device 202, the L2 cache memory device 203, and the bus interface unit 205 has at least one power-gated power domain. Each power-gated power domain is provided with one or more power switches. These power switches are controlled by a PG control signal.

[0135] Flip-flop 220 is used as a register. Flip-flop 220 has a backup circuit. The following is a description of flip-flop 220.

[0136] Figure 19A shows an example of the circuit configuration of the flip-flop 220. The flip-flop 220 includes a scan flip-flop 221 and a backup circuit 222.

[0137] The scan flip-flop 221 has nodes D1, Q1, SD, SE, RT, CK, and a clock buffer circuit 221A.

[0138] Node D1 is a data input node, node Q1 is a data output node, and node SD is an input node for scan test data. Node SE is an input node for signal SCE. Node CK is an input node for clock signal GCLK1. Clock signal GCLK1 is input to clock buffer circuit 221A. The analog switch of scan flip-flop 221 is connected to nodes CK1 and CKB1 of clock buffer circuit 221A. Node RT is an input node for the reset signal.

[0139] The signal SCE is a scan enable signal and is generated by the PMU193. The PMU193 generates signals BK and RC. The level shifter 214 level-shifts signals BK and RC to generate signals BKH and RCH. Signal BK is a backup signal, and signal RC is a recovery signal.

[0140] The circuit configuration of scan flip-flop 221 is not limited to Figure 19. Flip-flops available in standard circuit libraries can be used.

[0141] The backup circuit 222 includes nodes SD_IN, SN11, transistors M11 to M13, and a capacitive element C11.

[0142] Node SD_IN is the input node for scan test data and is connected to node Q1 of scan flip-flop 221. Node SN11 is the holding node of backup circuit 222. Capacitor element C11 is a holding capacitance for holding the voltage of node SN11.

[0143] Transistor M11 controls the conduction state between node Q1 and node SN11. Transistor M12 controls the conduction state between node SN11 and node SD. Transistor M13 controls the conduction state between node SD_IN and node SD. The on / off states of transistors M11 and M13 are controlled by signal BKH, and the on / off state of transistor M12 is controlled by signal RCH.

[0144] Transistors M11 to M13 are OS transistors, similar to transistors 61 to 63 in the memory circuit 32 described above. Transistors M11 to M13 are shown with back gates. The back gates of transistors M11 to M13 are connected to a power line that supplies voltage VBG1.

[0145] It is preferable that at least transistors M11 and M12 are OS transistors. Due to the characteristics of OS transistors, which have an extremely low off-current, the voltage drop at node SN11 can be suppressed, and since data retention consumes almost no power, the backup circuit 222 has non-volatile properties. Since data is rewritten by charging and discharging the capacitive element C11, the backup circuit 222 is, in principle, not limited in the number of rewrites, and data can be written and read with low energy.

[0146] It is highly preferable that all transistors in the backup circuit 222 are OS transistors. As shown in Figure 19B, the backup circuit 222 can be stacked on top of the scan flip-flop 221, which is composed of a silicon CMOS circuit.

[0147] The backup circuit 222 has significantly fewer elements than the scan flip-flop 221, so there is no need to change the circuit configuration or layout of the scan flip-flop 221 in order to stack the backup circuit 222. In other words, the backup circuit 222 is a highly versatile backup circuit. Furthermore, since the backup circuit 222 can be placed within the area where the scan flip-flop 221 is formed, the area overhead of the flip-flop 220 can be reduced to zero even when the backup circuit 222 is incorporated. Therefore, by providing the backup circuit 222 on the flip-flop 220, power gating of the CPU core 200 becomes possible. Because less energy is required for power gating, it is possible to power gate the CPU core 200 with high efficiency.

[0148] By providing the backup circuit 222, a parasitic capacitance from transistor M11 is added to node Q1. However, this is small compared to the parasitic capacitance from the logic circuit connected to node Q1, so it does not affect the operation of scan flip-flop 221. In other words, even with the backup circuit 222, the performance of flip-flop 220 is not substantially reduced.

[0149] For example, the CPU core 200 can be configured in low-power states such as clock gating, power gating, and hibernation. The PMU 193 selects the low-power mode for the CPU core 200 based on interrupt signals, the SLEEP1 signal, etc. For example, when transitioning from the normal operating state to the clock gating state, the PMU 193 stops generating the clock signal GCLK1.

[0150] For example, when transitioning from normal operation to hibernation, the PMU193 performs voltage and / or frequency scaling. For example, when performing voltage scaling, the PMU193 turns off power switch 210 and turns on power switch 211 to input voltage VDD1 to the CPU core 200. Voltage VDD1 is a voltage that does not cause data loss in scan flip-flop 221. When performing frequency scaling, the PMU193 reduces the frequency of the clock signal GCLK1.

[0151] When the CPU core 200 transitions from normal operation to power gating, the data on scan flip-flop 221 is backed up to backup circuit 222. When the CPU core 200 returns from power gating to normal operation, the data on backup circuit 222 is recovered to scan flip-flop 221.

[0152] Figure 20 shows an example of the power gating sequence for CPU core 200. In Figure 20, t1 to t7 represent time. Signals PSE0 to PSE2 are control signals for power switches 210 to 212 and are generated by PMU 193. When signal PSE0 is "H" or "L", power switch 210 is on or off. The same applies to signals PSE1 and PSE2.

[0153] Prior to time t1, the system is in a normal operation state. Power switch 210 is on, and voltage VDDD is input to the CPU core 200. Scan flip-flop 221 operates normally. At this time, level shifter 214 does not need to be operated, so power switch 212 is off, and signals SCE, BK, and RC are "L". Since node SE is "L", scan flip-flop 221 stores the data of node D1. In the example in Figure 20, at time t1, node SN11 of backup circuit 222 is "L".

[0154] The operation during backup is described below. At time t1, PMU193 stops the clock signal GCLK1 and sets the signal PSE2, BK, to "H". The level shifter 214 becomes active and outputs the "H" signal BKH to the backup circuit 222.

[0155] Transistor M11 of backup circuit 222 is turned on, and the data from node Q1 of scan flip-flop 221 is written to node SN11 of backup circuit 222. If node Q1 of scan flip-flop 221 is "L", node SN11 remains "L", and if node Q1 is "H", node SN11 becomes "H".

[0156] PMU193 sets signal PSE2 and BK to "L" at time t2, and signal PSE0 to "L" at time t3. At time t3, CPU core 200 transitions to the power gating state. Alternatively, signal PSE0 may be lowered at the same time as signal BK.

[0157] This section explains the operation during power-gating. When the signal PSE0 becomes "L," the voltage on the V_VDD line drops, causing data loss at node Q1. Node SN11 continues to retain the data from node Q1 at time t3.

[0158] The operation during recovery is described below. At time t4, PMU193 transitions from the power gating state to the recovery state by setting signal PSE0 to "H". Charging of the V_VDD line begins, and when the voltage of the V_VDD line reaches VDDD (time t5), PMU193 sets signals PSE2, RC, and SCE to "H".

[0159] Transistor M12 turns on, and the charge of capacitive element C11 is distributed to nodes SN11 and SD. If node SN11 is "H", the voltage at node SD rises. Since node SE is "H", the data from node SD is written to the input latch circuit of scan flip-flop 221. When the clock signal GCLK1 is input to node CK at time t6, the data from the input latch circuit is written to node Q1. In other words, the data from node SN11 has been written to node Q1.

[0160] At time t7, PMU193 sets signals PSE2, SCE, and RC to "L", and the recovery operation ends.

[0161] The backup circuit 222 using OS transistors is highly suitable for normally-off computing because it has low dynamic and static power consumption. The CPU 110, including the CPU core 200 with the OS transistor backup circuit 222, can be referred to as NoffCPU (registered trademark). NoffCPU has non-volatile memory and can stop power supply when operation is not required. Even with the addition of a flip-flop 220, it is possible to minimize performance degradation and dynamic power consumption increases of the CPU core 200.

[0162] The CPU core 200 may have multiple power domains capable of power gating. Each power domain is provided with one or more power switches for controlling voltage input. The CPU core 200 may also have one or more power domains that are not power gated. For example, a power gating control circuit for controlling the flip-flop 220 and power switches 210-212 may be provided in a power domain that is not power gated.

[0163] Note that the application of flip-flop 220 is not limited to CPU 110. In CPU 110, flip-flop 220 can be applied to registers located in power domains that are power-gated.

[0164] This embodiment can be appropriately combined with descriptions of other embodiments.

[0165] (Embodiment 4) This embodiment describes an example of a transistor configuration applicable to the CPU 110 and the accelerator described as the semiconductor device 10 in the above embodiment. As an example, a configuration in which transistors with different electrical characteristics are stacked is described. This configuration increases the design flexibility of the semiconductor device. Furthermore, stacking transistors with different electrical characteristics increases the integration density of the semiconductor device.

[0166] Figure 21 shows a part of the cross-sectional structure of a semiconductor device. The semiconductor device shown in Figure 21 includes a transistor 550, a transistor 500, and a capacitive element 600. Figure 22A is a cross-sectional view of transistor 500 in the channel length direction, and Figure 22B is a cross-sectional view of transistor 500 in the channel width direction. For example, transistor 500 corresponds to the OS transistor in the memory circuit 32 shown in the above embodiment, that is, a transistor having an oxide semiconductor in the channel formation region. Transistor 550 corresponds to the Si transistor in the arithmetic circuit section 40 shown in the above embodiment, that is, a transistor having silicon in the channel formation region. Capacitive element 600 corresponds to the capacitive element in the memory circuit 32.

[0167] Transistor 500 is an OS transistor. OS transistors have extremely low off-current. Therefore, it is possible to retain the data voltage or charge written to the memory node via transistor 500 for a long period of time. In other words, the frequency of refresh operations of the memory node can be reduced, or refresh operations can be eliminated, thereby reducing the power consumption of the semiconductor device.

[0168] In Figure 21, transistor 500 is located above transistor 550, and the capacitive element 600 is located above both transistor 550 and transistor 500.

[0169] The transistor 550 is provided on a substrate 311. The substrate 311 is, for example, a p-type silicon substrate. The substrate 311 may also be an n-type silicon substrate. The oxide layer 314 is preferably an insulating layer (also called a BOX layer) formed in the substrate 311 by burried oxide, for example, silicon oxide. The transistor 550 is provided on a single-crystal silicon substrate, a so-called SOI (Silicon On Insulator) substrate, which is provided on the substrate 311 via the oxide layer 314.

[0170] In the SOI substrate, the substrate 311 is provided with an insulator 313 that functions as an element isolation layer. The substrate 311 also has a well region 312. The well region 312 is a region to which n-type or p-type conductivity is imparted, depending on the conductivity type of the transistor 550. The single crystal silicon in the SOI substrate is provided with a semiconductor region 315, and low-resistance regions 316a and 316b that function as source or drain regions. In addition, there is a low-resistance region 316c on the well region 312.

[0171] The transistor 550 can be placed on top of a well region 312 to which impurity elements that impart conductivity are added. The well region 312 can function as the bottom gate electrode of the transistor 550 by independently changing its potential via a low-resistance region 316c. Therefore, the threshold voltage of the transistor 550 can be controlled. In particular, by applying a negative potential to the well region 312, the threshold voltage of the transistor 550 can be increased and the off-current can be reduced. Thus, by applying a negative potential to the well region 312, the drain current when the potential applied to the gate electrode of the Si transistor is 0V can be reduced. As a result, power consumption based on through-current etc. in the arithmetic circuit section 40 having the transistor 550 can be reduced, and the arithmetic efficiency can be improved.

[0172] It is preferable that the transistor 550 is of the so-called Fin type, in which the top surface and the side surface in the channel width direction of the semiconductor layer are covered with a conductor 318 via an insulator 317. By making the transistor 550 of the Fin type, the effective channel width can be increased, thereby improving the ON characteristics of the transistor 550. In addition, the contribution of the electric field of the gate electrode can be increased, thereby improving the OFF characteristics of the transistor 550.

[0173] Note that transistor 550 can be either a p-channel transistor or an n-channel transistor.

[0174] The conductor 318 may function as the first gate (also called the top gate) electrode. The well region 312 may also function as the second gate (also called the bottom gate) electrode. In this case, the potential applied to the well region 312 can be controlled via the low-resistance region 316c.

[0175] In the low-resistance region 316a and low-resistance region 316b, which are the region where the channel of the semiconductor region 315 is formed, the region near it, the source region, or the drain region, and the low-resistance region 316c, which is connected to the electrode that controls the potential of the well region 312, it is preferable that a semiconductor such as a silicon-based semiconductor is included, and it is preferable that single-crystal silicon is included. Alternatively, it may be formed from a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), etc. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing is also possible. Alternatively, by using GaAs and GaAlAs, the transistor 550 may be made into a HEMT (High Electron Mobility Transistor).

[0176] The well region 312, low-resistance region 316a, low-resistance region 316b, and low-resistance region 316c contain, in addition to the semiconductor material applied to the semiconductor region 315, elements that impart n-type conductivity, such as arsenic and phosphorus, or elements that impart p-type conductivity, such as boron.

[0177] The conductor 318, which functions as the gate electrode, can be a conductive material such as a semiconductor material, metal material, alloy material, or metal oxide material containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron, such as silicon. Alternatively, the conductor 318 may be a silicide such as nickel silicide.

[0178] Furthermore, since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use materials such as titanium nitride or tantalum nitride as the conductor. In addition, in order to achieve both conductivity and embedding properties, it is preferable to use metallic materials such as tungsten or aluminum as a laminate for the conductor, and tungsten is particularly preferable in terms of heat resistance.

[0179] The low-resistance regions 316a, 316b, and 316c may be configured by laminating another conductor, such as a silicide such as nickel silicide. This configuration can improve the conductivity of the regions that function as electrodes. In this case, an insulator that functions as a sidewall spacer (also called a sidewall insulating layer) may be provided on the side surface of the conductor 318 that functions as a gate electrode and on the side surface of the insulator that functions as a gate insulating film. This configuration can prevent the conductor 318 from becoming electrically conductive with the low-resistance regions 316a and 316b.

[0180] The transistor 550 is covered by insulators 320, 322, 324, and 326, which are stacked in that order.

[0181] For insulators 320, 322, 324, and 326, for example, silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, aluminum nitride, etc. may be used.

[0182] In this specification, silicon oxidizide refers to a material in which the oxygen content is greater than the nitrogen content, and silicon nitride refers to a material in which the nitrogen content is greater than the oxygen content. Furthermore, in this specification, aluminum oxidizide refers to a material in which the oxygen content is greater than the nitrogen content, and aluminum nitride refers to a material in which the nitrogen content is greater than the oxygen content.

[0183] The insulator 322 may also function as a planarizing film that flattens steps caused by transistors 550 or the like located below it. For example, the upper surface of the insulator 322 may be planarized by a planarizing treatment using chemical mechanical polishing (CMP) or the like to improve its flatness.

[0184] Furthermore, it is preferable to use a film for the insulator 324 that has barrier properties to prevent hydrogen and impurities from diffusing from the substrate 311 or the transistor 550 to the region where the transistor 500 is provided.

[0185] As an example of a film having barrier properties against hydrogen, silicon nitride formed by the CVD method can be used. However, when hydrogen diffuses into a semiconductor element having an oxide semiconductor, such as transistor 500, the properties of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between transistor 500 and transistor 550. Specifically, a film that suppresses hydrogen diffusion is a film that has a low hydrogen desorption rate.

[0186] The amount of hydrogen desorption can be analyzed, for example, using a thermal desorption gas analysis (TDS) method. For example, in TDS analysis, the amount of hydrogen desorption from insulator 324, when the film surface temperature is in the range of 50°C to 500°C, is calculated as 10 × 10¹⁶ hydrogen atoms per unit area of ​​insulator 324. 15 atoms / cm 2 The following is preferably 5 × 10 15 atoms / cm 2 The following is acceptable.

[0187] Furthermore, it is preferable that the dielectric constant of the insulator 326 is lower than that of the insulator 324. For example, the relative permittivity of the insulator 326 is preferably less than 4, and more preferably less than 3. Also, for example, the relative permittivity of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, than that of the relative permittivity of the insulator 324. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance occurring between wiring can be reduced.

[0188] Furthermore, insulators 320, 322, 324, and 326 have embedded conductors 328 and 330, which connect to the capacitive element 600 or the transistor 500. Conductors 328 and 330 function as plugs or wires. Conductors that function as plugs or wires may be grouped together and assigned the same reference numeral. Also, in this specification, the wire and the plug connected to the wire may be an integrated unit. That is, a part of the conductor may function as a wire, and a part of the conductor may function as a plug.

[0189] The plugs and wiring (conductor 328, conductor 330, etc.) can be made of conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials, which can be used in a single layer or in a laminated form. It is preferable to use high-melting-point materials such as tungsten or molybdenum that provide both heat resistance and conductivity, and tungsten is preferred. Alternatively, it is preferable to form them with low-resistance conductive materials such as aluminum or copper. Using low-resistance conductive materials can reduce the wiring resistance.

[0190] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Figure 21, insulators 350, 352, and 354 are stacked in order. Conductors 356 are formed on insulators 350, 352, and 354. Conductors 356 function as a plug or wiring for connecting to the transistor 550. Conductors 356 can be provided using the same material as conductors 328 and 330.

[0191] For example, it is preferable that the insulator 350, like the insulator 324, be an insulator having barrier properties against hydrogen. Furthermore, it is preferable that the conductor 356 includes a conductor having barrier properties against hydrogen. In particular, a conductor having barrier properties against hydrogen is formed in the openings of the hydrogen barrier insulator 350. With this configuration, transistors 550 and 500 can be separated by the barrier layer, and the diffusion of hydrogen from transistor 550 to transistor 500 can be suppressed.

[0192] For example, tantalum nitride may be used as the conductor that has barrier properties against hydrogen. Furthermore, by laminating tantalum nitride with highly conductive tungsten, it is possible to suppress the diffusion of hydrogen from the transistor 550 while maintaining conductivity as wiring. In this case, it is preferable that the tantalum nitride layer, which has barrier properties against hydrogen, is in contact with the insulator 350, which also has barrier properties against hydrogen.

[0193] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in Figure 21, insulators 360, 362, and 364 are stacked in order. Conductors 366 are formed on insulators 360, 362, and 364. Conductors 366 function as a plug or wiring. Conductors 366 can be provided using the same material as conductors 328 and 330.

[0194] For example, it is preferable that the insulator 360, like the insulator 324, be an insulator having barrier properties against hydrogen. Furthermore, it is preferable that the conductor 366 includes a conductor having barrier properties against hydrogen. In particular, a conductor having barrier properties against hydrogen is formed in the openings of the hydrogen barrier insulator 360. With this configuration, transistors 550 and 500 can be separated by the barrier layer, and the diffusion of hydrogen from transistor 550 to transistor 500 can be suppressed.

[0195] A wiring layer may be provided on the insulator 364 and the conductor 366. For example, in Figure 21, insulators 370, 372, and 374 are stacked in order. Conductors 376 are formed on insulators 370, 372, and 374. Conductors 376 function as a plug or wiring. Conductors 376 can be provided using the same material as conductors 328 and 330.

[0196] For example, it is preferable that the insulator 370, like the insulator 324, be an insulator having barrier properties against hydrogen. Furthermore, it is preferable that the conductor 376 includes a conductor having barrier properties against hydrogen. In particular, a conductor having barrier properties against hydrogen is formed in the openings of the hydrogen barrier insulator 370. With this configuration, transistors 550 and 500 can be separated by the barrier layer, and the diffusion of hydrogen from transistor 550 to transistor 500 can be suppressed.

[0197] A wiring layer may be provided on the insulator 374 and the conductor 376. For example, in Figure 21, insulators 380, 382, ​​and 384 are stacked in order. Conductors 386 are formed on insulators 380, 382, ​​and 384. Conductors 386 function as a plug or wiring. Conductors 386 can be provided using the same material as conductors 328 and 330.

[0198] For example, it is preferable that the insulator 380, like the insulator 324, be an insulator having barrier properties against hydrogen. Furthermore, it is preferable that the conductor 386 includes a conductor having barrier properties against hydrogen. In particular, a conductor having barrier properties against hydrogen is formed in the openings of the hydrogen barrier insulator 380. With this configuration, transistors 550 and 500 can be separated by the barrier layer, and the diffusion of hydrogen from transistor 550 to transistor 500 can be suppressed.

[0199] In the above, wiring layers including conductor 356, wiring layers including conductor 366, wiring layers including conductor 376, and wiring layers including conductor 386 have been described, but the semiconductor device according to this embodiment is not limited thereto. Three or fewer wiring layers similar to the wiring layer including conductor 356 may be used, or five or more wiring layers similar to the wiring layer including conductor 356 may be used.

[0200] Insulators 510, 512, 514, and 516 are arranged in order on the insulator 384. It is preferable that one of the insulators 510, 512, 514, and 516 is made of a material that has barrier properties against oxygen and hydrogen.

[0201] For example, it is preferable to use a film that has barrier properties against hydrogen and impurities in the insulator 510 and insulator 514, for example, in the region where the transistor 500 is installed, from the substrate 311 or the region where the transistor 550 is installed. Therefore, the same material as that used for insulator 324 can be used.

[0202] As an example of a film having hydrogen barrier properties, silicon nitride formed by the CVD method can be used. However, when hydrogen diffuses into a semiconductor element having an oxide semiconductor, such as transistor 500, the properties of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between transistor 500 and transistor 550.

[0203] Furthermore, as a film having barrier properties against hydrogen, it is preferable to use metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide for insulator 510 and insulator 514.

[0204] In particular, aluminum oxide exhibits a high barrier effect, preventing the penetration of both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical properties of transistors. Therefore, aluminum oxide can prevent the ingress of impurities such as hydrogen and moisture into the transistor 500 during and after the transistor manufacturing process. It can also suppress the release of oxygen from the oxides constituting the transistor 500. For this reason, it is suitable for use as a protective film for transistor 500.

[0205] Furthermore, for example, the same materials as insulator 320 can be used for insulators 512 and 516. Additionally, by applying materials with relatively low dielectric constants to these insulators, parasitic capacitance between wiring can be reduced. For example, silicon oxide films or silicon oxynitride films can be used as insulators 512 and 516.

[0206] Furthermore, the insulators 510, 512, 514, and 516 have a conductor 518 and a conductor constituting the transistor 500 (for example, conductor 503) embedded in them. The conductor 518 functions as a plug or wiring for connecting to the capacitive element 600 or the transistor 550. The conductor 518 can be provided using the same material as the conductors 328 and 330.

[0207] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor having barrier properties against oxygen, hydrogen, and water. With this configuration, transistor 550 and transistor 500 can be separated by a layer having barrier properties against oxygen, hydrogen, and water, and the diffusion of hydrogen from transistor 550 to transistor 500 can be suppressed.

[0208] A transistor 500 is provided above the insulator 516.

[0209] As shown in Figures 22A and 22B, the transistor 500 includes a conductor 503 arranged to be embedded in insulators 514 and 516, an insulator 522 arranged on top of insulators 516 and 503, an insulator 524 arranged on top of insulator 522, an oxide 530a arranged on top of insulator 524, an oxide 530b arranged on top of oxide 530a, conductors 542a and 542b arranged spaced apart from each other on oxide 530b, an insulator 580 arranged on top of conductors 542a and 542b with an opening formed between them, an insulator 545 arranged on the bottom and side surfaces of the opening, and a conductor 560 arranged on the forming surface of insulator 545.

[0210] Furthermore, as shown in Figures 22A and 22B, it is preferable that an insulator 544 is placed between the oxide 530a, oxide 530b, conductor 542a, and conductor 542b and the insulator 580. Also, as shown in Figures 22A and 22B, it is preferable that the conductor 560 has a conductor 560a provided inside the insulator 545 and a conductor 560b provided so as to be embedded inside the conductor 560a. Furthermore, as shown in Figures 22A and 22B, it is preferable that an insulator 574 is placed on top of the insulator 580, conductor 560, and insulator 545.

[0211] In this specification and other documents, oxide 530a and oxide 530b may be collectively referred to as oxide 530.

[0212] In the transistor 500, a configuration is shown in which two layers of oxide 530a and oxide 530b are stacked in the region where the channel is formed and in its vicinity, but the present invention is not limited to this. For example, a single layer of oxide 530b or a stacked configuration of three or more layers may be provided.

[0213] Furthermore, although the transistor 500 is shown with a two-layer stacked structure for the conductor 560, the present invention is not limited to this. For example, the conductor 560 may be a single layer or a stacked structure of three or more layers. Also, the transistor 500 shown in Figures 21, 22A, and 22B is just an example and is not limited to that configuration; an appropriate transistor may be used depending on the circuit configuration and driving method.

[0214] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and 542b function as the source electrode or drain electrode, respectively. As described above, the conductor 560 is formed to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductors 542a and 542b. The arrangement of the conductors 560, 542a, and 542b is selected in a self-aligned manner with respect to the opening of the insulator 580. In other words, in the transistor 500, the gate electrode can be positioned in a self-aligned manner between the source electrode and the drain electrode. Therefore, since the conductor 560 can be formed without providing a positional margin, the occupied area of ​​the transistor 500 can be reduced. This enables miniaturization and high integration of semiconductor devices.

[0215] Furthermore, since the conductor 560 is formed self-aligned in the region between the conductors 542a and 542b, the conductor 560 does not have any region that overlaps with the conductors 542a or 542b. This reduces the parasitic capacitance formed between the conductor 560 and the conductors 542a and 542b. Therefore, the switching speed of the transistor 500 can be improved, and it can be given high frequency characteristics.

[0216] Conductor 560 may function as the first gate (also called the top gate) electrode. Conductor 503 may function as the second gate (also called the bottom gate) electrode. In this case, the threshold voltage of transistor 500 can be controlled by changing the potential applied to conductor 503 independently of the potential applied to conductor 560, rather than in conjunction with it. In particular, by applying a negative potential to conductor 503, the threshold voltage of transistor 500 can be increased, and the off-current can be reduced. Therefore, applying a negative potential to conductor 503 reduces the drain current when the potential applied to conductor 560 is 0V compared to not applying a negative potential.

[0217] The conductor 503 is positioned so as to overlap with the oxide 530 and the conductor 560. As a result, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 connect, and can cover the channel-forming region formed in the oxide 530.

[0218] In this specification, a transistor configuration in which the channel formation region is electrically surrounded by the electric fields of a pair of gate electrodes (a first gate electrode and a second gate electrode) is referred to as a surrounded channel (S-channel) configuration. Furthermore, the S-channel configuration disclosed in this specification differs from the Fin-type configuration and the Planar-type configuration. By adopting an S-channel configuration, it is possible to increase resistance to short-channel effects, or in other words, to create a transistor in which short-channel effects are less likely to occur.

[0219] Furthermore, the conductor 503 has a similar configuration to the conductor 518, with conductor 503a formed in contact with the inner walls of the openings of the insulators 514 and 516, and conductor 503b formed further inside. Although the transistor 500 shows a configuration in which conductors 503a and conductor 503b are stacked, the present invention is not limited to this. For example, the conductor 503 may be provided as a single layer or as a stacked configuration of three or more layers.

[0220] Here, it is preferable to use a conductive material for the conductor 503a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (i.e., the above impurities are less permeable). Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one such as oxygen atoms or oxygen molecules) (i.e., the above oxygen is less permeable). In this specification, the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of any one or all of the above impurities or oxygen.

[0221] For example, the conductor 503a has a function of suppressing oxygen diffusion, which can prevent the conductor 503b from oxidizing and reducing its conductivity.

[0222] Furthermore, if the conductor 503 also functions as wiring, it is preferable that the conductor 503b be made of a highly conductive material mainly composed of tungsten, copper, or aluminum. In this embodiment, the conductor 503 is shown as a laminate of conductor 503a and conductor 503b, but the conductor 503 may also be in a single-layer configuration.

[0223] Insulators 522 and 524 function as second gate insulating films.

[0224] Here, it is preferable to use an insulator 524 that contains more oxygen than satisfactorily satisfactorily satisfactorily to be in contact with the oxide 530. This oxygen is easily released from the film by heating. In this specification, the oxygen released by heating is sometimes referred to as "excess oxygen." In other words, it is preferable that the insulator 524 has a region containing excess oxygen (also called an "excess oxygen region"). By providing such an insulator containing excess oxygen in contact with the oxide 530, oxygen deficiencies (V) in the oxide 530 can be reduced. O This reduces the oxygen vacancy (also known as the oxygen vacancy) and improves the reliability of the transistor 500. Furthermore, if hydrogen enters the oxygen vacancy in the oxide 530, the defect (hereinafter referred to as V) can be reduced. O Sometimes referred to as H, hydrogen acts as a donor, and can generate electrons, which are carriers. In addition, some hydrogen can combine with oxygen that is bonded to a metal atom, generating electrons, which are carriers. Therefore, transistors using oxide semiconductors that contain a lot of hydrogen tend to exhibit normally-on characteristics. Furthermore, since hydrogen in oxide semiconductors is easily moved by stress such as heat and electric fields, if the oxide semiconductor contains a lot of hydrogen, the reliability of the transistor may deteriorate. In one embodiment of the present invention, V in oxide 530 O It is preferable to reduce H as much as possible and make it high-purity intrinsic or substantially high-purity intrinsic. Thus, VO To obtain an oxide semiconductor with sufficiently reduced H content, it is important to remove impurities such as water and hydrogen from the oxide semiconductor (also called "dehydration" or "dehydrogenation") and to supply oxygen to the oxide semiconductor to compensate for oxygen deficiencies (also called "oxygenation"). O By using an oxide semiconductor with sufficiently reduced impurities such as H in the channel formation region of a transistor, stable electrical characteristics can be provided.

[0225] Specifically, as an insulator having an excess oxygen region, it is preferable to use an oxide material in which some of the oxygen is desorbed upon heating. An oxide that desorbs oxygen upon heating is one in which the amount of oxygen desorbed, converted to oxygen atoms, is 1.0 × 10⁻⁶ as determined by TDS (Thermal Desorption Spectroscopy) analysis. 18 atoms / cm 3 Preferably 1.0 × 10 19 atoms / cm 3 More preferably 2.0 × 10 19 atoms / cm 3 Above, or 3.0 × 10 20 atoms / cm 3 The oxide film is as described above. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C to 700°C, or 100°C to 400°C.

[0226] Furthermore, the insulator having the excess oxygen region described above and the oxide 530 may be brought into contact and subjected to one or more of the following treatments: heat treatment, microwave treatment, or RF treatment. By performing this treatment, water or hydrogen in the oxide 530 can be removed. For example, in the oxide 530, a reaction occurs in which the VoH bond is broken, in other words, "V O The reaction H → Vo + H occurs, allowing for dehydrogenation. Some of the hydrogen generated at this time may combine with oxygen to form H2O, which may be removed from oxide 530 or the insulator near oxide 530. In addition, some of the hydrogen may be gettered by conductor 542.

[0227] Furthermore, the above microwave processing is preferably carried out using, for example, a device having a power supply that generates high-density plasma, or a device having a power supply that applies RF to the substrate side. For example, by using an oxygen-containing gas and a high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or the insulator near the oxide 530. In addition, the above microwave processing should be carried out at a pressure of 133 Pa or higher, preferably 200 Pa or higher, and more preferably 400 Pa or higher. In addition, as the gas introduced into the device for microwave processing, for example, oxygen and argon should be used, and the oxygen flow rate ratio (O2 / (O2+Ar)) should be 50% or less, preferably 10% to 30% or less.

[0228] Furthermore, during the manufacturing process of the transistor 500, it is preferable to perform a heat treatment while the surface of the oxide 530 is exposed. This heat treatment may be performed, for example, at a temperature of 100°C to 450°C, more preferably 350°C to 400°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, it is preferable to perform the heat treatment in an oxygen atmosphere. This supplies oxygen to the oxide 530, thereby preventing oxygen deficiency (V O This can reduce the amount of oxygen released. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the oxygen that has been removed. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then continuously in an atmosphere of nitrogen gas or an inert gas.

[0229] Furthermore, by performing an oxygenation treatment on oxide 530, oxygen vacancies in oxide 530 can be repaired by the supplied oxygen, in other words, the reaction "Vo + O → null" can be promoted. In addition, the supplied oxygen reacts with the hydrogen remaining in oxide 530, removing the hydrogen as H2O (dehydration). As a result, the hydrogen remaining in oxide 530 recombines with the oxygen vacancies and V O This can suppress the formation of H.

[0230] Furthermore, if the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function to suppress the diffusion of oxygen (e.g., oxygen atoms, oxygen molecules, etc.) (i.e., the oxygen is less permeable).

[0231] The insulator 522 has the function of suppressing the diffusion of oxygen and impurities, so the oxygen contained in the oxide 530 does not diffuse towards the conductor 503, which is preferable. Furthermore, it is possible to suppress the reaction of the conductor 503 with the oxygen contained in the insulator 524 and the oxide 530.

[0232] The insulator 522 preferably uses a single-layer or multi-layer insulator containing so-called high-k materials such as aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more integrated, thinning of the gate insulating film can lead to problems such as leakage current. By using a high-k material as the insulator that functions as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0233] In particular, it is preferable to use an insulator containing an oxide of either aluminum or hafnium, or both, which is an insulating material that has the function of suppressing the diffusion of impurities and oxygen (the above-mentioned oxygen is less permeable). As an insulator containing an oxide of either aluminum or hafnium, or both, it is preferable to use aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). When an insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses the release of oxygen from the oxide 530 and the mixing of impurities such as hydrogen from the periphery of the transistor 500 into the oxide 530.

[0234] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be subjected to nitriding treatment. Silicon oxide, silicon oxynitride, or silicon nitride may be laminated onto the above insulators.

[0235] In Figures 22A and 22B, transistor 500 is shown with insulators 522 and 524 as a second gate insulating film consisting of a three-layer laminated structure. However, the second gate insulating film may have a single-layer, two-layer, or four-layer or more laminated structure. In that case, it is not limited to a laminated structure made of the same material, but may also be made of different materials.

[0236] The transistor 500 uses a metal oxide that functions as an oxide semiconductor in the oxide 530 containing the channel formation region. For example, as the oxide 530, a metal oxide such as In-M-Zn oxide (where element M is one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium) may be used.

[0237] The metal oxide that functions as an oxide semiconductor may be formed by sputtering or by ALD (Atomic Layer Deposition). The metal oxide that functions as an oxide semiconductor will be described in detail in other embodiments.

[0238] Furthermore, it is preferable to use a metal oxide with a band gap of 2 eV or more, preferably 2.5 eV or more, that functions as a channel-forming region in oxide 530. By using a metal oxide with a large band gap in this way, the off-current of the transistor can be reduced.

[0239] By having oxide 530a below oxide 530b, oxide 530 can suppress the diffusion of impurities from components formed below oxide 530a to oxide 530b.

[0240] Furthermore, it is preferable that the oxide 530 has a laminated structure of multiple oxide layers with different atomic ratios of each metal atom. Specifically, it is preferable that in the metal oxide used for oxide 530a, the atomic ratio of element M in the constituent elements is greater than the atomic ratio of element M in the constituent elements of the metal oxide used for oxide 530b. Also, it is preferable that in the metal oxide used for oxide 530a, the atomic ratio of element M to In is greater than the atomic ratio of element M to In in the metal oxide used for oxide 530b. Furthermore, it is preferable that in the metal oxide used for oxide 530b, the atomic ratio of In to element M is greater than the atomic ratio of In to element M in the metal oxide used for oxide 530a.

[0241] Furthermore, it is preferable that the energy at the lower end of the conduction band of oxide 530a is higher than the energy at the lower end of the conduction band of oxide 530b. In other words, it is preferable that the electron affinity of oxide 530a is smaller than the electron affinity of oxide 530b.

[0242] Here, at the junction of oxide 530a and oxide 530b, the energy level at the lower end of the conduction band changes smoothly. In other words, the energy level at the lower end of the conduction band at the junction of oxide 530a and oxide 530b can be said to change continuously or be continuously joined. To achieve this, it is desirable to lower the defect level density of the mixed layer formed at the interface between oxide 530a and oxide 530b.

[0243] Specifically, a mixed layer with a low defect level density can be formed if oxide 530a and oxide 530b have a common element other than oxygen (as the main component). For example, if oxide 530b is In-Ga-Zn oxide, then oxide 530a can be In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, etc.

[0244] In this case, the primary carrier pathway is oxide 530b. By configuring oxide 530a as described above, the defect level density at the interface between oxide 530a and oxide 530b can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and transistor 500 can obtain a high on-current.

[0245] Conductors 542a and 542b, which function as source electrodes and drain electrodes, are provided on the oxide 530b. It is preferable to use metallic elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or alloys composed of the above metallic elements, or alloys combining the above metallic elements, etc. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. In addition, metal nitride films such as tantalum nitride are preferred because they have barrier properties against hydrogen or oxygen.

[0246] Furthermore, although conductors 542a and 542b are shown as single-layer structures in Figure 22A, they may also be laminated in two or more layers. For example, a tantalum nitride film and a tungsten film may be laminated. Alternatively, a titanium film and an aluminum film may be laminated. In addition, a two-layer structure in which an aluminum film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, or a two-layer structure in which a copper film is laminated on a tungsten film may also be used.

[0247] Furthermore, there are three-layer configurations such as a titanium film or titanium nitride film, an aluminum film or copper film laminated on top of the titanium film or titanium nitride film, and a titanium film or titanium nitride film formed on top of that; and a molybdenum film or molybdenum nitride film, an aluminum film or copper film laminated on top of the molybdenum film or molybdenum nitride film, and a molybdenum film or molybdenum nitride film formed on top of that. Transparent conductive materials containing indium oxide, tin oxide, or zinc oxide may also be used.

[0248] Furthermore, as shown in Figure 22A, regions 543a and 543b may be formed as low-resistance regions at and near the interface between the oxide 530 and the conductor 542a (conductor 542b). In this case, region 543a functions as either a source region or a drain region, and region 543b functions as either a source region or a drain region. In addition, a channel-forming region is formed in the region sandwiched between regions 543a and 543b.

[0249] By providing the conductor 542a (conductor 542b) in contact with the oxide 530, the oxygen concentration in region 543a (region 543b) may be reduced. In addition, a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and the components of the oxide 530 may be formed in region 543a (region 543b). In such cases, the carrier density in region 543a (region 543b) increases, and region 543a (region 543b) becomes a low-resistance region.

[0250] The insulator 544 is provided so as to cover the conductors 542a and 542b, thereby suppressing oxidation of the conductors 542a and 542b. In this case, the insulator 544 may be provided so as to cover the side surface of the oxide 530 and be in contact with the insulator 524.

[0251] As the insulator 544, one or more metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, or magnesium can be used. Alternatively, silicon nitride or silicon nitride can also be used as the insulator 544.

[0252] In particular, it is preferable to use an insulator 544 that contains an oxide of either aluminum or hafnium, or both, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). Hafnium aluminate is especially preferable because it has higher heat resistance than hafnium oxide film. Therefore, it is preferable because it is less likely to crystallize during heat treatment in a later process. Note that if the conductors 542a and 542b are made of oxidation-resistant materials, or if their conductivity does not significantly decrease even when oxygen is absorbed, the insulator 544 is not an essential component. It should be designed appropriately according to the desired transistor characteristics.

[0253] The presence of the insulator 544 suppresses the diffusion of water and other impurities such as hydrogen contained in the insulator 580 into the oxide 530b via the insulator 545. Furthermore, it suppresses the oxidation of the conductor 560 due to excess oxygen present in the insulator 580.

[0254] The insulator 545 functions as the first gate insulating film. The insulator 545 is preferably formed using an insulator that contains an excess of oxygen and releases oxygen upon heating, similar to the insulator 524 described above.

[0255] Specifically, silicon oxide with excess oxygen, silicon oxide nitride, silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and silicon oxide with vacancies can be used. Silicon oxide and silicon oxide nitride are particularly preferred because they are stable to heat.

[0256] By providing an insulator containing excess oxygen as insulator 545, oxygen can be effectively supplied from insulator 545 to the channel formation region of oxide 530b. Also, similar to insulator 524, it is preferable that the concentration of impurities such as water or hydrogen in insulator 545 is reduced. The film thickness of insulator 545 is preferably 1 nm or more and 20 nm or less. Further, the above-described microwave treatment may be performed before and / or after the formation of insulator 545.

[0257] Also, in order to efficiently supply the excess oxygen possessed by insulator 545 to oxide 530, a metal oxide may be provided between insulator 545 and conductor 560. The metal oxide preferably suppresses the diffusion of oxygen from insulator 545 to conductor 560. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of excess oxygen from insulator 545 to conductor 560 is suppressed. That is, it is possible to suppress a decrease in the amount of excess oxygen supplied to oxide 530. Also, oxidation of conductor 560 by excess oxygen can be suppressed. As the metal oxide, a material that can be used for insulator 544 may be used.

[0258] Note that insulator 545 may have a stacked structure, similar to the second gate insulating film. As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulating film. Therefore, by forming an insulator that functions as a gate insulating film into a stacked structure of a high-k material and a thermally stable material, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. Also, a stacked structure that is thermally stable and has a high relative dielectric constant can be formed.

[0259] Conductor 560 that functions as the first gate electrode is shown as a two-layer structure in FIGS. 22A and 22B, but it may have a single-layer structure or a stacked structure of three or more layers.

[0260] It is preferable to use a conductive material for the conductor 560a that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2), and copper atoms. Alternatively, it is preferable to use a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). By having the function of suppressing the diffusion of oxygen, the conductor 560b can be prevented from being oxidized by the oxygen contained in the insulator 545 and the conductivity from decreasing. As the conductive material having the function of suppressing the diffusion of oxygen, for example, it is preferable to use tantalum, tantalum nitride, ruthenium, or ruthenium oxide. Also, an oxide semiconductor applicable to the oxide 530 can be used as the conductor 560a. In that case, by forming the conductor 560b by sputtering, the electrical resistance value of the conductor 560a can be decreased to make it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0261] Also, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum for the conductor 560b. Also, since the conductor 560b also functions as a wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used. Also, the conductor 560b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material may be used.

[0262] The insulator 580 is provided on the conductors 542a and 542b via the insulator 544. The insulator 580 preferably has an excess oxygen region. For example, the insulator 580 preferably has silicon oxide, silicon oxynitride, silicon nitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, porous silicon oxide, or a resin. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Silicon oxide and porous silicon oxide are particularly preferred because they can easily form an excess oxygen region in a later process.

[0263] The insulator 580 preferably has an excess oxygen region. By providing an insulator 580 that releases oxygen upon heating, oxygen in the insulator 580 can be efficiently supplied to the oxide 530. It is also preferable that the concentration of impurities such as water or hydrogen in the insulator 580 is reduced.

[0264] The opening in the insulator 580 is formed superimposed on the region between the conductors 542a and 542b. As a result, the conductor 560 is formed to be embedded in the opening in the insulator 580 and in the region sandwiched between the conductors 542a and 542b.

[0265] When miniaturizing semiconductor devices, it is necessary to shorten the gate length, but it is also necessary to ensure that the conductivity of the conductor 560 does not decrease. If the film thickness of the conductor 560 is increased to achieve this, the conductor 560 may take on a shape with a high aspect ratio. In this embodiment, since the conductor 560 is embedded in the opening of the insulator 580, even if the conductor 560 has a shape with a high aspect ratio, it can be formed without the conductor 560 collapsing during the manufacturing process.

[0266] The insulator 574 is preferably provided in contact with the upper surface of the insulator 580, the upper surface of the conductor 560, and the upper surface of the insulator 545. By depositing the insulator 574 by sputtering, an excess oxygen region can be created on the insulator 545 and the insulator 580. This allows oxygen to be supplied to the oxide 530 from the excess oxygen region.

[0267] For example, as the insulator 574, one or more metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium can be used.

[0268] In particular, aluminum oxide has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even in thin films between 0.5 nm and 3.0 nm in thickness. Therefore, aluminum oxide deposited by sputtering can function as both an oxygen source and a barrier film against impurities such as hydrogen.

[0269] Furthermore, it is preferable to provide an insulator 581 that functions as an interlayer film on top of the insulator 574. Similar to the insulator 524, it is preferable that the insulator 581 has a reduced concentration of impurities such as water or hydrogen in the film.

[0270] Furthermore, conductors 540a and 540b are placed in the openings formed in insulators 581, 574, 580, and 544. Conductors 540a and 540b are provided facing each other with conductor 560 in between. Conductors 540a and 540b have the same configuration as conductors 546 and 548, which will be described later.

[0271] An insulator 582 is provided on the insulator 581. It is preferable that the insulator 582 be made of a material that has barrier properties against oxygen and hydrogen. Therefore, the same material as that used for the insulator 514 can be used for the insulator 582. For example, it is preferable that the insulator 582 be made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0272] In particular, aluminum oxide exhibits a high barrier effect, preventing the penetration of both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical properties of transistors. Therefore, aluminum oxide can prevent the ingress of impurities such as hydrogen and moisture into the transistor 500 during and after the transistor manufacturing process. It can also suppress the release of oxygen from the oxides constituting the transistor 500. For this reason, it is suitable for use as a protective film for transistor 500.

[0273] Furthermore, an insulator 586 is provided on the insulator 582. The insulator 586 can be made of the same material as the insulator 320. By applying materials with relatively low dielectric constants to these insulators, parasitic capacitance between the wiring can be reduced. For example, silicon oxide films or silicon oxynitride films can be used as the insulator 586.

[0274] Furthermore, insulators 522, 524, 544, 580, 574, 581, 582, and 586 have conductors 546 and 548 embedded in them.

[0275] Conductors 546 and 548 function as plugs or wires for connecting to the capacitive element 600, transistor 500, or transistor 550. Conductors 546 and 548 can be provided using the same materials as conductors 328 and 330.

[0276] Furthermore, after the formation of the transistor 500, an opening may be formed to surround the transistor 500, and an insulator with high barrier properties against hydrogen or water may be formed to cover the opening. By enclosing the transistor 500 with the above-mentioned high-barrier insulator, it is possible to prevent moisture and hydrogen from entering from the outside. Alternatively, multiple transistors 500 may be encased together with an insulator with high barrier properties against hydrogen or water. When forming an opening to surround the transistor 500, for example, forming an opening that reaches the insulator 522 or insulator 514, and forming the above-mentioned high-barrier insulator in contact with the insulator 522 or insulator 514 is preferable because it can also serve as part of the manufacturing process for the transistor 500. For example, the same material as insulator 522 or insulator 514 may be used as the insulator with high barrier properties against hydrogen or water.

[0277] Next, a capacitive element 600 is provided above the transistor 500. The capacitive element 600 has a conductor 610, a conductor 620, and an insulator 630.

[0278] Furthermore, a conductor 612 may be provided on the conductors 546 and 548. The conductor 612 functions as a plug or wiring for connecting to the transistor 500. The conductor 610 functions as an electrode for the capacitive element 600. Note that the conductors 612 and 610 can be formed simultaneously.

[0279] For the conductor 612 and the conductor 610, a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film) containing the above-described elements as components can be used. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide can also be applied.

[0280] In this embodiment, the conductor 612 and the conductor 610 are shown in a single-layer configuration, but the configuration is not limited thereto, and a laminated configuration of two or more layers may be used. For example, a conductor having barrier properties, and a conductor having high adhesiveness to the conductor having barrier properties and the conductor having high conductivity may be formed between the conductor having barrier properties and the conductor having high conductivity.

[0281] The conductor 620 is provided so as to overlap the conductor 610 via the insulator 630. Note that the conductor 620 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high melting point material such as tungsten or molybdenum that achieves both heat resistance and conductivity, and it is particularly preferable to use tungsten. When formed simultaneously with other components such as a conductor, Cu (copper), Al (aluminum), or the like, which is a low-resistance metal material, may be used.

[0282] An insulator 640 is provided over the conductor 620 and the insulator 630. The insulator 640 can be formed using the same material as the insulator 320. Further, the insulator 640 may function as a planarization film that covers the uneven shape thereunder.

[0283] By using this configuration, miniaturization or high integration can be achieved in a semiconductor device using a transistor having an oxide semiconductor.

[0284] The configurations, structures, and methods shown in this embodiment can be used in appropriate combination with the configurations, structures, and methods shown in other embodiments and examples.

[0285] (Embodiment 5) In this embodiment, the configuration of the integrated circuit, including each of the components of the arithmetic processing system 100 described in the above embodiment, will be explained with reference to Figures 23A and 23B.

[0286] Figure 23A is an example of a schematic diagram illustrating an integrated circuit including the various components of the arithmetic processing system 100. The integrated circuit 390 shown in Figure 23A can be made into a single integrated circuit by integrating parts of the circuits of the CPU 110 and the accelerator described as the semiconductor device 10 using OS transistors.

[0287] As shown in Figure 23A, in the CPU 110, a backup circuit 222 can be provided on a layer having OS transistors located above the CPU core 200. Also, as shown in Figure 23A, in the accelerator described as the semiconductor device 10, a memory circuit 30 can be provided on a layer having OS transistors above the layer having Si transistors that constitute the arithmetic circuit 40. In addition, an OS memory 300N can be provided on the layer having OS transistors. As the OS memory 300N, in addition to the NOSRAM described in the above embodiment, DOSRAM can be applied. Furthermore, in the OS memory 300N, memory density can be improved by stacking a layer having OS transistors on a drive circuit provided on a layer having Si transistors.

[0288] As shown in Figure 23A, in the case of an SoC in which each circuit, such as the CPU 110, the accelerator described as the semiconductor device 10, and the OS memory 300N, is tightly coupled, there is a problem of heat generation. However, OS transistors are suitable because the amount of change in electrical characteristics due to heat is smaller compared to Si transistors. Furthermore, as shown in Figure 23A, by integrating the circuits in three dimensions, parasitic capacitance can be reduced compared to stacked structures using through silicon vias (TSVs), etc. Power consumption required for charging and discharging each wiring can be reduced. Therefore, the efficiency of computational processing can be improved.

[0289] Figure 23B shows an example of a semiconductor chip incorporating an integrated circuit 390. The semiconductor chip 391 shown in Figure 23B has leads 392 and an integrated circuit 390. As explained in Figure 23A, the integrated circuit 390 has various circuits as shown in the above embodiment provided on a single die. The integrated circuit 390 has a stacked structure and is broadly divided into a layer having Si transistors (Si transistor layer 393), a wiring layer 394, and a layer having OS transistors (OS transistor layer 395). Since the OS transistor layer 395 can be stacked on the Si transistor layer 393, the semiconductor chip 391 can be easily miniaturized.

[0290] In Figure 23B, a QFP (Quad Flat Package) is applied to the semiconductor chip 391, but the package configuration is not limited to this. Other configurations include through-hole type DIP (Dual In-line Package), PGA (Pin Grid Array), surface mount type SOP (Small Outline Package), SSOP (Shrink Small Outline Package), TSOP (Thin-Small Outline Package), LCC (Leaded Chip Carrier), QFN (Quad Flat Non-leaded package), BGA (Ball Grid Array), FBGA (Fine pitch Ball Grid Array), and contact mount type DTP (Dual Tape carrier Package), QTP (Quad Tape-carrier Package), etc., which can be used as appropriate.

[0291] The arithmetic circuit and switching circuit having Si transistors, and the memory circuit having OS transistors, can all be formed in the Si transistor layer 393, the wiring layer 394, and the OS transistor layer 395. In other words, the elements constituting the semiconductor device can be formed using the same manufacturing process. Therefore, the IC shown in Figure 23B does not require an increase in the manufacturing process even if the number of constituent elements increases, and the semiconductor device can be incorporated at a low cost.

[0292] According to one aspect of the present invention described above, a novel semiconductor device and electronic device can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device and electronic device with low power consumption can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device and electronic device capable of suppressing heat generation can be provided.

[0293] This embodiment can be appropriately combined with descriptions of other embodiments.

[0294] (Embodiment 6) In this embodiment, electronic devices, mobile devices, and computing systems to which the integrated circuit 390 described in the above embodiment can be applied will be described with reference to Figures 24 to 27.

[0295] Figure 24A shows an external view of an automobile as an example of a mobile device. Figure 24B is a simplified diagram of data exchange inside the automobile. The automobile 590 has multiple cameras 591, etc. The automobile 590 is also equipped with various sensors (not shown), such as infrared radar, millimeter-wave radar, and laser radar.

[0296] In the automobile 590, the above-described integrated circuit 390 (or a semiconductor chip 391 incorporating the above-described integrated circuit 390) can be used in the camera 591, etc. The automobile 590 processes multiple images obtained by the camera 591 in multiple imaging directions 592 using the integrated circuit 390 described in the above embodiment, and the multiple images are analyzed together by the host controller 594, etc. via the bus 593, etc., thereby determining the surrounding traffic conditions, such as the presence or absence of guardrails and pedestrians, and enabling autonomous driving. It can also be used in systems that perform road guidance, hazard prediction, etc.

[0297] The integrated circuit 390 can perform calculations such as neural network processing on the obtained image data, enabling processes such as image resolution enhancement, image noise reduction, face recognition (for security purposes, etc.), object recognition (for autonomous driving purposes, etc.), image compression, image correction (wide dynamic range enhancement), image restoration of lensless image sensors, positioning, character recognition, and reflection reduction.

[0298] Although automobiles are described above as an example of a mobile vehicle, mobile vehicles are not limited to automobiles. For example, mobile vehicles can also include trains, monorails, ships, and aerial vehicles (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), and a computer according to one aspect of the present invention can be applied to these mobile vehicles to provide them with a system utilizing artificial intelligence.

[0299] Figure 25A is an external view showing an example of a portable electronic device. Figure 25B is a simplified diagram illustrating data exchange within the portable electronic device. The portable electronic device 595 includes a printed circuit board 596, a speaker 597, a camera 598, a microphone 599, etc.

[0300] In the portable electronic device 595, the integrated circuit 390 can be provided on the printed circuit board 596. The portable electronic device 595 can improve user convenience by processing and analyzing multiple data obtained from the speaker 597, camera 598, microphone 599, etc., using the integrated circuit 390 described in the above embodiment. It can also be used in systems that perform voice guidance, image search, etc.

[0301] The integrated circuit 390 can perform calculations such as neural network processing on the obtained image data, enabling processes such as image resolution enhancement, image noise reduction, face recognition (for security purposes, etc.), object recognition (for autonomous driving purposes, etc.), image compression, image correction (wide dynamic range enhancement), image restoration of lensless image sensors, positioning, character recognition, and reflection reduction.

[0302] The portable game console 1100 shown in Figure 26A includes a housing 1101, housing 1102, housing 1103, a display unit 1104, a connection unit 1105, operation keys 1107, etc. Housings 1101, 1102, and 1103 are detachable. By attaching the connection unit 1105 provided on housing 1101 to housing 1108, the video output from the display unit 1104 can be output to another video device. On the other hand, by attaching housings 1102 and 1103 to housing 1109, housings 1102 and 1103 are integrated and function as an operation unit. The integrated circuit 390 shown in the previous embodiment can be incorporated into chips provided on the circuit boards of housings 1102 and 1103.

[0303] Figure 26B shows a USB-connected stick-type electronic device 1120. The electronic device 1120 has a housing 1121, a cap 1122, a USB connector 1123, and a circuit board 1124. The circuit board 1124 is housed in the housing 1121. For example, a memory chip 1125 and a controller chip 1126 are mounted on the circuit board 1124. The integrated circuit 390 shown in the previous embodiment can be incorporated into the controller chip 1126 of the circuit board 1124.

[0304] Figure 26C shows a humanoid robot 1130. The robot 1130 has sensors 2101 to 2106 and a control circuit 2110. For example, the control circuit 2110 can incorporate the integrated circuit 390 shown in the previous embodiment.

[0305] The integrated circuit 390 described in the above embodiment can also be used in a server that communicates with an electronic device, instead of being built into the electronic device itself. In this case, the electronic device and the server constitute a computing system. Figure 27 shows an example of the configuration of system 3000.

[0306] System 3000 consists of an electronic device 3001 and a server 3002. Communication between the electronic device 3001 and the server 3002 can be performed via an internet connection 3003.

[0307] The server 3002 has multiple racks 3004. Multiple circuit boards 3005 are provided in the multiple racks, and the integrated circuit 390 described in the above embodiment can be mounted on the circuit boards 3005. This configures a neural network in the server 3002. The server 3002 can then perform calculations on the neural network using data input from the electronic device 3001 via the internet line 3003. The results of the calculations performed by the server 3002 can be transmitted to the electronic device 3001 via the internet line 3003 as needed. This reduces the computational burden on the electronic device 3001.

[0308] This embodiment can be appropriately combined with descriptions of other embodiments.

[0309] (Notes regarding the descriptions in this specification, etc.) The above embodiments and a description of each component in those embodiments are provided below.

[0310] The configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments or examples to form one aspect of the present invention. Furthermore, if multiple configuration examples are shown within one embodiment, these configuration examples can be appropriately combined.

[0311] Furthermore, the content described in one embodiment (even if only a part of it) can be applied to, combined with, or substituted for other content described in the same embodiment (even if only a part of it), and / or content described in one or more other embodiments (even if only a part of it).

[0312] The content described in the embodiments refers to the content described using various figures or the content described using text in the specification in each embodiment.

[0313] Furthermore, a diagram (even a part of it) described in one embodiment can be combined with another part of that diagram, another diagram (even a part of it) described in that embodiment, and / or a diagram (even a part of it) described in one or more other embodiments to form even more diagrams.

[0314] Furthermore, in this specification, block diagrams classify components by function and show them as independent blocks. However, in actual circuits, it is difficult to separate components by function, and there may be cases where multiple functions are involved in a single circuit, or where a single function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, and can be appropriately rephrased depending on the situation.

[0315] Furthermore, in the drawings, the size, layer thickness, or area are shown at arbitrary sizes for the sake of explanation. Therefore, they are not necessarily limited to that scale. Also, the drawings are schematic for clarity and are not limited to the shapes or values ​​shown in the drawings. For example, they may include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences.

[0316] Furthermore, the positional relationships of the components illustrated in drawings are relative. Therefore, when explaining components with reference to drawings, terms such as "above" and "below" may be used for convenience. The positional relationships of the components are not limited to those described herein and can be appropriately rephrased depending on the situation.

[0317] In this specification and other documents, when describing the connections of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used to refer to the other of the source and drain. This is because the source and drain of a transistor vary depending on the transistor's structure or operating conditions. The terms source and drain of a transistor can be appropriately rephrased as source (drain) terminal or source (drain) electrode, depending on the context.

[0318] Furthermore, in this specification, the terms "electrode" and "wiring" do not functionally limit these components. For example, "electrode" may be used as part of "wiring," and vice versa. Moreover, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wiring" are formed as a single unit.

[0319] Furthermore, in this specification, voltage and potential may be used interchangeably as appropriate. Voltage is the potential difference from a reference potential; for example, if the reference potential is the ground voltage (earth voltage), then voltage can be replaced with potential. Ground potential does not necessarily mean 0V. Note that potential is relative, and depending on the reference potential, it may change the potential applied to wiring, etc.

[0320] Furthermore, in this specification, the term "node" can be replaced with terms such as terminal, wiring, electrode, conductive layer, conductor, impurity region, etc., depending on the circuit configuration and device structure. Also, terminals, wiring, etc., can be replaced with "node."

[0321] In this specification, when A and B are said to be connected, it means that A and B are electrically connected. Here, when A and B are electrically connected, it means that when an object (such as a switch, transistor, or diode, or a circuit including such an object and wiring) is present between A and B, the transmission of electrical signals between A and B is possible. Note that when A and B are electrically connected, this includes cases where A and B are directly connected. Here, when A and B are directly connected, it means that the transmission of electrical signals between A and B is possible via wiring (or electrodes, etc.) without the need for the aforementioned object. In other words, a direct connection means a connection that can be considered as the same circuit diagram when represented by an equivalent circuit.

[0322] In this specification, a switch refers to a device that has the function of controlling whether or not to allow current to flow by being in a conductive state (on state) or a non-conductive state (off state). Alternatively, a switch refers to a device that has the function of selecting and switching the path through which current flows.

[0323] In this specification, channel length refers, for example, to the distance between the source and drain in the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate overlap in a top view of a transistor, or in the region where the channel is formed.

[0324] In this specification, channel width refers, for example, to the length of the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate electrode overlap, or the region in which the channel is formed, where the source and drain face each other.

[0325] In this specification, terms such as "film" and "layer" may be interchanged depending on the context or situation. For example, the term "conductive layer" may be changed to "conductive film." Or, for example, the term "insulating film" may be changed to "insulating layer." [Explanation of symbols]

[0326] C11: Capacitor element, CK1: Node, D1: Node, GCLK1: Clock signal, LBL_n: Wiring, LBL_N: Wiring, LBL_1: Wiring, LBL_4: Wiring, LBL_6: Wiring, M11: Transistor, M12: Transistor, M13: Transistor, PSE0: Signal, PSE1: Signal, PSE2: Signal, Q1: Node, RWL_M: Read word line, RWL_1: Read word line, SLEEP1: Signal, SN11: Node, t1: Time, t2: Time, t3: Time, t4: Time, t5: Time, t6: Time, t7: Time, T0: Time, T1: Time, T6 :Time, WBL_1:Write bit line, WWL_M:Write word line, WWL_1:Write word line, 10:Semiconductor device, 12:Drive circuit, 13:Drive circuit, 14:Control circuit, 15:Processing circuit, 20:Arithmetic block, 21:Transistor, 22:Semiconductor layer, 23:Transistor, 24:Semiconductor layer, 30:Memory circuit section, 31:Circuit block, 32:Memory circuit, 32_N:Memory circuit, 32_P:Memory circuit, 32A:Memory circuit, 32B:Memory circuit, 32C:Memory circuit, 40:Arithmetic circuit section, 41:Switching circuit, 42:Add / accumulate circuit, 43:Activation function Calculation circuits, 44: Quantization arithmetic circuits, 44_1: Quantization arithmetic circuits, 44_9: Quantization arithmetic circuits, 45: Pre-pooling arithmetic circuits, 47: Post-pooling arithmetic circuits, 46: Dedicated arithmetic circuits, 46_1: Dedicated arithmetic circuits, 46_2: Dedicated arithmetic circuits, 46_3: Dedicated arithmetic circuits, 51: Multiplication circuits, 52: Addition circuits, 53: Registers, 54: Multiplexers, 55: Comparator circuits, 56: Registers, 61: Transistors, 61_N: Transistors, 61_P: Transistors, 61A: Transistors, 61B: Transistors, 62: Transistors, 62_N: Transistors, 62 _P: Transistor, 62B: Transistor, 63: Transistor, 63_N: Transistor, 63_P: Transistor, 64: Capacitive element, 64_N: Capacitive element, 64_P: Capacitive element, 64A: Capacitive element, 64B: Capacitive element, 100: Arithmetic processing system, 110: CPU, 120: Bus, 130: Accelerator section, 131: Control section, 193: PMU, 200: CPU core, 202: Cache memory device, 203: Cache memory device, 205: Bus interface section, 210: Power switch, 211: Power switch, 212: Power switch,214: Level shifter, 220: Flip-flop, 221: Scan flip-flop, 221A: Clock buffer circuit, 222: Backup circuit, 300N: OS memory, 311: Substrate, 312: Well area, 313: Insulator, 314: Oxide layer, 315: Semiconductor area, 316a: Low resistance area, 316b: Low resistance area, 316c: Low resistance area, 317: Insulator, 318: Conductor, 320: Insulator, 322: Insulator, 324: Insulator, 326: Insulator, 328: Conductor, 330: Conductor, 350: Insulator, 352: Insulator, 354: Insulator, 35 6: Conductor, 360: Insulator, 362: Insulator, 364: Insulator, 366: Conductor, 370: Insulator, 372: Insulator, 374: Insulator, 376: Conductor, 380: Insulator, 382: Insulator, 384: Insulator, 386: Conductor, 390: Integrated circuit, 391: Semiconductor chip, 392: Lead, 393: Si transistor layer, 394: Wiring layer, 395: OS transistor layer, 500: Transistor, 503: Conductor, 503a: Conductor, 503b: Conductor, 510: Insulator, 512: Insulator, 514: Insulator, 516: Insulator, 518: Conductor, 522: Insulator Body, 524: Insulator, 530: Oxide, 530a: Oxide, 530b: Oxide, 540a: Conductor, 540b: Conductor, 542: Conductor, 542a: Conductor, 542b: Conductor, 543a: Region, 543b: Region, 544: Insulator, 545: Insulator, 546: Conductor, 548: Conductor, 550: Transistor, 560: Conductor, 560a: Conductor, 560b: Conductor, 574: Insulator, 580: Insulator, 581: Insulator, 582: Insulator, 586: Insulator, 590: Automobile, 591: Camera, 592: Imaging direction, 593: Bus, 594: Host control -ra, 595: portable electronic device, 596: printed circuit board, 597: speaker, 598: camera, 599: microphone, 600: capacitive element, 610: conductor, 612: conductor, 620: conductor, 630: insulator, 640: insulator, 1100: portable game console, 1101: casing, 1102: casing, 1103: casing, 1104: display unit, 1105: connector, 1107: operation key, 1108: casing, 1109: casing, 1120: electronic device, 1121: casing, 1122: cap, 1123: USB connector, 1124: circuit board, 1125: memory chip,1126: Controller chip, 1130: Robot, 2101: Sensor, 2106: Sensor, 2110: Control circuit, 3000: System, 3001: Electronic equipment, 3002: Server, 3003: Internet connection, 3004: Rack, 3005: Circuit board

Claims

1. It has multiple memory circuits, a switching circuit, a multiply-accumulate circuit, and an activation function circuit. Each of the plurality of memory circuits has a first transistor having a metal oxide in the channel formation region, Each of the switching circuit, the sum-of-accumulate circuit, and the activation function circuit has a second transistor having silicon in its channel formation region. The switching circuit has the function of switching the conduction state between one of the plurality of memory circuits and the sum-of-accumulate circuit. The sum-of-accumulate circuit has the function of outputting a sum-of-accumulate output signal to the activation function circuit based on a sum-of-accumulate operation between the input data and the data selected by the switching circuit. A first insulating layer is provided above the second transistor. The first transistor is provided above the first insulating layer. A semiconductor device wherein the gate of the second transistor in the switching circuit is electrically connected to either the source or the drain of the first transistor in the memory circuit.

2. It has multiple memory circuits, a switching circuit, a multiply-accumulate circuit, and an activation function circuit. Each of the plurality of memory circuits has a first transistor having a metal oxide in the channel formation region, The aforementioned metal oxide contains In, Ga, and Zn. Each of the switching circuit, the sum-of-accumulate circuit, and the activation function circuit has a second transistor having silicon in its channel formation region. The switching circuit has the function of switching the conduction state between one of the plurality of memory circuits and the sum-of-accumulate circuit. The sum-of-products operation circuit has the function of outputting a first output signal to the activation function operation circuit based on a sum-of-products operation between the input data and the data selected by the switching circuit. A first insulating layer is provided above the second transistor. The first transistor is provided above the first insulating layer. A semiconductor device wherein the gate of the second transistor in the switching circuit is electrically connected to either the source or the drain of the first transistor.

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