Indication device

Abstract

To improve the reliability of a semiconductor device containing low resistance materials such as copper, aluminum, gold or silver as wiring.SOLUTION: The semiconductor device comprises as a pair of electrodes electrically connected to a semiconductor layer, a stacking structure of a first protective layer in contact with the semiconductor layer and a conductive layer containing low resistance materials abutting on the first protective layer. A top face of the conductive layer is covered by a second protective layer which functions as a mask for processing the conductive layer, and a side face thereof is covered by a third protective layer. This structure inhibits constituent elements of the conductive layer containing low resistance materials from migrating or dispersing to the semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the invention disclosed in this specification relates to a semiconductor device and a method of manufacturing the same. [Background Art]

[0002] Most of the transistors used in flat panel displays typified by liquid crystal display devices and light-emitting display devices are composed of silicon semiconductors such as amorphous silicon, single crystal silicon formed on a glass substrate or polycrystalline silicon. Further, transistors using such silicon semiconductors are also used in integrated circuits (ICs) and the like.

[0003] In addition, with the increase in the area and definition of flat panel displays, the driving frequency increases along with an increase in the resistance and parasitic capacitance of the wiring, resulting in wiring delay. Further, in order to suppress wiring delay techniques for forming wiring using low-resistance materials such as copper, aluminum, gold, silver, etc. have been studied (Patent Document 1). [Prior Art Documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-133422 [Summary of the Invention] [Problems to be Solved by the Invention]

[0005] However, there is a problem that elements constituting the wiring, such as copper, aluminum, gold, or silver, etc., diffuse into the semiconductor layer during processing.

[0006] Elements constituting the wiring, such as copper, aluminum, gold, or silver, etc., affect the electrical characteristics of the transistor​ It is one of the impurities that cause defects. Therefore, if this impurity gets mixed into the semiconductor layer... As a result, the semiconductor layer becomes less resistive, and due to changes over time and stress tests, transients occur. One of the problems with the electrical characteristics of a station is that the fluctuation in the threshold voltage increases.

[0007] Therefore, in one aspect of the present invention, low-resistance materials such as copper, aluminum, gold, or silver are used as wiring. One of the challenges is to improve the reliability of semiconductor devices that include [the specified component].

[0008] Furthermore, the description of these problems does not preclude the existence of other problems. One aspect of the present invention is It is not necessary to solve all of these issues. Furthermore, any issues other than those mentioned above should be detailed. This will become clear from the descriptions in the documents, etc., and it is not possible to extract any issues other than those mentioned above from the descriptions in the specifications, etc. It is possible to release it. [Means for solving the problem]

[0009] A semiconductor device according to one aspect of the present invention is characterized in that each of a pair of electrodes electrically connected to a semiconductor layer is A first protective layer in contact with a semiconductor layer, and a conductive layer containing a low-resistance material in contact with the first protective layer. It has a laminated structure, and the conductive layer also functions as a mask for processing the conductive layer on its upper surface. It is covered with a second protective layer, and its sides are covered with a third protective layer. The goal is to suppress the mixing or diffusion of constituent elements of a pair of conductive layers containing low-resistance materials into the semiconductor layer. ru.

[0010] Furthermore, in the electrode formation process described above, a first protective layer and a conductive layer containing a low-resistance material are formed. These are processed by separate etching processes. Here, when processing the conductive layer, semiconductor The body layer is covered by a membrane that forms the first protective layer. Also, when processing the first protective layer... The upper surface of the previously processed conductive layer is covered by a second protective layer, and the sides are covered by a third protective layer. Therefore, it is covered. As a result, the semiconductor of the constituent elements of the conductive layer in the electrode formation process This can suppress contamination of the body layer.

[0011] Furthermore, the first and third protective layers are anisotropic, with the second protective layer being an etchable protective film. It is possible to form them self-aligned by etching. Therefore, the pair of electrodes Without increasing the number of photomasks in the formation process, a protective layer (the) surrounding the conductive layer can be added. It becomes possible to provide a protective layer (1st protective layer, 2nd protective layer, and 3rd protective layer), improving reliability. This makes it possible to provide semiconductor devices with high productivity.

[0012] More specifically, the configuration can be as follows:

[0013] One aspect of the present invention comprises a semiconductor layer, a conductive layer, a first protective layer, a second protective layer, and a third protective layer It has a protective layer and a conductive layer, the lower surface of the conductive layer is in contact with the first protective layer, and the upper surface of the conductive layer is in contact with the second protective layer The conductive layer is in contact with the third protective layer, and the semiconductor layer is in contact with the first protective layer, and the conductive layer is in contact with the third protective layer. The layers include copper, aluminum, gold, or silver, and the lower end of the side of the third protective layer is the first protective layer. This is a semiconductor device that coincides with the upper edge of the side surface of the protective layer.

[0014] Furthermore, one aspect of the present invention comprises a semiconductor layer, a conductive layer, a first protective layer, a second protective layer, and It has three protective layers, the lower surface of the conductive layer is in contact with the first protective layer, and the upper surface of the conductive layer is in contact with the second The conductive layer is in contact with the protective layer, the side surface of the conductive layer is in contact with the third protective layer, and the semiconductor layer is in contact with the first protective layer. The conductive layer contains copper, aluminum, gold, or silver, and the lower end of the side of the third protective layer is The upper edge of the side surface of protective layer 1 coincides with the upper surface of the first protective layer and the conductive layer and the third protective layer. The semiconductor device is in contact with the conductive layer and the third protective layer, with the underside of the second protective layer in contact with the conductive layer and the third protective layer.

[0015] In the above, the first protective layer is a conductive layer. Furthermore, the conductive layer is Titanium, tantalum, tungsten, molybdenum in elemental form or alloy, or titanium nitride, nitrogen It is preferable that the material be formed from tantalum oxide, tungsten nitride, or molybdenum nitride.

[0016] In any one of the above-described semiconductor devices, a region in the semiconductor layer that is in contact with the first protective layer The film thickness in this region may be greater than the film thickness in other regions.

[0017] Furthermore, in any one of the above semiconductor devices, the semiconductor layer is made of indium, gallium, or It is preferable that the oxide semiconductor layer contains zinc.

[0018] Another aspect of the present invention is a semiconductor layer on which a first protective film, copper, and a first protective layer are placed. A conductive film containing luminium, gold, or silver, and a second protective film which serves as a second protective layer are formed. A first mask is formed on the second protective film, and the second protective film is processed using the first mask. Then, a second protective layer is formed, and the conductive film is processed using the second protective layer as a mask, A layer is formed, and the sides and top surface of the second protective layer, the sides of the conductive layer, and the first protective film are conductive A third protective film is formed in contact with the region exposed from the electrode layer, and the third protective film and the first protective film The film is processed by anisotropic etching to form a first protective layer located between the conductive layer and the semiconductor layer. This is a method for manufacturing a semiconductor device that forms a third protective layer in contact with the side surface of the conductive layer. [Effects of the Invention]

[0019] According to one aspect of the present invention, a low-resistance material such as copper, aluminum, gold, or silver is included as wiring. This can improve the reliability of semiconductor devices. [Brief explanation of the drawing]

[0020] [Figure 1] A plan view and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 2] A cross-sectional view illustrating one aspect of a semiconductor device fabrication method. [Figure 3] A cross-sectional view illustrating one aspect of a semiconductor device fabrication method. [Figure 4] A cross-sectional view illustrating a component of a semiconductor device according to one embodiment of the present invention. [Figure 5] A plan view and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 6] A plan view and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 7] A plan view and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 8] A diagram illustrating the band structure of a layered structure included in one embodiment of a semiconductor device. [Figure 9] Conceptual diagram and circuit diagram of a semiconductor device according to one aspect of the present invention. [Figure 10] A diagram showing an example of pixel layout. [Figure 11] A cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 12] A cross-sectional view illustrating one aspect of a semiconductor device fabrication method. [Figure 13] A cross-sectional view illustrating one aspect of a semiconductor device fabrication method. [Figure 14] A cross-sectional view illustrating one aspect of a semiconductor device fabrication method. [Figure 15]A cross-sectional view illustrating one aspect of a semiconductor device fabrication method. [Figure 16] A cross-sectional view illustrating one aspect of a semiconductor device fabrication method. [Figure 17] A diagram showing an example of an electronic device. [Figure 18] Cross-sectional photograph of the electrode structure fabricated in the example. [Figure 19] High-resolution TEM images and local Fourier transform images of a cross-section of an oxide semiconductor. [Figure 20] A diagram showing the nanobeam electron diffraction pattern of an oxide semiconductor film, and a diagram showing an example of a transmission electron diffraction measurement device. [Figure 21] A diagram showing the changes in the crystal structure due to electron irradiation. [Figure 22] A figure illustrating an example of structural analysis by transmission electron diffraction measurement, and a high-resolution TEM image in a planar view. [Modes for carrying out the invention]

[0021] The embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention is... Not limited to the following description, the present invention may have forms and characteristics that do not depart from the spirit and scope of the invention. Those skilled in the art will readily understand that the details can be modified in various ways. Therefore, the present invention This shall not be interpreted as being limited to the descriptions of the embodiments and examples shown below. In the embodiments and examples described below, the same part or a part having a similar function The same reference numeral or hatch pattern is used in common across different drawings, and its repetition is... The explanation will be omitted.

[0022] In each figure described herein, the size of each component, the thickness of the film, or the area is clearly indicated. It may be exaggerated for illustrative purposes. Therefore, it is not necessarily limited to that scale.

[0023] Furthermore, the ordinal numbers such as "1st," "2nd," etc. used in this specification are added to avoid confusion of constituent elements. It is a generalization and does not limit the number of items. Therefore, for example, "the first" can be changed to "the second." Alternatively, it can be explained by appropriately replacing it with "the third," etc.

[0024] Furthermore, the functions of "source" and "drain" are used when the direction of current changes during circuit operation. These may be replaced. For this reason, in this specification, etc., "source" and "dressing" are used. The term "in" may be used interchangeably.

[0025] Furthermore, voltage refers to the potential difference between two points, while electric potential refers to the electrostatic field at a given point. This refers to the electrostatic energy (electrical potential energy) possessed by a unit charge within a given object. Furthermore, generally speaking, the potential difference between the potential at a certain point and a reference potential (for example, the ground potential) This is simply called electric potential or voltage, and the terms electric potential and voltage are often used as synonyms. Therefore, unless otherwise specified in this specification, potential may be read as voltage. You may substitute "voltage" with "potential."

[0026] (Embodiment 1) In this embodiment, a semiconductor device and a method for manufacturing the same, which are aspects of the present invention, are shown in Figure 1. Please refer to Figure 4 for further explanation.

[0027] Figures 1(A) to 1(D) show examples of the configuration of transistor 200 included in a semiconductor device. Figure 1(A) is a plan view of transistor 200, and Figure 1(B) is a single-pointed chain view of Figure 1(A). This is a cross-sectional view along the line X1-Y1, and Figure 1(C) is a cross-sectional view along the dashed line V1-W1 in Figure 1(A). This is a cross-sectional view, and Figure 1(D) is a cross-sectional view along the dashed line V2-W2 in Figure 1(A). Yes. Note that in Figure 1(A), for clarity, some of the components of transistor 200 are shown (e.g., For example, insulating film 124, etc., are omitted in the illustration.

[0028] The transistor 200 shown in Figure 1 has a gate electrode 104 on the substrate 102 and a gate electrode 10 4 The insulating film 106 and insulating film 108 on the surface, and the gate via insulating film 106 and insulating film 108 A semiconductor layer 110 overlapping electrode 104, and a pair of electrodes 116a, 1 in contact with the semiconductor layer 110. 16b, a pair of electrodes 116a, a pair of second protective layers 118a in contact with the upper surface of 116b, 118b and a pair of third protective layers 120a in contact with the sides of the pair of electrodes 116a and 116b , including 120b.

[0029] In transistor 200, an insulating layer is provided between the gate electrode 104 and the semiconductor layer 110. The edge film 106 and insulating film 108 function as gate insulating films. Also, transistor 20 In 0, the gate electrode 104 has a stacked structure of gate electrode 104a and gate electrode 104b. It has a structure.

[0030] The pair of electrodes 116a and 116b function as source and drain electrodes. In electrodes 116a and 116b, electrode 116a is a first protective electrode in contact with the semiconductor layer 110. It has at least a laminated structure of layer 112a and conductive layer 114a. Furthermore, electrode 116b is The stacked structure of the first protective layer 112b and conductive layer 114b in contact with the semiconductor layer 110 is reduced. It also possesses.

[0031] Furthermore, each of the pair of conductive layers 114a and 114b contained within the pair of electrodes 116a and 116b A pair of second protective layers 118a and 118b are provided in contact with the upper surface. The sides of each of the electrode layers 114a and 114b, and the pair of second protective layers 118a and 118b A pair of third protective layers 120a and 120b are provided to cover at least a portion of each side. It gets kicked.

[0032] The pair of first protective layers 112a and 112b constitute the pair of conductive layers 114a and 114b. A conductive layer having the function of suppressing the diffusion of metal elements into the semiconductor layer 110. The first protective layers 112a and 112b are titanium, tantalum, molybdenum, and tungsten. Individual elements or alloys, or titanium nitride, tantalum nitride, molybdenum nitride, tungsten nitride It can be formed using the appropriate materials, etc.

[0033] The pair of conductive layers 114a and 114b are made from low-resistance materials such as copper, aluminum, gold, or silver. A single-layer or multilayer structure containing an element or alloy, or a compound having these as its main component. It can be constructed in such a way. For example, a pair of conductive layers 114a and 114b may contain silicon. Single-layer structure of aluminum film, double-layer structure of titanium film laminated on aluminum film, copper-magnesium A two-layer structure in which a copper film, silver film, or gold film is laminated on a cium-aluminum alloy film. A two-layer structure in which a titanium film or titanium nitride film is formed on a copper film, silver film, or gold film, i is a molybdenum film or molybdenum nitride film, and the molybdenum film or molybdenum nitride An aluminum film, copper film, silver film, or gold film is layered on top of the film, and then molybdenum is added on top of that. It can be a three-layer structure that forms a densate film or a molybdenum nitride film.

[0034] Since the pair of electrodes 116a and 116b also function as wiring, the pair of electrodes 116a and 11 A pair of conductive layers 114a and 114b contained in 6b are made of low-grade materials such as copper, aluminum, gold, or silver. By forming it using a resistive material, wiring can be used, such as when a large-area substrate is used as the substrate 102. Even if the wiring length increases, it becomes possible to manufacture semiconductor devices that suppress wiring delays. .

[0035] A pair of second protective layers 118a are provided in contact with the upper surfaces of the pair of conductive layers 114a and 114b. , 118b and a pair of third elements provided in contact with the sides of the pair of conductive layers 114a, 114b The protective layers 120a and 120b are made by expanding the metallic elements that make up the pair of conductive layers 114a and 114b. It has the function of preventing scattering. Therefore, a pair of second protective layers 118a, 118b and a pair of third The protective layers 120a and 120b are made of the metallic elements that make up the pair of conductive layers 114a and 114b. In contrast, it is formed using a material that has barrier properties.

[0036] A pair of second protective layers 118a, 118b etched a pair of conductive layers 114a, 114b During the process, a material with etching resistance is used for formation. Therefore, a pair of second protective layers 118a and 118b are used when etching the pair of conductive layers 114a and 114b. It functions as a protective film.

[0037] A pair of third protective layers 120a, 120b are located on the sides of a pair of second protective layers 118a, 118b. Surface, side surfaces of the pair of conductive layers 114a, 114b and dew from the pair of conductive layers 114a, 114b It is provided so as to cover the upper surfaces of the first protective layers 112a and 112b that have been exposed. (See Figure 1(B) and As shown in Figure 1(D), in the cross-sectional shape, a pair of third protective layers 120a and 120b The lower end of the side coincides with the upper end of the side of the pair of first protective layers 112a, 112b.

[0038] A pair of second protective layers 118a, 118b and a pair of third protective layers 120a, 120b Specifically, these are the silicon nitride layer, the silicon nitride oxide layer, and the aluminum nitride layer, respectively. It can be formed using an appropriate nitride insulating film such as an aluminum nitride oxide layer. In this specification, the silicon nitride layer and the aluminum nitride layer refer to a layer of which is more nitrate than oxygen. This refers to layers with a high content (atomic ratio) of certain elements, such as silicon oxide nitride layers and aluminum oxide nitride layers. This refers to a layer where the oxygen content (atomic ratio) is higher than that of nitrogen.

[0039] Alternatively, a pair of second protective layers 118a, 118b and a pair of third protective layers 120a, 12 0b contains indium tin oxide (hereinafter also referred to as ITO) and tungsten oxide. Indium oxide containing tungsten, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide A transparent material formed using conductive materials such as silicon oxide and indium tin oxide. A conductive film may be used.

[0040] However, a pair of second protective layers 118a, 118b or a pair of third protective layers 120a, 12 If the above-mentioned light-transmitting conductive film is used as 0b, the light-transmitting conductive film is also It functions as part of the pair of electrodes 116a and 116b.

[0041] Alternatively, a pair of second protective layers 118a, 118b and a pair of third protective layers 120a, 12 0b may be formed using an oxide semiconductor containing In, Ga, or Zn as appropriate. Oxide semiconductors containing In, Ga, or Zn can also be used in semiconductor layer 110. It is Noh.

[0042] In addition, transistor 200 has a pair of second protective layers 118a and 118b, and a pair of third protective layers. The example shows the case where the protective layers 120a and 120b are formed using the same material. In this case, a pair of second protective layers 118a, 118b and a pair of third protective layers 120a, 1 The boundary of 20b can sometimes be unclear. In Figure 1, these boundaries are schematically shown with dashed lines. This is also true for subsequent drawings.

[0043] In transistor 200, a pair of second protective layers 118a, 118b and semiconductor layer 11 An insulating film 122 is provided so as to cover 0, and an insulating film 124 is provided on top of the insulating film 122. The insulating film 122 and / or insulating film 124 are included as components of the transistor 200. This is also acceptable. Note that Figure 1 illustrates the sequentially stacked insulating film 122 and insulating film 124. However, a single-layer insulating film may be provided instead of insulating films 122 and 124. Furthermore, three or more stacked insulating films may be provided.

[0044] As shown in the cross-sectional views of transistor 200 in Figures 1(B) and 1(D), the cross-sectional shape is The conductive layer 114a is located between both sides of the first protective layer 112a and the second protective layer 118a It is located between both sides of the first protective layer 112b. Furthermore, it is located between both sides of the second protective layer 118b. Therefore, the first protective layer 112a The upper surface is in contact with the conductive layer 114a and the third protective layer 120a, and the second protective layer 118a The lower surface is in contact with the conductive layer 114a and the third protective layer 120a. The upper surface of 2b is in contact with the conductive layer 114b and the third protective layer 120b, and the second protective layer 118 The lower surface of b is in contact with the conductive layer 114b and the third protective layer 120b. Transistor 200 In this, the channel region is formed between the first protective layer 112a and the first protective layer 112b. Therefore, by providing conductive layers 114a and 114b at the above positions, conductive layer 11 4a and 114b can be moved away from the channel region. Therefore, the non- Diffusion of metal elements constituting the conductive layers 114a and 114b, which can become pure substances, into the semiconductor layer 110 This makes it possible to prevent it more effectively.

[0045] Furthermore, a pair of electrodes 116a and 116b near the channel region are covered with a pair of first protective layers 11 By using a single-layer structure of 2a and 112b, the region (a pair of first protective layers 112a, 11 Area where only 2b is provided) Other areas (a pair of first protective layers 112a, 112 Compared to the region consisting of a laminated structure of b and a pair of conductive layers 114a and 114b, the resistance is increased. This makes it possible to relax the electric field between the source and drain.

[0046] As shown above, the transistor 200 has a pair of conductive layers 114a, 1 containing a low-resistance material. By using 14b as wiring, wiring delay can be suppressed while the pair of conductive layers 114 The lower, upper, and side surfaces of a, 114b are a pair of first layers capable of functioning as a barrier layer. By covering it with a third protective layer, the incorporation and diffusion of impurities into the semiconductor layer 110 is prevented. This makes it possible to suppress impurities. Transistor 2 having a semiconductor layer 110 with reduced impurities 00 is a highly reliable transistor with suppressed variations in electrical characteristics.

[0047] Furthermore, a pair of first protective layers 1 function as barrier layers for the pair of conductive layers 114a and 114b. 12a, 112b, a pair of second protective layers 118a, 118b and a pair of third protective layers 12 0a and 120b contain the metal elements that make up the pair of conductive layers 114a and 114b as impurities. It may be mixed in. However, the concentration of metal elements that may be mixed in as impurities is the same as that of a pair of conductive layers. The region in contact with 114a and 114b is the highest, and the region away from the pair of conductive layers 114a and 114b... It is preferable to reduce it as much as possible.

[0048] The following describes the details of other configurations of transistor 200.

[0049] There are no major restrictions on the material of the substrate 102, but it should at least be able to withstand subsequent heat treatment. It must have heat resistance. For example, glass substrate, ceramic substrate, quartz substrate, saffron A wire substrate or the like may be used as the substrate 102. Alternatively, silicon or silicon carbide may be used. Single-crystal semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, S It is also possible to use OI substrates, and semiconductor elements are provided on these substrates. It may also be used as substrate 102. Note that when using a glass substrate as substrate 102, 6th generation (1500mm x 1850mm), 7th generation (1870mm x 2200mm), 8th generation (2200mm x 2400mm), 9th generation (2400mm x 2800mm), By using large-area substrates such as the 10th generation (2950mm x 3400mm), large displays can be created. The device can be manufactured.

[0050] Furthermore, a flexible substrate is used as the substrate 102, and the transistor 200 is directly mounted on the flexible substrate. Alternatively, a release layer may be provided between the substrate 102 and the transistor 200. The delamination layer is separated from the substrate 102 after the semiconductor device has been partially or completely completed on it. It can be separated and transferred to another substrate. In this case, transistor 200 is heat resistant. It can be transferred to substrates with inferior properties or flexible substrates.

[0051] The gate electrode 104 has a structure in which gate electrode 104a and gate electrode 104b are stacked. The gate electrode 104a is made of the same material as the first protective layers 112a and 112b, as appropriate. It can be formed in the same way as the conductive layers 114a and 114b. It can be formed using various materials as appropriate. By providing the gate electrode 104a, the substrate The adhesion between 102 and gate electrode 104b can be improved.

[0052] Furthermore, the electrode 104b is indium containing indium tin oxide and tungsten oxide. Indium zinc oxide containing oxides, tungsten oxide, and indium acid containing titanium oxide Contains indium tin oxide, indium zinc oxide, and silicon oxide, which contain titanium oxide. It can also be formed using a light-transmitting conductive material such as indium tin oxide. Alternatively, a laminated structure of the above-mentioned light-transmitting conductive material and the above-mentioned metal element can be used.

[0053] The insulating film 106 and insulating film 108, which function as gate insulating films, are, for example, silicon oxide. Silicon oxide nitride, silicon nitride, silicon nitride, silicon nitride, aluminum oxide Aluminum oxide, aluminum nitride, aluminum nitride, aluminum oxide, hafniac oxide Metals such as gallium oxide or Ga-Zn-based metal oxides can be used. In the embodiment of the application, a gate insulating film having a laminated structure of insulating film 106 and insulating film 108 is provided. The example shown is a combination, but it is not limited to this; a single-layer gate insulating film may also be used, or a three-layer or more gate insulating film. The gate insulating film may also include a multilayer structure.

[0054] In the gate insulating film, silicon nitride is used as the insulating film 106 that contacts the gate electrode 104. Forming nitride insulating films such as silicon nitride, aluminum nitride, and aluminum nitride. By doing so, the diffusion of the metal elements constituting the gate electrode 104b contained in the gate electrode 104 is achieved. It is preferable because it can be prevented.

[0055] Furthermore, using a silicon nitride film or a silicon nitride oxide film as the insulating film 106 is more effective. Preferred. Silicon nitride film or silicon nitride oxide film has a relative dielectric compared to silicon oxide film. Because the rate is high and the thickness of film required to obtain equivalent capacitance is large, the gate insulating film is physically... Thick films can be made. For example, the film thickness of insulating film 106 can be increased to 300 nm or more and 400 nm or less. This can be done. Therefore, the reduction in the dielectric breakdown voltage of transistor 200 can be suppressed or the dielectric breakdown voltage can be reduced. This can improve performance and suppress electrostatic discharge (ESD) in semiconductor devices.

[0056] Furthermore, a nitride insulating film that can be suitably used as insulating film 106 can form a dense film. This allows for the prevention of metallic element diffusion in the gate electrode 104b, while also preventing the defect level density and internal Because the local stress is large, forming an interface with the semiconductor layer 110 causes fluctuations in the threshold voltage. There is a risk of rubbing. Therefore, when forming a nitride insulating film as insulating film 106, Between 106 and the semiconductor layer 110, silicon oxide, silicon oxide, and silicon nitride are used as insulating film 108. It is preferable to provide an oxide insulating film such as aluminum oxide or aluminum oxide nitride. Between the conductive layer 110 and the insulating film 106 made of nitride insulating film, there is an insulating film 10 made of oxide insulating film. By forming 8, it is possible to stabilize the interface between the gate insulating film and the semiconductor layer 110. ru.

[0057] The thickness of the insulating film 108 can be, for example, 25 nm or more and 150 nm or less. When an oxide semiconductor, as described later, is used as the semiconductor layer 110, the insulating material in contact with the semiconductor layer 110 By using an oxide insulating film as the border film 108, oxygen can also be supplied to the semiconductor layer 110. It is possible. Oxygen vacancies contained in oxide semiconductors make the oxide semiconductor n-type, affecting its electrical properties. To cause fluctuations, supplying oxygen from the insulating film 108 and compensating for oxygen deficiencies is necessary. It is effective in improving reliability.

[0058] Alternatively, as insulating film 106 or insulating film 108, hafnium silicate (HfSiO x ) , nitrogen-added hafnium silicate (HfSi x O y N z ), nitrogen added HfAl x O y N z ), hafnium oxide, yttrium oxide, etc. By using high-k materials, gate leakage in transistors can be reduced.

[0059] The semiconductor layer 110 is made of semiconductor materials such as silicon, germanium, gallium arsenide, and gallium nitride. Elements can be used as appropriate. In addition, the semiconductor layer 110 can have a single crystal structure or a non-single crystal structure as appropriate. It can be made into a structure. Non-single crystal structures include, for example, polycrystalline structures, microcrystalline structures, or amorphous structures. Includes qualitative structure.

[0060] Semiconductor layer 110 can be made of materials such as silicon, germanium, gallium arsenide, or gallium nitride. When using a single element, the thickness of the semiconductor layer 110 is preferably 20 nm to 500 nm. The wavelength is 50 nm to 200 nm, more preferably 70 nm to 150 nm.

[0061] Furthermore, the semiconductor layer 110 can use an oxide semiconductor containing In, Ga, or Zn. Oxide semiconductors containing In, Ga, or Zn are typically In-Ga oxides. In-Zn oxide, In-M-Zn oxide (where M is Ti, Ga, Y, Zr, La, Ce, It contains Nd or Hf.

[0062] Oxide semiconductors are In-M-Zn oxides (where M is Ti, Ga, Y, Zr, La, Ce, Nd Or, in the case of Hf, a sputtering machine used to deposit In-M-Zn oxide film. The atomic ratio of the metal elements in the GET is preferably such that In ≥ M and Zn ≥ M. The atomic ratio of metal elements in a sputtering target is In:M:Zn = 1:1:1 In:M:Zn = 3:1:2 is preferred. These represent the atomic ratio of the metal elements contained in the sputtering target mentioned above, as an error. This includes fluctuations of plus or minus 30%.

[0063] When the oxide semiconductor is an In-M-Zn oxide, In and M are excluded from Zn and O. The atomic ratio is preferably 25 atomic% or more of In and 75 atomic% or less of M. More preferably, In is 34 atomic% or more and M is less than 66 atomic%. ru.

[0064] The oxide semiconductor has an energy gap of 2 eV or more, preferably 2.5 eV or more. The energy gap is 3 eV or more. In this way, oxide semiconductors with a wide energy gap are used as semiconductors. By using it in layer 110, the off-current of transistor 200 can be reduced.

[0065] Oxide semiconductors can be configured as single-crystal or non-single-crystal structures as appropriate. Non-single-crystal structures are... For example, CAAC-OS (C Axis Aligned Crystalli) will be discussed later. (Oxide Semiconductor), polycrystalline structure, microcrystalline structure described later, or includes an amorphous structure. In non-single crystal structures, the amorphous structure has the highest defect level density. CAAC-OS has the lowest defect level density.

[0066] When an oxide semiconductor is used as the semiconductor layer 110, the thickness of the semiconductor layer 110 is 3 nm or more. 200nm or less, preferably 3nm to 100nm, more preferably 3nm to 5nm The nm size should be 0 nm or less.

[0067] Furthermore, an oxide semiconductor with a low impurity concentration and low defect level density is used as the oxide semiconductor. This is preferable because it allows for the fabrication of transistors with even better electrical characteristics. Here, high purity is defined as having a low impurity concentration and a low defect level density (few oxygen vacancies). This is called genuine or substantially high-purity genuine.

[0068] High-purity intrinsic or substantially high-purity intrinsic oxide semiconductors have few carrier sources. Therefore, it is sometimes possible to lower the carrier density. In this case, an oxide semiconductor is used. In a transistor where a channel region is formed in the semiconductor layer 110, the threshold voltage is negative. It is less likely to have the resulting electrical characteristics (also referred to as normally on).

[0069] The carrier density of the oxide semiconductor is 1×10 17 per cm 3 or less, preferably 1×10 15 per cm 3 or less, more preferably 1×10 13 per cm 3 or less, even more preferably 1×1 0 11 per cm 3 or less, which is preferable.

[0070] In addition, an oxide semiconductor that is highly pure intrinsic or substantially highly pure intrinsic has a low density of defect levels Therefore, the trap level density may also be low.

[0071] In addition, a transistor having an oxide semiconductor that is highly pure intrinsic or substantially highly pure intrinsic , has an extremely small off-current. Even for a device with a channel width of 1×10 6 μm and a channel length L of 10 μm [[ID=​​​​​​​​​​​​​​​​​​​These include elements, alkali metals, or alkaline earth metals.

[0073] Furthermore, the hydrogen contained in oxide semiconductors reacts with the oxygen that bonds with the metal atoms to form water. This forms an oxygen deficiency in the lattice (or the part where oxygen has been removed). When hydrogen enters the atmosphere, electrons, which act as carriers, can be generated. Also, a part of hydrogen In some cases, when it combines with oxygen that bonds with metal atoms, it can generate electrons, which act as carriers. Therefore, transistors using oxide semiconductors containing hydrogen exhibit normally-on characteristics. This is likely to happen. Therefore, the amount of hydrogen contained in oxide semiconductors is reduced as much as possible. This is preferable. Specifically, in oxide semiconductors, secondary ion mass spectrometry (SIMS:S Hydrogen obtained by econdary ion mass spectrometry The concentration is 2 × 10 20 atoms / cm 3 The following is preferably 5 × 10 19 ate / c m 3 More preferably 1 × 10 19 atoms / cm 3 The following is more convenient: 5x1 0 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 below, Comfortable 5x10 17 atoms / cm 3 More preferably 1 × 10 16 a toms / cm 3 The following applies:

[0074] Furthermore, in oxide semiconductors, if silicon or carbon, which are among the Group 14 elements, Oxygen vacancies increase, leading to n-type formation. This is why silicon and carbon in oxide semiconductors... The concentration of , 2 × 10 18 atoms / cm 3 The following is preferably 2 × 10 17 atoms / cm 3 The following applies:

[0075] Furthermore, in oxide semiconductors, alkali metals obtained by secondary ion mass spectrometry or The concentration of alkaline earth metals is 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 16 atoms / cm 3 The following applies: Alkali metals and alkaline earth metals are oxide semiconductors. When it binds to a body, it can generate carriers, which increases the transistor's off-current. This can happen. For this reason, the concentration of alkali metals or alkaline earth metals in oxide semiconductors is It is preferable to reduce it.

[0076] Furthermore, if nitrogen is present in the oxide semiconductor, electrons, which act as carriers, are generated, increasing the carrier density. The amount increases, making it easier to convert to n-type. As a result, transistors using oxide semiconductors containing nitrogen... Distors tend to exhibit normally-on properties. Therefore, in the oxide semiconductor in question, nitrogen is It is preferable that it be reduced as much as possible. For example, it can be obtained by secondary ion mass spectrometry. The nitrogen concentration is 5 × 10 18 atoms / cm 3 The following is preferable:

[0077] Furthermore, in the semiconductor layer 110, the concentrations of copper, aluminum, gold, or silver are 1 × 10⁻⁶. 18 atoms / cm 3 The following applies: Copper, aluminum, gold, or silver in semiconductor layer 110. By setting the concentration to the above concentration, the electrical characteristics of the transistor can be improved. Furthermore, it can improve the reliability of transistors.

[0078] The pair of first protective layers 112a and 112b are made of titanium, tantalum, and tungsten. Alternatively, if a conductive material that readily bonds with oxygen, such as elemental molybdenum or an alloy, is used, acid Oxygen contained in the ion semiconductor and conductive material contained in a pair of first protective layers 112a and 112b When bonded, oxygen vacancy regions are formed in the semiconductor layer 110, which is made of an oxide semiconductor. Furthermore, a pair of first protective layers 112a are applied to the semiconductor layer 110 formed of an oxide semiconductor. In some cases, some of the constituent elements of the conductive material that forms 112b may be mixed in. As a result, acid In a semiconductor layer 110 formed of a synthetic semiconductor, a pair of first protective layers 112a, 112 A low-resistance region is formed near the region in contact with b. The low-resistance region is formed near the pair of first protective layers 1 In contact with 12a and 112b, and the insulating film 108 and a pair of first protective layers 112a and 112b It is formed between them. The low-resistance region is formed of an oxide semiconductor because of its high conductivity. It is possible to reduce the contact resistance between layer 110 and the first protective layers 112a and 112b. It is possible to increase the on-current of the transistor.

[0079] Insulating films 122 and 124 can be made of oxide insulating films or nitride insulating films as appropriate. .

[0080] Here, an oxide semiconductor is used as the semiconductor layer 110, and an oxide semiconductor is used as the insulating film 122. Using an oxide insulating film that can reduce oxygen deficiency in the body, the insulating film 124 is used from the outside A nitride insulating film is used that can prevent impurities from migrating to the semiconductor layer 110. Below are oxide insulating films that can be used as insulating film 122, and insulating film 124 Details of the nitride insulating films that can be used will be described below.

[0081] The oxide insulating film uses an oxide insulating film that contains more oxygen than satisfactorily satisfactorily satisfactorily. It is formed by adding more oxygen than satisfactorily satisfying the stoichiometric composition. Heat causes some of the oxygen to be removed. Acids contain more oxygen than the oxygen required to satisfy the stoichiometric composition. The ion insulating film has a surface temperature of 100°C to 700°C, preferably 100°C to 500°C. TDS (Thermal Desorption Spectrometer) is performed using the following heat treatment. Roscopy analysis showed that the amount of oxygen removed, converted to oxygen atoms, was 1.0 × 10⁻⁶. 18 at oms / cm 3 Preferably 3.0 × 10 20 atoms / cm 3 The above is the oxide. It is an insulating film.

[0082] Oxide insulating films that can be used as insulating film 122 have a thickness of 30 nm or more and 50 nm or more. silicon oxide, silicon oxide nitride, silicon oxide nitride, which have a wavelength of 0 nm or less, preferably 50 nm to 400 nm. There are things like n.

[0083] Nitride insulating films that can be used as insulating film 124 include oxygen, hydrogen, water, and alkali metals. , has a blocking effect on alkaline earth metals, etc. Nitride insulating film is used as insulating film 124. By providing this, oxygen can diffuse from the semiconductor layer 110 to the outside and from the outside to the semiconductor layer 110. It can prevent the intrusion of hydrogen, water, etc. Examples of nitride insulating films include silicon nitride films and nitride films. Examples include silicon oxide films, aluminum nitride films, and aluminum nitride oxide films. Note that oxygen, Nitride insulating film having a blocking effect against hydrogen, water, alkali metals, alkaline earth metals, etc. Alternatively, an oxide insulating film having a blocking effect such as oxygen, hydrogen, or water may be provided. As an oxide insulating film having a blocking effect on oxygen, hydrogen, water, etc., aluminum oxide Aluminum film, aluminum oxide nitride film, gallium oxide film, gallium oxide nitride film, yttrium oxide Examples include yttrium oxide film, hafnium oxide film, and hafnium oxide film.

[0084] Below, an example of a method for fabricating the transistor 200 of this embodiment is shown using Figures 2 and 3. explain.

[0085] First, a layered structure including gate electrode 104a and gate electrode 104b is placed on the substrate 102. A gate electrode 104 is formed, and insulating film 106 and insulating film 108 are laminated on the gate electrode 104. (See Figure 2(A)).

[0086] The method for forming the gate electrode 104 is shown below. First, the sputtering method and CVD (Ch By methods such as chemical vapor deposition, the gate electrode 1 A conductive film that will become 04a and a conductive film that will become the therapeutic film 104b are formed, and photolithography is applied to the conductive film. A mask is formed by a sography process. Next, the gate electrode 104a and A portion of the conductive film that will become the gate electrode 104b is etched, A gate electrode 104 is formed, consisting of a gate electrode 104a and a gate electrode 104b. Next, remove the mask.

[0087] Furthermore, the gate electrode 104 may be formed by electroplating, printing, or inkjet instead of the above-mentioned formation method. It may also be formed by the jet method or other methods.

[0088] Here, a 35nm thick titanium film and a 200nm thick copper film are applied by sputtering. They are formed in order. Next, a mask is formed by a photolithography process, and the mask is used Then, a portion of the copper film and a portion of the titanium film are dry-etched, and a gate is formed from the titanium film. An electrode 104a and a gate electrode 104b formed from a copper film are created.

[0089] In this embodiment, a gate electrode 104 having a stacked structure is shown, but a single-layer structure is also shown. It may also be a gate electrode 104 made of a gate electrode 10. For example, gate electrode 104b alone may be used You may form a 4.

[0090] Insulating films 106 and 108, which function as gate insulating films, are manufactured by sputtering, CV Formed by methods such as D-method or vapor deposition.

[0091] Insulating film 106 and insulating film 108 may be silicon oxide film, silicon oxide nitride film, or nitride When forming a silicon oxide film, the raw material gas is a silicon-containing sedimentary gas and an oxide It is preferable to use a silicon-containing gas. Typical examples of silicon-containing depositional gases include silane. Examples include disilane, trisilane, and silane fluoride. Oxidizing gases include oxygen, ozone, and 1 Examples include nitrous oxide and nitrogen dioxide.

[0092] Furthermore, when forming a gallium oxide film as insulating film 106 or insulating film 108, MOCVD (Metal Organic Chemical Vapor Deposition It can be formed using the ) method.

[0093] Next, island-shaped semiconductor layers 110 are formed on the insulating film 108 (see Figure 2(B)).

[0094] The method for forming the semiconductor layer 110 is described below. A semiconductor layer 11 A semiconductor film with a value of 0 is formed. Next, a mask is applied to the semiconductor film using a photolithography process. After forming the mask, a portion of the semiconductor film is etched using the mask, resulting in Figure 2(B). A semiconductor layer 110 with isolated elements is formed as shown. After this, the mask is removed.

[0095] The semiconductor film that will become the semiconductor layer 110 can be produced by sputtering, coating, pulsed laser deposition, It can be formed using methods such as laser ablation and CVD.

[0096] Furthermore, when forming an oxide semiconductor layer as the semiconductor layer 110, the sputtering method is used to form the plasma The power supply for generating the signal may include an RF power supply, AC power supply, DC power supply, etc., as appropriate. It can be used.

[0097] Sputtering gases include noble gases (typically argon), oxygen, and mixtures of noble gases and oxygen. Use as appropriate. In the case of a mixture of noble gas and oxygen, the gas ratio of oxygen to noble gas It is preferable to increase it.

[0098] Furthermore, the target can be appropriately selected according to the composition of the oxide semiconductor layer to be formed.

[0099] To obtain an oxide semiconductor layer that is of high purity intrinsic or substantially high purity intrinsic, a chamber In addition to evacuating the inside to a high vacuum, it is also necessary to purify the sputtering gas. The oxygen gas or argon gas used has a dew point of -40°C or lower, preferably -80°C or lower. A gas that has been purified to a temperature of -100°C or lower, more preferably -120°C or lower. By using this method, it is possible to prevent moisture and other substances from being incorporated into the oxide semiconductor film as much as possible. .

[0100] Here, we use an In-Ga-Zn oxide target (In:Ga:Zn=1:1:1). By sputtering, a 35nm thick In-Ga-Zn oxide semiconductor layer was created. A physical film is formed. Next, a mask is formed on the oxide semiconductor layer, and a portion of the oxide semiconductor layer is selected. A semiconductor layer 110 is formed by selective etching.

[0101] A first heat treatment may be performed after this. The semiconductor layer 110 is formed of an oxide semiconductor layer. In this case, the first heat treatment removes hydrogen, water, etc. contained in the semiconductor layer 110, and oxidation occurs. The hydrogen and water concentrations contained in the semiconductor layer can be reduced. The temperature of the heat treatment is Typically, the temperature is between 300°C and 400°C, preferably between 320°C and 370°C. .

[0102] The first heat treatment is performed using an electric furnace or an RTA (Rapid Thermal Annealing) device. The following can be used. By using an RTA device, the substrate can be subjected to a stress level above the substrate's stress point for a short period of time. Heat treatment can be performed at this temperature. Therefore, the heating treatment time can be shortened.

[0103] The first heat treatment involves nitrogen, oxygen, and ultra-dry air (with a water content of 20 ppm or less, preferably). Air (1 ppm or less, preferably 10 ppb or less), or noble gas (argon, helium) The procedure should be carried out under the following atmospheres: nitrogen, oxygen, ultra-dry air, or noble gases with hydrogen. It is preferable that it does not contain water, etc. Also, after heat treatment in a nitrogen or noble gas atmosphere, It may be heated in an oxygen or ultra-dry air atmosphere. As a result, the semiconductor layer 110 contains This allows for the removal of hydrogen, water, etc., while simultaneously supplying oxygen into the semiconductor layer 110. As a result, the amount of oxygen vacancies contained in the semiconductor layer 110 can be reduced.

[0104] The first heat treatment may be performed before processing the semiconductor layer 110 into island shapes.

[0105] Next, a first protective film 112, a conductive film 114, and a second protective layer A second protective film 113 is then formed (see Figure 2(C)).

[0106] The first protective film 112, the conductive film 114, and the second protective film 113 are formed by sputtering, C It is formed using methods such as VD (Vacuum Deposition) and vapor deposition.

[0107] Here, a 35 nm thick titanium film is applied as the first protective film 112 by sputtering. Formed. Also, a copper film with a thickness of 200 nm is formed as the conductive film 114 by sputtering. Furthermore, as a second protective film 113, a 230 nm thick nitrogen film is produced by plasma CVD. A silicon dioxide film is formed.

[0108] Next, masks 115a and 115b are formed on the second protective film 113, mask 115a, Using 115b, a portion of the second protective film 113 is etched to form a pair of second protective layers 11 Forms 3a and 113b (see Figure 2(D)). Masks 115a and 115b are available. A mask made of a resin (typically a resist mask) can be applied.

[0109] The second protective film 113 is etched using dry etching, wet etching, etc., as appropriate. It is possible to do so. Furthermore, the pair of second protective layers 113a and 113b are hardened in a later process. It functions as a screen, and the second protective layers 113a, 113b are formed as hard masks. Since the distance between protective layers 112a and 112b is equal to the channel length L of the transistor, the second The protective film 113 is preferably processed using dry etching that enables anisotropic etching. It seems so.

[0110] Next, a portion of the conductive film 114 is etched using the second protective layers 113a and 113b. This forms a pair of conductive layers 114a and 114b (see Figure 3(A)). Here, the first retain The condition is used to selectively etch the conductive film 114 without etching the protective film 112. As a result, the semiconductor layer 110 is not exposed in the etching process, and therefore the conductive film 114 Suppresses the mixing of metal elements constituting the conductive film 114 into the semiconductor layer 110 during etching. It can be controlled.

[0111] Furthermore, by etching the conductive film 114 using the wet etching method, isotropically conductive Because the film 114 is etched, the conductive layer 114a is etched by the first protective layer 1 that is formed later. A conductive layer 11 is formed between both sides of 12a and between both sides of the second protective layer 118a. 4b is between both sides of the first protective layer 112b which is formed later, and the second protective layer 118 It is formed between both sides of b. The conductive film 114 is selected without etching the first protective film 112. For selective etching, the etchant can be nitric acid, perchloric acid, phosphoric acid, acetic acid, or nitric acid. A mixture of these (aluminum oxide solution) can be used as appropriate.

[0112] Here, a wet etching method using a mixed solution of hydrogen peroxide, ammonium acetate, malonic acid, ethylenediaminetetraacetic acid, and 5-amino-1H-tetrazole monohydrate is used to selectively etch the conductive film 114.

[0113] Next, the masks 115a and 115b are removed. Here, the masks are decomposed in the gas phase by plasma (hereinafter referred to as ashing treatment) to facilitate the removal of the masks 115a and 115b, and then the masks 115a and 115b are removed using a stripping solution.

[0114] Note that the removal of the masks 115a and 115b can also be performed before the etching treatment of the conductive film 114. However, since the side surfaces of the pair of conductive layers 114a and 114b obtained by processing the conductive film 114 are located between the both side surfaces of the pair of second protective layers 113a and 113b, they are less likely to be exposed to the plasma (for example, oxygen plasma) applied to the ashing treatment of the masks 115a and 115b. When the pair of conductive layers 114a and 114b are irradiated with plasma, a metal element and oxygen constituting the pair of conductive layers 114a and 114b react to generate a compound (metal oxide). Since the compound has high reactivity and becomes an impurity when diffused into the semiconductor layer​​​​​​​​​​​​​​​​​​​​​​​​​​​The third protective film 120 is formed using methods such as sputtering, CVD, or vapor deposition.

[0117] Here, as the third protective film 120, a nitride film with a thickness of 230 nm is applied by plasma CVD. It forms a reconstituted film.

[0118] Next, the third protective film 120 and the first protective film 112 are etched by anisotropic etching. Then, a pair of second protective layers 118a, 118b and a pair of first protective layers 112a, 1 12b, the sides of a pair of second protective layers 118a, 118b and a pair of conductive layers 114a, 1 A third protective layer 120a, 120b covers the side of 14b and forms (see Figure 3(C)). .

[0119] An anisotropic etching process here results in the first protective layer 112a and the conductive layer 114a An electrode 116a is formed, and an electrode 116b is formed, consisting of a first protective layer 112b and a conductive layer 114b. It will be done.

[0120] The anisotropic etching process is carried out in a direction approximately perpendicular to the substrate 102, and the third protective film 120 and The first protective film 112 is etched to the thickness of the film. In this embodiment, chlorine, boron chloride, salt A third protective film is formed by dry etching using chlorine-based gases such as silicon dioxide and carbon tetrachloride. Etching is performed on 120 and the first protective film 112.

[0121] In addition, in the etching process of the first protective film 112, a pair of second protective layers 113a, 113 Since b is also exposed to etching gas, one side of the surface of the pair of second protective layers 113a and 113b A pair of second protective layers 118a and 118b are formed, with the portion also etched and the film thickness reduced. A pair of second protective layers 118a, 118b are burrs of a pair of conductive layers 114a, 114b. Since it functions as the A layer, it disappears during the etching process of the first protective film 112 In order not to, it is necessary to select the materials and film thicknesses of the pair of second protective layers 113a and 113b, or the etching conditions. Specifically, let the etching rate of the first protective film 112 be ER1, the film thickness be t1, the etching rate of the second protective layers 113a and 113b be ER2, and the film thickness be t 2. Then, it is necessary to satisfy t1 / ER1 < t2 / ER2.

[0122] In the etching processes of the third protective film 120 and the first protective film 112, the upper surfaces of the pair of conductive layers 1 114a and 114b are covered by the pair of second protective layers 118a and 118b, and the side surfaces of the pair of conductive layers 114a and 114b are covered by the pair of third protective layers 120a and 120b. Therefore, the pair of conductive layers 114a and 114 b are not exposed to the plasma used in the etching process, and the formation of compounds of the metal elements constituting the pair of conductive layers 114a and 114b by the plasma is prevented. Thus, even if the surface of the semiconductor layer 110 is exposed by the etching process here, the diffusion of the metal elements (or their compounds) constituting the pair of conductive layers 114a and 114b into the semiconductor layer 110 can be suppressed. As a result, it is possible to reduce the impurity concentration of the semiconductor layer 110.

[0123]

[0124] Also, in the etching process of the first protective film 112, a part of the semiconductor layer 110 and / or a part of the insulating film 108 (specifically, the region exposed from the pair of first protective layers 112a and 112b) may be etched, and the film thickness of the region may decrease. In addition, the metal elements constituting the conductive film 114 scattered by the etching treatment of the conductive film 114 If (for example, copper) remains on the surface of the first protective film 112, the metal element may adhere to the surface of the semiconductor layer 110 by the etching process of the first protective film 112. Therefore, after forming the pair of first protective layers 112a and 112b, it is preferable to perform a cleaning process on the semiconductor layer 110 exposed from the pair of first protective layers 112a and 11 2b.

[0125] The cleaning process can be performed, for example, with an alkaline solution such as a TMAH (Tetramethylammonium Hydr oxide) solution, an acidic solution such as dilute hydrofluoric acid, oxalic acid, or phosphoric acid, or by plasma treatment (such as oxygen plasma treatment). Note that due to the cleaning process, a part of the semiconductor layer 110 exposed from the pair of first protective layers 112a and 112b may be etched, and the film thickness of the region may decrease.

[0126] When an oxide semiconductor layer is applied as the semiconductor layer 110, after the cleaning process, the semiconductor layer 110 may be exposed to plasma generated in an oxidizing atmosphere to supply oxygen to the semiconductor layer 110. Examples of the oxidizing atmosphere include an atmosphere of oxygen, ozone, dinitrogen monoxide, nitrogen dioxide, etc. Further, in the plasma treatment, exposing the semiconductor layer 110 to the plasma generated without applying a bias to the substrate 102 side is preferable because oxygen can be supplied to the semiconductor layer 110 without damaging it. Also, the etching residue of the semiconductor film (for example, halogens such as fluorine and chlorine) that may remain on the surface of the semiconductor layer 110 by the plasma treatment here can be removed. Further, when the plasma treatment is performed while heating at 300°C or higher, oxygen in the plasma combines with hydrogen contained in the semiconductor layer 110 and desorbs as water. As a result, the hydrogen and water content in the semiconductor layer 110 can be reduced.

[0127] In this process, plasma treatment was used as a cleaning treatment or as a subsequent oxygen supply treatment. Even so, the bottom, top and side surfaces of the pair of conductive layers 114a and 114b are, respectively, a pair 1 protective layer 112a, 112b, a pair of second protective layers 118a, 118b and a pair of third Since it is covered by protective layers 120a, 120b, a pair of conductive layers 114a, 114 Surface b is not exposed to plasma. Therefore, the contamination of semiconductor layer 110 with impurities is prevented. It will be stopped.

[0128] Next, the semiconductor layer 110, the pair of electrodes 116a, 116b and the pair of second protective layers 118 Insulating films 122 and 124 are formed on a and 118b (see Figure 3(D)).

[0129] The insulating film 122 and insulating film 124 are formed by plasma CVD and sputtering methods. It is possible.

[0130] Formation of insulating film 122 and insulating film 124 provided on a pair of electrodes 116a and 116b At the same time, the lower and upper surfaces of a pair of conductive layers 114a and 114b containing copper, aluminum, gold, or silver The sides are covered by the first to third protective layers. Therefore, insulating film 122 and / or when depositing the insulating film 124, even if plasma is used, the pair of conductive layers 1 The surfaces of 14a and 114b are not exposed to the plasma. As a result, the pair of conductive layers 114a, 1 Compounds (for example, metals) are produced by the reaction of the metal elements constituting 14b with the plasma. It suppresses the formation of oxides and the metal elements constituting the pair of conductive layers 114a and 114b. This reduces the mixing or diffusion of substances into the semiconductor layer 110.

[0131] Insulating films 122 and 124 can be silicon oxide film, gallium oxide film, or aluminum oxide. Aluminum film, silicon nitride film, silicon oxide nitride film, aluminum oxide nitride film, or nitride A silicon oxide film or the like can be used as a single layer or in a laminated form. However, the semiconductor layer 110 and When applying an oxide semiconductor layer, the insulating film 122 in contact with the semiconductor layer 110 is as follows: When an oxide insulating film is formed, the oxide insulating film supplies oxygen to the oxide semiconductor layer. This is preferable because it makes this possible.

[0132] For example, a substrate placed in the vacuum-evacuated processing chamber of a plasma CVD apparatus is subjected to temperatures above 180°C. Maintain the temperature below 400°C, more preferably between 200°C and 370°C, and introduce the raw material gas into the processing chamber. By introducing this, the pressure inside the processing chamber is set to 30 Pa or more and 250 Pa or less, more preferably 40 The pressure is set to be between Pa and 200 Pa, and the conditions for supplying high-frequency power to electrodes installed in the processing chamber are as follows: A silicon oxide film or silicon oxide-nitride film may be formed. This allows for the formation of an oxide insulating film that releases oxygen.

[0133] Furthermore, after forming the oxide insulating film that releases oxygen, the plasma CVD apparatus is not opened to the atmosphere. The substrate placed in the ventilated processing chamber is subjected to a temperature of 180°C to 250°C, more preferably. Maintain the temperature between 180°C and 230°C, and introduce the raw material gas into the processing chamber to maintain the pressure within the processing chamber. The pressure is set to 100 Pa or more and 250 Pa or less, more preferably 100 Pa or more and 200 Pa or less. , 0.17 W / cm² is applied to the electrode installed in the processing chamber. 2 More than 0.5W / cm 2 Below, further better The current level is 0.26 W / cm². 2 More than 0.35W / cm 2 The following conditions apply to supplying high-frequency power: A silicon oxide film or silicon oxide-nitride film may be formed. This increases the decomposition efficiency of the raw material gas in the plasma, increasing oxygen radicals and the raw material gas As oxidation progresses, the oxygen content in the formed silicon oxide film or silicon oxidnitride film increases. The amount of material becomes greater than the stoichiometric composition. Also, at the substrate temperature mentioned above, silicon and Because the oxygen bond is weak, some of the oxygen is removed upon heating. As a result, the stoichiometric ratio is not satisfied. It forms an oxide insulating film that contains more oxygen than is added, and some of the oxygen is removed upon heating. It is possible.

[0134] It is preferable to use a nitride insulating film as the insulating film 124 provided on the insulating film 122. i. By providing a nitride insulating film as insulating film 124, the oxygen outside the semiconductor layer 110 This prevents diffusion into the semiconductor layer 110 and prevents the intrusion of hydrogen, water, etc. from the outside. Examples of insulating films include silicon nitride film, silicon nitride oxide film, aluminum nitride film, and silicon nitride oxide film. Aluminum films and the like can be used.

[0135] Furthermore, when forming nitride insulating films using the plasma CVD method, the plasma CVD equipment must be vacuumed. The substrate placed in the processing chamber is heated to a temperature of 300°C to 400°C, more preferably 320°C. It is preferable to set the temperature between ℃ and 370℃ because this allows for the formation of a dense nitride insulating film.

[0136] Furthermore, when an oxide semiconductor layer is used as the semiconductor layer 110, after the insulating film 122 is formed... A heat treatment may be performed before forming the insulating film 124. The temperature of the heat treatment is typically The heating temperature shall be between 150°C and 300°C, preferably between 200°C and 250°C. The process can be carried out in the same manner as the first heat treatment. This heat treatment causes the insulating film 122 to A portion of the contained oxygen is moved to the semiconductor layer 110, and the oxidized material used as the semiconductor layer 110 is then transferred. It is possible to reduce oxygen vacancies contained in the semiconductor. As a result, the semiconductor layer 110 The amount of oxygen deficiency can be reduced.

[0137] If water, hydrogen, etc. are present, an insulating film 124 having a function to block water, hydrogen, etc. When heat treatment is performed after formation, water, hydrogen, etc. contained in the insulating film 122 are released into the semiconductor layer 110. This can cause defects to form in the semiconductor layer 110. However, the insulating film 124 By performing a heat treatment before formation, water, hydrogen, etc. contained in the insulating film 122 are removed. This makes it possible to reduce variations in the electrical characteristics of transistor 200, and also to reduce the threshold. It is possible to suppress fluctuations in the voltage value.

[0138] Furthermore, by forming the insulating film 122 while heating the substrate 102, oxygen is introduced into the semiconductor layer 110. Because it is possible to move the oxygen vacancies contained in the semiconductor layer 110, Heat treatment is not required.

[0139] Furthermore, the heat treatment temperature is 150°C or higher and 300°C or lower, preferably 200°C or higher and 250°C or lower. By doing so, the diffusion of copper, aluminum, gold, or silver can be suppressed.

[0140] Furthermore, when forming the pair of electrodes 116a and 116b, a pair of first protective layers 112a and 11 The etching of 2b damages the semiconductor layer 110, and the back of the semiconductor layer 110 Oxygen vacancies may occur on the channel side. However, the insulating film 122 satisfies the stoichiometric composition. By applying an oxide insulating film containing more oxygen than the added oxygen, the heat treatment can be performed This allows for the repair of oxygen vacancies that have formed on the back channel side. This reduces the defects contained in transistor 0, thereby improving the reliability of transistor 200. It is possible.

[0141] Furthermore, heat treatment may be performed after the formation of the insulating film 124. The temperature of the heat treatment is typically The temperature should be between 150°C and 300°C, preferably between 200°C and 250°C.

[0142] By following the above steps, transistor 200 can be manufactured.

[0143] Figure 4 shows a cross-sectional view of the electrode 116a included in the transistor of this embodiment, in the direction of the channel length. A magnified view is shown. Figures 4(A) to 4(E) show the electrode 116 near the channel region. This is an enlarged view of a and its surrounding components. Note that in Figure 4, electrode 116a and its The surrounding area is shown in magnified view, but the electrode 116b and its surrounding area are assumed to have a similar configuration.

[0144] Figure 4(A) shows a portion of the upper surface of the first protective layer 112a, the side surface of the conductive layer 114a and the second When the third protective layer 120a covering the side surface of the protective layer 118a has different film thicknesses in different regions This is shown in the example. Specifically, in the third protective layer 120a, the second protective layer 118a and In the overlapping region 50, other regions (for example, regions in contact with the side surface of the second protective layer 118a) The film thickness is smaller than that. Also, the film thickness increases in steps as you approach the channel region. A third protective layer 120a is formed on the sea urchin.

[0145] In the cross-sectional shape, the side surface of the conductive layer 114a is located inward from the side surface of the second protective layer 118a. Because the width of the conductive layer 114 is shorter than the width of the second protective layer 118a, the third protective layer In the process of forming the film 120, a second protective layer 118a protrudes from the side surface of the conductive layer 114a. In the overlapping region, the third protective film 120 is difficult to form. Therefore, as shown in Figure 4(A) In addition, a third protective layer 120a having different film thicknesses in each region may be formed.

[0146] Figure 4(B) shows the case where the side surface of the conductive layer 114a is curved. Conductive film 114 Depending on the etching conditions, the side surface of the conductive layer 114a being processed may have a curved surface. If the side surface of the conductive layer 114a is curved, a third protective layer 1 is provided in contact with the side surface. This can improve the coverage of 20a.

[0147] In Figures 4(C) and 4(D), the second protective layer 118a and the third protective layer 120a are shown. This shows an example using materials with different etching rates. Figure 4(C) shows the third retaining As for protective layer 120a, the etching rate is greater than the etching rate of the second protective layer 118a. This shows the case when a different material is applied. In the configuration shown in Figure 4(C), the third protective layer 120a is Because it is more easily etched than the second protective layer 118a, the upper surface of the third protective layer 120a It is located closer to the surface of the substrate 102 than the upper surface of the second protective layer 118a.

[0148] Furthermore, in Figure 4(D), the etching rate of the third protective layer 120a is the same as that of the second protective layer 1 This shows the case where a material with an etching rate lower than that of 18a is applied. The configuration is shown in Figure 4(D). Therefore, the third protective layer 120a is less susceptible to etching than the second protective layer 118a. The upper surface of the second protective layer 118a is closer to the surface of the substrate 102 than the upper surface of the third protective layer 120a. It is located in [location].

[0149] In Figure 4(E), in the cross-sectional shape, the upper end of the side surface of the conductive layer 114a is the second protective layer 1 This example shows the case where it coincides with the lower end of the side of 18a. With this configuration, the third In the protective layer 120a, the side facing the second protective layer 118a and the conductive layer 114a The third protective layer 120a may have a curved surface. The covering properties of the insulating film 122, which is provided in contact with the protective layer 120a, can be improved.

[0150] The configuration shown in Figure 4 can be used in appropriate combination with other configurations specified herein. .

[0151] The semiconductor device shown in this embodiment uses low-resistance materials such as copper, aluminum, gold, or silver for its wiring. By incorporating this material, it is possible to suppress wiring delays even when applying large-area substrates. Therefore, it becomes possible to enhance the functionality of semiconductor devices.

[0152] Furthermore, the semiconductor device shown in this embodiment has a conductive layer containing a low-resistance material on its lower surface, upper surface, and side It has a protective layer that functions as a barrier layer, covering the surface. This means that the conductive layer does not include This makes it possible to suppress the incorporation and diffusion of impurities into the semiconductor layer in contact with the wiring. The goal is to provide a highly reliable semiconductor device in which fluctuations in the electrical characteristics of transistors are suppressed. It becomes possible.

[0153] Furthermore, the semiconductor device shown in this embodiment has a conductive layer containing a low-resistance material on its lower surface, upper surface and side The protective layer on the surface is added to increase the number of photomasks compared to when no protective layer is provided. It is possible to form it self-consistently without any problems. Therefore, semiconductors with good functionality Body equipment can be produced at low cost and with high yield. Also, the number of photomasks can be increased. Since a margin that takes into account the alignment accuracy is not required, transistors with short channel lengths can be used. It will also be possible to manufacture them.

[0154] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in combination as appropriate.

[0155] (Embodiment 2) In this embodiment, a semiconductor device according to one aspect of the present invention having a configuration different from that of Embodiment 1 is described. I will explain this using the same configuration as in Embodiment 1. Since it is possible to take that into consideration, a detailed explanation will be omitted.

[0156] Figures 5(A) to 5(C) show the transistor 230 included in the semiconductor device of this embodiment. This is shown. Figure 5(A) is a plan view of transistor 230, and Figure 5(B) is a plan view of Figure 5(A). Figure 5(C) is a cross-sectional view along the dashed line X4-Y4, and Figure 5(A) is a cross-sectional view along the dashed line V7- This is a cross-sectional view at W7. Note that in Figure 5(A), for clarity, transistor 230 Some of the components (for example, insulating film 124, etc.) are omitted in the illustration.

[0157] The transistor 230 shown in Figure 5 is a channel-etch type transistor, and is located on substrate 102 The gate electrode 104 formed on top, and the insulating film 106 and insulating film 10 on the gate electrode 104 8 and a semiconductor layer 110 that overlaps with the gate electrode 104 via insulating film 106 and insulating film 108. And a pair of electrodes 116a and 116b that are in contact with the semiconductor layer 110, and the upper surface of the pair of electrodes A pair of second protective layers 118a, 118b and a pair of electrodes 116a, 116b on one side A pair of third protective layers 120a, 120b in contact with the part, and a pair of electrodes 116a, 116b An insulating film 122 is provided there, an insulating film 124 is on the insulating film 122, and on the insulating film 124 It includes a gate electrode 126 superimposed on the semiconductor layer 110.

[0158] In the transistor 230 of this embodiment, an oxide semiconductor layer is used as the semiconductor layer 110. Let's explain using an example.

[0159] In transistor 230, insulating film 106 and insulating film 108 are the first gate insulating film and It functions in this way. In addition, insulating film 122 and insulating film 124 function as a second gate insulating film. do.

[0160] The transistor 230 has a gate electrode 126 on the insulating film 124, It differs from 200. The other configurations are the same as in Embodiment 1 and produce the same effects. This is possible. In other words, the transistor 230 has a pair of conductive layers 114a containing a low-resistance material. A pair of first layers acting as a barrier layer to cover the bottom, top, and sides of 114b It has a third protective layer. This provides a wiring that includes a pair of conductive layers 114a and 114b. This makes it possible to suppress the incorporation and diffusion of impurities into the semiconductor layer 110 that is in contact with it. Therefore, Transistor 230 is a highly reliable transistor with suppressed fluctuations in its electrical characteristics.

[0161] Furthermore, in transistor 230, the gate electrode 126 is insulated as shown in Figure 5(A). The film 122 and insulating film 124 overlap with the side surface of the semiconductor layer 110.

[0162] Furthermore, as shown in the cross-sectional view in Figure 5(C), insulating film 124, insulating film 122, insulating film 108, The insulating film 106 is provided on one outer side of the side surface in the channel width direction of the semiconductor layer 110. It has an opening 52, and gate electrode 104 and gate electrode 126 are connected at the opening 52. In this case, the gate electrode 126 at the opening 52 is located in a region on the semiconductor layer 110, This includes the region below the semiconductor layer 110. Furthermore, the gate electrode 126 is in the channel width direction. It overlaps from one end to the other of the semiconductor layer 110.

[0163] In Figure 5, the opening is provided on one outer side of the side surface of the semiconductor layer 110 in the channel width direction. The example shown is one in which the channel width of the semiconductor layer 110 may vary. Openings may be formed on the outside of both sides in the direction. In this case, the gate electrode 126 is open The opening includes a region above the semiconductor layer 110 and a region below the semiconductor layer 110.

[0164] As shown in Figure 5(C), the channel between the end of the gate electrode 126 and the end of the semiconductor layer 110 The distance d3 in the width direction is the distance of the first gate insulating film (insulating film 106 and insulating film 108) The sum of the film thickness t1 and the film thickness t2 of the second gate insulating film (insulating film 122 and insulating film 124) If the thickness is 1x or more, the electric field formed by the gate electrode 126 is on the side of the semiconductor layer 110 or This affects the end, including the side and its vicinity, and therefore the side or the side and its vicinity The generation of parasitic channels at the edges can be suppressed. On the other hand, the distance d3 is the film thickness t1 If the total thickness of the film and film thickness t2 is 7.5 times or less, reduce the area of ​​the transistor. It is possible.

[0165] The transistor 230 shown in this embodiment has a channel length of 0.5 μm or more and 6 μm or less, More preferably greater than 1 μm and 4 μm or less, and more preferably greater than 1 μm and 3.5 μm or less. More preferably, it should be greater than 1 μm and 2.5 μm or less. Transistor ON-voltage The flow increases as the ratio of channel length to channel width (L / W) decreases, so By reducing the channel length of the ZISTA 230 to approximately the range described above, the on-current can be improved. It is possible.

[0166] Furthermore, as shown in Embodiment 1, a pair of first conductive layers 114a and 114b are covered by a pair of first conductive layers The third protective layer can be formed self-aligningly, and the number of photomasks increases. Since a margin considering alignment accuracy is not required, the channel length is short within the range mentioned above. Even transistors that require high production yield can be manufactured with good efficiency.

[0167] The semiconductor layer 110 contained in the transistor 230 has a side surface in the channel length direction that is a pair of electrodes. 116a and 116b overlap, and one of the side surfaces in the channel width direction overlaps with the gate electrode 126. It has the following configuration. The edges of the semiconductor layer 110 are edges for processing the semiconductor layer 110 into island shapes. When exposed to plasma during etching, chlorine radicals and fluorine generated from the etching gas are produced. It readily reacts with radicals, etc. When an oxide semiconductor layer is applied as semiconductor layer 110. Therefore, the metal elements constituting the oxide semiconductor readily bond with the aforementioned radicals. At the edges of the oxide semiconductor layer, oxygen that was bonded to the metal element is in a state where it is easily detached. Therefore, oxygen vacancies can form, making it prone to becoming n-type. However, transistor 2 In 30, the side surface of the semiconductor layer 110 is a pair of electrodes 116a, 116b and a gate electrode 126 Because it overlaps with gate electrode 126 (including gate electrode 104 which is at the same potential as gate electrode 126). By controlling the potential of the terminal, the electric field applied to that end can be controlled. Therefore, an oxide semiconductor layer is applied as the semiconductor layer 110, and the edges of the oxide semiconductor layer are n-type. Even if this is the case, between the pair of electrodes 116a and 116b via the n-type region The current that can flow can be controlled by the potential applied to a pair of gate electrodes.

[0168] Specifically, a potential is applied to the pair of gate electrodes such that transistor 230 becomes non-conductive. When this happens, the off-current flowing between the pair of electrodes 116a and 116b through the end is reduced. It can be suppressed. Therefore, in order to obtain a large on current in transistor 230 By shortening the channel length, as a result, the pair of electrodes 116a at the edge of the semiconductor layer 110, Even if the length between 16b is shortened, it is possible to keep the off-current low. That is, Transistor 230 can obtain a large on-current when conducting, and when not conducting. In this state, it is a transistor that can keep the off-current low.

[0169] Furthermore, transistor 230 has gate electrode 104 and gate electrode 126, and The terminal electrode 104 and the gate electrode 126 are at the same potential, and the channel width of the semiconductor layer 110 is set. The side facing the gate electrode 126 is positioned opposite the first gate insulating film and the second gate insulating film. Carriers are present not only at the interface between the edge film and the semiconductor layer 110, but also in the bulk of the semiconductor layer 110. As a result of the current flow, the amount of carrier movement in transistor 230 increases. As the ON current of the inverter 230 increases, the field effect mobility also increases, and typically The field effect mobility is 10 cm. 2 / V·s or larger, or 20cm 2 It will be / V·s or greater. Here, the field-effect mobility is not an approximation of the mobility as a physical property of oxide semiconductor films. This is the field-effect mobility in the saturation region of a transistor.

[0170] Furthermore, transistor 230 has gate electrode 104 and gate electrode 126. Each of them has the function of shielding against an external electric field, so the substrate 102 and the gate electrode 10 During 4 and / or on the gate electrode 126, the charge of charged particles, etc., on the semiconductor layer 110 It has no effect. As a result, stress testing (for example, applying a negative potential to the gate electrode) - Characteristics in GBT (Gate Bias-Temperature Stress Test) This suppresses degradation and also changes the on-current rise voltage at different drain voltages. It can suppress movement.

[0171] BT stress testing is a type of accelerated testing that tests the stress on transistors that occur under prolonged use. Changes in characteristics (i.e., changes over time) can be evaluated in a short time. In particular, BT stress tests The change in the transistor's threshold voltage before and after testing is an important indicator for examining reliability. This serves as a benchmark. The smaller the fluctuation in threshold voltage before and after the BT stress test, the more reliable the result. It can be said that this is a transistor with high performance.

[0172] In transistor 230, the gate electrode 126 uses a transparent conductive film. It is possible. The transparent conductive film is made of ITO, indium zinc oxide, tung oxide. Indium oxide containing tungsten, indium zinc oxide containing tungsten oxide, and tungsten oxide. Indium oxide containing tan, indium tin oxide containing titanium oxide, silicon oxide containing It can be formed using conductive materials such as indium tin oxide.

[0173] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in combination as appropriate.

[0174] (Embodiment 3) In this embodiment, when an oxide semiconductor layer is applied as the semiconductor layer, defects in the oxide semiconductor layer Refer to the drawing for a semiconductor device having a transistor capable of further reducing the depression. This will be explained. The transistor described in this embodiment is either Embodiment 1 or Embodiment 2. In comparison, it differs in that it has a multilayer film comprising multiple oxide semiconductor layers. Here, the implementation is The details of the transistor will be explained using the semiconductor device shown in Figure 1 of Embodiment 1.

[0175] Figures 6(A) to 6(D) show a plan view and a cross-section of the transistor 210 of the semiconductor device. The diagram is shown.

[0176] Figure 6(A) is a top view of transistor 210, and Figure 6(B) is the same as Figure 6(A) but with a dashed line. This is a cross-sectional view in X2-Y2, and Figure 6(C) is shown along the dashed line V3-W3 in Figure 6(A). This is a cross-sectional view, and Figure 6(D) is a cross-sectional view along the dashed line V4-W4 in Figure 6(A). Note that in Figure 6(A), for clarity, some of the components of transistor 210 are shown (for example) For example, insulating film 124, etc., are omitted in the illustration.

[0177] The transistor 210 included in the semiconductor device shown in Figure 6 is made of insulating film 108 and insulating film 122 In that the semiconductor layer 110 provided between the two has a stacked structure, the transistor shown in Figure 1 It differs from the Zista 200. The other components are the same as in Figure 1, so please refer to the previous explanation. can.

[0178] In the transistor 210 shown in this embodiment, the semiconductor layer 110 is an oxide semiconductor layer The semiconductor layer 110 has an oxide semiconductor layer 107 and an oxide semiconductor layer 109. Furthermore, in transistor 210, a channel region is formed in the oxide semiconductor layer 107.

[0179] The oxide semiconductor layer 109 is made of gold that makes up the oxide semiconductor layer 107 in which the channel region is formed. This is an oxide semiconductor layer composed of one or more elemental groups. Therefore, the oxide semiconductor layer 10 Interfacial scattering is less likely to occur at the interface between 7 and the oxide semiconductor layer 109. In this case, the movement of carriers is not hindered, so the field-effect mobility of the transistor is high. ru.

[0180] The oxide semiconductor layer applied to the oxide semiconductor layer 109 contains at least In or Zn. Formed from metal oxides, typically In-Ga oxide, In-Zn oxide, In-M- Zn oxide (where M is Al, Ga, Y, Zr, La, Ce, or Nd), and an oxide. The energy at the lower end of the conduction band is lower than that of the oxide semiconductor layer applied to semiconductor layer 107, compared to the vacuum level. In the near future, and more typically, the energy at the lower end of the conduction band of the oxide semiconductor layer 109, and the oxide semiconductor The energy difference from the lower end of the conduction band in layer 107 is 0.05 eV or more, 0.07 eV or more, 0.1eV or higher, or 0.15eV or higher and 2eV or lower, 1eV or lower, 0.5eV or lower It is below or 0.4 eV. That is, the electron affinity of the oxide semiconductor layer 109 and the oxide The difference from the electron affinity of semiconductor layer 107 is 0.05 eV or more, 0.07 eV or more, and 0.1 eV. V or greater, or 0.15eV or greater, and 2eV or less, 1eV or less, 0.5eV or less, It is less than 0.4 eV.

[0181] The oxide semiconductor layer 109 has increased carrier mobility (electron mobility) due to the inclusion of In. Therefore, it is preferable. Also, as the oxide semiconductor layer 109, Al, Ga, Y, Zr, La, Ce Alternatively, having Nd in a higher atomic ratio than In may have the following effects. (1) Increase the energy gap of the oxide semiconductor layer 109. (2) Oxide semiconductor layer (3) Reduce the electron affinity of 10⁹. (4) Reduce the diffusion of impurities from the outside. Compared to the ionized semiconductor layer 107, the insulating properties are higher.

[0182] Furthermore, Ga, Y, Zr, La, Ce, or Nd are metallic elements that have a strong bonding force with oxygen. Therefore, the oxide semiconductor layer 109 is made of Ga, Y, Zr, La, Ce, or Nd rather than In. Having a high atomic ratio makes it less likely for oxygen deficiency to occur.

[0183] When the oxide semiconductor layer 109 is an In-M-Zn oxide, In is present excluding Zn and O. The atomic ratio of In and M is preferably less than 50 atomic%, and M is 50 atomic%. mic% or more, more preferably In is less than 25 atomic% and M is 75 atomic%. The percentage must be c% or higher.

[0184] Furthermore, oxide semiconductor layer 107 and oxide semiconductor layer 109 are made of In-M-Zn oxide (M is In the case of Ga, Y, Zr, La, Ce, or Nd, compared with oxide semiconductor layer 107 The original M (Ga, Y, Zr, La, Ce, or Nd) contained in the oxide semiconductor layer 109 The atom ratio is large, and typically, compared to the atoms contained in the oxide semiconductor layer 107, The atomic ratio is 0.5 times or higher, preferably 2 times or higher, and more preferably 3 times or higher.

[0185] Furthermore, oxide semiconductor layer 107 and oxide semiconductor layer 109 are made of In-M-Zn oxide (M is In the case of Al, Ga, Y, Zr, La, Ce, or Nd, the oxide semiconductor layer 109 is In :M:Zn=x1:y1:z1[atomic ratio], oxide semiconductor layer 107 In:M:Zn= If x2:y2:z2 [atomic ratio], then y1 / x1 is greater than y2 / x2, which is preferable. In this case, y1 / x1 is 1.5 times or more than y2 / x2. More preferably, y1 / x 1 is at least twice as large as y2 / x2, and more preferably, y1 / x1 is larger than y2 / x2 It is more than three times larger. In this case, in the oxide semiconductor layer, if y2 is x2 or greater, the acid It is preferable because it can impart stable electrical characteristics to transistors using a synthetic semiconductor layer. Furthermore, when y2 becomes more than three times x2, the field effect of the transistor using the oxide semiconductor layer Since fruit mobility decreases, it is preferable that y2 is less than three times x2.

[0186] The oxide semiconductor layer 107 is In-M-Zn oxide (where M is Ga, Y, Zr, La, Ce, etc.) In the case of Nd, the target used to form the oxide semiconductor layer 107 is, If the atomic ratio of the metal elements is In:M:Zn = x²:y²:z², then 、 x2 / y2 is 1 / 3 to 6, and moreover 1 to 6, and z² / y² is 1 / 3 to 6, and further It is preferable that z2 / y2 be between 1 and 6. This facilitates the formation of the CAAC-OS film, described later, as the oxide semiconductor layer 107. Typical examples of the atomic ratio of metal elements in a net include In:M:Zn=1:1:1, In:M: Examples include Zn=1:1:1.2 and In:M:Zn=3:1:2.

[0187] The oxide semiconductor layer 109 is In-M-Zn oxide (where M is Ga, Y, Zr, La, Ce, etc.) In the case of Nd, the target used to form the oxide semiconductor layer 109 is, If the atomic ratio of the metal elements is In:M:Zn=x1:y1:z1, then 、 x1 / y1 <x2 / It is preferable that y2 is such that z1 / y1 is between 1 / 3 and 6, and moreover, between 1 and 6. It seems so. Furthermore, by setting z1 / y1 to between 1 and 6, the oxide semiconductor layer 109 can be made C AAC-OS film formation becomes easier. Typical examples of atomic ratios of target metal elements include... are In:M:Zn=1:3:2, In:M:Zn=1:3:4, In:M:Zn=1: Examples include 3:6 and In:M:Zn=1:3:8.

[0188] Note that the atomic ratios of oxide semiconductor layer 107 and oxide semiconductor layer 109 are considered to be within the margin of error. This includes variations of plus or minus 40% in the above atomic ratio.

[0189] The thickness of the oxide semiconductor layer 109 is 3 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less. It should be less than or equal to nm.

[0190] In transistor 210, the oxide semiconductor layer 107 and insulating film 12 form the channel region. Between 2, there is an oxide semiconductor layer 109, and the oxide semiconductor layer 107 and insulating film 122 Even if a trap level is formed between the two due to impurities and defects, the trap level There is a gap between the oxide semiconductor layer 107 and the other material. As a result, the oxide semiconductor layer 107 flows Electrons are less likely to be trapped in trap levels, which increases the on-current of the transistor. It is possible, and the field effect mobility can be increased. Also, electrons in the trap level When captured, the electron becomes a negative fixed charge, causing the transistor's threshold voltage to fluctuate. However, by having the oxide semiconductor layer 109, at the trap level It is possible to reduce electron trapping, and the threshold voltage in transistor 210 This can reduce fluctuations.

[0191] Furthermore, the oxide semiconductor layer 109 can shield against external impurities, It is possible to reduce the amount of impurities that migrate from the part to the oxide semiconductor layer 107. The oxide semiconductor layer 109 is less likely to form oxygen vacancies. For these reasons, the oxide semiconductor layer 10 It is possible to reduce the impurity concentration and oxygen deficiency in step 7.

[0192] Furthermore, the oxide semiconductor layer 107 and the oxide semiconductor layer 109 are not simply stacked films. <Continuous junction (here, in particular, a structure in which the energy at the lower end of the conduction band changes continuously between each film) The film is fabricated so that trap centers and recombination centers are formed at the interface of each film. The layered structure is designed so that there are no impurities that would form a defect level like the one at the center. Impurities are mixed between the stacked oxide semiconductor layer 107 and oxide semiconductor layer 109. As a result, the continuity of the energy bands is lost, and carriers are trapped at the interface, or re-energized. They combine and then disappear.

[0193] To form continuous bonds, a multi-chamber deposition apparatus equipped with a load-lock chamber is required. (Using a sputtering device) to continuously stack each film without exposing it to the atmosphere. This is necessary. Each chamber in the sputtering apparatus is inefficient for the oxide semiconductor layer. To remove as much pure water as possible, an adsorption-type vacuum pump such as a cryopump is used. Using high vacuum evacuation (pressure of 5 × 10 -7 Pa~1×10 -4 It is preferable to do so (around Pa). It seems so. Alternatively, you can combine a turbomolecular pump and a cold trap to remove air from the exhaust system. It is preferable to prevent gases, especially those containing carbon or hydrogen, from flowing back into the bar. stomach.

[0194] Figure 7 shows another example of a transistor configuration having semiconductor layers including a stacked structure.

[0195] Figure 7(A) is a top view of transistor 220, and Figure 7(B) is the same as Figure 7(A) but with a dashed line. This is a cross-sectional view in X3-Y3, and Figure 7(C) is shown along the dashed line V5-W5 in Figure 7(A). This is a cross-sectional view, and Figure 7(D) is a cross-sectional view along the dashed line V6-W6 in Figure 7(A). Note that in Figure 7(A), for clarity, some of the components of transistor 220 are shown (for example) For example, insulating film 124, etc., are omitted in the illustration.

[0196] The transistor 220 included in the semiconductor device shown in Figure 7 is made of insulating film 108 and insulating film 122 The semiconductor layer 110 provided between the oxide semiconductor layer 105 and the oxide semiconductor layer 107 and It differs from the transistor in Figure 6 in that it has a stacked structure including an oxide semiconductor layer 109. The other components are the same as in Figure 6, and the previous explanation can be considered.

[0197] In transistor 220, oxide semiconductor layer 105, oxide semiconductor layer 107, and oxide semiconductor The conductive layer 109 is sequentially stacked on the insulating film 108. Also, in transistor 220, A channel region is formed in the oxide semiconductor layer 107.

[0198] The oxide semiconductor layer applied to the oxide semiconductor layer 105 is similar to the oxide semiconductor layer 109. Materials and forming methods can be used as appropriate.

[0199] Oxide semiconductor layer 105 and oxide sandwiching oxide semiconductor layer 107 in which the channel region is formed Each semiconductor layer 109 is preferably thinner than the oxide semiconductor layer 107. The thickness of the oxide semiconductor layer 105 and the oxide semiconductor layer 109 is preferably 1 nm or more and 5 nm or less. By setting the wavelength between 1 nm and 3 nm, the fluctuation in the transistor's threshold voltage is reduced. It is possible.

[0200] In transistor 220, between the insulating film 108 and the oxide semiconductor layer 107, there is an oxide semiconductor A layer 105 is provided, and between the oxide semiconductor layer 107 and the insulating film 122, an oxide semiconductor Because the body layer 109 is provided, silicon near the interface of the oxide semiconductor layer 107 The carbon concentration can be reduced.

[0201] The transistor according to this embodiment, having such a structure, has a channel region formed Because the number of defects in the multilayer film containing the oxide semiconductor layer is extremely low, the electrical characteristics of the transistor It is possible to improve these factors, typically by increasing the on-current and improving the field-effect mobility. This is possible. In addition, examples of stress tests include the BT stress test and the photo-BT stress test. The threshold voltage fluctuation in the test was small, resulting in high reliability.

[0202] <Transistor Band Structure> Next, the stacked structure included in transistor 210 shown in Figure 6, and the transistor shown in Figure 7. The band structure of the layered structure included in 220 will be explained using Figure 8.

[0203] Here, as an example, the oxide semiconductor layer 107 has an energy gap of 3.15 eV. Using a certain InGa-Zn oxide, the energy gap of the oxide semiconductor layer 109 is The energy gap is assumed to be 3.5 eV for In-Ga-Zn oxide. The measurement was performed using a meter (HORIBA JOBIN YVON UT-300).

[0204] The energy between the vacuum level of oxide semiconductor layer 107 and oxide semiconductor layer 109 and the upper edge of the valence band The differences (also called ionization potentials) were 8 eV and 8.2 eV, respectively. Oh, the energy difference between the vacuum level and the upper end of the valence band can be determined by ultraviolet photoelectron spectroscopy (UPS:Ult). raviolet Photoelectron Spectroscopy (P) device (P Measurements were taken using HI VersaProbe.

[0205] Therefore, the vacuum level and the lower end of the conduction band of the oxide semiconductor layer 107 and the oxide semiconductor layer 109 The energy differences (also called electron affinity) were 4.85 eV and 4.7 eV, respectively. Ta.

[0206] Figure 8(A) schematically shows a portion of the band structure of the multilayer structure contained in transistor 210. Here, insulating film 108 and insulating film 122 are silicon oxide films, and semiconductor layer 1 The case where 10 is provided in contact with the silicon oxide film will be explained. Note that E shown in Figure 8(A) cI1 represents the energy at the lower end of the conduction band of the silicon oxide film, and EcS1 represents the energy of the oxide semiconductor layer 1 This shows the energy at the lower end of the conduction band of 07, and EcS2 is the energy at the lower end of the conduction band of the oxide semiconductor layer 109. The energy is shown, and EcI2 represents the energy at the lower end of the conduction band of the silicon oxide film. EcI1 corresponds to insulating film 108, and EcI2 corresponds to insulating film 122.

[0207] As shown in Figure 8(A), in oxide semiconductor layer 107 and oxide semiconductor layer 109, The energy at the lower end of the guide changes smoothly. In other words, it changes continuously. This is possible because the oxide semiconductor layer 107 and the oxide semiconductor layer 109 contain common elements. Furthermore, oxygen moves between the oxide semiconductor layer 107 and the oxide semiconductor layer 109. This can be attributed to the formation of a mixed layer.

[0208] From Figure 8(A), the energy Ec of the lower end of the conduction band of the oxide semiconductor layer 107 of semiconductor layer 110. S1 becomes a well, and the transistor using the semiconductor layer 110 of the stacked structure... This shows that the channel region is formed in the oxide semiconductor layer 107.

[0209] Furthermore, as shown in Figure 8(A), near the interface between the oxide semiconductor layer 109 and the insulating film 122 Although trap levels may be formed due to impurities and defects, the oxide semiconductor layer 109 By providing this, the oxide semiconductor layer 107 and the trap level can be kept apart. Yes. However, if the energy difference between EcS1 and EcS2 is small, the oxide semiconductor layer 10 Electrons 7 may exceed the energy difference and reach the trap level. When a child is captured, a negative fixed charge is generated at the insulating film interface, which is the threshold of the transistor. The voltage value shifts in the positive direction. Therefore, the energy between EcS1 and EcS2 - If the difference is 0.1eV or more, preferably 0.15eV or more, the threshold of the transistor is This is preferable because it reduces fluctuations in the voltage value and results in stable electrical characteristics.

[0210] Figure 8(B) schematically shows a portion of the band structure of the multilayer structure contained in transistor 220. Here, insulating film 108 and insulating film 122 are silicon oxide films, and semiconductor layer 1 The case where 10 is provided in contact with the silicon oxide film will be explained. Note that E shown in Figure 8(B) cI1 represents the energy at the lower end of the conduction band of the silicon oxide film, and EcS1 represents the energy of the oxide semiconductor layer 1 This shows the energy at the lower end of the conduction band of 07, and EcS2 is the energy at the lower end of the conduction band of the oxide semiconductor layer 109. EcS3 indicates the energy at the lower end of the conduction band of the oxide semiconductor layer 105. EcI2 represents the energy at the lower end of the conduction band of the silicon oxide film. EcI1 represents the energy at the insulating film. EcI2 corresponds to 108, and EcI2 corresponds to insulating film 122.

[0211] As shown in Figure 8(B), oxide semiconductor layer 105, oxide semiconductor layer 107, and oxide semiconductor In the conductor layer 109, the energy at the lower end of the conduction band changes smoothly. In other words, It can also be said that it changes continuously. This is the oxide semiconductor layer 105, oxide semiconductor layer 107 and the oxide semiconductor layer 109 contain common elements, and in the stacked structure, oxygen This can be attributed to the formation of a mixed layer through mutual movement.

[0212] From Figure 8(B), the energy EcS1 at the lower end of the conduction band of the oxide semiconductor layer 107 is the well. In transistor 220, the channel region is formed in the oxide semiconductor layer 107. It can be seen that this will happen.

[0213] Furthermore, near the interface between the semiconductor layer 110 and the insulating film 108 and / or insulating film 122, impurities Although trap levels can be formed due to defects, as shown in Figure 8(B), oxide The semiconductor layers 105 and 109 are provided, and the oxide semiconductor layer 107 and the trapping junction It is possible to move the positions apart. However, the energy difference between EcS1 and EcS2, and Ec When the energy difference between S1 and EcS3 is small, the electrons of the oxide semiconductor layer 107 The Ghee difference can exceed the trap level. Therefore, between EcS1 and EcS2 The energy difference, and the energy difference between EcS1 and EcS3, are preferably 0.1 eV or greater. Setting it to 0.15eV or higher reduces the fluctuation in the transistor's threshold voltage, resulting in a more stable response. This is suitable because it provides electrical properties.

[0214] Note that the configurations and methods shown in this embodiment may differ from those shown in other embodiments. It can be used in combination with other elements as appropriate.

[0215] (Embodiment 4) In this embodiment, the transistor included in the semiconductor device described in the above embodiment is In this case, when an oxide semiconductor film is used as the semiconductor film, one applicable to the oxide semiconductor film The manner will be explained.

[0216] In the following description, "parallel" means a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Also, " perpendicular" means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Also, in this specification, when a crystal is a trigonal crystal or a rhombohedral crystal, it is expressed as a hexagonal crystal system.

[0217] The oxide semiconductor film is roughly classified into a non-single crystal oxide semiconductor film and a single crystal oxide semiconductor film. Non The single crystal oxide semiconductor film refers to a CAAC-OS film, a polycrystalline oxide semiconductor film, a microcrystalline oxide semi conductor film, an amorphous oxide semiconductor film, etc.

[0218] <CAAC-OS film> First, the CAAC-OS film will be described.

[0219] The CAAC-OS film is one of the oxide semiconductor films having a plurality of crystal parts oriented in the c-axis direction.

[0220] By observing the bright field image and the composite analysis image of the diffraction pattern (also referred to as a high resolution TEM image) of the CAAC-OS film by a transmission electron microscope (TEM: Transmission Electron Micro scope), a plurality of crystal parts can be confirmed. On the one hand, the boundaries between clear crystal parts, that is, grain boundaries (also called grain boundaries ] ary), cannot be confirmed by the high-resolution TEM image. Therefore, it can be said that the CAAC-OS film is less likely to cause a decrease in electron mobility due to grain boundaries. <00016,50> When observing the high-resolution TEM image of the cross section of the CAAC-OS film from a direction substantially parallel to the sample surface, In the crystalline region, it can be confirmed that the metal atoms are arranged in layers. Each layer of metal atoms is This reflects the unevenness of the surface (also called the surface to be formed) or the upper surface of the CAAC-OS film. It has a specific shape and is arranged parallel to the surface or top surface of the CAAC-OS film to be formed.

[0222] On the other hand, a high-resolution TEM image of the CAAC-OS film plane was observed from a direction roughly perpendicular to the sample surface. Then, it was confirmed that the metal atoms in the crystalline region are arranged in a triangular or hexagonal shape. Yes, it is possible. However, no regularity is observed in the arrangement of metal atoms between different crystalline regions.

[0223] Figure 19(A) is a high-resolution TEM image of a cross-section of the CAAC-OS film. Also, Figure 19(B) Figure 19(A) is a high-resolution TEM image of a cross-section that is further enlarged, making it easier to understand. The atomic arrangement is highlighted for this purpose.

[0224] Figure 19(C) shows the area enclosed by a circle (diameter approximately 4n) between AO and A' in Figure 19(A). This is the local Fourier transform image of m). From Figure 19(C), the c-axis orientation in each region is It can be confirmed. Also, the orientation of the c-axis is different between A and O and between O and A', so different grades This suggests that it is in. Also, between A and O, the angle of the c axis is 14.3° and 16.6°. It can be seen that it changes gradually and continuously, such as ° and 26.4°. Similarly, O-A' In between, the angle of the c-axis changes gradually and continuously from -18.3°, -17.6°, to -15.9°. It can be seen that it has transformed.

[0225] Furthermore, when electron diffraction is performed on the CAAC-OS film, oriented spots (bright spots) can be observed. It is measured. For example, on the upper surface of the CAAC-OS film, an electric field of, for example, between 1 nm and 30 nm is measured. When electron diffraction using a sub-beam (also called nanobeam electron diffraction) is performed, a spot is observed. (See Figure 20(A).)

[0226] High-resolution TEM images of the cross-section and high-resolution TEM images of the planar region of the CAAC-OS film It can be seen that it has orientation.

[0227] Furthermore, most of the crystalline parts contained in the CAAC-OS film are cubes with sides less than 100 nm long. It is small enough to fit inside. Therefore, the crystalline portion contained in the CAAC-OS film has a side length of 10n. This also includes cases that fit within a cube smaller than m, smaller than 5 nm, or smaller than 3 nm. Furthermore, multiple crystalline regions contained in the CAAC-OS film are linked together, forming one large crystalline region. This can sometimes form. For example, in a high-resolution planar TEM image, at 2500 nm 2 That's all. , 5μm 2 or greater than 1000 μm 2 In some cases, crystal regions exceeding the above size may be observed.

[0228] X-ray diffraction (XRD) applied to the CAAC-OS film. When structural analysis is performed using this method, for example, a CAAC-OS film having InGaZnO4 crystals is found. In the out-of-plane analysis, the diffraction angle (2θ) shows a peak near 31°. This peak may appear. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is generally aligned with the surface to be formed or the upper surface. It can be confirmed that it is facing in a nearly vertical direction.

[0229] On the other hand, in-pl X-rays are incident on the CAAC-OS film from a direction approximately perpendicular to the c-axis. In analysis using the ANE method, a peak may appear when 2θ is around 56°. This peak is It is attributed to the (110) plane of the InGaZnO4 crystal. Single crystal oxidation of InGaZnO4 For a solid semiconductor film, fix 2θ to around 56°, and use the normal vector of the sample surface as the axis (φ axis). When the sample is rotated while the analysis (φ scan) is performed, the crystal plane equivalent to the (110) plane is found. Six attributed peaks are observed. In contrast, in the case of the CAAC-OS film, 2θ is set to 5 Even when fixed at approximately 6° and scanned using the φ scan function, no clear peak appears.

[0230] From the above, it can be concluded that in CAAC-OS films, the orientation of the a-axis and b-axis is inconsistent between different crystalline regions. It is a rule, but it has c-axis orientation and the c-axis is parallel to the normal vector of the surface to be formed or the upper surface. It can be seen that it is facing in that direction. Therefore, as confirmed by the high-resolution TEM observation of the cross-section mentioned above, Each layer of metal atoms arranged in layers is a plane parallel to the ab-plane of the crystal.

[0231] The crystalline portion is formed when the CAAC-OS film is deposited, or when crystallization treatment such as heat treatment is performed. It is formed when this occurs. As mentioned above, the c-axis of the crystal is the surface on which the CAAC-OS film is formed or It is oriented in a direction parallel to the normal vector of the upper surface. Therefore, for example, the shape of the CAAC-OS film When the shape is altered by etching or other means, the c-axis of the crystal becomes the surface on which the CAAC-OS film is formed. Alternatively, it may not be parallel to the normal vector of the top surface.

[0232] Furthermore, the distribution of c-axis oriented crystalline regions within the CAAC-OS film does not need to be uniform. For example, the crystalline portion of the CAAC-OS film is formed by crystal growth from near the top surface of the CAAC-OS film. When formed in this way, the region near the top surface has a more c-axis oriented crystalline structure than the region near the surface being formed. The proportion of impurities can increase. Also, in CAAC-OS films with added impurities, the impurities The added region is altered, and regions with different proportions of partially c-axis-oriented crystals are formed. Sometimes.

[0233] Furthermore, the out-of-plane method for CAAC-OS films containing InGaZnO4 crystals. Analysis revealed that in addition to a peak near 2θ = 31°, a peak also appeared near 2θ = 36°. In some cases, this may occur. Peaks near 36° 2θ indicate c-axis orientation in a portion of the CAAC-OS film. This indicates that it contains crystals that do not have [the specified characteristic]. The CAAC-OS film has 2θ near 31°. It is preferable that a peak is observed, and that no peak is observed near 36° for 2θ.

[0234] CAAC-OS films are oxide semiconductor films with low impurity concentrations. The impurities include hydrogen, carbon, These are elements other than silicon and transition metal elements, which are the main components of oxide semiconductor films. In particular, silicon Elements such as ions, which have a stronger bonding force with oxygen than the metal elements that make up oxide semiconductor films, By removing oxygen from the material semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, reducing its crystallinity. This is a contributing factor. Also, heavy metals such as iron and nickel, argon, and carbon dioxide have a certain atomic radius. Because of its large molecular radius, when it is contained within an oxide semiconductor film, the oxide semiconductor film This disrupts the atomic arrangement and reduces crystallinity. Furthermore, these impurities are present in oxide semiconductor films. Objects can sometimes act as carrier traps or carrier sources.

[0235] Furthermore, CAAC-OS films are oxide semiconductor films with a low defect level density. For example, oxide Oxygen vacancies in semiconductor films can act as carrier traps or capture hydrogen. It can be a source of carrier activity.

[0236] A low impurity concentration and low defect level density (few oxygen vacancies) is referred to as high-purity intrinsic or This is essentially called high-purity intrinsic. High-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film Because there are fewer carrier sources, the carrier density can be kept low. Transistors using oxide semiconductor films exhibit electrical characteristics where the threshold voltage is negative (no Also called Marion.) It rarely becomes high-purity genuine or substantially high-purity genuine. Oxide semiconductor films, being of a certain nature, have few carrier traps. Therefore, the oxide semiconductor film Transistors using this technology exhibit less variation in electrical characteristics and are highly reliable. Furthermore, the time required to release the charge trapped in the carrier trap of the oxide semiconductor film is [time]. The interval is long, and it can behave as if it were a fixed charge. Therefore, the impurity concentration is high. Transistors using oxide semiconductor films with a high defect level density exhibit unstable electrical properties. There are cases where this is the case.

[0237] Furthermore, transistors using CAAC-OS films exhibit electrical characteristics under irradiation with visible light and ultraviolet light. The fluctuations are small.

[0238] <Polycrystalline oxide semiconductor film> Next, we will explain polycrystalline oxide semiconductor films.

[0239] Polycrystalline oxide semiconductor films allow for the identification of crystal grains in high-resolution TEM images. The crystal grains contained in the crystalline oxide semiconductor film are, for example, 2 nm or larger in high-resolution TEM images. The particle size must be 0 nm or less, 3 nm to 100 nm, or 5 nm to 50 nm. There are many such cases. Also, in polycrystalline oxide semiconductor films, grain boundaries can be confirmed in high-resolution TEM images. There is a match.

[0240] A polycrystalline oxide semiconductor film has multiple crystal grains, and the crystal orientation between these multiple crystal grains There may be differences. Also, when a polycrystalline oxide semiconductor film is constructed using an XRD device, When fabrication analysis is performed, for example, the out of a polycrystalline oxide semiconductor film having InGaZnO4 crystals -In the analysis using the -of-plane method, there is a peak near 31° for 2θ and a peak near 36° for 2θ. A peak, or other peaks, may appear.

[0241] Polycrystalline oxide semiconductor films may have high electron mobility due to their high crystallinity. Therefore, transistors using polycrystalline oxide semiconductor films have high field-effect mobility. However, polycrystalline oxide semiconductor films may have impurities segregated at the grain boundaries. In crystalline oxide semiconductor films, the grain boundaries become defect levels. In polycrystalline oxide semiconductor films, the grain boundaries are Because they can act as carrier traps or carrier sources, polycrystalline oxide semiconductor films are used. The transistors used showed less variation in electrical characteristics compared to transistors using CAAC-OS film. This can result in large, unreliable transistors.

[0242] <Microcrystalline oxide semiconductor film> Next, we will explain microcrystalline oxide semiconductor films.

[0243] Microcrystalline oxide semiconductor films have areas where crystalline regions can be confirmed in high-resolution TEM images. It has regions where a clear crystalline structure cannot be observed, and regions where a clear crystalline structure cannot be identified. Microcrystalline oxide semiconductor film The crystalline portion contained therein is between 1 nm and 100 nm in size, or between 1 nm and 10 nm in size. This is often the case. In particular, the minute particles are between 1 nm and 10 nm, or between 1 nm and 3 nm. An oxide semiconductor film having nanocrystals (nc) which are crystalline, -OS(nanocrystalline oxide semiconductor) It is called a film. Furthermore, nc-OS films, for example, clearly show grain boundaries in high-resolution TEM images. There may be cases where it cannot be recognized.

[0244] nc-OS films are used in minute regions (for example, regions between 1 nm and 10 nm, especially regions larger than 1 nm). The atomic arrangement has periodicity in the region of 3 nm or less. Also, the nc-OS film is different No regularity in crystal orientation is observed between the crystalline regions. Therefore, no orientation is observed throughout the film. In some cases, nc-OS films are indistinguishable from amorphous oxide semiconductor films depending on the analytical method. There are cases where XRD equipment using X-rays with a diameter larger than that of the crystalline region is used on nc-OS films. When structural analysis is performed using this method, the out-of-plane method reveals the crystal planes. No peaks are detected. Also, for nc-OS films, the probe diameter is larger than that of the crystalline region. For example, electron diffraction (also called limited-field electron diffraction) is performed using an electron beam of 50 nm or greater. Then, a diffraction pattern resembling a halo pattern is observed. On the other hand, for the nc-OS film, Nanobeam electron diffraction using an electron beam with a probe diameter close to or smaller than the size of the crystal region. When this is done, a spot is observed. Furthermore, nanobeam electron diffraction is performed on the nc-OS film. In some cases, a region of high brightness may be observed in a circular (ring-shaped) pattern. - When nanobeam electron diffraction is performed on the OS film, multiple spots are observed within a ring-shaped region. This may occur (see Figure 20(B)).

[0245] nc-OS films are oxide semiconductor films with higher orderliness than amorphous oxide semiconductor films. Therefore, nc-OS films have a lower defect level density than amorphous oxide semiconductor films. However, In nc-OS films, no regularity is observed in the crystal orientation between different crystalline regions. Therefore, nc-O The S film has a higher defect level density compared to the CAAC-OS film.

[0246] Therefore, nc-OS films may have a higher carrier density compared to CAAC-OS films. Oxide semiconductor films with high carrier density may have high electron mobility. Therefore, Transistors using nc-OS films may have high field-effect mobility. Because nc-OS films have a higher defect level density compared to CAAC-OS films, carrier traps The number of particles may increase. Therefore, transistors using nc-OS films are CAAC-O Compared to transistors using S film, these transistors exhibit greater variation in electrical characteristics and are less reliable. This is the result. However, nc-OS films can be formed even if they contain a relatively large amount of impurities. Therefore, it is easier to form than CAAC-OS films and can be suitably used depending on the application. This is possible in some cases. Therefore, semiconductor equipment having transistors using nc-OS films In some cases, the installation can be done with high productivity.

[0247] <Amorphous oxide semiconductor film> Next, we will explain amorphous oxide semiconductor films.

[0248] Amorphous oxide semiconductor films have an irregular atomic arrangement within the film and do not contain crystalline regions. These are physical semiconductor films. One example is an oxide semiconductor film that has an amorphous state, such as quartz.

[0249] In amorphous oxide semiconductor films, crystalline regions cannot be observed in high-resolution TEM images.

[0250] When structural analysis of amorphous oxide semiconductor films is performed using an XRD device, out-of-p Analysis using the Lane method did not detect any peaks indicating crystal planes. Furthermore, amorphous oxide semi-crystalline materials were found. When electron diffraction is performed on a conductive film, a halo pattern is observed. Furthermore, amorphous oxide semiconductors... When nanobeam electron diffraction is performed on a conductive film, no spots are observed, and a halo pattern is not seen. It is observed.

[0251] Amorphous oxide semiconductor films are oxide semiconductor films that contain high concentrations of impurities such as hydrogen. Furthermore, amorphous oxide semiconductor films are oxide semiconductor films with a high defect level density.

[0252] Oxide semiconductor films with high impurity concentrations and high defect level densities are prone to carrier traps and carriers. It is an oxide semiconductor film with many sources of emission.

[0253] Therefore, amorphous oxide semiconductor films have an even higher carrier density compared to nc-OS films. This can sometimes happen. Therefore, transistors using amorphous oxide semiconductor films are normally... It tends to have the electrical characteristics of a normal-on transistor. Therefore, transistors that require the electrical characteristics of a normally-on transistor It may be suitable for use in certain applications. Amorphous oxide semiconductor films have a high defect level density. Therefore, carrier traps may increase. Compared to transistors using CAAC-OS film or nc-OS film, these transistors have a different electrical performance. The transistor exhibits large variations in its thermal characteristics, resulting in low reliability.

[0254] <Single-crystal oxide semiconductor film> Next, we will explain single-crystal oxide semiconductor films.

[0255] Single-crystal oxide semiconductor films have low impurity concentrations and low defect level density (few oxygen vacancies). It is an oxide semiconductor film. Therefore, the carrier density can be lowered. Transistors using crystalline oxide semiconductor films rarely exhibit normally-on electrical characteristics. Furthermore, single-crystal oxide semiconductor films have a low impurity concentration and a low defect level density, so Rear trapping may be reduced. Therefore, transients using single-crystal oxide semiconductor films This results in a transistor with minimal variation in electrical characteristics and high reliability.

[0256] Furthermore, oxide semiconductor films have a higher density when they have fewer defects. Also, oxide semiconductor films are bonded Higher crystallinity results in higher density. Also, oxide semiconductor films have lower concentrations of impurities such as hydrogen. The density increases. Single-crystal oxide semiconductor films have a higher density than CAAC-OS films. Also, CAAC-OS films have a higher density than microcrystalline oxide semiconductor films. Body films have a higher density than microcrystalline oxide semiconductor films. Also, microcrystalline oxide semiconductor films are amorphous. It has a higher density than a sodium oxide semiconductor film.

[0257] Furthermore, oxide semiconductor films exhibit physical properties between nc-OS films and amorphous oxide semiconductor films. It may have such a structure. Oxide semiconductor films having such a structure are particularly amorphous-like oxide Amorphous-like semiconductor (amorphous-like OS: amorphous-like Ox It is called an IDE Semiconductor film.

[0258] Amorphous-like OS films exhibit porosity (also known as voids) in high-resolution TEM images. In some cases, the following may be observed. Also, the crystalline portion can be clearly identified in high-resolution TEM images. It has regions where this can be done and regions where the crystalline part cannot be observed. Phosphorus-like OS films can be bonded by minute electron irradiation, such as that observed by TEM. Crystallization may occur, and growth of crystalline regions may be observed. On the other hand, if the nc-OS film is of good quality... Crystallization is hardly observed even with minute amounts of electron irradiation, such as that observed by TEM.

[0259] Furthermore, the size of the crystalline portion of the amorphous-like OS film and nc-OS film is measured. Measurement can be performed using high-resolution TEM images. For example, an InGaZnO4 crystal is It has a layered structure, with two Ga-Zn-O layers between the In-O layers. (InGaZnO4) The unit cell of this crystal has 3 In-O layers and 6 Ga-Zn-O layers, for a total of 9 It has a structure in which layers are stacked in a layered manner along the c-axis. Therefore, the spacing between these adjacent layers is It is approximately the same as the lattice plane spacing (also called the d value) of the (009) plane, and from crystal structure analysis, The value has been determined to be 0.29 nm. Therefore, we focused on the lattice fringes in the high-resolution TEM image. Furthermore, in areas where the spacing between the grid lines is between 0.28 nm and 0.30 nm, The lattice fringes were considered to correspond to the ab-plane of the InGaZnO4 crystal. Observation of the lattice fringes The maximum length in the region is defined as the amorphous-like OS film and nc-OS. This refers to the size of the crystalline portion of the film. Specifically, crystalline portions larger than 0.8 nm are selected. evaluate.

[0260] Figure 21 shows high-resolution TEM images of an amorphous-like OS film and nc -This is an example of investigating the change in the average size of the crystalline regions (20 to 40 locations) of the OS film. As shown in Figure 21, the amorphous-like OS film crystallizes depending on the cumulative dose of electrons irradiated. It can be seen that the part gets larger. Specifically, in the initial stages of observation using TEM, 1. The crystalline portion, which was about 2 nm in size, changed when the cumulative irradiation dose reached 4.2 × 10⁻¹⁴ 8 e - / nm 2 In It can be seen that it has grown to a size of about 2.6 nm. On the other hand, a good quality nc-OS film is The cumulative dose of electrons from the start of electron irradiation was 4.2 × 10⁻⁶. 8 e - / nm 2 The range until it reaches Therefore, it can be seen that there is no change in the size of the crystal region regardless of the cumulative dose of electrons irradiated.

[0261] Furthermore, the crystals of the amorphous-like OS film and the nc-OS film are shown in Figure 21. The change in the size of the part is linearly approximated, and the cumulative electron irradiation dose is 0e - / nm 2 Extrapolating to this point, It can be seen that the average size of the crystal region takes a positive value. Therefore, amorphous-li The crystalline portions of the ke-OS film and nc-OS film were present before TEM observation. You can understand that.

[0262] Note that oxide semiconductor films include, for example, amorphous oxide semiconductor films, microcrystalline oxide semiconductor films, and CA The AC-OS film may be a multilayer film having two or more types.

[0263] When an oxide semiconductor film has multiple structures, its structure can be analyzed using nanobeam electron diffraction. It may be possible.

[0264] Figure 20(C) shows the electron gun chamber 2010, the optical system 2012 below the electron gun chamber 2010, and the optical system. Sample chamber 2014 below system 2012, optical system 2016 below sample chamber 2014, and optical system 2 Observation room 2020 below 016, camera 2018 installed in observation room 2020, and observation room A transmission electron diffraction measuring apparatus with a film chamber 2022 below 2020 is shown. Camera 2 Unit 018 will be installed facing the interior of observation room 2020. Note that there is no film room 2022. It's okay if you don't have to.

[0265] Furthermore, Figure 20(D) shows the internal structure of the transmission electron diffraction measurement device shown in Figure 20(C). Inside the transmission electron diffraction measurement device, electrons emitted from the electron gun installed in the electron gun chamber 2010... The light is irradiated onto material 2028, which is placed in sample chamber 2014, via optical system 2012. Electrons that passed through material 2028 were placed inside observation chamber 2020 via optical system 2016. The electrons are incident on the fluorescent screen 2032. The fluorescent screen 2032 displays a pattern corresponding to the intensity of the incident electrons. The appearance of 'n' allows for the measurement of the transmission electron diffraction pattern.

[0266] Camera 2018 is positioned facing fluorescent panel 2032, and when the P It is possible to photograph the turn. The center of the lens of camera 2018, and the fluorescent screen 20 The angle between the straight line passing through the center of 32 and the top surface of the fluorescent board 2032 is, for example, 15° or more. The angle shall be 80° or less, 30° to 75° or less, or 45° to 70° or less. The more the image is processed, the greater the distortion of the transmission electron diffraction pattern captured by Camera 2018. If the angle is known in advance, the distortion of the obtained transmission electron diffraction pattern can be corrected. It is also possible to install camera 2018 in film room 2022. There is a match. For example, when camera 2018 is placed in film chamber 2022, the incident direction of electron 2024 and They may be installed facing each other. In this case, less distortion is transmitted from the back of the fluorescent board 2032. It is possible to capture electron diffraction patterns.

[0267] Sample chamber 2014 is equipped with a holder for securing the sample substance 2028. The holder has a structure that allows electrons to pass through material 2028. The holder is, For example, it may have a function to move substance 2028 along the X, Y, and Z axes. The movement function of the luda is, for example, between 1 nm and 10 nm, between 5 nm and 50 nm, and 10 nm. Examples include m to 100 nm, 50 nm to 500 nm, 100 nm to 1 μm, etc. It is sufficient to have the precision to move within a range. These ranges are determined by the structure of material 2028. You just need to set an appropriate range.

[0268] Next, the transmission electron diffraction pattern of the material is measured using the transmission electron diffraction measuring device described above. I will explain the method.

[0269] For example, as shown in Figure 20(D), the irradiation position of electrons 2024, which are a nanobeam, in a material By changing its position (scanning), we can observe how the structure of a substance changes. This can be achieved. In this case, if material 2028 is a CAAC-OS film, it is shown in Figure 20(A). Such diffraction patterns are observed. Alternatively, if material 2028 is an nc-OS film, see Figure 2. A diffraction pattern like that shown in 0(B) is observed.

[0270] By the way, even if substance 2028 is a CAAC-OS film, it is partially an nc-OS film. Similar diffraction patterns may be observed. Therefore, the quality of the CAAC-OS film is , the percentage of the region in which the diffraction pattern of the CAAC-OS film is observed within a certain range (CAA It can sometimes be expressed as (also called the carbonization rate). For example, with a good quality CAAC-OS film If present, the CAAC conversion rate should be 50% or more, preferably 80% or more, and more preferably 90%. More preferably, the diffraction pattern is 95% or higher. The region in which this is observed is referred to as the non-CAAC rate.

[0271] For example, immediately after film deposition (indicated as-sputtered), or in an oxygen-containing atmosphere. The upper surface of each sample having a CAAC-OS film after heat treatment at 450°C was scanned. While doing so, a transmission electron diffraction pattern was acquired. Here, a speed of 5 nm / second was used for 60 seconds. The diffraction pattern is observed while scanning, and the observed diffraction pattern is converted into a still image every 0.5 seconds. The CAAC conversion rate was derived by performing the conversion. The electron beam used had a probe diameter of 1 nm. A nanobeam was used. Similar measurements were performed on six samples. And the CAAC conversion rate The average value across six samples was used for the calculation.

[0272] Figure 22(A) shows the CAAC conversion rate for each sample. CAAC-OS film immediately after deposition. The AC conversion rate was 75.7% (the non-CAAC conversion rate was 24.3%). Furthermore, the 450°C heating treatment was performed. The CAAC conversion rate of the CAAC-OS film after processing was 85.3% (the non-CAAC conversion rate was 14.7%). Yes, it was found. Compared to immediately after film deposition, the CAAC conversion rate after 450°C heat treatment is higher. Furthermore, heat treatment at high temperatures (e.g., 400°C or higher) results in a lower non-CAAC conversion rate. It can be seen that this occurs (the CAAC conversion rate increases). Also, in heat treatment below 500°C This shows that a CAAC-OS film with a high CAAC conversion rate can be obtained.

[0273] Here, most of the diffraction patterns that differ from those of the CAAC-OS film are similar to those of the nc-OS film. It was a pattern. Furthermore, the amorphous oxide semiconductor film could be confirmed in the measurement area. It was not possible. Therefore, by heat treatment, regions having a structure similar to that of the nc-OS film were created. This suggests that the structure of adjacent regions influences the rearrangement and subsequent transformation into CAAC (Computer-Aware Algebraic) structures.

[0274] Figures 22(B) and 22(C) show CAAC-O immediately after deposition and after heat treatment at 450°C. This is a high-resolution TEM image of the planar surface of the S film. By comparing Figure 22(B) and Figure 22(C)... This indicates that the CAAC-OS film after heat treatment at 450°C has a more homogeneous film quality. In other words, it was found that the film quality of the CAAC-OS film is improved by heat treatment at high temperatures. Light.

[0275] Using this measurement method, it is possible to analyze the structure of oxide semiconductor films that have multiple structures. This can happen.

[0276] Note that the configurations and methods shown in this embodiment may differ from those shown in other embodiments. It can be used in combination with other elements as appropriate.

[0277] (Embodiment 5) In this embodiment, a semiconductor device, which is one aspect of the present invention, will be described with reference to the drawings. In this embodiment, a semiconductor device, which is one aspect of the present invention, will be described using a display device as an example. Furthermore, in this embodiment, an oxide semiconductor layer will be used as the semiconductor layer for the explanation.

[0278] Figure 9(A) shows an example of a semiconductor device. The semiconductor device shown in Figure 9(A) has a pixel section 401 The scan line drive circuit 404 and the signal line drive circuit 406 are arranged in parallel or approximately parallel to each other. Furthermore, m scan lines 407 whose potential is controlled by the scan line drive circuit 404, and each The two are arranged in parallel or nearly parallel, and the potential is controlled by the signal line drive circuit 406. It has signal lines 409 and, furthermore, the pixel section 401 is a plurality of arranged in a matrix. It has pixels 301. Also, along the scan line 407, each is arranged parallel or substantially parallel to the others. It has capacitance lines 415. The capacitance lines 415 are parallel to each other along the signal lines 409. Alternatively, they may be arranged in approximately parallel directions. Also, the scan line drive circuit 404 and the signal line drive circuit Sometimes, the entire 406 unit is referred to as the drive circuit section.

[0279] Each scan line 407 is one of the pixels 301 arranged in m rows and n columns in the pixel section 401. It is electrically connected to n pixels 301 arranged in any row. Also, each signal line 409 m pixels 301, among the m pixels 301 arranged in m rows and n columns, located in any of the columns. It is electrically connected to m and n, both of which are integers greater than or equal to 1. Also, each capacitance line 415 is , n pixels 301 located in any row of the m rows and n columns They are electrically connected. Furthermore, the capacitance line 415 runs parallel to the signal line 409, and each is parallel to the other. If they are arranged in roughly parallel directions, then any of the pixels 301 arranged in m rows and n columns It is electrically connected to m pixels 301 arranged in a row.

[0280] Figures 9(B) and 9(C) can be used for pixel 301 of the display device shown in Figure 9(A). This shows the circuit configuration.

[0281] The pixel 301 shown in Figure 9(B) consists of a liquid crystal element 132, a transistor 131_1, and a capacitance element. Child 133_1 and,

[0282] The potential of one of the pair of electrodes of the liquid crystal element 132 is set appropriately according to the specifications of the pixel 301. The orientation state of the liquid crystal element 132 is set according to the data being written to it. A common potential (common potential) is applied to one of the pair of electrodes of the liquid crystal element 132 that each of the element 301 possesses. You may also assign a position to one of the pair of electrodes of the liquid crystal element 132 for each pixel 301 in each row. A different potential may be applied.

[0283] For example, the driving method for a display device equipped with a liquid crystal element 132 may be TN mode, STN mode D, VA mode, ASM (Axially Symmetric Aligned Mi cro-cell) mode, OCB (Optically Compensated B irefringence) mode, FLC (Ferroelectric Liqui d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode, MVA mode, PVA (Patterned Ver (Critical Alignment) mode, IPS mode, FFS mode, or TBA You may also use modes such as (Transverse Bend Alignment). In addition, as a method of driving the display device, there is also ECB (Electric Ally Controlled Birefringence) mode, PDLC (P Olymer Dispersed Liquid Crystal (PNLC) mode, (Polymer Network Liquid Crystal) mode, guest host There are modes such as St Mode. However, this is not limited to these, and various types of liquid crystal elements and their driving methods exist. Various materials can be used.

[0284] Furthermore, a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent More liquid crystal elements may be constructed. Liquid crystals exhibiting the blue phase have a short response time of 1 msec or less. Furthermore, because it is optically isotropic, orientation processing is unnecessary, and it exhibits low dependence on the viewing angle.

[0285] In pixel 301 at row m, column n, the source electrode and drain electrode of transistor 131_1 One pole is electrically connected to the signal line DL_n, and the other is connected to the pair of electrodes of the liquid crystal element 132. It is electrically connected to the other side. Also, the gate electrode of transistor 131_1 is on the scan line GL. It is electrically connected to _m. Transistor 131_1 can be in an ON or OFF state. This provides a function to control the writing of data to the data signal.

[0286] One of the pair of electrodes of the capacitive element 133_1 is connected to a wiring (hereinafter referred to as the capacitance line CL) to which a potential is supplied. One end is electrically connected to the other end of a pair of electrodes of the liquid crystal element 132, and the other end is electrically connected to the other end of the pair of electrodes of the liquid crystal element 132. The potential value of the capacitance line CL is set appropriately according to the specifications of pixel 301. Capacitive element 133_1 functions as a storage capacity for holding the written data.

[0287] For example, in the display device having pixels 301 as shown in Figure 9(B), each is driven by the scan line driving circuit 404 The pixels 301 in each row are selected sequentially, and transistor 131_1 is turned on to process the data signal. Write the data.

[0288] The pixel 301 on which data has been written is maintained by the transistor 131_1 being turned off. The image enters a state of being held. By performing this sequentially for each row, the image can be displayed.

[0289] Furthermore, the pixel 301 shown in Figure 9(C) consists of a transistor 131_2 and a capacitive element 133_2 It also includes a transistor 134 and a light-emitting element 135.

[0290] When a data signal is applied to either the source electrode or the drain electrode of transistor 131_2, It is electrically connected to the wiring (hereinafter referred to as signal line DL_n). Furthermore, transistor 1 The gate electrode of 31_2 is the wiring to which the gate signal is applied (hereinafter referred to as scan line GL_m). It is electrically connected to it.

[0291] Transistor 131_2, by being in an ON or OFF state, controls the data signal. It has a function to control the feeding process.

[0292] One of the pair of electrodes of the capacitive element 133_2 is connected to a wire to which a potential is supplied (hereinafter referred to as the potential supply line V). It is electrically connected to L_a, and the other side is the source electrode of transistor 131_2 and It is electrically connected to the other end of the drain electrode.

[0293] Capacitive element 133_2 functions as a retention capacitor that holds the written data.

[0294] One of the source and drain electrodes of transistor 134 is electrically connected to the potential supply line VL_a. They are connected to each other. Furthermore, the gate electrode of transistor 134 is connected to transistor 131_2 It is electrically connected to the source electrode and the other of the drain electrode.

[0295] One of the light-emitting element 135, either the anode or the cathode, is electrically connected to the potential supply line VL_b. The other end is electrically connected to the source electrode and drain electrode of transistor 134. It can be done.

[0296] For example, the light-emitting element 135 is an organic electroluminescent element (also known as an organic EL element). (u) and the like can be used. However, the light-emitting element 135 is not limited to this, Inorganic EL elements made of inorganic materials may also be used.

[0297] Furthermore, a high power supply potential VDD is supplied to one of the potential supply lines VL_a and VL_b. On the other hand, a low power supply potential VSS is applied.

[0298] In the display device having pixels 301 shown in Figure 9(C), the scan line driving circuit 404 drives the pixels of each row. Select 301 sequentially, turn on transistor 131_2, and write the data signal. To dig in.

[0299] The pixel 301 on which data has been written is maintained by the transistor 131_2 being turned off. It enters a holding state. Furthermore, the transistor 134 operates according to the potential of the written data signal. The amount of current flowing between the drain electrode and the light-emitting element 135 is controlled by the current flowing through it. It emits light with brightness corresponding to the amount of light. By doing this sequentially for each row, an image can be displayed.

[0300] Next, a specific example of a liquid crystal display device using a liquid crystal element in pixel 301 will be described. In Figure 10, a top view of pixel 301, shown in Figure 9(B), is presented. The counter electrode, liquid crystal element, and the first protective layers 314d and 314e are omitted.

[0301] In Figure 10, the conductive layer 304c, which functions as a scan line, is oriented in a direction approximately perpendicular to the signal line (Figure It is provided extending in the central left-right direction. The conductive layer 313d, which functions as a signal line, scans It is provided extending in a direction approximately perpendicular to the line (up and down in the diagram). It functions as a capacity line. The conductive layer 313f is provided extending in a direction parallel to the signal line. The conductive layer 304c is electrically connected to the scan line drive circuit 404 (see Figure 9(A)). It is configured to have a conductive layer 313d that functions as a signal line and a conductive layer 31 that functions as a capacitance line. 3f is electrically connected to the signal line drive circuit 406 (see Figure 9(A)).

[0302] Transistor 403 is located in the region where the scan line and signal line intersect. T403 is a conductive layer 304c that functions as a gate electrode, and a gate insulating film (shown in Figure 10) . ), semiconductor layer 308b in which a channel region is formed on the gate insulating film, It is composed of conductive layers 313d and 313e that function as a drain electrode and a drain electrode. Oh, the conductive layer 304c also functions as a scan line, and the region that overlaps with the semiconductor layer 308b is a trace. It functions as the gate electrode of the inverter 403. The conductive layer 313d also functions as a signal line. The region that functions and overlaps with semiconductor layer 308b is the source electrode or drain of transistor 403. It functions as an in electrode. Also, in Figure 10, the scanning line has a semicircular end in the top surface shape. It is located outside the edge of the conductor layer 308b. Therefore, the scan lines are located near light sources such as backlights. It functions as a light-shielding film that blocks light from entering. As a result, the semiconductor layer 30 contained in the transistor Since light is not irradiated onto 8b, fluctuations in the electrical characteristics of the transistor can be suppressed.

[0303] Furthermore, the conductive layer 313e has light-transmitting properties that allow it to function as a pixel electrode in the opening 362c. It is electrically connected to the conductive layer 320b.

[0304] The capacitive element 405 is connected to the conductive layer 313f, which functions as a capacitance line in the aperture 362. Furthermore, the capacitive element 405 has a conductive layer 30 formed on the gate insulating film. 8c, a light-transmitting conductive layer 320b that functions as a pixel electrode, and a transistor 403 It is composed of a dielectric film formed by a nitride insulating film provided on top. The conductive layer 308c formed therein is light-transmitting. That is, the capacitive element 405 is light-transmitting. It has a sexual nature.

[0305] Since the capacitive element 405 is light-transmitting, the capacitive element 405 can be placed larger within the pixel 301. It can be formed over a large area. Therefore, while increasing the opening ratio, typically 55% or less Preferably, it is possible to set it to 60% or more, and the semiconductor has increased charge capacity. A device can be obtained. For example, a high-resolution semiconductor device, such as a liquid crystal display device. Therefore, the pixel area becomes smaller, and the area of ​​the capacitive element also becomes smaller. In semiconductor devices, the charge capacitance stored in capacitive elements decreases. However, in reality Since the capacitive element 405 shown in the embodiment is light-transmitting, the capacitive element is provided in the pixel. This allows for obtaining sufficient charge capacitance in each pixel while increasing the aperture ratio. Typically, high-resolution semiconductor devices with a pixel density of 200 ppi or more, and even 300 ppi or more. It can be suitably used for the following purposes.

[0306] Furthermore, the pixel 301 shown in Figure 10 has sides parallel to the conductive layer 313d, which functions as a signal line, and ratio In comparison, the side parallel to the conductive layer 304c, which functions as a scan line, is longer, and the capacitance The conductive layer 313f, which functions as a line, is parallel to the conductive layer 313d, which functions as a signal line. It is extended and provided in this manner. As a result, the area of ​​the conductive layer 313f in the pixel 301 is reduced. Because this is possible, the aperture ratio can be increased. Furthermore, it functions as a capacitance line. Since the conductive layer 313f is in direct contact with the conductive layer 308c without using connecting electrodes, This allows for an increase in the aperture ratio.

[0307] Furthermore, one aspect of the present invention allows for an increase in the aperture ratio even in high-resolution display devices. Therefore, it is possible to efficiently utilize the light from light sources such as backlights, and the power consumption of the display device is reduced. This can be reduced.

[0308] Next, Figure 11 shows a cross-sectional view between the dashed lines C and D in Figure 10. The drive circuit section includes the scan line drive circuit 404 and the signal line drive circuit 406 (top view omitted). A cross-sectional view of the semiconductor device is shown at AB. In this embodiment, the semiconductor device has a display function. As an example, we will describe a liquid crystal display device using a longitudinal electric field method.

[0309] The display device shown in this embodiment has a liquid crystal element 3 between a pair of substrates (substrate 302 and substrate 342). 22 is being held in place.

[0310] The liquid crystal element 322 has a translucent conductive layer 320b above the substrate 302 and controls the orientation. A film (hereinafter referred to as alignment film 323, 352), a liquid crystal layer 321, and a conductive layer 350, It has. Furthermore, the light-transmitting conductive layer 320b is used as one electrode of the liquid crystal element 322. The conductive layer 350 functions as the other electrode of the liquid crystal element 322.

[0311] Thus, a liquid crystal display device refers to a device that has liquid crystal elements. The configuration includes a drive circuit for driving multiple pixels. Furthermore, the liquid crystal display device is mounted on a separate substrate. Includes the arranged control circuit, power supply circuit, signal generation circuit and backlight module, etc. It is sometimes called a crystal module.

[0312] In the drive circuit section, a conductive layer 304a functions as a gate electrode, and a gate insulating film is used. insulating film 305 and insulating film 306, semiconductor layer 308a in which a channel region is formed, Conductive layers 313a, 313b and a first protective layer 3, which function as a drain electrode and a drain electrode. 14a and 314b constitute transistor 402. Semiconductor layer 308a is gate insulating It is provided on the edge film. The upper surface of the conductive layers 313a and 313b is the second protective layer 312a and 31 2b is provided, and third protective layers 324a and 324b are provided on the sides. The protective layers 312a, 312b and / or the third protective layer 324a, 324b are light-transmitting. When formed with a conductive layer, the second protective layer 312a, 312b and / or the third protective layer 3 24a and 324b function as source and drain electrodes, and transistor 402 It constitutes.

[0313] In the pixel area, a conductive layer 304c functions as a gate electrode, and a gate insulating film functions as... Insulating films 305 and 306, and a channel region formed on the gate insulating film are formed A semiconductor layer 308b, conductive layers 313d and 31 that function as source and drain electrodes. The transistor 403 is formed by 3e and the first protective layers 314d and 314e. Layer 308b is provided on the gate insulating film. The upper surface of the conductive layers 313d and 313e is provided with a second A protective layer 312d, 312g is provided, and a third protective layer 324d, 324e is provided on the side. An insulating film 316 and an insulating film 318 are provided on the second protective layers 312d and 312g. It is provided as a protective layer. Furthermore, the second protective layer 312d, 312g and / or the third protective layer When protective layers 324d and 324e are formed of a light-transmitting conductive film, the second protective layer 312 d, 312g and / or the third protective layer 324d, 324e are the source electrode and drain electrode. It functions as such and also constitutes transistor 403.

[0314] Furthermore, a light-transmitting conductive layer 320b that functions as a pixel electrode is located on the second protective layer 312g. In the openings provided in the insulating film 316 and insulating film 318, the conductive layer 313e is connected. do.

[0315] Furthermore, one of the electrodes is a conductive layer 308c, and the dielectric film is an insulating layer. The edge film 318 and the translucent conductive layer 320b that functions as the other electrode form a capacitive element 4 It constitutes 05. The conductive layer 308c is provided on the gate insulating film.

[0316] Furthermore, in the drive circuit section, the conductive layer 304 is formed simultaneously with the conductive layers 304a and 304c. b and conductive layer 313 formed simultaneously with conductive layers 313a, 313b, 313d, and 313e c is a transparent conductive layer 320 that is formed simultaneously with the transparent conductive layer 320b. They are connected by 'a'.

[0317] The conductive layer 304b and the light-transmitting conductive layer 320a are in insulating film 306 and insulating film 316. The connection is made at the provided opening. Also, the conductive layer 313c and the light-transmitting conductive layer 32 0a is provided in the openings in the second protective layer 312f, the insulating film 316, and the insulating film 318. Connect them in place. Note that the sides of the conductive layer 313c are covered with a third protective layer 324c. .

[0318] The components of the display device shown in Figure 11 will be described below.

[0319] Conductive layers 304a, 304b, and 304c are formed on the substrate 302. 4a functions as the gate electrode of the transistor in the drive circuit section. Also, conductive layer 3 04c is formed in the pixel portion 401 and functions as the gate electrode of the transistor in the pixel portion. Furthermore, the conductive layer 304b is formed on the scan line drive circuit 404 and is connected to the conductive layer 313c. ru.

[0320] The substrate 302 can be made from the same material as the substrate 102 shown in Embodiment 1.

[0321] The conductive layers 304a, 304b, and 304c are the gate electrode 104 shown in Embodiment 1. Materials and manufacturing methods can be used as appropriate.

[0322] On the substrate 302 and the conductive layers 304a, 304c, and 304b, there is an insulating film 305 and an insulating film 3 06 is formed. Insulating film 305 and insulating film 306 are the gates of the transistor in the drive circuit section. It functions as a gate insulating film and as a gate insulating film for the transistor of the pixel section 401.

[0323] As the insulating film 305, the nitride insulating film described in the insulating film 106 shown in Embodiment 1 is used. It is preferable to form it in this way. The insulating film 306 is the insulating film 108 shown in Embodiment 1. It is preferable to form it using the oxide insulating film described above.

[0324] A semiconductor layer 308a, 308b, and a conductive layer 308c are formed on the insulating film 306. The semiconductor layer 308a is formed in a position where it overlaps with the conductive layer 304a, and the drive circuit section It functions as the channel region of the transistor. Also, the semiconductor layer 308b is the conductive layer 30 It is formed in a position that overlaps with 4c and functions as the channel region of the transistor in the pixel area. The conductive layer 308c functions as one electrode of the capacitive element 405.

[0325] The semiconductor layers 308a, 308b, and the conductive layer 308c are the semiconductor layers shown in Embodiment 1. The materials and manufacturing methods for the conductive layer 110 can be used as appropriate.

[0326] The conductive layer 308c is a layer having the same metallic elements as the semiconductor layers 308a and 308b. It is characterized by being and containing impurities. The impurity is hydrogen. Oh, instead of hydrogen, the impurities are boron, phosphorus, tin, antimony, noble gas elements, and aluminum. Potassium metals, alkaline earth metals, etc. may be included.

[0327] The semiconductor layers 308a, 308b, and the conductive layer 308c are all located on the gate insulating film. Although they are formed, their impurity concentrations are different. Specifically, compared with the semiconductor layers 308a and 308b the impurity concentration of the conductive layer 308c is high. For example, the hydrogen concentration contained in the semiconductor layers 308a and 308 b is less than 5×10 19 atoms / cm 3 preferably less than 5×10 1 8 atoms / cm 3 preferably less than 1×10 18 atoms / cm 3 or less, more preferably preferably less than 5×10 17 atoms / cm 3 preferably less than 1×10 16 atoms / cm 3 or less, and the hydrogen concentration contained in the conductive layer 308c is 8×10 19 a toms / cm 3 or more, preferably 1×10 20 atoms / cm 3 or more, more preferably is 5×10 20 atoms / cm 3 or more. Also, compared with the semiconductor layers 308a and 308b the hydrogen concentration contained in the conductive layer 308c is 2 times, preferably 10 times or more higher.

[0328] In addition, the conductive layer 308c has a lower resistivity than the semiconductor layers 308a and 308b. The resistivity of the conductive layer 308c is preferably 1×10 - 8 times or more and 1×10 -1 times or less, and typically 1×10 -3 Ωcm or more 1×10 4 Ωcm or less, more preferably, the resistivity is 1×10 -3 Ωcm or more and 1×10 - 1 It should be less than Ωcm.

[0329] The semiconductor layers 308a and 308b are interfaces with the semiconductor layer, such as the insulating film 306 and insulating film 316. Because it is in contact with a film formed of a material that can improve properties, semiconductor layer 308a 308b functions as a semiconductor, and the transistor has semiconductor layers 308a and 308b. It possesses excellent electrical properties.

[0330] On the other hand, the conductive layer 308c provides insulation at the opening 362 (see Figure 14(A)). It comes into contact with the film 318. The insulating film 318 is protected from external impurities, such as water, alkali metals, etc. A film formed of a material that prevents the diffusion of earth metals such as rutile into the semiconductor layer, and furthermore, water It contains elements. Therefore, hydrogen in the insulating film 318 is formed simultaneously with the semiconductor layers 308a and 308b. When hydrogen diffuses into a semiconductor layer, it combines with oxygen in the semiconductor layer, and the hydrogen acts as a carrier. A child is generated. In addition, the insulating film 318 is deposited by plasma CVD or sputtering. As a result, semiconductor layers 308a and 308b are exposed to the plasma, and oxygen vacancies are generated. When hydrogen contained in the insulating film 318 enters the oxygen vacancy, electrons, which act as carriers, are generated. As a result, the semiconductor layer becomes highly conductive, becoming a conductive layer 308c. The conductive layer 308c can also be described as a highly conductive oxide semiconductor layer. The layer 308c having this property can also be described as a highly conductive metal oxide film.

[0331] However, one embodiment of the present invention is not limited thereto, and the conductive layer 308c is In some cases, it is possible that it is not in contact with the insulating film 318.

[0332] Furthermore, one embodiment of the present invention is not limited thereto, and the conductive layer 308c is In some cases, the semiconductor layer 308a or 308b may be formed in a separate process. In that case, the conductive layer 308c is different from the semiconductor layers 308a and 308b. It may have a material. For example, the conductive layer 308c contains tungsten oxide. Indium oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide, indium tin oxide containing titanium oxide, indium tin oxide, indium It may also be formed using zinc oxide, indium tin oxide containing silicon oxide, etc.

[0333] The semiconductor device shown in this embodiment has a semiconductor layer of a transistor and one of the capacitive elements simultaneously. An electrode is formed. In addition, a light-transmitting conductive film that functions as a pixel electrode is formed on the capacitive element. It is used as the other electrode. For these purposes, a new conductive film is formed in order to create a capacitive element. This eliminates the need for a manufacturing process, thus reducing the manufacturing steps for semiconductor devices. Furthermore, the pair of electrodes are light-transmitting. Because it possesses light-transmitting properties, the capacitive element is light-transmitting. As a result, the occupied area of ​​the capacitive element can be increased. Furthermore, the aperture ratio of the pixels can be increased.

[0334] The first protective layers 314a, 314b, 314c, 314d, and 314e are shown in Embodiment 1. The materials and manufacturing methods for the first protective layers 112a and 112b can be used as appropriate.

[0335] The conductive layers 313a, 313b, 313c, 313d, and 313e are a pair as shown in Embodiment 1. Suitable materials and manufacturing methods for the conductive layers 114a and 114b that constitute electrodes 116a and 116b. It can be used as appropriate.

[0336] The second protective layers 312a, 312b, 312f, 312d, and 312g are shown in Embodiment 1. The materials and manufacturing methods for the second protective layers 118a and 118b can be used as appropriate.

[0337] The third protective layers 324a, 324b, 324c, 324d, and 324e are shown in Embodiment 1. The materials and manufacturing methods for the third protective layers 120a and 120b can be used as appropriate.

[0338] insulating film 306, semiconductor layers 308a, 308b, conductive layer 308c, first protective layer 314a, 314b, 314c, 314d, 314e, conductive layer 313a, 313b, 31 3c, 313d, 313e, second protective layer 312a, 312b, 312f, 312d, 3 12g, and on the third protective layers 324a, 324b, 324c, 324d, 324e, Insulating films 316 and 318 are formed. Insulating film 316 is formed in the same way as insulating film 306. By using a material that can improve the interfacial properties with semiconductor layers 308a and 308b. Preferably, the same materials and manufacturing methods as those used for the oxide insulating film shown in at least Embodiment 1 are suitable. It can be used as appropriate.

[0339] The insulating film 318, like the insulating film 305, is protected from external impurities, such as water and alkali metals. It is preferable to use a material that prevents alkaline earth metals, etc., from diffusing into the semiconductor layer, and nitrogen Nitrided insulating materials such as silicon oxide, silicon nitride, aluminum nitride, and aluminum nitride. A film can be used as appropriate. The thickness of the insulating film 318 is preferably 30 nm to 200 nm. The minimum wavelength shall be between 50 nm and 150 nm. The insulating film 318 shall be coated by sputtering, CV It can be formed using method D or other appropriate methods.

[0340] Furthermore, transparent conductive layers 320a and 320b are formed on the insulating film 318. The light-transmitting conductive layer 320a conducts through the opening 364a (see Figure 15(A)). Electrically connected to layer 313a, the conductive layer at the opening 364b (see Figure 15(A)) It is electrically connected to 313c. That is, it is a connection that connects conductive layer 304a and conductive layer 313c. It functions as a follow-up electrode. The light-transmitting conductive layer 320b has an opening 364c (Figure 15(A). (See reference.) It is electrically connected to the conductive layer 313e in ) and functions as a pixel electrode of the pixel. It has. In addition, the light-transmitting conductive layer 320b is used as one of the pair of electrodes of the capacitive element. It is possible.

[0341] In order to create a connection structure in which conductive layer 304a and conductive layer 313c are in direct contact, conductive layer 31 Before forming 3c, patterning is used to form openings in insulating film 305 and insulating film 306. It is necessary to perform a test and form a mask, but the connection structure in Figure 11 shows that the photomask It is unnecessary. However, as shown in Figure 11, the transparent conductive layer 320a provides a conductive layer. By connecting the conductive layer 304a and the conductive layer 313c, the conductive layer 304a and the conductive layer 313c This eliminates the need to create a connection point where the parts directly touch, allowing for one less photomask. This means that it is possible to reduce the manufacturing process for semiconductor devices.

[0342] The light-transmitting conductive layers 320a and 320b are indium containing tungsten oxide. Indium zinc oxide containing oxides, tungsten oxide, and indium acid containing titanium oxide Indium tin oxide containing titanium oxide, ITO, indium zinc oxide, silicon oxide A light-transmitting conductive material such as indium tin oxide containing condensate can be used.

[0343] Furthermore, a colored film (hereinafter referred to as the colored film 346) is formed on the substrate 342. The colored film 346 functions as a color filter. An adjacent light-shielding film 344 is formed on the substrate 342. The light-shielding film 344 is a black matrix It functions as a display device. Also, the colored film 346 is not necessarily required to be provided; for example, it can be used as a display device. In cases where the image is black and white, for example, the colored film 346 may be omitted.

[0344] The colored film 346 can be any colored film that transmits light in a specific wavelength range, for example, red A red (R) color filter that transmits light in the wavelength range of the color, and a green color filter that transmits light in the wavelength range of the color A green (G) color filter that transmits light in the blue wavelength range, and a blue (B) color filter that transmits light in the blue wavelength range. Ruta and similar items can be used.

[0345] The light-shielding film 344 only needs to have the function of blocking light in a specific wavelength band, and is a metal film. Alternatively, an organic insulating film containing a black pigment or the like can be used.

[0346] Furthermore, an insulating film 348 is formed on the colored film 346. The insulating film 348 is a planarization layer. It functions as a filter, or it suppresses the diffusion of impurities that the colored film 346 may contain to the liquid crystal element. It has the function of doing so.

[0347] Furthermore, a conductive layer 350 is formed on the insulating film 348. The conductive layer 350 is formed on the pixel portion It functions as the other electrode of the pair of electrodes that make up the liquid crystal element. Furthermore, it has a light-transmitting conductive layer. An insulating film having the function of an alignment film is separately applied to 320a, 320b, and the conductive layer 350. A path may be formed.

[0348] Furthermore, between the light-transmitting conductive layers 320a and 320b and the conductive layer 350, there is a liquid crystal layer 32 1 is formed. The liquid crystal layer 321 is also formed on the substrate 30 using a sealing material (not shown). It is sealed between 2 and substrate 342. The sealing material prevents moisture and other substances from entering from the outside. To suppress this, a configuration in which the material comes into contact with an inorganic material is preferred.

[0349] Furthermore, a liquid crystal layer 321 is placed between the light-transmitting conductive layers 320a and 320b and the conductive layer 350. Spacers may be provided to maintain the thickness (also called the cell gap).

[0350] The method for fabricating the element portion provided on the substrate 302 shown in Figure 11 of the semiconductor device is described in Figure This will be explained using Figures 12 through 15.

[0351] First, prepare the substrate 302. Here, a glass substrate is used as the substrate 302.

[0352] Next, a conductive film is formed on the substrate 302, and the conductive film is processed into a desired shape to form a conductive layer Form 304a, 304b, and 304c. Note that conductive layers 304a, 304b, and 304c The formation involves creating a mask by first patterning in the desired region, and covering the mask It can be formed by etching the areas that have not been etched (see Figure 12(A)).

[0353] Furthermore, the conductive layers 304a, 304b, and 304c are typically produced by vapor deposition, CVD, etc. It can be formed using methods such as sputtering and spin coating.

[0354] Next, an insulating film 305 is formed on the substrate 302 and the conductive layers 304a, 304b, and 304c. Then, an insulating film 306 is formed on the insulating film 305 (see Figure 12(A)).

[0355] The insulating film 305 and insulating film 306 can be formed by sputtering, CVD, or the like. Yes, it is possible. Note that if insulating film 305 and insulating film 306 are formed continuously in a vacuum, impurities will be present. Contamination is suppressed, which is desirable.

[0356] Next, a semiconductor film 307 is formed on the insulating film 306 (see Figure 12(B)).

[0357] The semiconductor film 307 was produced by sputtering, coating, pulsed laser deposition, and laser abrasion. It can be formed using methods such as the ionization method.

[0358] Next, the semiconductor film 307 is processed into a desired shape to form island-shaped semiconductor layers 308a, 308 Form b and 308d. Note that the formation of semiconductor layers 308a, 308b, and 308d is optional. A second patterning mask is formed in the region, and the region not covered by the mask It can be formed by etching. Dry etching is one method of etching. Wet etching, or etching combining both methods, can be used (Figure) 12(C)).

[0359] Next, a first heat treatment may be performed. The first heat treatment is the first heating shown in Embodiment 1. The same conditions as for the heat treatment are used. The first heat treatment removes the insulating film 306 and the semiconductor layer 3 Impurities such as hydrogen and water can be removed from 08a, 308b, and 308d. A first heat treatment may be performed before etching the semiconductor film.

[0360] Next, a first protective film 3 is applied to the insulating film 306 and the semiconductor layers 308a, 308b, and 308d. 09, the conductive film 310, and the second protective film 311 are formed in order (see Figure 13(A)).

[0361] The first protective film 309 and the conductive film 310 are formed, for example, by sputtering. This can be done. Also, as the second protective film 311, for example, CVD method, sputtering It can be formed using methods such as the shaping method.

[0362] Next, the second protective film 311 is processed into a desired shape, thereby forming the second protective layers 312a, 31 Forms 2b, 312c, 312d, and 312e. Note that the second protective layer 312a, 312 The formation of b, 312c, 312d, and 312e is achieved by a third patterning in the desired region. The mask is formed by creating a screen and etching the areas not covered by the mask. This can be done. After this, remove the mask (see Figure 13(B)).

[0363] Next, the conductive film 310 is processed into the desired shape, thereby creating conductive layers 313a, 313b, 313 c, 313d, and 313e are formed. Note that here, the second protective layers 312a and 312b 312c, 312d, and 312e are used as masks, and areas not covered by the masks It can be formed by etching the area.

[0364] Next, so as to cover the sides of the conductive layers 313a, 313b, 313c, 313d, and 313e A third protective film is placed on top of the second protective layers 312a, 312b, 312c, 312d, and 312e. A third protective film and the first protective film 309 are formed (not shown) by anisotropic etching. Processed to create the third protective layer 324a, 324b, 324c, 324d, 324e and the first These form protective layers 314a, 314b, 314c, 314d, and 314e (Figure 13(C)). (See reference). Note that the anisotropic etching here results in the second protective layers 312a, 312b, The surfaces of 312c, 312d, and 312e are also etched simultaneously, resulting in a reduced film thickness.

[0365] The third protective film can be formed using methods such as CVD or sputtering. .

[0366] Next, insulating film 306, semiconductor layers 308a, 308b, 308d, first protective layer 314a, 314b, 314c, 314d, 314e, conductive layer 313a, 313b, 313c, 31 3d, 313e, second protective layer 312a, 312b, 312c, 312d, 312e, and And covering the third protective layers 324a, 324b, 324c, 324d, and 324e, A border film 315 is formed (see Figure 14(A)).

[0367] As the insulating film 315, the same configuration as the insulating film 122 shown in Embodiment 1 is applied, and an oxide An insulating film can preferably be applied.

[0368] Next, by processing the insulating film 315 into the desired shape, the insulating film 316 and the opening 362 are formed. Formed. Note that the formation of the insulating film 315 and the opening 362 is performed by forming a fourth pattern in the desired region. Form a mask by etching, and etch the areas not covered by the mask. And it can be formed (see Figure 14(B)).

[0369] Furthermore, the opening 362 is formed so that the surface of the semiconductor layer 308d is exposed. As a method for forming 2, for example, a dry etching method can be used. However, The method for forming the opening 362 is not limited to this, and may include wet etching or dry etching. A formation method combining the etching method and the wet etching method may also be used.

[0370] A second heat treatment may be performed after this. A portion of the oxygen contained in the insulating film 315 is absorbed into the semiconductor layer. Move to 308a and 308b to reduce oxygen vacancies in semiconductor layers 308a and 308b. This makes it possible to determine the amount of oxygen vacancies contained in semiconductor layers 308a and 308b. It can be reduced.

[0371] Next, an insulating film 317 is formed on the insulating film 316 and the semiconductor layer 308d (see Figure 14(C)). (see).

[0372] The insulating film 317 is designed to block external impurities, such as oxygen, hydrogen, water, alkali metals, etc. It is preferable to use a material that prevents the diffusion of earth metals such as rutile into the multilayer film, and furthermore, water It is preferable that the material contains an element, and typically an inorganic insulating material containing nitrogen, such as a nitride insulating film, is used. It is possible to use methods such as CVD or sputtering as the insulating film 317. It can be formed by doing so.

[0373] When the insulating film 317 is formed using CVD, sputtering, etc., the semiconductor layer 308d When exposed to plasma, oxygen vacancies are generated in the semiconductor layer 308d. Also, the insulating film 317 External impurities, such as water, alkali metals, and alkaline earth metals, can spread into the semiconductor layer. It is a film formed of a material that prevents dispersion, and furthermore, it contains hydrogen. For these reasons, insulating film 3 When 17 hydrogen atoms diffuse into the semiconductor layer 308d, the hydrogen atoms in the semiconductor layer 308d become oxygen-deficient. It combines with loss, generating electrons, which are carriers. Alternatively, hydrogen in the insulating film 317 becomes part of the semiconductor layer. When it diffuses into 308d, hydrogen combines with oxygen in the semiconductor layer 308d and becomes a carrier. Electrons are generated. As a result, the semiconductor layer 308d becomes highly conductive and possesses conductivity. This becomes layer 308c.

[0374] Furthermore, the insulating film 317 is preferably formed at a high temperature in order to enhance its blocking properties. For example, the substrate temperature should be 100°C or higher and below the substrate's strain point, more preferably 300°C or higher and 400°C or higher. It is preferable to heat and deposit the film at the following temperature. Also, when depositing the film at a high temperature, the semiconductor layer 30 Oxygen may be released from 8a and 308b, causing an increase in carrier concentration. Therefore, the temperature should be set so that this phenomenon does not occur.

[0375] Furthermore, before forming the insulating film 317, the semiconductor layer 308d was subjected to a plasma containing a rare gas and hydrogen. Exposure creates oxygen vacancies in the semiconductor layer 308d, and hydrogen vacancies are formed in the semiconductor layer 308d. It is possible to add this. As a result, electrons, which are carriers in the semiconductor layer 308d It is possible to further increase this and further enhance the conductivity of the conductive layer 308c. It is possible.

[0376] Next, the insulating film 317 and the second protective layers 312c and 312e are processed into the desired shape. Insulating film 318, second protective layers 312f, 312g, and openings 364a, 364b, 36 4c is formed. Note that the insulating film 318 and the openings 364a, 364b, and 364c are A fifth patterning mask is formed in the desired region, and the region not covered by the mask is... It can be formed by etching the area (see Figure 15(A)). Also, the second retain When protective layers 312c and 312e are formed of a transparent conductive film, in the process, It is not necessary to etch the protective layers 312c and 312e of layer 2.

[0377] Furthermore, the opening 364a is formed so that the surface of the conductive layer 304a is exposed. The portion 364b is formed so that the conductive layer 313c is exposed. The opening 364c is also a conductive Formed so that the electrode layer 313e is exposed.

[0378] For example, dry etching is used to form the openings 364a, 364b, and 364c. A forming method can be used. However, the method for forming openings 364a, 364b, and 364c is not specified. This includes, but is not limited to, wet etching methods, or dry etching methods and wet etching methods. A formation method combining a etching method may also be used.

[0379] Next, a conductive film 319 is applied to the insulating film 318 so as to cover the openings 364a, 364b, and 364c. It forms (see Figure 15(B)).

[0380] The conductive film 319 can be formed, for example, by sputtering.

[0381] Next, the conductive film 319 is processed into a desired shape to form light-transmitting conductive layers 320a, 3 Form 20b. Note that the formation of the light-transmitting conductive layers 320a and 320b is done in the desired region. A mask is formed in the region by a sixth patterning, and the region not covered by the mask is... It can be formed by cutting (see Figure 15(C)).

[0382] In the above steps, a pixel section having a transistor and a drive circuit section are formed on the substrate 302. This is possible. In addition, in the manufacturing process shown in this embodiment, the first to sixth patterns This means that transistors and capacitive elements can be formed simultaneously using six masks. ru.

[0383] In this embodiment, hydrogen contained in the insulating film 318 is diffused into the semiconductor layer 308d. The conductivity of semiconductor layer 308d was increased, but semiconductor layers 308a and 308b were covered with a mask. Impurities in semiconductor layer 308d include, typically, hydrogen, boron, phosphorus, tin, antimony, and rare gases. By adding elements such as alkali metals and alkaline earth metals, the conductivity of the semiconductor layer 308d is increased. It may be added. Hydrogen, boron, phosphorus, tin, antimony, noble gas elements, etc. in the semiconductor layer 308d Methods for adding it include ion doping and ion implantation. On the other hand, the semiconductor layer A method for adding alkali metals, alkaline earth metals, etc. to 308d includes the impurities... One method involves coating the semiconductor layer 308d with the solution.

[0384] Next, regarding the structure formed on the substrate 342 which is provided opposite the substrate 302, the following explanation will be given. To perform the task.

[0385] First, prepare substrate 342. The material used for substrate 342 is the same as that used for substrate 302. This can be done. Next, a light-shielding film 344 and a colored film 346 are formed on the substrate 342 (Figure 16(A )reference).

[0386] The light-shielding film 344 and the colored film 346 are produced using various materials by printing, inkjet, and other methods. These are formed at the desired locations using etching methods such as photolithography.

[0387] Next, an insulating film 348 is formed on the light-shielding film 344 and the colored film 346 (see Figure 16(B)). ).

[0388] Examples of insulating film 348 include organic insulating films such as acrylic resin, epoxy resin, and polyimide. This can be used. By forming an insulating film 348, for example, in the colored film 346 This can suppress the diffusion of impurities and other substances contained in the liquid crystal layer 321. The insulating film 348 is not necessarily required, and the structure may be configured without the insulating film 348. stomach.

[0389] Next, a conductive layer 350 is formed on the insulating film 348 (see Figure 16(C)). The conductive layer 350 and Therefore, the material shown in conductive film 319 can be used.

[0390] The structure to be formed on the substrate 342 can be created through the above process.

[0391] Next, the insulating film 318 formed on substrate 302 and substrate 342, more specifically on substrate 302. , transparent conductive layers 320a, 320b and conductive layer 350 formed on substrate 342 On top of that, alignment film 323 and alignment film 352 are formed respectively. It can be formed using methods such as rubbing and photo-alignment. After that, the substrate 302 and the substrate A liquid crystal layer 321 is formed between 342 and 342. The method for forming the liquid crystal layer 321 is to dispense The method involves either the drop method or bonding substrates 302 and 342 together and then using capillary action to apply liquid. An injection method can be used to inject crystals.

[0392] By following the above steps, the display device shown in Figure 11 can be manufactured.

[0393] This embodiment can be appropriately combined with other embodiments shown herein. .

[0394] (Embodiment 6) In this embodiment, regarding an electronic device capable of mounting a semiconductor device according to one aspect of the present invention, I will explain.

[0395] An electronic device to which a semiconductor device according to one aspect of the present invention is applied is, for example, a television apparatus (Te TVs (also called television receivers), monitors for computers, digital cameras, etc. Cameras, digital video cameras, digital photo frames, mobile phones (mobile phones, portable phones) Large devices such as (also called communication devices), portable game consoles, portable information terminals, sound playback devices, and pachinko machines. Examples include game consoles. Specific examples of these electronic devices are shown in Figure 17.

[0396] Figure 17(A) shows an example of a television system. The television system 7100 is, The display unit 7103 is integrated into the housing 7101. The display unit 7103 displays video. It is possible to do this, and the semiconductor device can be used in the display unit 7103. The diagram shows a configuration in which the stand 7105 supports the chassis 7101.

[0397] The television unit 7100 is operated using the control switches on the housing 7101 and a separate remote control. This can be done using the remote controller 7110. The control keys 7109 allow you to operate the channel and volume, and the display unit 710 The image displayed in 3 can be controlled. Also, the remote controller 7110 can be used to control the image. The configuration includes a display unit 7107 that displays information output from the remote controller. That's fine.

[0398] The television system 7100 will consist of a receiver, modem, and other components. It can receive more general television broadcasts, and furthermore, it can connect via a modem, either wired or wirelessly. By connecting to the communication network, one-way (sender to receiver) or two-way communication is possible. It is also possible to communicate information (between a sender and a receiver, or between receivers, etc.).

[0399] Figure 17(B) is a computer, consisting of the main unit 7201, the casing 7202, the display unit 7203, and a key - Includes board 7204, external connection port 7205, pointing device 7206, etc. Furthermore, the computer was manufactured by using a semiconductor device, for example, in the display unit 7203. It can be done.

[0400] Figure 17(C) shows a portable gaming machine, which consists of two cabinets, cabinet 7301 and cabinet 7302. It is connected by a connecting part 7303 so that it can be opened and closed. The housing 7301 has a display unit The 7304 is incorporated, and the display unit 7305 is incorporated into the housing 7302. The portable gaming machine shown in 17(C) also includes a speaker section 7306 and a recording medium insertion section 730. 7. LED lamp 7308, input means (operation key 7309, connection terminal 7310, sensor 7 311 (force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, Chemical substances, sound, time, hardness, electric field, electric current, voltage, power, radiation, flow rate, humidity, gradient, vibration Equipped with functions to measure motion, odor, or infrared radiation, microphones (7312), etc. Of course, the configuration of portable gaming machines is not limited to those described above, and at least the display unit It is sufficient to use a display device in both or either of 7304 and the display unit 7305, Other auxiliary equipment may be provided as appropriate. (Figure 17(C) shows a portable gaming machine.) This device reads programs or data recorded on a recording medium and displays them on a display unit. It also has the ability to communicate wirelessly with other portable gaming machines and share information. (See Figure 17) The functions of the portable gaming machine shown in (C) are not limited to those shown, and it may have a variety of functions. can.

[0401] Figure 17(D) shows an example of a mobile phone. Mobile phone 7400 has a housing 7401 In addition to the display unit 7402 incorporated into it, there are operation buttons 7403, an external connection port 7404, and It is equipped with a speaker 7405, a microphone 7406, etc. The mobile phone 7400 is semiconductor It is manufactured by using the body device as the display unit 7402.

[0402] The mobile phone 7400 shown in Figure 17(D) allows information to be conveyed by touching the display unit 7402 with a finger or the like. You can enter information. You can also perform operations such as making phone calls or composing emails. This can be done by touching the display unit 7402 with a finger or the like.

[0403] The display unit 7402 has three main modes. The first is a display that primarily displays images. The first mode is display mode, the second is input mode which is mainly for inputting information such as characters. The third is display mode. This is a display + input mode, which is a combination of two modes: display mode and input mode.

[0404] For example, when making a phone call or composing an email, the display unit 7402 is used for text input. In this case, the primary text input mode should be used, and you should perform the input operation for the characters displayed on the screen. It is preferable to display a keyboard or number buttons on most of the screen of the display unit 7402. It seems so.

[0405] Furthermore, the 7400 mobile phone has internal sensors that detect tilt, such as a gyroscope and an accelerometer. By providing a detection device, the orientation (vertical or horizontal) of the mobile phone 7400 can be determined, and the display The display on the display unit 7402 can be automatically switched.

[0406] Furthermore, the screen mode can be switched by touching the display unit 7402 or by operating the housing 7401. This is done by operating the action button 7403. Also, the type of image displayed on the display unit 7402 It can also be configured to switch between modes. For example, if the image signal displayed on the display unit is a video If the data is in a specific format, it switches to display mode; if it's text data, it switches to input mode.

[0407] Furthermore, in input mode, the signal detected by the optical sensor of the display unit 7402 is detected and displayed If there is no input via touch operation on unit 7402 for a certain period of time, the screen mode will be changed to input mode. You may also control the system to switch from that display mode to a different mode.

[0408] The display unit 7402 can also function as an image sensor. For example, the display unit 74 By touching device 02 with the palm or fingers, the user can be authenticated by capturing images of their palm print, fingerprints, etc. Furthermore, the display unit may have a backlight that emits near-infrared light or a sensing light that emits near-infrared light. Using the appropriate source, it is also possible to image finger veins, palmar veins, and other veins.

[0409] Figure 17(E) shows an example of a foldable computer. The Pewter 7450 consists of housings 7451L and 7451R connected by hinge 7454. It is equipped with the control button 7453, the left speaker 7455L and the right speaker 74 In addition to 55R, there is an external connection port 7456 on the side of the computer 7450, which is not shown in the illustration. It is equipped with a display unit 7452L provided in the housing 7451L and a display unit 7452L provided in the housing 7451R. When the hinge 7454 is folded so that the raised display units 7452R face each other, the display unit The enclosure can protect it.

[0410] Display units 7452L and 7452R not only display images, but also input information when touched with a finger or other object. You can do this. For example, you can select an installed program by touching its icon with your finger. You can launch the program. Alternatively, change the distance between your fingers touching two points on the displayed image. You can zoom in or out of the image. Alternatively, you can move your finger that is touching a part of the displayed image to zoom in or out. The image can be moved. Additionally, a keyboard image can be displayed, allowing you to touch the displayed characters and symbols with your finger. You can also select and enter information.

[0411] Furthermore, the 7450 computer is equipped with a gyroscope, accelerometer, and GPS (Global Power Point). (Stationing System) Equipped with a receiver, fingerprint sensor, and video camera. It is also possible. For example, a detection device having a sensor that detects tilt, such as a gyroscope or accelerometer. By providing this, the orientation of the computer 7450 (portrait or landscape) is determined, and the screen to be displayed is... It can be configured to automatically switch orientations.

[0412] Furthermore, the computer 7450 can connect to a network. In addition to displaying information on the network, it can also remotely access other electronic devices connected to the network. It can be used as a terminal for operation.

[0413] This embodiment can be appropriately combined with other embodiments shown herein. . [Examples]

[0414] In this embodiment, the manufacturing method shown in Embodiment 1 is used to produce a first protective layer, a second protective layer and An example of a conductive layer covered with a third protective layer is shown.

[0415] In this embodiment, the semiconductor material provided on the substrate is formed by the process shown in Figures 2(C) to 3(C). On the body membrane, there is an electrode consisting of a first protective layer and a conductive layer, and a second protective layer covering the upper surface of the conductive layer. The second protective layer and the side surface of the conductive layer, and the upper surface of the first protective layer exposed from the conductive layer, are covered by the second protective layer. A protective layer (3) and [another material] were fabricated. The details of the method for fabricating the sample in this example are shown below.

[0416] First, a 100 nm thick In-Ga-Zn oxide film is formed on the substrate as a semiconductor film. The In-Ga-Zn oxide film was oxidized in an In:Ga:Zn=1:1:1 [atomic ratio] manner. The film was formed by sputtering using a material target. The deposition conditions were an oxygen partial pressure of 50%. Under ambient conditions, with a pressure of 0.6 Pa, a power supply (AC) of 2.5 kW, and a substrate temperature of 170°C, the experiment was conducted.

[0417] Next, a 35 nm thick titanium film was formed as the first protective layer using the sputtering method. The film deposition conditions were: argon atmosphere (flow rate 100 sccm), pressure 0.3 Pa, power supply (D C) The power consumption was set to 58kW and the substrate temperature to 100°C.

[0418] A copper film with a thickness of 200 nm was formed on the first protective film as a conductive film by sputtering. The film deposition conditions were: argon atmosphere (flow rate 150 sccm), pressure 0.9 Pa, power supply ( The power consumption was set to 20kW (DC) and the substrate temperature to 80°C.

[0419] Subsequently, a silicon nitride film was formed on the conductive film as a second protective film using the CVD method. Silicon film deposition was performed under a pressure of 200 Pa and a power supply of 1000 W, with silicone as the supply gas. N (flow rate 50 sccm), nitrogen (flow rate 5000 sccm), ammonia (flow rate 100 sccm) A mixed gas of (cm) was used.

[0420] Similar to the process in Figure 2(D), a resist mask is formed on the second protective film, and the resist mask A portion of the second protective film was selectively etched using a tool to form a second protective layer. Figure 3 Similar to step (A), the second protective layer is used as a mask to selectively remove a portion of the conductive copper film. Etching of the conductive film Wet etching was used for the etched pattern.

[0421] Figure 18(A1), Figure 18 shows a cross-sectional photograph of the sample obtained by the steps taken so far in this embodiment. (A2) is shown.

[0422] Note that the cross-sectional images shown in Figures 18(A1) to 18(C2) were obtained using a scanning transmission electron microscope (Sc anning Transmission Electron Microscope; These are STEM images taken by STEM. Also, see Figures 18(A1) and 18(B1). Figure 18(C1) is a phase contrast image (TE image), and Figure 18(A2) is a phase contrast image (TE image). 1) is the Z-contrast image (ZC image), and Figure 18(B2) is the Z-contrast image of Figure 18(B1) This is the last image (ZC image), and Figure 18(C2) is the Z-contrast image (ZC) of Figure 18(C1). It is a statue.

[0423] As shown in Figure 18(A2), a second protective layer is provided on the copper layer provided as a conductive layer. The thickness of the silicon nitride layer is 198 nm, and the distance between the side surface of the copper layer and the side surface of the silicon nitride layer The wavelength was confirmed to be 217 nm.

[0424] Next, similar to the process in Figure 3(B), the upper surface of the first protective film, the side surface of the conductive layer and the second protective film A silicon nitride film was formed by CVD as a third protective film covering the top and sides of the layer. The silicon dioxide film deposition was carried out under a pressure of 200 Pa and a power supply of 1000 W, with the supplied gas being silicon. Lan (flow rate 50 sccm), Nitrogen (flow rate 5000 sccm), Ammonia (flow rate 100 s) A mixed gas of ccm was used.

[0425] Figure 18 shows a cross-sectional photograph of the sample in this embodiment after the formation of the silicon nitride film used as the third protective layer. (B1) is shown in Figure 18(B2).

[0426] In this embodiment, silicon nitride was used as the second and third protective films under the same deposition conditions. In order to form a film, the interface between the two layers is not clearly defined in Figures 18(B1) and 18(B2). However, in Figure 18(B2), the silicon nitride layer (second) provided on the copper layer The thickness of the protective layer and the third protective film is 288 nm, and it is located on the side of the copper layer and the side of the silicon nitride layer. Since the distance from the surface is 266 nm, by comparison with Figure 18(A2), the conductive layer is The third layer is provided to cover the sides of the copper layer and the sides and top of the second protective layer, with good coverage. It was confirmed that a protective film had been formed.

[0427] Next, the first protective film and the third protective film are anisotropically etched, similar to the process in Figure 3(C). The first and third protective layers were formed by self-aligned etching.

[0428] Etching here is done using ICP (Inductively Coupled Plasma). a: Dry etching using an inductively coupled plasma etching method was applied. The conditions are: a mixed gas of boron trichloride and chlorine (BCl3:Cl2=75) as the etching gas. Using 0 sccm:150 sccm, power supply power 0W, bias power 1500W, pressure 2 The etching process was performed for 270 seconds with a pressure of 0 Pa and a lower electrode temperature of 20°C. The etching rate for the titanium film used as the first protective layer is 86.1 nm / min. For the silicon nitride film used as the third protective layer, the density was 31.4 nm / min.

[0429] Cross-sectional photographs of the sample obtained in this embodiment are shown in Figures 18(C1) and 18(C2).

[0430] From Figures 18(C1) and 18(C2), the sides and top surface of the copper layer used as the conductive layer are covered. A silicon nitride layer is formed to be used as the second and third protective layers, and the lower surface of the copper layer An electrode structure according to one aspect of the present invention is obtained, wherein a titanium layer used as a first protective layer is formed thereon. It was confirmed that this had been done. The upper surface of the titanium layer exposed from the copper layer was covered by the silicon nitride layer. It is covered.

[0431] In Figure 18(C2), a silicon nitride layer (second protective layer and third protective layer) is provided on the copper layer. The thickness of the protective layer is 129 nm, and the distance between the side of the copper layer and the side of the silicon nitride layer is 260 It was in nm.

[0432] The electrode structure of this embodiment described above is suitable as a pair of electrodes in contact with the semiconductor layer of a transistor. By using this method, it is possible to form highly reliable transistors. [Explanation of symbols]

[0433] 50 areas 52 Opening 102 circuit boards 105 Oxide semiconductor layer 104 Guard gate 104a Shut-off gate 104b Guard gate 106 Insulating film 107 Oxide semiconductor layer 108 Insulating Film 10⁹ Oxide semiconductor layer 110 Semiconductor layer 112 Protective film 112a Protective layer 112b Protective layer 113 Protective film 113a Protective layer 113b Protective layer 114 Conductive film 114a conductive layer 114b Conductive layer 115a Mask 115b Mask 116a electrode 116b Electrode 118a Protective layer 118b Protective layer 120 Protective film 120a protective layer 120b protective layer 122 Insulating film 124 Insulating film 126 Gate 131_1 Transistor 131_2 Transistor 132 liquid crystal elements 133_1 Capacitive element 133_2 Capacitive element 134 transistors 135 Light-emitting element 200 transistors 210 transistors 220 transistors 230 transistors 301 pixels 302 circuit board 304a conductive layer 304b conductive layer 304c conductive layer 305 Insulating film 306 Insulating Film 307 Semiconductor film 308a Semiconductor layer 308b Semiconductor layer 308c layer 308d semiconductor layer 309 Protective film 310 Conductive film 311 Protective film 312a protective layer 312b Protective layer 312c protective layer 312d protective layer 312e protective layer 312f protective layer 312g protective layer 313a conductive layer 313b Conductive layer 313c conductive layer 313d conductive layer 313e conductive layer 313f conductive layer 314a protective layer 314b protective layer 314c protective layer 314d protective layer 314e protective layer 315 Insulating film 316 Insulating film 317 Insulating Film 318 Insulating film 319 Conductive film 320a conductive layer 320b conductive layer 321 Liquid crystal layer 322 liquid crystal elements 323 Orientation film 324a protective layer 324b protective layer 324c protective layer 324d protective layer 324e protective layer 342 circuit boards 344 Light-shielding film 346 Colored film 348 Insulating film 350 conductive layer 352 Alignment film 362 Opening 362c opening 364a opening 364b opening 364c opening 401 pixel section 402 transistors 403 Transistors 404 Scan Line Drive Circuit 405 Capacitive element 406 Signal Line Drive Circuit 407 scan lines 409 signal line 415 Capacity Line 7100 Television equipment 7101 enclosure 7103 Display section 7105 Stand 7107 Display section 7109 Operation Keys 7110 Remote Controller 7201 Main Unit 7202 enclosure 7203 Display section 7204 Keyboard 7205 External connection port 7206 Pointing device 7301 enclosure 7302 enclosure 7303 Connection section 7304 Display section 7305 Display section 7306 Speaker section 7307 Recording media insertion section 7308 LED Lamp 7309 Operation Keys 7310 Connection terminal 7311 Sensor 7312 Microphone 7400 mobile phones 7401 enclosure 7402 Display section 7403 Operation Buttons 7404 External connection port 7405 Speaker 7406 Microphone 7450 Computer 7451L enclosure 7451R cabinet 7452L Display section 7452R Display section 7453 Operation Buttons 7454 Hinge 7455L Left speaker 7455R Right speaker 7456 External connection port

Claims

1. A display device having a plurality of pixels, each having a transistor and a capacitive element electrically connected to the transistor, A first conductive layer having the function of a gate electrode of the transistor, A first insulating film having a region located above the first conductive layer and having silicon nitride, A second insulating film having a region located above the first insulating film and containing silicon oxide, An oxide semiconductor film having a region in contact with the upper surface of the second insulating film and having a channel formation region for the transistor, A second conductive layer having a region in contact with the upper surface of the second insulating film and functioning as an electrode of the capacitive element, A third conductive layer having a region in contact with the upper surface of the oxide semiconductor film and functioning as one of the source and drain electrodes of the transistor, A third insulating film having silicon oxide and having a region in contact with the upper surface of the oxide semiconductor film, a region in contact with the upper surface of the second conductive layer, and a region in contact with the upper surface of the third conductive layer, A fourth insulating film having silicon nitride and having a region located above the third insulating film and a region in contact with the upper surface of the second conductive layer, The fourth conductive layer has a region located above the second conductive layer via the fourth insulating film and functions as a pixel electrode, The third conductive layer has a laminated structure comprising a first film having a region in contact with the upper surface of the oxide semiconductor film, a second film having a region located above the first film, and a third film having a region located above the second film. In a cross-sectional view, the first film has a region that protrudes more than the edge of the second film. In a cross-sectional view, the third film has a region that protrudes more than the edge of the second film. The thickness of the second film is greater than the thickness of the first film. A display device wherein the thickness of the second film is greater than the thickness of the third film.

2. A display device having a plurality of pixels, each having a transistor and a capacitive element electrically connected to the transistor, A first conductive layer having the function of a gate electrode of the transistor, A first insulating film having a region located above the first conductive layer and having silicon nitride, A second insulating film having a region located above the first insulating film and containing silicon oxide, An oxide semiconductor film having a region in contact with the upper surface of the second insulating film and having a channel formation region for the transistor, A second conductive layer having a region in contact with the upper surface of the second insulating film and functioning as an electrode of the capacitive element, A third conductive layer having a region in contact with the upper surface of the oxide semiconductor film and functioning as one of the source and drain electrodes of the transistor, A third insulating film having silicon oxide and having a region in contact with the upper surface of the oxide semiconductor film, a region in contact with the upper surface of the second conductive layer, and a region in contact with the upper surface of the third conductive layer, A fourth insulating film having silicon nitride and having a region located above the third insulating film and a region in contact with the upper surface of the second conductive layer, The fourth conductive layer has a region located above the second conductive layer via the fourth insulating film and functions as a pixel electrode, The third conductive layer has a laminated structure comprising a first film having a region in contact with the upper surface of the oxide semiconductor film, a second film having a region located above the first film, and a third film having a region located above the second film. In a cross-sectional view, the first film has a region that protrudes more than the edge of the second film. In a cross-sectional view, the third film has a region that protrudes more than the edge of the second film. The thickness of the second film is greater than the thickness of the first film. The thickness of the second film is greater than the thickness of the third film. A display device wherein the thickness of the third insulating film is greater than the thickness of the fourth insulating film.

3. In claim 1 or 2, A display device wherein the thickness of the first insulating film is greater than the thickness of the second insulating film.

Images