End-to-end action recognition in intelligent video analytics and edge computing systems

Abstract

Apparatus, systems, and techniques for performing action recognition. In at least one embodiment, action recognition is performed using one or more neural networks and a hardware accelerator, where the one or more neural networks are processed, for example, based on one or more quantization and pruning processes.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 17 / 225,924, filed Apr. 8, 2021, entitled "END TO END ACTION RECOGNITION IN INTELLIGENT VIDEO ANALYSIS AND EDGE COMPUTING SYSTEMS", the entire content of which is hereby incorporated by reference for all purposes.

[0002] At least one embodiment relates to processing resources used to perform and facilitate action recognition in images and video frames. For example, at least one embodiment relates to a processor or computing system used to perform action recognition in an image using a neural network.

Background Art

[0003] Action recognition is an important task in various environments such as video surveillance and autonomous driving. Often, action recognition requires a large amount of computing resources to perform. This can result in situations where some computing devices in a particular computing environment do not have the processing power to perform action recognition. Therefore, the amount of memory, time, or computing resources used to perform action recognition can be improved.

Prior Art Documents

Non-Patent Documents

[0004]

Non-Patent Document 1

[0005] [Figure 1] This figure shows an example of a system for action recognition, based on at least one embodiment. [Figure 2] This figure shows an example of pruning a neural network, based on at least one embodiment. [Figure 3] This figure shows one example of quantizing the weights of a neural network, based on at least one embodiment. [Figure 4] This figure shows an example of image processing for a system for action recognition, based on at least one embodiment. [Figure 5] This figure shows an example of an edge device and system for action recognition, based on at least one embodiment. [Figure 6] This figure shows an example of a process for a system for action recognition, based on at least one embodiment. [Figure 7A] This figure shows the inference and / or training logic according to at least one embodiment. [Figure 7B] This figure shows the inference and / or training logic according to at least one embodiment. [Figure 8] This figure shows the training and deployment of a neural network in at least one embodiment. [Figure 9] This figure shows an exemplary data center system according to at least one embodiment. [Figure 10A] This figure shows an example of an autonomous vehicle, based on at least one embodiment. [Figure 10B] This figure shows an example of camera location and field of view for the autonomous vehicle shown in Figure 10A, according to at least one embodiment. [Figure 10C] A block diagram showing an exemplary system architecture for an autonomous vehicle, according to at least one embodiment, as shown in Figure 10A. [Figure 10D] This figure shows a system for communication between (one or more) cloud-based servers and the autonomous vehicle shown in Figure 10A, according to at least one embodiment. [Figure 11] A block diagram of a computer system according to at least one embodiment. [Figure 12] A block diagram of a computer system according to at least one embodiment. [Figure 13] This figure shows a computer system according to at least one embodiment. [Figure 14] This figure shows a computer system according to at least one embodiment. [Figure 15A] This figure shows a computer system according to at least one embodiment. [Figure 15B] This figure shows a computer system according to at least one embodiment. [Figure 15C] This figure shows a computer system according to at least one embodiment. [Figure 15D] This figure shows a computer system according to at least one embodiment. [Figure 15E] This figure shows a shared programming model based on at least one embodiment. [Figure 15F] This figure shows a shared programming model based on at least one embodiment. [Figure 16] A diagram showing an exemplary integrated circuit and related graphics processor according to at least one embodiment. [Figure 17A] A diagram showing an exemplary integrated circuit and related graphics processor according to at least one embodiment. [Figure 17B] A diagram showing an exemplary integrated circuit and related graphics processor according to at least one embodiment. [Figure 18A] A diagram showing additional exemplary graphics processor logic according to at least one embodiment. [Figure 18B] A diagram showing additional exemplary graphics processor logic according to at least one embodiment. [Figure 19] A diagram showing a computer system according to at least one embodiment. [Figure 20A] A diagram showing a parallel processor according to at least one embodiment. [Figure 20B] A diagram showing a partition unit according to at least one embodiment. [Figure 20C] A diagram showing a processing cluster according to at least one embodiment. [Figure 20D] A diagram showing a graphics multiprocessor according to at least one embodiment. [Figure 21] A diagram showing a multi-graphics processing unit (GPU) system according to at least one embodiment. [Figure 22] A diagram showing a graphics processor according to at least one embodiment. [Figure 23] A block diagram showing a processor microarchitecture for a processor according to at least one embodiment. [Figure 24] A diagram showing a deep learning application processor according to at least one embodiment. [Figure 25]A block diagram showing an exemplary neuromorphic processor with at least one embodiment. [Figure 26] This figure shows at least a portion of a graphics processor according to one or more embodiments. [Figure 27] This figure shows at least a portion of a graphics processor according to one or more embodiments. [Figure 28] This figure shows at least a portion of a graphics processor according to one or more embodiments. [Figure 29] This is a block diagram of the graphics processing engine of a graphics processor, according to at least one embodiment. [Figure 30] This is a block diagram of at least a portion of a graphics processor core, according to at least one embodiment. [Figure 31A] This figure shows thread execution logic including an array of processing elements for a graphics processor core, according to at least one embodiment. [Figure 31B] This figure shows thread execution logic including an array of processing elements for a graphics processor core, according to at least one embodiment. [Figure 32] This figure shows a parallel processing unit ("PPU") according to at least one embodiment. [Figure 33] This figure shows a general-purpose processing cluster ("GPC") in at least one embodiment. [Figure 34] This figure shows a memory partition unit of a parallel processing unit ("PPU") according to at least one embodiment. [Figure 35] This figure shows a streaming multiprocessor according to at least one embodiment. [Figure 36] This is an exemplary data flow diagram for an advanced computing pipeline, with at least one implementation example. [Figure 37] This is a system diagram for an exemplary system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline, with at least one embodiment. [Figure 38] This figure includes an illustrative diagram of an advanced computing pipeline 3710A for processing imaging data, according to at least one embodiment. [Figure 39A] This figure includes an illustrative data flow diagram of a virtual device supporting an ultrasonic device, according to at least one embodiment. [Figure 39B] This figure includes an illustrative data flow diagram of a virtual device supporting a CT scanner, according to at least one embodiment. [Figure 40A] This is a data flow diagram for the process of training a machine learning model, with at least one example. [Figure 40B] This is an illustrative diagram of a client-server architecture for extending annotation tools with a pre-trained annotation model, based on at least one embodiment. [Modes for carrying out the invention]

[0006] In various embodiments, action recognition is a resource-intensive task that requires a large amount of computing resources to perform. The techniques described herein relate to a system for action recognition that can efficiently classify the actions of objects based on video data so that the system can be used on a variety of devices with limited computing resources, such as edge devices. More specifically, the system can classify the actions of one or more objects represented in the video data based on input video data. Objects can refer to any suitable entity or object represented in the video data. Actions can include motor actions, such as sitting, walking, running, climbing, and various other actions, but are not limited to these. The system can be efficient so that it can be deployed on computing devices with limited processing capability.

[0007] The system can utilize various neural network models for object detection and action recognition, which undergo various pruning processes after training. In various embodiments, these models are pruned by calculating the L1 norm values ​​of the kernels of those models and removing kernels with L1 norm values ​​below a defined threshold. Furthermore, the weights of the neural network models may be quantized to further improve performance. The pruned and quantized networks can efficiently perform object detection and action recognition functions.

[0008] Additionally, the system may utilize hardware accelerators to compute optical flow vectors for objects in video data. The hardware accelerators may be configured specifically for optical flow computation, further increasing the system's efficiency. The system may also utilize pruned and quantized networks with respect to hardware accelerators to efficiently classify object actions from video data. By utilizing pruned and quantized networks and hardware accelerators, the system can perform action recognition in real time and in various environments where computing resources may be limited, such as on various edge devices.

[0009] Various techniques are described in the above and below descriptions. For the purpose of explanation, specific configurations and details are provided to give a complete understanding of possible ways of implementing the techniques. However, it will also be apparent that the techniques described below may be practiced in different configurations without specific details. Furthermore, well-known features may be omitted or simplified to avoid obscuring the techniques being described.

[0010] The techniques described and implied in this disclosure can improve the field of action recognition, particularly in the context of performing action recognition using limited computing resources, by providing systems that perform action recognition using various techniques, such as pruning, quantization, and hardware acceleration, to increase system efficiency. In addition, the techniques described and implied in this disclosure can improve the speed of performing action recognition on various computing systems. Moreover, the techniques described and implied in this disclosure are inherently rooted in computer technology, in particular, to overcome the problems that arise with performing action recognition in real time using limited computing resources.

[0011] Figure 1 shows an example 100 of a system for action recognition, according to at least one embodiment. In one embodiment, the system for action recognition 102 processes video data 104 to determine one or more action classifications 128. The system for action recognition 102 may be a collection of one or more hardware and / or software computing resources having instructions that, when executed, determine one or more action classifications based on video data. In some embodiments, the system for action recognition 102 is a software program running on computer hardware, an application running on computer hardware, and / or a variation thereof. In one embodiment, one or more processes of the system for action recognition 102 are executed by any preferred processing system or unit (e.g., a graphics processing unit (GPU), a parallel processing unit (PPU), a central processing unit (CPU)), and in any preferred manner, including sequential, parallel, and / or variations thereof.

[0012] The action recognition system 102 may acquire or receive video data 104. In one embodiment, video data 104 is digital data encoding a representation of a moving visual image (e.g., video). Video data 104 may comprise one or more images, also called frames, which together form a video. Video data 104 may be implemented using any suitable digital video format, such as advanced video coding (AVC), motion picture experts group (MPEG) format, and / or variations thereof. Video data 104 may be implemented as a sequence of images in any suitable raster image file format (e.g., bitmap image file, JPEG (Joint Photographic Experts Group) file) and / or vector image file format (e.g., SVG (Scalable Vector Graphics) file). Video data 104 may be compressed or uncompressed. The video data 104 may be generated from one or more video and / or image capture devices, such as one or more systems including autonomous vehicles, robots, surveillance systems, medical imaging systems, and satellite imaging systems. The video data 104 may represent video in any preferred color scheme, such as red-green-blue (RGB), black-and-white (BW), grayscale, and / or variations thereof.

[0013] The action recognition system 102 may acquire or otherwise receive video data 104 from one or more systems with respect to various video and / or image capture devices. In some examples, the action recognition system 102 is part of a system comprising video capture hardware and / or software, where the action recognition system 102 acquires video data 104 from the video capture hardware and / or software. The video data 104 may be acquired or otherwise received by the action recognition system 102 in any preferred manner, such as physically (e.g., via a wired connection to a device associated with the action recognition system 102), remotely (e.g., via a wireless communication network to a device associated with the action recognition system 102), and / or variations thereof.

[0014] A decoder 106 of the action recognition system 102 may process video data 104. In one embodiment, decoder 106 is a collection of one or more hardware and / or software computing resources having instructions that, when executed, perform one or more video processing operations. Decoder 106 may determine frames from video data 104. In some examples, video data 104 is compressed, where decoder 106 decompresses video data 104 to determine frames. Decoder 106 may determine image states 108 from video data 104. Image states 108 may be data structures or data objects that store or otherwise encode video frames. Image states 108 may contain one or more frames of video data 104. Frames of video data 104 may be images that are represented or otherwise stored in any preferred image file format, such as various raster and / or vector formats. The frames of the video data 104 may be in compressed or uncompressed form in the image state 108.

[0015] The decoder 106 may output frames (for example, frames of image state 108) to the accelerator 110 and the detector 114. In some examples, the decoder 106 outputs frames to the object cropping 118, as will be described in more detail below. The detector 114 may process the frames output by the decoder 106. In one embodiment, the detector 114 is a collection of one or more hardware and / or software computing resources that, when executed, have instructions to perform one or more object detection operations. The detector 114 may utilize various neural network models for object detection, such as perceptron models, radial basis networks (RBNs), autoencoders (AEs), Boltzmann machines (BMs), restricted Boltzmann machines (RBMs), deep belief networks (DBNs), deep convolutional networks (DCNs), extreme learning machines (ELMs), deep residual networks (DRNs), and / or variations thereof. The detector 114 may determine the frame features of image state 108. The detector 114 may determine the bounding box for the object in the frame of image state 108. The object may refer to any suitable entity or object in the scene represented in one or more frames, such as a person, an object in the environment, a vehicle, a robot, and / or variations thereof. In one embodiment, a bounding box refers to an indication of the location and / or position of an object represented in an image. A bounding box may be defined by a set of coordinates corresponding to the corners of the bounding box. A bounding box may indicate an area or region of the image (e.g., a frame) containing an object.The detector 114 can determine bounding boxes for any number of objects represented in one or more frames of the image state 108 and output the determined bounding boxes to the object cropping 118 and the optical flow cropping 122.

[0016] In some examples, the detector 114 does not determine a bounding box for each frame of image state 108, but only determines a bounding box for one or more frames of image state 108, where the determined bounding box is output to the tracker 116. In one embodiment, the tracker 116 is a collection of one or more hardware and / or software computing resources that, when executed, have instructions to perform one or more computer vision processes. The tracker 116 may implement one or more computer vision algorithms that determine the bounding box for one or more frames based on the bounding boxes of one or more previous frames and / or one or more subsequent frames for that one or more frames. The detector 114 and / or the tracker 116 may consist of a parameter sometimes called the tracking distance, which determines which frames of image state 108 should be processed by the detector 114 and / or the tracker 116. The tracking distance, which should be processed by the detector 114, can indicate the number of frames between frames and can be any suitable integer value. For example, a tracking distance of 0 indicates that the detector 114 should process every frame of image state 108, a tracking distance of 1 indicates that the detector 114 should process every other frame of image state 108, and so on. The tracker 116 may determine the bounding boxes for each frame of image state 108 that is not processed by the detector 114. For example, the detector 114 determines the bounding boxes for every other frame of image state 108 (e.g., the first frame, the third frame, the fifth frame, etc.), where the tracker 116 determines the bounding boxes for the remaining frames of image state 108 (e.g., the second frame, the fourth frame, the sixth frame, etc.).The tracker 116 may perform various object tracking processes, such as one or more kernel-based tracking processes and / or contour tracking processes, to determine the bounding box for an object in a frame based on the bounding box for that object in a previous frame and / or the bounding box for that object in a subsequent frame.

[0017] The tracker 116 can determine bounding boxes for any number of objects in any number of frames based on the bounding boxes determined by the detector 114. The object cropping 118 can process the frames output by the decoder 106 (e.g., frames of image state 108) based on the bounding boxes output by the detector 114 and / or the tracker 116, which may indicate the objects represented in the frames. In one embodiment, the object cropping 118 is a set of one or more hardware and / or software computing resources having instructions to perform one or more image cropping operations when executed. The object cropping 118 may crop frames to determine a set of images, where each image in the set of images corresponds to a bounding box of a frame. Object cropping 118 may crop the frame with respect to one or more bounding boxes for the frame (for example, determined by detector 114 and / or tracker 116) to determine one or more images corresponding to one or more bounding boxes, where each image of one or more images includes an area or region of the frame indicated by the corresponding bounding box of one or more bounding boxes.

[0018] For example, given a frame (e.g., a frame of image state 108) and a first bounding box indicating a first object in that frame (determined, for example, by detector 114 and / or tracker 116), object cropping 118 crops the frame to determine a first image from the frame that includes the area or region indicated by the first bounding box indicating the first object, and so on for any number of other bounding boxes indicating other objects in the frame. Object cropping 118 may crop a particular frame to determine a set of images, also called cropped frames, corresponding to any number of bounding boxes for that particular frame. Cropped frames may refer to images determined from the frame based on the bounding boxes for objects represented in the frame. Object cropping 118 may output one or more cropped frames determined from the frame (e.g., a frame of image state 108) to the object box buffer 120.

[0019] The object box buffer 120 may store one or more cropped frames output from object cropping 118. In one embodiment, the object box buffer 120 is a data buffer that stores one or more images. The object box buffer 120 may be implemented using software and / or hardware resources. The object box buffer 120 may be implemented using one or more data structures, such as arrays or lists. The object box buffer 120 may store one or more images corresponding to one or more bounding boxes of one or more objects in the frames of image state 108. The object box buffer 120 may output one or more images (e.g., cropped frames) to the action recognition model 126.

[0020] In one embodiment, accelerator 110, also called an optical flow accelerator, is a hardware-accelerated computing device for calculating optical flow. Accelerator 110 may comprise various hardware processing components, such as one or more PPUs, GPUs, etc. Accelerator 110 can be any suitable hardware accelerator. In one embodiment, hardware accelerator refers to computer hardware used to perform one or more processes in particular. Hardware accelerator can perform various functions (e.g., the optical flow calculation process) using fewer computing resources than other software and / or hardware used to perform various functions, such as software using a general-purpose CPU.

[0021] Optical flow can refer to a distinct pattern of motion of objects, surfaces, and edges in a visual scene. Optical flow can be represented using an optical flow field, which may be a vector field indicating the motion of an object between image frames. In one embodiment, an optical flow field for two or more image frames includes a set of vectors, where each vector represents the motion of an object between frames of the two or more image frames. For example, a first image may show a first object at a first position, and a second image may show the first object at a second position, where the optical flow field for the first and second images includes a vector indicating the movement of the first object from the first position to the second position.

[0022] The accelerator 110 may process the frames output by the decoder 106 (for example, the frames of image state 108) to determine one or more flow fields, optical flow fields, and / or their modified forms, also known as vector fields. The accelerator 110 may utilize various information determined by the detector 114 to determine the flow fields, such as feature information, bounding box information, and / or their modified forms. In some examples, the accelerator 110 divides the frames into one or more regions or blocks, also known as patches, and determines the flow fields based on the corresponding regions or blocks of the frames. For example, for a first frame and a second frame, the accelerator 110 divides the frames into sets of blocks, determines that a block in the first frame correlates with or otherwise contains an object in a block in the second frame, and calculates a flow field containing one or more vectors indicating the movement of an object from a first position indicated by the block in the first frame to a second position indicated by the block in the second frame.

[0023] The optical flow state 112 may be a data structure or data object that stores or otherwise encodes a flow field. The accelerator 110 may determine an optical flow state 112 that includes one or more flow fields. In one embodiment, each flow field in the optical flow state 112 corresponds to a pair of frames in the image state 108. The flow fields of the optical flow state 112 may represent the movement of an object in the frames of the image state 108. The flow fields may represent the movement of each pixel between frames in the image state 108, where the pixels may correspond to one or more objects represented in the frames. For example, the first flow field of the optical flow state 112 corresponds to a first frame showing a first object at a first position and a second frame showing the first object at a second position, where the first flow field includes one or more vectors showing the movement of the first object from the first position to the second position. The flow field of optical flow state 112 can represent the motion of any number of objects in the frames of image state 108. The flow field can be output to optical flow cropping 122 by accelerator 110.

[0024] The optical flow cropping 122 can process the flow field of the optical flow state 112 and the bounding box output from the detector 114 and / or tracker 116. In one embodiment, the optical flow cropping 122 is a set of one or more hardware and / or software computing resources that, when executed, have instructions to perform one or more flow field cropping operations. The optical flow cropping 122 may crop the flow field corresponding to a frame (e.g., a frame of image state 108) to determine a set of cropped flow fields, where each cropped flow field in the set of cropped flow fields corresponds to the bounding box of the frame. Optical flow cropping 122 can crop the flow field based on corresponding pairs of frames and one or more bounding boxes for the frames in the pair of frames (determined, for example, by detector 114 and / or tracker 116) to determine one or more cropped flow fields corresponding to one or more bounding boxes, where each cropped flow field corresponds to an area or region of the flow field corresponding to an area or region of the frame indicated by the corresponding bounding box among the one or more bounding boxes.

[0025] For example, with respect to a given flow field corresponding to a first frame and a second frame (e.g., the frame of image state 108) and a first bounding box indicating a first object in the first frame (e.g., determined by detector 114 and / or tracker 116), optical flow cropping 122 crops the flow field to determine a first cropped flow field that includes an area or region of the flow field corresponding to the area or region of the first frame indicated by the first bounding box indicating the first object, and so on for any number of other bounding boxes indicating other objects in the first frame. Optical flow cropping 122 may crop the flow field based on one or more bounding boxes for the first frame and / or second frame of a corresponding pair of frames to determine a set of cropped flow fields corresponding to one or more bounding boxes. A cropped flow field, also called a cropped motion, can refer to a flow field that represents the motion of a particular object (e.g., indicated by a bounding box) represented in one or more frames. In one embodiment, the cropped flow field corresponding to the bounding box of an object includes a vector indicating the motion of the object. Optical flow cropping 122 may output one or more cropped flow fields determined from the flow field (e.g., the flow field of the optical flow state 112) to the optical flow box buffer 124.

[0026] The optical flow box buffer 124 may store one or more flow fields output from the optical flow cropping 122. In one embodiment, the optical flow box buffer 124 is a data buffer that stores one or more flow fields. The optical flow box buffer 124 may be implemented using software and / or hardware resources. The optical flow box buffer 124 may be implemented using one or more data structures, such as arrays or lists. The optical flow box buffer 124 may store one or more cropped flow fields (determined, for example, from the flow fields of the optical flow state 112) corresponding to one or more bounding boxes of one or more objects in the frames of the image state 108. The optical flow box buffer 124 may output one or more flow fields to the action recognition model 126.

[0027] The action recognition model 126 can process cropped frames output from the object box buffer 120 and cropped flow fields output from the optical flow box buffer 124. In one embodiment, each flow field in the optical flow box buffer 124 corresponds to a cropped frame in the object box buffer 120. The cropped flow fields in the optical flow box buffer 124 may represent the movement of an object in the bounding box corresponding to the cropped frame in the object box buffer 120. For example, the first cropped frame in the object box buffer 120 corresponds to the bounding box of an object, where the corresponding cropped flow field includes a vector representing the movement of the object. Based on the cropped frames output from the object box buffer 120 and the cropped flow fields output from the optical flow box buffer 124, the action recognition model 126 can determine the action of an object shown in the frame of image state 108.

[0028] In one embodiment, the action recognition model 126 is a set of one or more hardware and / or software computing resources having instructions to perform one or more action recognition classification processes when executed. The action recognition model 126 may utilize a variety of neural network models for action recognition, such as perceptron models, radial basis networks (RBNs), autoencoders (AEs), Boltzmann machines (BMs), restricted Boltzmann machines (RBMs), deep belief networks (DBNs), deep convolutional networks (DCNs), extreme learning machines (ELMs), deep residual networks (DRNs), and / or variations thereof. The action recognition model 126 may utilize one or more classifier neural network algorithms and / or models, such as logistic regression models, naive Bayesian models, stochastic gradient descent models, K-nearest neighbor models, decision tree models, random forest models, support vector machine models, and / or variations thereof. In one embodiment, the action recognition model 126 includes one or more gated recurrent unit (GRU) models. The action recognition model 126 may utilize a first model to process a flow field (e.g., a cropped flow field of the optical flow box buffer 124) and a second model to process an image (e.g., a cropped frame of the object box buffer 120).

[0029] The action recognition model 126 may determine one or more action classifications 128, which may include one or more labels for one or more actions performed by one or more objects in the video data 104. Actions may be indicated by labels that include the action classification corresponding to the action. In some embodiments, the action classification is a classification or other identifier that indicates an action. In one embodiment, one or more action classifications 128 is a set of one or more data structures and / or data objects that encode the results of one or more neural network processes of the action recognition model 126. One or more action classifications 128 may store the labels determined by the action recognition model 126.

[0030] The action recognition model 126 can classify the actions of objects represented in frames of image state 108, which may be frames of video data 104. The action recognition model 126 can determine a single label for each object represented in frames of image state 108 (e.g., indicated by one or more bounding boxes determined by detectors 114 and / or trackers 116 and shown in one or more images determined by object cropping 118), the single label indicating a specific classification or class, also called an action classification, corresponding to the action of the object (e.g., an action performed by the object in one or more frames). The label for an object represented in one or more frames (e.g., frames of image state 108) may include an action classification corresponding to the action of the object, and / or an indication of the location or position of the object represented in one or more frames (e.g., via bounding boxes or other preferred indications). Action classifications may represent actions such as sitting, walking, running, climbing (obstacles such as walls, stairs, and / or variations thereof), jumping, and / or any suitable actions. Action classifications may represent any actions that can be performed by a person or other object in a real-world environment. For example, action recognition model 126 determines a label for an object represented in video data 104 that includes an action classification corresponding to walking, which indicates that action recognition model 126 has determined that the object represented in video data 104 is performing the action of walking. Action recognition model 126 may classify an object's actions (for example, via labels) as belonging to an action classification among any number of action classifications corresponding to any number of suitable actions.

[0031] In some examples, the label for an object includes probabilities for different action classifications. The label for an object includes a first value indicating the probability of a first class of action, a second value indicating the probability of a second class of action, and so on for any number of actions. For example, the label for an object might show a 90% probability of the action classification corresponding to walking and a 10% probability of the action classification corresponding to standing, indicating that the action recognition model 126 has determined that the action performed by the object is either the action of walking with a 90% probability or the action of standing with a 10% probability. In various embodiments, for an object with multiple action classifications and probabilities, the action classification with the highest or maximum probability is used for the label for the object.

[0032] In one embodiment, one or more neural networks of the action recognition system 102 undergo one or more pruning processes. The action recognition system 102, and / or systems associated with the action recognition system 102, such as the training framework system, may perform one or more pruning processes on one or more neural network models of the detector 114 and / or the action recognition model 126. In various embodiments, the system (for example, the action recognition system 102, and / or systems associated with the action recognition system 102, such as the training framework system) trains one or more neural network models of the action recognition system 102, applies one or more pruning processes to one or more neural network models, and performs additional training processes on the pruned one or more neural network models. One or more pruning processes may include those involving pruning weights, kernels, and / or variations thereof, as well as any suitable pruning processes based on any suitable logic, heuristic, rule, function, and / or variations thereof. In some examples, pruning is performed by the system by calculating the L1 norm values ​​of the kernels of one or more neural networks of system 102 for action recognition and removing kernels with L1 norm values ​​below a defined threshold. Further information regarding pruning can be found in the description in Figure 2.A pruned neural network may contain fewer kernels than an unpruned neural network, and therefore may require fewer computing resources to process data than an unpruned neural network. Thus, a pruned neural network may utilize fewer computing resources to process data than an unpruned neural network.

[0033] In one embodiment, one or more neural networks of the action recognition system 102 undergo one or more quantization processes. One or more neural networks of the action recognition system 102 may include quantized weights. The action recognition system 102, and / or systems associated with the action recognition system 102, such as the training framework system, may perform one or more quantization processes on one or more neural network models of the detector 114 and / or the action recognition model 126. In various embodiments, a system (for example, system 102 for action recognition, and / or a system associated with system 102 for action recognition, such as a training framework system) applies one or more quantization processes to one or more neural network models of system 102 for action recognition, such as one or more quantization processes during training (e.g., quantization-aware training (QAT)) and / or one or more quantization processes after training (e.g., post-training quantization (PTQ)). In some examples, quantization is performed by the system by converting one or more weights of one or more neural networks of system 102 for action recognition from a first data type representation (e.g., floating-point 32-bit precision (FP32)) to a second data type representation (e.g., 8-bit integer (INT8)) using any suitable logic, heuristics, rules, functions, and / or variations thereof. Further information regarding quantization can be found in the description in Figure 3.A quantized neural network may have fewer bits of data type representation weights than a non-quantized neural network, and therefore may require fewer computing resources to process the data than a non-quantized neural network.

[0034] The action recognition system 102 may perform action recognition in real time. In one embodiment, real time may refer to processing in which the input is processed within a time interval in which the input is generated. The time interval for real-time processing may be on the order of milliseconds, microseconds, or any preferred time interval. The action recognition system 102 may determine (one or more) action classifications 128 from video data 104 within a time interval in which video data 104 is generated (for example, from one or more image and / or video capture systems). For example, the action recognition system 102 is part of a computing system (e.g., an edge device) associated with video capture hardware and / or software, where the video data 104 is generated from the video capture hardware and / or software, and the action recognition system 102 determines (one or more) action classifications 128 from video data 104 within a time interval in which the video data 104 is generated from the video capture hardware and / or software.

[0035] In various embodiments, the system 102 for action recognition is a software module that runs using one or more computing systems of one or more devices or systems, such as vehicles (e.g., manual vehicles, semi-autonomous vehicles, autonomous vehicles, or drones), robots, edge devices, or other systems with neural network capabilities. Edge devices can refer to computing devices such as mobile phones, tablets, laptops, Internet of Things (IoT) devices (e.g., sensors, embedded devices), and / or variations thereof. In one embodiment, the edge device is a computing device with limited memory and / or processing power. One or more computing systems, such as a server or data center system, may deploy or otherwise implement the system 102 for action recognition on an edge device, where the edge device may perform various action recognition processes using the system 102 for action recognition. Edge devices may utilize the system 102 for action recognition to perform action recognition in various environments. Further information regarding the use of edge devices with the system for action recognition can be found in the description of Figure 5.

[0036] Figure 2 shows an example 200 of pruning a neural network, according to at least one embodiment. In this example 200, kernel 202, which may be a kernel of one or more neural network models, undergoes pruning 204 to produce kernel 206, which may be kernel 202 after one or more pruning processes. In one embodiment, kernel 202 and / or kernel 206 are one or more kernels of one or more neural network models, such as those described with respect to the system for action recognition in Figure 1.

[0037] Kernel 202 may be one or more kernels of one or more detector neural network models and / or action recognition models as described with respect to Figure 1. A kernel may include an array of one or more weights of any preferred dimension. In one embodiment, the weights of a kernel refer to the numerical values ​​of the kernel used in one or more multiplication processes as part of processing the input data of the neural network. A kernel may be applied to data being processed by the neural network to determine the features and / or other properties of the data. A filter may include a set of kernels. A single kernel that forms a filter may also be called a filter. Referring to Figure 2, kernel 202 may include a first kernel 202A, a second kernel 202B, a third kernel 202C, a fourth kernel 202D, a fifth kernel 202E, and / or various other kernels not shown in Figure 2.

[0038] The weights of kernel 202 may be updated as part of the training process of one or more neural network models, such as the detector's neural network model and / or the action recognition model, by one or more systems, such as the system for action recognition (e.g., system 102 for action recognition in Figure 1) and / or systems related to the system for action recognition, such as the training framework system described with respect to Figure 8. For example, kernel 202 is the kernel of one or more neural network models of the detector (e.g., detector 114 in Figure 1), where the weights of kernel 202 are updated as part of the training process of one or more of the detectors. As another example, kernel 202 is the kernel of one or more neural network models of the action recognition model (e.g., action recognition model 126 in Figure 1), where the weights of kernel 202 are updated as part of the training process of one or more of the action recognition models.

[0039] One or more systems, such as a system for action recognition and / or systems associated with the system for action recognition, may determine one or more values ​​for each kernel of kernel 202, which may include values ​​such as L1 norm value, L2 norm value, maximum norm value, and / or variations thereof. In one embodiment, the L1 norm value refers to a numerical value calculated as the sum of the absolute values ​​of the kernel weights. In one embodiment, the L2 norm value refers to a numerical value calculated as the square root of the sum of the squares of the kernel weights. In one embodiment, the maximum norm value refers to a numerical value calculated as the maximum value of the kernel weights. One or more systems may calculate the L1 norm value for each kernel of kernel 202. Figure 2 shows the L1 norm value, but note that any suitable value, such as the L2 norm value, maximum norm value, and / or variations thereof, may be used.

[0040] In one embodiment, pruning 204 refers to one or more neural network pruning processes performed by one or more systems, such as a system for action recognition and / or a system associated with the system for action recognition. Pruning 204 can be implemented as a set of instructions to be performed by one or more systems. One or more systems may perform pruning 204 on kernels 202. Pruning 204 may include one or more processes in which L1 norm values ​​are calculated for kernels, as described in more detail above. Pruning 204 may include one or more processes in which kernels with L1 norm values ​​above a threshold, also called a pruning threshold, are removed. The pruning threshold used as part of pruning 204 can be any preferred numerical value. In some examples, the pruning threshold is determined by one or more systems with respect to one or more neural network training processes. The pruning threshold can be determined by one or more systems through any preferred process, such as through defined logical rules / functions, neural network training / inference processes, and / or variations thereof.

[0041] For example, if the first L1 norm value calculated for a first kernel of kernel 202 exceeds a pruning threshold, then the first kernel is removed from kernel 202 as part of pruning 204. In some examples, a set of kernels forms a filter, where an average L1 norm value is calculated based on one or more L1 norm values ​​of one or more kernels in the set of kernels (for example, by adding one or more L1 norm values ​​and dividing the sum by the number of kernels, or by any preferred method), and the average L1 norm value can be used to determine whether the set of kernels forming the filter should be removed. For example, if a first kernel and a second kernel of kernel 202 form a filter, where the average L1 norm value calculated based on the L1 norm values ​​of the first kernel and the second kernel exceeds a pruning threshold, then the first kernel and the second kernel are removed from kernel 202 as part of pruning 204.

[0042] Pruning 204 may produce kernel 206, which may be kernel 202 after one or more pruning processes of pruning 204. One or more kernels and / or filters of kernel 202 may be removed to produce kernel 206 if the calculated L1 norm value for one or more kernels and / or filters exceeds the pruning threshold in pruning 204. For example, referring to Figure 2, kernel 202A corresponds to kernel 206A, kernel 202B corresponds to kernel 206B, kernel 202C corresponds to kernel 206C, kernel 202E corresponds to kernel 206E, and the calculated L1 norm value for kernel 202D exceeds the pruning threshold, where kernel 202D is removed from kernel 202 as part of pruning 204 to produce kernel 206.

[0043] The weights of kernel 206 may be updated as part of the training process of one or more neural network models, such as the detector's neural network model and / or the action recognition model, by one or more systems, such as the system for action recognition (e.g., system 102 for action recognition in Figure 1) and / or systems related to the system for action recognition, such as the training framework system described with respect to Figure 8. For example, kernel 206 is the kernel of one or more neural network models of the detector (e.g., detector 114 in Figure 1) determined through one or more pruning processes (e.g., pruning 204), where the weights of kernel 206 are updated as part of the training process of one or more detectors. As another example, kernel 206 is the kernel of one or more neural network models of an action recognition model (e.g., action recognition model 126 in Figure 1) determined through one or more pruning processes (e.g., pruning 204), where the weights of kernel 206 are updated as part of the training process of one or more action recognition models.

[0044] Figure 3 shows an example of quantizing the weights of a neural network, according to at least one embodiment. Example 300 may include weights 302A-302F, which may be the weights of one or more neural network models, weights 302A-302F undergo quantization 304 to produce weights 306A-306F, also called quantized weights, weights 306A-306F, which may be the weights after one or more quantization processes of 302A-302F. In one embodiment, weights 302A-302F and / or weights 306A-306F are the weights of one or more neural network models, such as those described in relation to the system for action recognition in Figure 1.

[0045] Weights 302A–302F may be the weights of one or more detector neural network models and / or action recognition models as described with respect to Figure 1. In one embodiment, weights refer to numerical values ​​used in one or more processes that process the input data of the neural network. Referring to Figure 3, weights 302A–302F may include the first weight 302A, the second weight 302B, the third weight 302C, the fourth weight 302D, the fifth weight 302E, the sixth weight 302F, and / or various other weights not shown in Figure 3. In one embodiment, weights 302A–302F are represented through 32-bit floating-point numbers (FP32) or any preferred numerical representation. In one embodiment, weights 306A–306F are represented through 8-bit integers (INT8) or any preferred numerical representation.

[0046] Weights 302A-302F may be quantized as part of one or more processes of quantization 304. In one embodiment, quantization 304 refers to one or more neural network quantization processes performed by one or more systems, such as a system for action recognition (e.g., system 102 for action recognition in Figure 1) and / or a system associated with the system for action recognition, such as the training framework system described with respect to Figure 8. Quantization 304 may be implemented as a set of instructions to be performed by one or more systems. One or more systems may perform quantization 304 on weights 302A-302F. In one embodiment, quantization 304 includes one or more processes, where weights represented in a first representation (e.g., weights 302A-302F represented in FP32) are scaled, converted, or otherwise mapped to weights represented in a second representation (e.g., weights 306A-306F represented in INT8).

[0047] Quantization 304 may involve one or more processes, where a threshold is defined for a weight (e.g., weights 302A to 302F) for a first range of values ​​(e.g., shown in Figure 3 by range -|threshold|~+|threshold|), where the weights in the first range of values ​​(e.g., weights 302B to 302E that fall within range -|threshold|~+|threshold|) are scaled or otherwise mapped to a second range of values ​​(e.g., shown in Figure 3 by range -127~+127). For example, weight 302B is scaled to weight 306B, weight 302C is scaled to weight 306C, weight 302D is scaled to weight 306D, and weight 302E is scaled to weight 306E. Scaling may include one or more linear scaling processes, or any preferred scaling processes, that can scale the input data based on a scaling factor (for example, a scaling factor for scaling a first range of values ​​to a second range of values). In one embodiment, weights that are above or at the highest value of the first range of values ​​(e.g., +|threshold| in Figure 3) are mapped to the highest value of the second range of values ​​(e.g., +127 in Figure 3), and weights that are below or at the lowest value of the first range of values ​​(e.g., -|threshold|) are mapped to the lowest value of the second range of values ​​(e.g., -127 in Figure 3). For example, weight 302F has a value above the highest value of the first range of values ​​(e.g., +|threshold| shown in Figure 3), where weight 302F is mapped to weight 306F, which has the highest value of the second range of values ​​(e.g., +127 in Figure 3). As another example, referring to Figure 3, weight 302A has a value below the lowest value in a first range of values ​​(for example, indicated by -|threshold| in Figure 3), where weight 302A is mapped to weight 306A, which has the lowest value in a second range of values ​​(for example, -127 in Figure 3).

[0048] A threshold (e.g., the threshold in Figure 3) may be determined by one or more systems to determine the range of values ​​for the first set of weights to be used to map the first set of weights of the first representation (e.g., weights 302A-302F) to the second set of weights of the second representation (e.g., weights 306A-306F). The threshold used in quantization 304 can be any preferred number. In some examples, the threshold is determined by one or more systems with respect to one or more neural network training processes. The threshold may be determined by one or more systems through any preferred process, such as through defined logical rules / functions, neural network training / inference processes, and / or variations thereof. In some examples, a threshold is determined that minimizes the value of the Kullback-Leibler divergence, also called relative entropy or KL divergence. The KL divergence may refer to a measure of the difference between the first and second probability distributions.

[0049] One or more systems may determine thresholds based on calculated KL divergence values. KL divergence values ​​may be calculated based on a first distribution (e.g., a distribution of weights 302A–302F) and a second distribution based on a threshold (e.g., a distribution of weights 306A–306F determined based on the range -|threshold| to +|threshold| indicated by the threshold). One or more systems may calculate a set of KL divergence values ​​based on a set of thresholds. For example, one or more systems may calculate a first KL divergence value based on a first distribution (e.g., a distribution of weights 302A–302F) and a second distribution based on a first threshold (e.g., a distribution of weights 302A–302F mapped to a second range of values ​​based on a first range of values ​​indicated by the first threshold), and so on for any number of thresholds. One or more systems may determine thresholds based on a threshold for the smallest KL divergence value in the set of KL divergence values.

[0050] One or more quantization processes 304 may be performed during training (e.g., QAT), after training (e.g., PTQ), and / or in variations thereof. Quantization 304 may comprise one or more steps. In the first step, QAT may be applied by quantizing all weights and activations of the neural network model, except for layers that require a finer granularity in representation than 8-bit quantization can provide (e.g., regression layers). This may result in a mixed-precision neural network model. In the second step, the quantization of activations determined by QAT may not be utilized, where PTQ may then be applied to the QAT model. The weights of the QAT model may again be quantized, and the range / scale factor for activations may be calibrated using the PTQ process. While the activations were quantized during the QAT process using the running statistics of their distributions, the activations can be requantized by recalculating those statistics against one or more datasets used in the QAT process, such as calibration datasets. By applying PTQ to the QAT-quantized model, all layers of the neural network model can then be quantized.

[0051] Quantization 304 may involve one or more processes, where weights 302A-302F, which may be the weights of one or more neural network models and / or action recognition models of the detector as described with respect to Figure 1, are quantized by one or more systems to produce weights 306A-306F. For example, weights 302A-302F are the weights of one or more neural network models of the detector (e.g., detector 114 in Figure 1), where weights 306A-306F are determined from weights 302A-302F for one or more neural network models of the detector through one or more quantization processes by one or more systems (e.g., quantization 304). As another example, weights 302A–302F are the weights of one or more neural network models of the action recognition model (e.g., action recognition model 126 in Figure 1), where weights 306A–306F are determined from weights 302A–302F for one or more neural network models of the action recognition model through one or more quantization processes by one or more systems (e.g., quantization 304).

[0052] Figure 4 shows an example 400 of processing images with respect to a system for action recognition, according to at least one embodiment. Example 400 may include a system 406 for action recognition that processes images 402 and 404 to determine an action classification visualization 408. In one embodiment, the system 406 for action recognition and images 402-404 are those described with respect to Figure 1.

[0053] Images 402-404 may be frames of video data. In some examples, images 402-404 are images captured from one or more video and / or image capture devices, such as one or more systems, including autonomous vehicles, robots, surveillance systems, medical imaging systems, and satellite imaging systems. Images 402 and / or 404 may be images with any preferred color scheme, such as red-green-blue (RGB), black and white (BW), grayscale, and / or variations thereof. Images 402 and / or 404 may be in any preferred image file format, such as various raster formats and / or vector formats. Images 402 and / or 404 may be in compressed or uncompressed form. In one embodiment, image 402 is the first frame of video data, and image 404 is the second frame of video data. Referring to Figure 4, Image 402 may show the first object at a first position, and Image 404 may show the first object at a second position.

[0054] The action recognition system 406 may be a collection of one or more hardware and / or software computing resources that, when executed, have instructions for determining one or more action classifications based on video data. In some examples, the action recognition system 406 is a software program running on computer hardware, an application running on computer hardware, and / or variations thereof. The action recognition system 406 may acquire or receive images 402-404 from one or more systems with respect to various video and / or image capture devices. In various embodiments, the action recognition system 406 acquires or receives images 402-404 encoded in video data, where the action recognition system 406 extracts or decodes images 402-404 from video data. In some examples, the action recognition system 406 is part of a system comprising video capture hardware and / or software, where the action recognition system 406 acquires images 402-404 from the video capture hardware and / or software. Images 402-404 can be acquired or otherwise received by the action recognition system 406 in any preferred manner, such as physically (e.g., via a wired connection to a device associated with the action recognition system 406), remotely (e.g., via a wireless communication network to a device associated with the action recognition system 406), and / or variations thereof.

[0055] The action recognition system 406 may perform various processes to determine the action classification visualization 408 from images 402-404. The action recognition system 406 may determine the bounding boxes of objects in images 402-404. For example, referring to Figure 4, the action recognition system 406 determines a first bounding box for the object shown in image 402 and a second bounding box for the object shown in image 404. The action recognition system 406 may determine a flow field for images 402-404. In some embodiments, the action recognition system 406 uses one or more PPUs to determine the flow field for images 402-404. The flow field may indicate the movement of objects. For example, the flow field for images 402-404 includes a vector indicating the movement of an object at a first position in image 402 to an object at a second position in image 404.

[0056] The action recognition system 406 may perform various cropping processes on the determined flow field and images 402-404 based on bounding boxes. The action recognition system 406 may use one or more neural network models to process the cropped flow field and cropped images (e.g., images 402 and / or images 404 cropped based on one or more bounding boxes) to determine one or more labels. The action recognition system 406 may determine an action classification visualization 408 by overlaying one or more labels indicating the action classification onto one or more images (e.g., images 402 and / or images 404). The action classification visualization 408 may be a visual representation of the labels indicating the action classification, which may show one or more actions performed by one or more objects in images 402-404. The actions may be indicated by labels containing the action classification corresponding to the action. The labels may include indication of the location and / or position of the object performing the action. In some embodiments, the action classification is a classification or other identifier that indicates an action. Referring to Figure 4, the action classification visualization 408 may include a label indicating the action classification corresponding to walking (for example, shown in Figure 4 as “Walking”), indicating that the action being performed by the objects in images 402–404 is the walking action, and the location of the object (for example, shown in Figure 4 as a box surrounding the object).

[0057] Figure 5 shows an example 500 of an edge device and system for action recognition, according to at least one embodiment. Example 500 may include an edge device 502 that implements a system 504 for action recognition to determine an action classification visualization 508 based on a scene 506. In one embodiment, the edge device 502, the system 504 for action recognition, and the action classification visualization 508 are as described with respect to Figures 1 and 4.

[0058] In some embodiments, the edge device 502 is a computing device, such as a mobile phone, tablet, laptop, Internet of Things (IoT) device (e.g., sensor, embedded device), and / or a variation thereof. In one embodiment, the edge device 502 is a computing device with limited memory and / or processing power. The edge device 502 may comprise one or more processors, such as one or more CPUs, GPUs, PPUs, Data Processing Units (DPUs), and / or other processing units. The edge device 502 may comprise various hardware accelerators, such as various GPUs, PPUs, Vision Processing Units (VPUs), Deep Learning Accelerators (DLAs), and the like. The edge device 502 may implement a system 504 for action recognition. In various embodiments, the system 504 for action recognition is implemented as a software program on the edge device 502. The action recognition system 504 may include a set of instructions for various processes of the action recognition system 504, which are performed by one or more processing units of the edge device 502.

[0059] The edge device 502 may be operated by one or more users. The edge device 502 may include various image and / or video capture hardware and / or software. The edge device 502 may capture video of scene 506. In one embodiment, scene 506 is a real-world environment. Scene 506 may include various objects performing various actions. Referring to Figure 5, scene 506 may include a first object (e.g., a person) performing the action of standing.

[0060] The edge device 502 may capture video of scene 506 and provide the video to the system 504 for action recognition. In some embodiments, the edge device 502 is associated with one or more video capture systems that capture video of scene 506 and provide the video to the system 504 for action recognition of the edge device 502. The system 504 for action recognition may perform various processes to determine an action classification visualization 508 from the video of scene 506. The system 504 for action recognition may extract frames from the video of scene 506. The system 504 for action recognition may determine the bounding boxes of objects in the frames. The system 504 for action recognition may determine a flow field for the frames. In some embodiments, the system 504 for action recognition utilizes one or more PPUs of the edge device 502 to determine the flow field for the frames. The action recognition system 504 may interact with the hardware accelerators of the edge device 502 to cause one or more PPUs of the hardware accelerators to calculate the flow field.

[0061] The action recognition system 504 may perform various cropping processes on the determined flow field and frames from the video of scene 506 based on bounding boxes. The action recognition system 504 may utilize one or more neural network models to process the cropped flow field and cropped frames to determine one or more labels. The action recognition system 504 may determine an action classification visualization 508 by overlaying one or more labels indicating the action classification onto one or more frames (for example, one or more frames from the video of scene 506). The action classification visualization 508 may be a visual representation of the labels indicating the action classification, which may show one or more actions performed by one or more objects in the frames of the video of scene 506. The actions may be indicated by labels containing the action classification corresponding to the action. The labels may include indication of the location and / or position of the object performing the action. In some embodiments, the action classification is a classification or other identifier indicating the action. Referring to Figure 5, the action classification visualization 508 may include a label indicating the action classification corresponding to standing (for example, shown in Figure 5 as "standing"), indicating that the action being performed by the object in the video frame of scene 506 is a standing action, and the location of the object (for example, shown in Figure 5 as a box surrounding the object).

[0062] Figure 6 shows an example of a process 600 for a system for action recognition, according to at least one embodiment. In at least one embodiment, part or all of process 600 (or any other processes described herein, or variations and / or combinations thereof) is carried out under the control of one or more computer systems consisting of computer-executable instructions and is implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more applications) that is collectively executed by hardware, software, or a combination thereof on one or more processors. In at least one embodiment, the code is stored in a computer-readable storage medium in the form of a computer program comprising a plurality of computer-readable instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-temporary computer-readable medium. In at least one embodiment, at least some computer-readable instructions available for carrying out process 600 are not stored using merely temporary signals (e.g., transient electrical or electromagnetic transmissions that propagate). In at least one embodiment, the non-temporary computer-readable medium does not necessarily include non-temporary data storage circuitry (e.g., buffers, caches, and queues) within a temporary signal transceiver. In at least one embodiment, process 600 is performed at least partially on a computer system, such as those described elsewhere in this disclosure.

[0063] In at least one embodiment, a system performing at least a portion of process 600 includes executable code in 602 for receiving multiple frames of video. The system may receive or acquire from the video multiple frames, which may be any preferred video data. The video data may be generated from one or more video and / or image capture devices, such as one or more systems, such as autonomous vehicles, robots, surveillance systems, medical imaging systems, and satellite imaging systems. The video data may represent video with any preferred color scheme, such as red-green-blue (RGB), black and white (BW), grayscale, and / or variations thereof, and may be in any preferred format. The system may acquire the video data and determine multiple frames from the video data. The system may determine the multiple frames using one or more decoders (for example, decoder 106 in Figure 1).

[0064] In at least one embodiment, a system performing at least a portion of process 600 includes executable code in 604 for determining one or more objects represented in a plurality of frames. The system may determine one or more bounding boxes that represent one or more objects represented in a plurality of frames. In some examples, each bounding box represents a specific object shown in one of the plurality of frames. A bounding box may be defined by a set of coordinates corresponding to the locations of the corners of the bounding box relative to the frame. The system may compute one or more bounding boxes for each frame of the plurality of frames. The system may determine the bounding boxes using one or more detectors and / or trackers (for example, detector 114 and / or tracker 116 in Figure 1). Detectors and / or trackers are sometimes referred to as a first neural network.

[0065] In at least one embodiment, a system performing at least a portion of process 600 includes executable code in 606 to cause a parallel processing unit to compute the movement of one or more objects represented in one or more pixels between frames of a plurality of frames. The parallel processing unit may be part of a hardware accelerator or other hardware device / system. The system may cause the parallel processing unit to compute one or more flow fields indicating the movement of one or more objects represented in one or more pixels between frames of a plurality of frames (e.g., by interacting with a hardware accelerator through hardware and / or software). In some examples, pixels correspond to one or more objects represented or otherwise shown in a frame, where one or more flow fields indicate the movement of one or more objects between frames. The system may cause the parallel processing unit to compute flow fields for each pair of frames of a plurality of frames (e.g., flow fields for the first and second frames, flow fields for the second and third frames, etc.).

[0066] In at least one embodiment, a system performing at least a portion of process 600 includes executable code in 608 to cause a neural network to classify one or more actions performed by one or more objects and represented in a plurality of frames, at least in part on computed movement and one or more objects determined. The system may perform one or more cropping operations on a flow field corresponding to computed movement and on a plurality of frames, based on bounding boxes corresponding to the determined objects. In some examples, the flow field may represent the movement of each pixel between a pair of frames and may be called one or more movement between frames, where the cropped flow field is called one or more cropped movement between frames. The system may perform a first set of cropping operations on the flow field to crop the flow field to produce a cropped flow field corresponding to an area or region of the corresponding frame indicated by the bounding box. The system may perform a second set of cropping operations on a plurality of frames to crop the frames to produce a cropped frame corresponding to an area or region indicated by the bounding box.

[0067] The system can process cropped movement and cropped frames using various action recognition models (for example, action recognition model 126 in Figure 1). Action recognition models are sometimes called second neural networks. Action recognition models can utilize various neural network models for action recognition, such as perceptron models, radial basis networks (RBNs), autoencoders (AEs), Boltzmann machines (BMs), restricted Boltzmann machines (RBMs), deep belief networks (DBNs), deep convolutional networks (DCNs), extreme learning machines (ELMs), deep residual networks (DRNs), and / or variations thereof. Action recognition models can utilize one or more classifier neural network algorithms and / or models, such as logistic regression models, naive Bayesian models, stochastic gradient descent models, K-nearest neighbor models, decision tree models, random forest models, support vector machine models, and / or variations thereof.

[0068] The system may classify one or more actions through one or more action classifications using various action recognition models. An action classification can be a classification or other identifier that indicates an action. The system may determine an action classification for each action represented in multiple frames. Actions represented in multiple frames that can be indicated by an action classification may include actions such as sitting, walking, running, climbing (e.g., climbing obstacles such as walls, stairs, and / or variations thereof), jumping, and / or any suitable action. For example, a walking action represented in multiple frames (e.g., performed by an object represented in multiple frames) may be indicated by a label and / or variations thereof that includes the action classification indicated by “walking”.

[0069] In one embodiment, one or more neural networks utilized by and / or associated with a system that implements at least a portion of process 600 undergo one or more pruning and quantization processes. One or more pruning processes may include those involving pruning weights, kernels, and / or variations thereof, as well as any suitable pruning processes based on any suitable logic, heuristics, rules, functions, and / or variations thereof. In some examples, pruning is performed by the system by calculating the L1 norm values ​​of the kernels of one or more neural networks and removing kernels with L1 norm values ​​below a defined threshold; further information regarding pruning can be found in the description of Figure 2. One or more quantization processes may include any suitable quantization processes, such as various QAT processes and / or PTQ processes. In some examples, quantization is performed by the system by converting one or more weights of one or more neural networks from a first data type (e.g., floating-point 32-bit precision representation (FP32)) to a second data type (e.g., 8-bit integer representation (INT8)) using any suitable logic, heuristics, rules, functions, and / or variations thereof. Further information regarding quantization can be found in the description in Figure 3.

[0070] A system performing at least a portion of process 600 may perform one or more processes of process 600 in real time. In one embodiment, real time or real-time processing may refer to processing in which an input is processed within a time interval in which the input is generated. The system may process multiple frames of video to classify one or more actions represented in multiple frames within a time interval in which the system acquires multiple frames of video, where the time interval may be on the order of milliseconds, microseconds, or any preferred time interval.

[0071] A system that performs at least part of process 600 may be a computing system such as one or more computing systems of one or more devices or systems, including vehicles (e.g., manual vehicles, semi-autonomous vehicles, autonomous vehicles, or drones), robots, edge devices, or other systems with neural network capabilities. Edge devices may refer to computing devices such as mobile phones, tablets, laptops, IoT devices (e.g., sensors, embedded devices), and / or variations thereof. In one embodiment, the edge device is a computing device with limited memory and / or processing power. The edge device may perform one or more processes of process 600, and may perform one or more processes in real time. For example, the edge device may take at least multiple frames of video, cause a processing unit associated with the edge device (e.g., a parallel processing unit) to compute the movement of each pixel between the frames of the multiple frames, determine the objects represented in the multiple frames, and cause a neural network to classify one or more actions represented in the multiple frames, at least in part on the computed movement and the determined objects.

[0072] Although processes 602-608 of process 600 are shown as a sequence, it should be noted that embodiments may omit some of processes 602-608, perform some of them in parallel or in an order other than that shown, or include additional steps in addition to those shown in process 600. Therefore, the order shown in Figure 6 should not be interpreted in a manner that limits potential embodiments to only those that conform to the shown order.

[0073] Reasoning and training logic Figure 7A shows the inference and / or training logic 715 used to perform inference and / or training operations related to one or more embodiments. Further details regarding the inference and / or training logic 715 are provided below in conjunction with Figures 7A and / or 7B.

[0074] In at least one embodiment, the inference and / or training logic 715 may include, but not limited to, code and / or data storage 701 for storing forward and / or output weights and / or input / output data, and / or other parameters, for constituting neurons or layers of a neural network used for training and / or inference in one or more embodiments. In at least one embodiment, the training logic 715 may include, or be coupled to, code and / or data storage 701 for storing graph code or other software for controlling timing and / or sequence, and weight and / or other parameter information should be loaded into the code and / or data storage 701 to constitute logic including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, the code, such as graph code, loads weight or other parameter information into the processor ALU based on the architecture of the neural network to which such code corresponds. In at least one embodiment, the code and / or data storage 701 stores the weight parameters and / or input / output data of each layer of the neural network being trained or used in conjunction with one or more embodiments during the forward propagation of input / output data and / or weight parameters during training and / or inference using the embodiments of one or more embodiments. In at least one embodiment, any portion of the code and / or data storage 701 may be included together with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0075] In at least one embodiment, any portion of the code and / or data storage 701 may be inside or outside one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or code and / or data storage 701 may be cache memory, dynamic randomly addressable memory ("DRAM"), static randomly addressable memory ("SRAM"), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the selection of whether the code and / or code and / or data storage 701 is inside or outside the processor, or whether it includes DRAM, SRAM, flash, or any other type of storage, may depend on available storage, on-chip vs. off-chip, latency requirements of the training and / or inference functions being performed, batch size of data used in neural network inference and / or training, or any combination of these factors.

[0076] In at least one embodiment, the inference and / or training logic 715 may include code and / or data storage 705 for storing backward and / or output weights and / or input / output data corresponding to neurons or layers of a neural network used to train and / or infer in one or more embodiments, but not limited to. In at least one embodiment, the code and / or data storage 705 stores weight parameters and / or input / output data for each layer of the neural network used to train or in conjunction with one or more embodiments during backward propagation of input / output data and / or weight parameters during training and / or inference using one or more embodiments. In at least one embodiment, the training logic 715 may include, or be coupled to, code and / or data storage 705 for storing graph code or other software for controlling timing and / or sequence, in which weight and / or other parameter information should be loaded into the code and / or data storage 705 to constitute logic including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)).

[0077] In at least one embodiment, code such as graph code triggers the loading of weight or other parameter information into the processor ALU based on the architecture of the corresponding neural network. In at least one embodiment, any part of the code and / or data storage 705 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any part of the code and / or data storage 705 may be inside or outside one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 705 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the selection of whether the code and / or data storage 705 is, for example, internal or external to the processor, or whether it includes DRAM, SRAM, flash memory, or any other type of storage, may depend on the available storage, on-chip vs. off-chip, latency requirements of the training and / or inference functions being performed, the batch size of the data used in the neural network inference and / or training, or any combination of these factors.

[0078] In at least one embodiment, the code and / or data storage 701 and the code and / or data storage 705 may be separate storage structures. In at least one embodiment, the code and / or data storage 701 and the code and / or data storage 705 may be a combined storage structure. In at least one embodiment, the code and / or data storage 701 and the code and / or data storage 705 may be partially combined and partially separate. In at least one embodiment, any portion of the code and / or data storage 701 and the code and / or data storage 705 may be included together with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0079] In at least one embodiment, the inference and / or training logic 715 may include, but not limited to, one or more arithmetic logic units ("ALUs") 710, including integer and / or floating-point units, for performing logical and / or mathematical operations that are at least partially based on or shown by training and / or inference code (e.g., graph code), the result of which activations (e.g., output values ​​from layers or neurons in a neural network) stored in activation storage 720, and these activations are functions of input / output and / or weight parameter data stored in code and / or data storage 701 and / or code and / or data storage 705. In at least one embodiment, the activation stored in the activation storage 720 is generated according to linear algebra and / or matrix-based mathematics performed by (one or more) ALUs 710 in response to the execution of an instruction or other code, and the weight values ​​stored in the code and / or data storage 705 and / or data storage 701 are used as operands along with other values ​​such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in the code and / or data storage 705 or the code and / or data storage 701, or in other on-chip or off-chip storage.

[0080] In at least one embodiment, the (one or more) ALU 710 are contained within one or more processors or other hardware logic devices or circuits, but in another embodiment, the (one or more) ALU 710 may be outside of the processors or other hardware logic devices or circuits (e.g., coprocessors) that use them. In at least one embodiment, the ALU 710 may be contained within an execution unit of a processor, or otherwise contained within a bank of ALUs accessible by execution units of a processor, either within the same processor or distributed across different types of processors (e.g., a central processing unit, a graphics processing unit, a fixed-function unit, etc.). In at least one embodiment, the code and / or data storage 701, the code and / or data storage 705, and the activation storage 720 may share a processor or other hardware logic devices or circuits, but in another embodiment, they may be in different processors or other hardware logic devices or circuits, or in some combination of the same processor or other hardware logic devices or circuits and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of the activated storage 720 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Furthermore, inference and / or training code may be stored together with other code accessible to the processor or other hardware logic or circuitry, and may be fetched and / or processed using the processor's fetch, decode, schedule, execute, retirement, and / or other logic circuits.

[0081] In at least one embodiment, the activated storage 720 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the activated storage 720 may be located entirely or partially within or outside one or more processors or other logic circuits. In at least one embodiment, the selection of whether the activated storage 720 is located, for example, inside or outside the processor, or whether it includes DRAM, SRAM, flash memory, or any other storage type may depend on the available storage, on-chip vs. off-chip, latency requirements of the training and / or inference functions being performed, batch size of data used in neural network inference and / or training, or any combination of these factors.

[0082] In at least one embodiment, the inference and / or training logic 715 shown in Figure 7A may be used in conjunction with an application-specific integrated circuit ("ASIC"), such as a TensorFlow® processing unit from Google, an inference processing unit (IPU) from Graphcore®, or a Nervana® (e.g., "Lake Crest") processor from Intel Corp. In at least one embodiment, the inference and / or training logic 715 shown in Figure 7A may be used in conjunction with other hardware, such as a central processing unit ("CPU") hardware, a graphics processing unit ("GPU") hardware, or a field-programmable gate array ("FPGA").

[0083] Figure 7B shows inference and / or training logic 715 according to at least one embodiment. In at least one embodiment, the inference and / or training logic 715 may include, but is not limited to, hardware logic in which computational resources are dedicated or, otherwise, used only in conjunction with weight values ​​or other information corresponding to one or more layers of neurons in a neural network. In at least one embodiment, the inference and / or training logic 715 shown in Figure 7B may be used in conjunction with application-specific integrated circuits (ASICs), such as a TensorFlow® processing unit from Google, an inference processing unit (IPU) from Graphcore®, or a Nervana® (e.g., "Lake Crest") processor from Intel Corp. In at least one embodiment, the inference and / or training logic 715 shown in Figure 7B may be used in conjunction with other hardware, such as a central processing unit (CPU) hardware, a graphics processing unit (GPU) hardware, or a field-programmable gate array (FPGA). In at least one embodiment, the inference and / or training logic 715 includes, but is not limited to, code and / or data storage 701 and code and / or data storage 705, which may be used to store code (e.g., graph code), weight values, and / or other information including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. In at least one embodiment shown in Figure 7B, each of the code and / or data storage 701 and code and / or data storage 705 is associated with a dedicated computing resource, such as compute hardware 702 and compute hardware 706, respectively. In at least one embodiment, each of the compute hardware 702 and compute hardware 706 comprises one or more ALUs that perform mathematical functions, such as linear algebraic functions, only on the information stored in the code and / or data storage 701 and code and / or data storage 705, respectively, and the results are stored in the activation storage 720.

[0084] In at least one embodiment, each of the code and / or data storages 701 and 705 and the corresponding compute hardware 702 and 706 correspond to different layers of a neural network, so that the activation resulting from one storage / compute pair 701 / 702 of the code and / or data storage 701 and compute hardware 702 is provided as input to the next storage / compute pair 705 / 706 of the code and / or data storage 705 and compute hardware 706 to mirror the conceptual organization of the neural network. In at least one embodiment, the storage / compute pairs 701 / 702 and 705 / 706 may correspond to two or more neural network layers. In at least one embodiment, additional storage / compute pairs (not shown) may be included in the inference and / or training logic 715 after or in parallel with the storage / compute pairs 701 / 702 and 705 / 706.

[0085] In at least one embodiment, one or more systems shown in Figures 7A-7B are used to implement a system for action recognition as described with respect to Figures 1-6. In at least one embodiment, one or more systems shown in Figures 7A-7B are used to perform one or more quantization and pruning processes on one or more neural networks. In at least one embodiment, one or more systems shown in Figures 7A-7B are used to perform action recognition using a hardware accelerator and / or one or more neural networks processed through one or more quantization and pruning processes.

[0086] Neural network training and implementation Figure 8 shows the training and deployment of a deep neural network in at least one embodiment. In at least one embodiment, an untrained neural network 806 is trained using a training dataset 802. In at least one embodiment, the training framework 804 is the PyTorch framework, while in other embodiments, the training framework 804 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frameworks. In at least one embodiment, the training framework 804 trains the untrained neural network 806 and enables it to be trained using the processing resources described herein to produce a trained neural network 808. In at least one embodiment, the weights may be randomly selected or selected by pre-training using a deep belief network. In at least one embodiment, training may be performed in a supervised, partially supervised, or unsupervised manner.

[0087] In at least one embodiment, an untrained neural network 806 is trained using supervised learning, and the training dataset 802 contains inputs paired with desired outputs for inputs, or the training dataset 802 contains inputs with known outputs, and the outputs of the neural network 806 are manually scored. In at least one embodiment, the untrained neural network 806 is trained in a supervised manner, processing inputs from the training dataset 802 and comparing the resulting outputs to a set of expected or desired outputs. In at least one embodiment, errors are then backpropagated through the untrained neural network 806. In at least one embodiment, the training framework 804 adjusts the weights controlling the untrained neural network 806. In at least one embodiment, the training framework 804 includes tools for monitoring how well the untrained neural network 806 is converging toward a model such as a trained neural network 808 that is suitable for generating the correct answer in result 814, etc., based on input data such as a new dataset 812. In at least one embodiment, the training framework 804 iteratively trains the untrained neural network 806, adjusting the weights to improve the output of the untrained neural network 806 using a loss function and a modulating algorithm such as stochastic gradient descent. In at least one embodiment, the training framework 804 trains the untrained neural network 806 until it achieves a desired accuracy. In at least one embodiment, the trained neural network 808 may then be introduced to implement any number of machine learning operations.

[0088] In at least one embodiment, an untrained neural network 806 is trained using unsupervised learning, and the untrained neural network 806 attempts to train itself using unlabeled data. In at least one embodiment, the unsupervised learning training dataset 802 includes input data that has no associated output data or “ground truth” data. In at least one embodiment, the untrained neural network 806 can learn grouping within the training dataset 802 and determine how individual inputs relate to the untrained dataset 802. In at least one embodiment, unsupervised training may be used to generate a self-organizing map in a trained neural network 808 that is capable of performing useful operations in reducing the dimensionality of a new dataset 812. In at least one embodiment, unsupervised training may also be used to perform anomaly detection, which enables the identification of data points in the new dataset 812 that deviate from the normal pattern of the new dataset 812.

[0089] In at least one embodiment, semi-supervised learning may be used, which is a technique that includes a mixture of labeled and unlabeled data in the training dataset 802. In at least one embodiment, the training framework 804 may be used to implement incremental learning, such as through a transfer learning technique. In at least one embodiment, incremental learning allows the trained neural network 808 to adapt to a new dataset 812 without forgetting the knowledge that was taught within the trained neural network 808 during the initial training.

[0090] In at least one embodiment, one or more systems shown in Figure 8 are used to implement a system for action recognition as described with respect to Figures 1 to 6. In at least one embodiment, one or more systems shown in Figure 8 are used to perform one or more quantization and pruning processes on one or more neural networks. In at least one embodiment, one or more systems shown in Figure 8 are used to perform action recognition using a hardware accelerator and / or one or more neural networks processed through one or more quantization and pruning processes.

[0091] Data center Figure 9 shows an exemplary data center 900 in which at least one embodiment may be used. In at least one embodiment, the data center 900 includes a data center infrastructure layer 910, a framework layer 920, a software layer 930, and an application layer 940.

[0092] In at least one embodiment, as shown in Figure 9, the data center infrastructure layer 910 may include a resource orchestrator 912, grouped computing resources 914, and node computing resources ("node CRs") 916(1) to 916(N), where "N" represents a positive integer (which may be a different integer "N" than that used in other figures). In at least one embodiment, nodes CR916(1) to 916(N) may include, but not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field-programmable gate arrays (FPGAs), graphics processors, etc.), memory and storage devices 918(1) to 918(N) (e.g., dynamic read-only memory, solid-state storage, or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VMs"), power modules, and cooling modules, etc. In at least one embodiment, one or more nodes CR from among nodes CR916(1) to 916(N) may be servers having one or more of the computing resources described above.

[0093] In at least one embodiment, the grouped computing resources 914 may include separate groupings of node CRs housed in one or more racks (not shown), or many racks housed in a data center at various geographical locations (also not shown). In at least one embodiment, the separate groupings of node CRs within the grouped computing resources 914 may include grouped compute resources, network resources, memory resources, or storage resources that can be configured or allocated to support one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped in one or more racks to provide compute resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0094] In at least one embodiment, the resource orchestrator 912 may configure or otherwise control one or more nodes CR916(1) to 916(N) and / or a grouped computing resource 914. In at least one embodiment, the resource orchestrator 912 may include a software design infrastructure ("SDI") management entity for the data center 900. In at least one embodiment, the resource orchestrator 712 may include hardware, software, or any combination thereof.

[0095] In at least one embodiment, as shown in Figure 9, the framework layer 920 includes a job scheduler 922, a configuration manager 924, a resource manager 926, and a distributed file system 928. In at least one embodiment, the framework layer 920 may include a framework for supporting software 932 of the software layer 930 and / or one or more applications 942 of the application layer 940. In at least one embodiment, the software 932 or (one or more) applications 942 may each include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 920 may be a type of free and open-source software web application framework, such as Apache Spark® ("Spark"), which can leverage the distributed file system 928 for large-scale data processing (e.g., "big data"). In at least one embodiment, the job scheduler 922 may include a Spark driver to facilitate scheduling of workloads supported by various layers of the data center 900. In at least one embodiment, the configuration manager 924 may be able to configure different layers, such as the software layer 930 and the framework layer 920, which includes Spark and a distributed file system 928 to support large-scale data processing. In at least one embodiment, the resource manager 926 may be able to manage clustered or grouped computing resources that are mapped or allocated to support the distributed file system 928 and the job scheduler 922. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 914 in the data center infrastructure layer 910.In at least one embodiment, the resource manager 926 may work in conjunction with the resource orchestrator 912 to manage these mapped or allocated computing resources.

[0096] In at least one embodiment, the software 932 contained within the software layer 930 may include software used by nodes CR916(1) to 916(N), grouped computing resources 914, and / or at least a portion of the distributed file system 928 of the framework layer 920. In at least one embodiment, one or more types of software may include, but are not limited to, internet web page search software, email virus scanning software, database software, and streaming video content software.

[0097] In at least one embodiment, one or more applications 942 included in the application layer 940 may include one or more types of applications used by nodes CR916(1) to 916(N), grouped computing resources 914, and / or at least a portion of the distributed file system 928 of the framework layer 920. In at least one embodiment, one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive compute applications, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0098] In at least one embodiment, any of the configuration manager 924, resource manager 926, and resource orchestrator 912 may implement any number and type of self-correcting actions based on any amount and type of data obtained in any technically feasible manner. In at least one embodiment, the self-correcting actions may relieve the data center operator of data center 900 of the task of determining potentially faulty configurations and potentially avoiding underutilized and / or underperforming portions of the data center.

[0099] In at least one embodiment, the data center 900 may include tools, services, software, or other resources for training one or more machine learning models or for predicting or inferring information using one or more machine learning models according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by computing weight parameters according to a neural network architecture using the software and computing resources described above with respect to the data center 900. In at least one embodiment, a trained machine learning model corresponding to one or more neural networks may be used to infer or predict information using the resources described above with respect to the data center 900 by using weight parameters computed through one or more training techniques described herein.

[0100] In at least one embodiment, the data center may use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to perform training and / or inference using the resources described above. Furthermore, one or more of the software and / or hardware resources described above may be configured as services that enable users to train information or perform inference on information, such as image recognition, speech recognition, or other artificial intelligence services.

[0101] The inference and / or training logic 715 is used to perform inference and / or training operations related to one or more embodiments. Details relating to the inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, the inference and / or training logic 715 may be used in the system of Figure 9 for inference or prediction operations, at least in part, based on weight parameters calculated using the neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0102] In at least one embodiment, one or more systems shown in Figure 9 are used to implement a system for action recognition as described with respect to Figures 1 to 6. In at least one embodiment, one or more systems shown in Figure 9 are used to perform one or more quantization and pruning processes on one or more neural networks. In at least one embodiment, one or more systems shown in Figure 9 are used to perform action recognition using a hardware accelerator and / or one or more neural networks processed through one or more quantization and pruning processes.

[0103] Autonomous vehicles Figure 10A shows an example of an autonomous vehicle 1000 according to at least one embodiment. In at least one embodiment, the autonomous vehicle 1000 (alternatively referred to herein as "vehicle 1000") may be a passenger vehicle, including, but not limited to, a car, truck, bus, and / or another type of vehicle that accommodates one or more passengers. In at least one embodiment, vehicle 1000 may be a semi-tractor-trailer truck used for transporting cargo. In at least one embodiment, vehicle 1000 may be an aircraft, a robotic vehicle, or another type of vehicle.

[0104] Autonomous vehicles can be described in terms of automation levels as defined by the National Highway Traffic Safety Administration ("NHTSA"), a division of the U.S. Department of Transportation, and Non-Patent Document 1 of the Society of Automotive Engineers ("SAE"). In at least one embodiment, vehicle 1000 may be capable of functioning at one or more of the autonomous driving levels from Level 1 to Level 5. For example, in at least one embodiment, vehicle 1000 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on the embodiment.

[0105] In at least one embodiment, the vehicle 1000 may include components such as a chassis, a vehicle body, wheels (e.g., two, four, six, eight, eighteen, etc.), tires, axles, and other components of the vehicle. In at least one embodiment, the vehicle 1000 may include a propulsion system 1050, such as an internal combustion engine, a hybrid power plant, a fully electric engine, and / or another propulsion system type. In at least one embodiment, the propulsion system 1050 may be connected to the drivetrain of the vehicle 1000, and the drivetrain may include a transmission to enable the propulsion of the vehicle 1000, but is not limited. In at least one embodiment, the propulsion system 1050 may be controlled in response to receiving a signal from one or more throttles / accelerators 1052.

[0106] In at least one embodiment, a steering system 1054, which may include a steering wheel, is used to steer the vehicle 1000 (for example, along a desired path or route) when the propulsion system 1050 is operating (for example, when the vehicle 1000 is moving). In at least one embodiment, the steering system 1054 may receive signals from one or more steering actuators 1056. In at least one embodiment, the steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, a brake sensor system 1046 may be used to operate the vehicle brakes in response to receiving signals from one or more brake actuators 1048 and / or brake sensors.

[0107] In at least one embodiment, but not limited to, one or more controllers 1036 which may include one or more system-on-chip ("SoC") (not shown in Figure 10A) and / or one or more graphics processing units ("GPU") provide signals (for example, representing commands) to one or more components and / or systems of the vehicle 1000. For example, in at least one embodiment, one or more controllers 1036 may send signals to operate the vehicle brakes via one or more brake actuators 1048, signals to operate the steering system 1054 via one or more steering actuators 1056, and signals to operate the propulsion system 1050 via one or more throttle / accelerators 1052. In at least one embodiment, the controller 1036 (one or more) may include one or more onboard (e.g., integrated) computing devices that process sensor signals and output operational commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving the vehicle 1000. In at least one embodiment, the controller 1036 (one or more) may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functions (e.g., computer vision), a fourth controller for infotainment functions, a fifth controller for emergency redundancy, and / or other controllers. In at least one embodiment, a single controller may address two or more of the above functions, two or more controllers may address a single function, and / or any combination thereof.

[0108] In at least one embodiment, one or more controllers 1036 provide signals for controlling one or more components and / or systems of the vehicle 1000 in response to sensor data (e.g., sensor inputs) received from one or more sensors. In at least one embodiment, the sensor data may include, but are not limited to, one or more global navigation satellite system ("GNSS") sensors 1058 (e.g., one or more global positioning system sensors), one or more radar sensors 1060, one or more ultrasonic sensors 1062, one or more lithium-ion sensors 1064, or one or more inertial measurement units ("IMUs"). The unit includes: 1066 sensors (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), 1096 microphones, 1068 stereo cameras, 1070 wide-angle cameras (e.g., fisheye cameras), 1072 infrared cameras, and 1074 ambient cameras (e.g., 360-degree cameras). ), long-range cameras (not shown in Figure 10A), (one or more) medium-range cameras (not shown in Figure 10A), (one or more) speed sensors 1044 (for measuring the speed of vehicle 1000), (one or more) vibration sensors 1042, (one or more) steering sensors 1040, (one or more) brake sensors (for example, as part of a brake sensor system 1046), and / or other sensor types may be received.

[0109] In at least one embodiment, one or more of the (one or more) controllers 1036 may receive inputs (represented, for example, by input data) from the instrument cluster 1032 of the vehicle 1000 and provide outputs (represented, for example, by output data, display data, etc.) via the human-machine interface ("HMI") display 1034, an audible annunciator, a loudspeaker, and / or other components of the vehicle 1000. In at least one embodiment, the outputs may include information such as vehicle speed, vehicle speed, time, map data (e.g., a high-resolution map (not shown in Figure 10A)), location data (e.g., the location of the vehicle 1000, such as on a map), direction, location of other vehicles (e.g., an occupied grid), and information about objects and the status of objects sensed by the (one or more) controllers 1036. For example, in at least one embodiment, the HMI display 1034 may display information regarding the presence of one or more objects (e.g., road signs, warning signs, changes in traffic signals, etc.) and / or information regarding driving operations that the vehicle has performed, is performing, or will perform (e.g., currently changing lanes, exiting at Exit 34B 3.22 km (2 miles) ahead, etc.).

[0110] In at least one embodiment, the vehicle 1000 further includes a network interface 1024, which may use (one or more) wireless antennas 1026 and / or (one or more) modems to communicate over one or more networks. For example, in at least one embodiment, the network interface 1024 may be capable of communicating over Long-Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA®"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile Communication ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000") networks, and the like. Furthermore, in at least one embodiment, one or more wireless antennas 1026 may enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.) using one or more local area networks such as Bluetooth, Bluetooth Low Energy ("LE"), Z-wave, ZigBee, and / or one or more low-power wide-area networks ("LPWAN") such as protocols such as LoRaWAN, SigFox, etc.

[0111] The inference and / or training logic 715 is used to perform inference and / or training operations related to one or more embodiments. Details relating to the inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, the inference and / or training logic 715 may be used in the system of Figure 10A for inference or prediction operations, at least in part, based on weight parameters calculated using the neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0112] Figure 10B shows an example of camera locations and fields of view for the autonomous vehicle 1000 of Figure 10A, according to at least one embodiment. In at least one embodiment, the cameras and their respective fields of view are exemplary embodiments and are not limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included, and / or the cameras may be located in different locations on the vehicle 1000.

[0113] In at least one embodiment, the camera type for a camera may include, but is not limited to, a digital camera that can be adapted for use with components and / or systems of vehicle 1000. In at least one embodiment, one or more cameras may operate at Automotive Safety Integrity Level ("ASIL") B and / or another ASIL. In at least one embodiment, the camera type may be capable of any image capture rate, depending on the embodiment, such as 60 frames per second (fps), 1220 fps, 240 fps, etc. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red, clear, clear, clear ("RCCC") color filter array, a red, clear, clear, blue ("RCCB") color filter array, a red, blue, green, clear ("RBGC") color filter array, a Foveon X3 color filter array, a Bayer sensor ("RGGB") color filter array, a monochrome sensor color filter array, and / or other types of color filter arrays. In at least one embodiment, a clear pixel camera may be used to increase light sensitivity, such as a camera with RCCC, RCCB, and / or RBGC color filter arrays.

[0114] In at least one embodiment, one or more of the cameras may be used to implement advanced driver assistance system ("ADAS") functions (for example, as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function mono-camera may be installed to provide functions including lane departure warning, traffic sign assistance, and intelligent headlight control. In at least one embodiment, one or more of the cameras (for example, all of the cameras) may simultaneously record and provide image data (for example, video).

[0115] In at least one embodiment, one or more cameras may be mounted in a mounting assembly, such as a custom-designed (three-dimensional ("3D") printed) assembly, to eliminate stray light and reflections from within the vehicle (e.g., reflections from the dashboard to the windshield) that could interfere with the camera image data capture ability. Referring to a door mirror mounting assembly, in at least one embodiment, the door mirror assembly may be custom 3D printed so that the camera mounting plate matches the shape of the door mirror. In at least one embodiment, one or more cameras may be integrated into the door mirror. In at least one embodiment, for a side-view camera, one or more cameras may be integrated into the four pillars at each corner of the cabin.

[0116] In at least one embodiment, a camera having a field of view including a portion of the environment in front of the vehicle 1000 (e.g., a front camera) may be used for a perimeter view to help identify the path and obstacles ahead and to assist in providing information essential for generating an occupied grid and / or determining a preferred vehicle path, with the help of one or more of the controllers 1036 and / or control SoCs. In at least one embodiment, the front camera may be used to implement many ADAS functions similar to LIDAR, including, but not limited to, emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the front camera may also be used for ADAS functions and systems, including, but not limited to, lane departure warning ("LDW"), autonomous cruise control ("ACC"), and / or traffic sign recognition.

[0117] In at least one embodiment, various cameras, including a monocular camera platform including, for example, a CMOS ("complementary metal oxide semiconductor") color imager, may be used in a front configuration. In at least one embodiment, a wide-angle camera 1070 may be used to perceive objects entering the view from the periphery (e.g., pedestrians, crossing traffic, or bicycles). Although only one wide-angle camera 1070 is shown in Figure 10B, in other embodiments, there may be any number of wide-angle cameras (including zero) on the vehicle 1000. In at least one embodiment, any number of long-range cameras 1098 (e.g., long-view stereo camera pairs) may be used for depth-based object detection, particularly for objects for which a neural network has not yet been trained. In at least one embodiment, the long-range cameras 1098 may also be used for object detection and classification, as well as basic object tracking.

[0118] In at least one embodiment, any number of stereo cameras 1068 may also be included in the front configuration. In at least one embodiment, one or more of the (one or more) stereo cameras 1068 may include an integrated control unit with a scalable processing unit, which may provide a programmable logic ("FPGA") and a multicore microprocessor having an integrated Controller Area Network ("CAN") or Ethernet interface on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the environment of the vehicle 1000, including distance estimation for all points in the image. In at least one embodiment, one or more of the (one or more) stereo cameras 1068 may include, but are not limited to, one or more compact stereo vision sensors, which may include, but are not limited to, two camera lenses (one on the left and one on the right) and an image processing chip capable of measuring the distance from a vehicle 1000 to a target object and using the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of (one or more) stereo cameras 1068 may be used in addition to or as an alternative to those described herein.

[0119] In at least one embodiment, a camera having a field of view that includes a portion of the environment to the sides of the vehicle 1000 (e.g., a side-view camera) may be used for the surrounding view and provide information used to create and update the occupy grid and generate side collision warnings. For example, in at least one embodiment, one or more surrounding cameras 1074 (e.g., four surrounding cameras shown in Figure 10B) may be positioned on the vehicle 1000. In at least one embodiment, one or more surrounding cameras 1074 may include, but are not limited to, any number and combination of wide-angle cameras, one or more fisheye cameras, one or more 360-degree cameras, and / or similar cameras. For example, in at least one embodiment, four fisheye cameras may be positioned in front of, behind, and to the sides of the vehicle 1000. In at least one embodiment, the vehicle 1000 may use three surrounding cameras 1074 (e.g., left, right, and rear) and may utilize one or more other cameras (e.g., a front camera) as a fourth surrounding view camera.

[0120] In at least one embodiment, a camera having a field of view that includes a portion of the environment behind the vehicle 1000 (e.g., a rear-view camera) may be used for parking assistance, surrounding view, rear collision warning, and creation and updating of the occupancy grid. In at least one embodiment, a wide variety of cameras may be used, including, but not limited to, cameras that are also suitable as (one or more) front cameras as described herein (e.g., a long-range camera 1098 and / or (one or more) medium-range cameras 1076, (one or more) stereo cameras 1068, (one or more) infrared cameras 1072, etc.).

[0121] The inference and / or training logic 715 is used to perform inference and / or training operations related to one or more embodiments. Details relating to the inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, the inference and / or training logic 715 may be used in the system of Figure 10B for inference or prediction operations, at least in part, based on weight parameters calculated using the neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0122] Figure 10C is a block diagram illustrating an exemplary system architecture for the autonomous vehicle 1000 of Figure 10A, according to at least one embodiment. In at least one embodiment, each of the components, features, and systems of the vehicle 1000 in Figure 10C is shown as being connected via a bus 1002. In at least one embodiment, the bus 1002 may include, but is not limited to, a CAN data interface (alternatively referred to herein as the “CAN bus”). In at least one embodiment, the CAN may be an internal network of the vehicle 1000 used to assist in the control of various features and functionalities of the vehicle 1000, such as brake activation, acceleration, brake control, steering, and windshield wipers. In at least one embodiment, the bus 1002 may be configured to have tens or even hundreds of nodes, each having its own unique identifier (e.g., a CAN ID). In at least one embodiment, bus 1002 may be read to find the steering angle, ground speed, engine revolutions per minute ("RPM"), button position, and / or other vehicle status indicators. In at least one embodiment, bus 1002 may be an ASIL B compliant CAN bus.

[0123] In at least one embodiment, the FlexRay and / or Ethernet protocols may be used in addition to or as an alternative to CAN. In at least one embodiment, there may be any number of buses forming bus 1002, which may include, but are not limited to, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using different protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or for redundancy. For example, a first bus may be used for collision avoidance functionality and a second bus may be used for operation control. In at least one embodiment, each bus of bus 1002 may communicate with any of the components of vehicle 1000, and two or more buses of bus 1002 may communicate with corresponding components. In at least one embodiment, each of any number of system-on-chip ("SoC") 1004 (such as SoC 1004(A) and SoC 1004(B)), each of the (one or more) controllers 1036, and / or each computer in the vehicle may have access to the same input data (e.g., inputs from sensors in the vehicle 1000) and may be connected to a common bus such as a CAN bus.

[0124] In at least one embodiment, the vehicle 1000 may include one or more controllers 1036, such as those described herein with respect to Figure 10A. In at least one embodiment, one or more controllers 1036 may be used for a variety of functions. In at least one embodiment, one or more controllers 1036 may be coupled to any of the various other components and systems of the vehicle 1000 and may be used for controlling the vehicle 1000, the artificial intelligence of the vehicle 1000, infotainment for the vehicle 1000, and / or other functions.

[0125] In at least one embodiment, the vehicle 1000 may include any number of SoCs 1004. In at least one embodiment, each of the SoCs 1004 may include, but not limited to, a central processing unit ("CPU") 1006, a graphics processing unit ("GPU") 1008, one or more processors 1010, one or more caches 1012, one or more accelerators 1014, one or more data stores 1016, and / or other components and features not shown. In at least one embodiment, one or more SoCs 1004 may be used to control the vehicle 1000 on various platforms and systems. For example, in at least one embodiment, one or more SoCs 1004 may be combined in a system (for example, a system for a vehicle 1000) that has a high-definition ("HD") map 1022 that can receive map refreshes and / or updates from one or more servers (not shown in Figure 10C) via a network interface 1024.

[0126] In at least one embodiment, one or more CPUs 1006 may include a CPU cluster or CPU complex (alternatively referred to herein as “CCPLEX”). In at least one embodiment, one or more CPUs 1006 may include multiple cores and / or Level 2 ("L2") caches. For example, in at least one embodiment, one or more CPUs 1006 may include eight cores in a coherent multiprocessor configuration. In at least one embodiment, one or more CPUs 1006 may include four dual-core clusters, each cluster having a dedicated L2 cache (e.g., a 2 megabyte (MB) L2 cache). In at least one embodiment, one or more CPUs 1006 (e.g., CCPLEX) may be configured to support concurrent cluster operation, which allows any combination of clusters of one or more CPUs 1006 to be active at any given time.

[0127] In at least one embodiment, one or more of the (one or more) CPUs 1006 may implement power management capabilities, which include, but are not limited to, one or more of the following features: individual hardware blocks may be automatically clock-gated when idle to conserve dynamic power; each core clock may be gated when such core is not actively executing instructions by executing an interrupt-wait ("WFI") / event-wait ("WFE") instruction; each core may be power-gated independently; each core cluster may be clock-gated independently when all cores are clock-gated or power-gated; and / or each core cluster may be power-gated independently when all cores are power-gated. In at least one embodiment, one or more CPUs 1006 may further implement an extended algorithm for managing power states, where acceptable power states and expected wake-up times are specified, and the hardware / microcode determines which power state is best to enter for the core, cluster, and CCPLEX. In at least one embodiment, the processing core may support a simple power state entry sequence in software where the work is offloaded to the microcode.

[0128] In at least one embodiment, one or more GPUs 1008 may include an integrated GPU (alternatively referred to herein as an “iGPU”). In at least one embodiment, one or more GPUs 1008 may be programmable and efficient for parallel workloads. In at least one embodiment, one or more GPUs 1008 may use an extended tensor instruction set. In at least one embodiment, one or more GPUs 1008 may include one or more streaming microprocessors, each streaming microprocessor may include a Level 1 ("L1") cache (e.g., an L1 cache with at least 96KB of storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with 512KB of storage capacity). In at least one embodiment, one or more GPUs 1008 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPU1008 may use one or more compute application programming interfaces (APIs). In at least one embodiment, one or more GPU1008 may use one or more parallel computing platforms and / or programming models (for example, NVIDIA's CUDA model).

[0129] In at least one embodiment, one or more of the (one or more) GPU1008s may be power-optimized for best performance in automotive and embedded use cases. For example, in at least one embodiment, the (one or more) GPU1008s may be fabricated on Fin field-effect transistor ("FinFET") circuit elements. In at least one embodiment, each streaming microprocessor may incorporate several mixed-precision processing cores divided into multiple blocks. For example, but not limited to, 64 PF32 cores and 32 PF64 cores may be divided into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, 2 mixed-precision NVIDIA Tensor cores for deep learning matrix arithmetic, a Level 0 ("L0") instruction cache, a warp scheduler, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor may include independent parallel integer and floating-point data paths to efficiently execute workloads involving a mixture of computation and addressing calculations. In at least one embodiment, the streaming microprocessor may include independent thread scheduling capabilities to enable finer-grained synchronization and coordination between parallel threads. In at least one embodiment, the streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0130] In at least one embodiment, one or more of the (one or more) GPU1008 may include high-bandwidth memory ("HBM") and / or a 16GB HBM2 memory subsystem to provide a peak memory bandwidth of approximately 900 GB / s in some examples. In at least one embodiment, in addition to or as an alternative to HBM memory, synchronous graphics random-access memory ("SGRAM"), such as graphics double data rate type five synchronous random-access memory ("GDDR5").

[0131] In at least one embodiment, one or more GPUs 1008 may include unified memory technology. In at least one embodiment, address translation service (ATS) support may be used to enable one or more GPUs 1008 to directly access the page tables of one or more CPUs 1006. In at least one embodiment, when a GPU in the GPU 1008 memory management unit (MMU) encounters a miss, an address translation request may be sent to one or more CPUs 1006. In at least one embodiment, in response, two of the CPUs 1006 may look up virtual-physical mappings for addresses in their page tables and send the translation back to one or more GPUs 1008. In at least one embodiment, the unified memory technology enables a single, unified virtual address space for the memory of both the (one or more) CPUs 1006 and the (one or more) GPUs 1008, thereby simplifying the programming of the (one or more) GPUs 1008 and the porting of applications to the (one or more) GPUs 1008.

[0132] In at least one embodiment, one or more GPUs 1008 may include any number of access counters that can track how often one or more GPUs 1008 access the memory of other processors. In at least one embodiment, one or more access counters can help ensure that memory pages are moved to the physical memory of the processor that accesses the page most frequently, thereby improving the efficiency of memory ranges shared between processors.

[0133] In at least one embodiment, one or more of the (one or more) SoC 1004 may include any number of caches 1012, including those described herein. For example, in at least one embodiment, the (one or more) caches 1012 may include a Level 3 ("L3") cache that is available to both the (one or more) CPUs 1006 and the (one or more) GPUs 1008 (for example, connected to the (one or more) CPUs 1006 and the (one or more) GPUs 1008). In at least one embodiment, the (one or more) caches 1012 may include a write-back cache that can track the state of the line, for example by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, the L3 cache may include 4 MB or more of memory, depending on the embodiment, but smaller cache sizes may be used.

[0134] In at least one embodiment, one or more of the (one or more) SoC 1004 may include one or more accelerators 1014 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, the (one or more) SoC 1004 may include a hardware acceleration cluster which may include an optimized hardware accelerator and / or a large on-chip memory. In at least one embodiment, the large on-chip memory (e.g., 4 MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may complement the (one or more) GPU 1008 and be used to offload some of the tasks of the (one or more) GPU 1008 (e.g., to free up more cycles of the (one or more) GPU 1008 to perform other tasks). In at least one embodiment, accelerator 1014 may be used for workloads of interest that are stable enough to accept acceleration (e.g., perception, convolutional neural networks ("CNN"), recurrent neural networks ("RNN"), etc.). In at least one embodiment, the CNN may include region-based CNNs, i.e., regional convolutional neural networks ("RCNN"), and fast RCNNs (such as those used for object detection), or other types of CNNs.

[0135] In at least one embodiment, one or more accelerators 1014 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators ("DLAs"). In at least one embodiment, one or more DLAs may include, but not limited to, one or more Tensor processing units ("TPUs"), which may be configured to provide additional, 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, a TPU may be configured to perform image processing functions (e.g., for CNNs, RCNNs, etc.) and may be an accelerator optimized for that purpose. In at least one embodiment, one or more DLAs may be further optimized for specific neural network types and sets of floating-point operations, as well as for inference. In at least one embodiment, a design of one or more DLAs may provide more performance per millisecond than a typical general-purpose GPU, and generally far exceed the performance of a CPU. In at least one embodiment, one or more TPUs may implement several functions, including, for example, a single-instance convolution function supporting INT8, INT16, and FP16 data types for both features and weights, as well as a post-processing function. In at least one embodiment, one or more DLAs may rapidly and efficiently run neural networks, particularly CNNs, on processed or unprocessed data for any of a variety of functions, including, but not limited to, CNNs for object recognition and detection using data from camera sensors, CNNs for distance estimation using data from camera sensors, CNNs for emergency vehicle detection and identification and detection using data from microphones, CNNs for face recognition and vehicle owner identification using data from camera sensors, and / or CNNs for security and / or safety-related events.

[0136] In at least one embodiment, one or more DLAs may perform any function of one or more GPUs 1008, and for example, by using inference accelerators, the designer may target either one or more DLAs or one or more GPUs 1008 for any function. For example, in at least one embodiment, the designer may concentrate CNN and floating-point arithmetic processing on one or more DLAs and offload other functions to one or more GPUs 1008 and / or one or more accelerators 1014.

[0137] In at least one embodiment, one or more accelerators 1014 may include a programmable vision accelerator ("PVA"), which may be referred to herein as a computer vision accelerator instead. In at least one embodiment, the PVA may be designed and configured to accelerate computer vision algorithms for advanced driver-assistance systems ("ADAS") 1038, autonomous driving, augmented reality ("AR") applications, and / or virtual reality ("VR") applications. In at least one embodiment, the PVA may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA may include, for example, any number of reduced instruction set computer ("RISC") cores, direct memory access ("DMA"), and / or any number of vector processors.

[0138] In at least one embodiment, the RISC core may interact with an image sensor (e.g., an image sensor of any camera described herein), one or more image signal processors, and so on. In at least one embodiment, each RISC core may include any amount of memory. In at least one embodiment, the RISC core may use one of several protocols, depending on the embodiment. In at least one embodiment, the RISC core may run a real-time operating system ("RTOS"). In at least one embodiment, the RISC core may be implemented using one or more integrated circuit devices, application-specific integrated circuits ("ASICs"), and / or memory devices. For example, in at least one embodiment, the RISC core may include an instruction cache and / or tightly coupled RAM.

[0139] In at least one embodiment, the DMA may enable components of the PVA to access system memory independently of one or more CPUs 1006. In at least one embodiment, the DMA may support any number of features used to provide optimization to the PVA, including, but not limited to, support for multidimensional addressing and / or circular addressing. In at least one embodiment, the DMA may support up to six or more addressing dimensions, these addressing dimensions may include, but not limited to, block width, block height, block depth, horizontal block stepping, vertical block stepping, and / or depth stepping.

[0140] In at least one embodiment, a vector processor is a programmable processor that can be designed to efficiently and flexibly perform programming for computer vision algorithms and can provide signal processing capabilities. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, one or more DMA engines (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem may act as the primary processing engine of the PVA and may include a vector processing unit ("VPU"), an instruction cache, and / or vector memory (e.g., "VMEM"). In at least one embodiment, the VPU core may include a digital signal processor, such as a single instruction, multiple data ("SIMD") or very long instruction word ("VLIW") digital signal processor. In at least one embodiment, a combination of SIMD and VLIW can improve throughput and speed.

[0141] In at least one embodiment, each vector processor may include an instruction cache and be coupled to dedicated memory. As a result, in at least one embodiment, each vector processor may be configured to operate independently of other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute a common computer vision algorithm, but on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on a single image, or even execute different algorithms on a contiguous image or portion of an image. In at least one embodiment, among other things, any number of PVAs may be included in a hardware acceleration cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional error correction code ("ECC") memory to improve the overall safety of the system.

[0142] In at least one embodiment, one or more accelerators 1014 may include a computer vision network on-chip and static random-access memory ("SRAM") to provide high-bandwidth, low-latency SRAM for one or more accelerators 1014. In at least one embodiment, the on-chip memory may include, for example, at least 4 MB of SRAM including, but not limited to, eight field-configurable memory blocks, which may be accessible by both the PVA and DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus ("APB") interface, configurable circuit elements, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and DLA may access the memory via a backbone that provides high-speed access to the memory. In at least one embodiment, the backbone may include a computer vision network on a chip that interconnects the PVA and DLA to memory (for example, using an APB).

[0143] In at least one embodiment, the computer vision network on chip may include an interface in which both the PVA and DLA determine to provide ready and enable signals before any control signals / addresses / data are transmitted. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as burst-type communication for continuous data transfer. In at least one embodiment, the interface may conform to the International Organization for Standardization (ISO) 26262 or the International Electrotechnical Commission (IEC) 61508 standard, but other standards and protocols may be used.

[0144] In at least one embodiment, one or more of the (one or more) SoC1004 may include a real-time ray tracing hardware accelerator. In at least one embodiment, the real-time ray tracing hardware accelerator may be used to quickly and efficiently determine the location and extent of objects (e.g., in a world model) to generate real-time visualization simulations for RADAR signal interpretation, sound propagation synthesis and / or analysis, SONAR system simulation, general waveform propagation simulation, comparison with LIDAR data for localization and / or other functions, and / or other uses.

[0145] In at least one embodiment, one or more accelerators 1014 can have diverse uses for autonomous driving. In at least one embodiment, PVA can be used for key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of PVA are well matched for algorithmic domains requiring predictable processing at low power and low latency. In other words, PVA performs well even on small datasets for semi-dense or dense regular computations that may require predictable runtime along with low latency and low power. In at least one embodiment, such as in vehicle 1000, PVA can be designed to run conventional computer vision algorithms, as they may be efficient in object detection and integer calculations.

[0146] For example, according to at least one embodiment of the technology, PVA is used to implement computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm may be used in some examples, but is not limited to this. In at least one embodiment, an application for Level 3–5 autonomous driving uses motion estimation / stereo matching (e.g., structure from motion, pedestrian recognition, lane detection, etc.) on the fly. In at least one embodiment, PVA may implement computer stereo vision functionality for input from two monocular cameras.

[0147] In at least one embodiment, PVA may be used to perform high-density optical flow. For example, in at least one embodiment, PVA may process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, PVA may be used for time-of-flight depth processing by processing raw time-of-flight data to provide processed time-of-flight data.

[0148] In at least one embodiment, DLA may be used to power any type of network for improving control and driving safety, including, for example, a neural network that outputs a measure of confidence for each object detection. In at least one embodiment, confidence may be expressed or interpreted as the probability of each detection compared to other detections, or as providing its relative “weight.” In at least one embodiment, the confidence measure allows the system to make further determinations about which detections should be considered true positive detections rather than false positive detections. In at least one embodiment, the system may set a threshold for confidence and consider only detections exceeding the threshold as true positive detections. In embodiments where an automatic emergency braking (“AEB”) system is used, a false positive detection would cause the vehicle to automatically apply the emergency brakes, which is obviously undesirable. In at least one embodiment, a highly reliable detection may be considered a trigger for the AEB. In at least one embodiment, DLA may power a neural network to regress confidence values. In at least one embodiment, the neural network may take as its input at least a subset of parameters, including, among other things, the dimensions of the bounding box, ground plane estimates obtained (e.g., from another subsystem), outputs from one or more IMU sensors 1066 correlated with the orientation of the vehicle 1000, distance, and 3D location estimates of objects obtained from the neural network and / or other sensors (e.g., one or more LiDAR sensors 1064 or one or more RADAR sensors 1060).

[0149] In at least one embodiment, one or more of the (one or more) SoC1004 may include (one or more) datastores 1016 (e.g., memory). In at least one embodiment, the (one or more) datastores 1016 may be on-chip memory of the (one or more) SoC1004, which may store neural networks to be run on the (one or more) GPUs 1008 and / or DLA. In at least one embodiment, the capacity of the (one or more) datastores 1016 may be large enough to store multiple instances of the neural network for redundancy and safety. In at least one embodiment, the (one or more) datastores 1016 may include (one or more) L2 or L3 caches.

[0150] In at least one embodiment, one or more of the (one or more) SoC 1004 may include any number of (one or more) processors 1010 (e.g., embedded processors). In at least one embodiment, the (one or more) processors 1010 may include a boot and power management processor, which may be a dedicated processor and subsystem for handling boot power and management functions and related security enforcement. In at least one embodiment, the boot and power management processor may be part of the boot sequence of the (one or more) SoC 1004 and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assistance with system low-power state transitions, management of thermal and temperature sensors of the (one or more) SoC 1004, and / or management of the power state of the (one or more) SoC 1004. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to the temperature, and (one or more) SoC 1004 may use the ring oscillator to detect the temperatures of (one or more) CPU 1006, (one or more) GPU 1008, and / or (one or more) accelerator 1014. In at least one embodiment, if it is determined that the temperature exceeds a threshold, the boot and power management processor may enter a temperature fault routine to put (one or more) SoC 1004 into a low-power state and / or put the vehicle 1000 into chauffeur-to-safe stop mode (e.g., to safely stop the vehicle 1000).

[0151] In at least one embodiment, the (one or more) processor 1010 may further include a set of embedded processors that can act as an audio processing engine, which may be an audio subsystem enabling full hardware support for multi-channel audio via multiple interfaces and a wide range of flexible audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core having a digital signal processor with dedicated RAM.

[0152] In at least one embodiment, the (one or more) processors 1010 may further include an always-on processor engine that can provide the hardware features necessary to support low-power sensor management and startup use cases. In at least one embodiment, the always-on processor engine may include, but is not limited to, a processor core, tightly coupled RAM, supporting peripherals (e.g., timer and interrupt controllers), various I / O controller peripherals, and routing logic.

[0153] In at least one embodiment, the (one or more) processor 1010 may further include a safety cluster engine, which may include, but is not limited to, a dedicated processor subsystem for addressing safety management for automotive applications. In at least one embodiment, the safety cluster engine may include, but is not limited to, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.), and / or routing logic. In safety mode, the two or more cores may, in at least one embodiment, operate in lockstep mode and function as a single core with comparison logic for detecting any differences between their operations. In at least one embodiment, the (one or more) processor 1010 may further include a real-time camera engine, which may include, but is not limited to, a dedicated processor subsystem for addressing real-time camera management. In at least one embodiment, the processor 1010 (one or more) may further include a high dynamic range signal processor, which may include, but is not limited to, an image signal processor that is a hardware engine that is part of a camera processing pipeline.

[0154] In at least one embodiment, the (one or more) processor 1010 may include a video image synthesizer, which may be a processing block (for example, implemented on a microprocessor) that implements video post-processing functions required by a video playback application to produce a final image for a player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on the (one or more) wide-angle camera 1070, the (one or more) ambient camera 1074, and / or the (one or more) cabin surveillance camera sensors. In at least one embodiment, the (one or more) cabin surveillance camera sensors are preferably monitored by a neural network running on another instance of the SoC 1004, which is configured to identify and respond to events within the cabin. In at least one embodiment, the in-cabin system may perform lip-reading to activate cellular services, make phone calls, write emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, and provide voice-activated web surfing. In at least one embodiment, some functions are available to the driver when the vehicle is operating in autonomous mode and are unavailable in other cases.

[0155] In at least one embodiment, the video image synthesizer may include extended temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, if motion occurs in the video, the noise reduction appropriately weights the spatial information and reduces the weight of the information provided by adjacent frames. In at least one embodiment, if the image or part of the image does not contain motion, the temporal noise reduction performed by the video image synthesizer may use information from previous images to reduce noise in the current image.

[0156] In at least one embodiment, the video image synthesizer may also be configured to perform stereo rectification on the input stereo lens frame. In at least one embodiment, the video image synthesizer may be further used for user interface compositing when the operating system desktop is in use, and (one or more) GPUs 1008 are not required to continuously render new surfaces. In at least one embodiment, when (one or more) GPUs 1008 are powered on, active, and performing 3D rendering, the video image synthesizer may be used to offload (one or more) GPUs 1008 to improve performance and responsiveness.

[0157] In at least one embodiment, one or more of the SoCs 1004 may further include a Mobile Industry Processor Interface ("MIPI") camera serial interface, a high-speed interface, and / or a video input block that can be used for the camera and associated pixel input functions for receiving video and input from the camera. In at least one embodiment, one or more of the SoCs 1004 may further include one or more input / output controllers, which may be controlled by software and may be used to receive I / O signals not committed to a specific role.

[0158] In at least one embodiment, one or more of the (one or more) SoCs 1004 may further include a wide range of peripheral interfaces for enabling communication with peripherals, audio encoders / decoders ("codecs"), power management, and / or other devices. In at least one embodiment, the (one or more) SoCs 1004 may be used to process data from cameras (e.g., connected via Gigabit Multimedia Serial Link and Ethernet Channel), data from sensors (e.g., one or more LiDAR sensors 1064, one or more RADAR sensors 1060, etc., which may be connected via Ethernet Channel), data from bus 1002 (e.g., vehicle speed, steering wheel position, etc.), data from one or more GNSS sensors 1058 (e.g., connected via Ethernet Bus or CAN Bus), and the like. In at least one embodiment, one or more of the (one or more) SoCs 1004 may further include a dedicated high-performance, high-capacity storage controller, which may include its own DMA engine and may be used to free the (one or more) CPUs 1006 from routine data management tasks.

[0159] In at least one embodiment, one or more SoCs 1004 may be an end-to-end platform with a flexible architecture spanning automation levels 3–5, thereby providing a comprehensive functional safety architecture that leverages and efficiently utilizes computer vision and ADAS techniques for diversity and redundancy, and can provide a platform for a flexible, reliable driving software stack, along with deep learning tools. In at least one embodiment, one or more SoCs 1004 may be faster, more reliable, and more energy-efficient and space-efficient than conventional systems. For example, in at least one embodiment, one or more accelerators 1014, when combined with one or more CPUs 1006, one or more GPUs 1008, and one or more data stores 1016, may provide a fast and efficient platform for Level 3–5 autonomous vehicles.

[0160] In at least one embodiment, a computer vision algorithm may run on a CPU, and this algorithm may be configured using a high-level programming language such as C to execute a wide variety of processing algorithms across a wide variety of visual data. However, in at least one embodiment, the CPU often fails to meet the performance requirements of many computer vision applications, such as requirements related to execution time and power consumption. In at least one embodiment, many CPUs are unable to execute complex object detection algorithms in real time, as used in in-vehicle ADAS applications and in actual Level 3-5 autonomous vehicles.

[0161] The embodiments described herein enable multiple neural networks to be implemented simultaneously and / or sequentially, allowing the results to be combined to enable Level 3–5 autonomous driving functionality. For example, in at least one embodiment, a CNN running on a DLA or a separate GPU (e.g., one or more GPU1020) may include text and word recognition, enabling the neural network to read and understand traffic signs, including signs that the neural network has not been specifically trained on. In at least one embodiment, the DLA may further include a neural network that can identify and interpret signs, provide a semantic understanding of the signs, and pass that semantic understanding to a route planning module running on a CPU complex.

[0162] In at least one embodiment, multiple neural networks may be operating simultaneously with respect to Level 3, 4, or 5 driving. For example, in at least one embodiment, a warning sign with an electric light and the text "Caution: Flashing light indicates icy condition" may be interpreted independently or collectively by several neural networks. In at least one embodiment, such a warning sign itself may be identified as a traffic sign by a first introduced neural network (e.g., a trained neural network), and the text "Flashing light indicates icy condition" may be interpreted by a second introduced neural network, which informs the vehicle's route planning software (preferably running on the CPU complex) that an icy condition is present when a flashing light is detected. In at least one embodiment, the flashing light may be identified by running a third introduced neural network over multiple frames, which informs the vehicle's route planning software of the presence (or absence) of the flashing light. In at least one embodiment, all three neural networks may run simultaneously within the DLA and / or on (one or more) GPUs 1008, etc.

[0163] In at least one embodiment, a CNN for facial recognition and vehicle owner identification may use data from camera sensors to identify the presence of an authorized driver and / or owner of vehicle 1000. In at least one embodiment, an always-on sensor processing engine may be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and in security mode to disable such vehicle when the owner leaves such vehicle. In this way, (one or more) SoCs 1004 provide security against theft and / or vehicle hijacking.

[0164] In at least one embodiment, a CNN for emergency vehicle detection and identification may use data from microphone 1096 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 1004 use a CNN to classify environmental and urban sounds, as well as visual data. In at least one embodiment, a CNN running on a DLA is trained to identify the relative speed at which an emergency vehicle is approaching (for example, by using the Doppler effect). In at least one embodiment, a CNN may also be trained to identify emergency vehicles specific to the area in which the vehicle is operating, as identified by one or more GNSS sensors 1058. In at least one embodiment, when operating in Europe, the CNN attempts to detect European sirens, and when in North America, the CNN attempts to identify only North American sirens. In at least one embodiment, when an emergency vehicle is detected, a control program may be used to execute an emergency vehicle safety routine, slow down the vehicle, pull over to the side of the road, stop the vehicle, and / or idle the vehicle in conjunction with one or more ultrasonic sensors 1062 until the emergency vehicle has passed.

[0165] In at least one embodiment, the vehicle 1000 may include (one or more) CPUs 1018 (e.g., (one or more) individual CPUs, or (one or more) dCPUs), and the (one or more) CPUs 1018 may be coupled to the (one or more) SoCs 1004 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, the (one or more) CPUs 1018 may include, for example, an x86 processor. The (one or more) CPUs 1018 may be used to perform any of a variety of functions, including, for example, mediating potentially inconsistent results between ADAS sensors and the (one or more) SoCs 1004, and / or monitoring the status and health of the (one or more) controllers 1036 and / or the infotainment system ("Infotainment SoC") 1030 on the chip.

[0166] In at least one embodiment, the vehicle 1000 may include (one or more) GPUs 1020 (e.g., (one or more) individual GPUs, or (one or more) dGPUs), and the (one or more) GPUs 1020 may be coupled to the (one or more) SoCs 1004 via a high-speed interconnect (e.g., NVIDIA's NVLINK channel). In at least one embodiment, the (one or more) GPUs 1020 may provide additional artificial intelligence functionality, such as by running redundant and / or different neural networks, and may be used to train and / or update neural networks based at least in part on input from the vehicle 1000's sensors (e.g., sensor data).

[0167] In at least one embodiment, vehicle 1000 may further include a network interface 1024, which may include, but is not limited to, one or more wireless antennas 1026 (e.g., one or more wireless antennas for different communication protocols, such as cellular antennas, Bluetooth antennas, etc.). In at least one embodiment, the network interface 1024 may be used to enable wireless connectivity to Internet cloud services (e.g., with one or more servers and / or other network devices) with other vehicles and / or computing devices (e.g., passenger client devices). In at least one embodiment, a direct link may be established between vehicle 100 and other vehicles for communication with other vehicles, and / or an indirect link may be established (e.g., over a network and via the Internet). In at least one embodiment, the direct link may be provided using an inter-vehicle communication link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 1000 with information about nearby vehicles (e.g., vehicles in front of, to the side of, and / or behind vehicle 1000). In at least one embodiment, such the aforementioned functionality may be part of the cooperative adaptive driving control functionality of vehicle 1000.

[0168] In at least one embodiment, the network interface 1024 may include an SoC that provides modulation and demodulation functionality, enabling one or more controllers 1036 to communicate over a wireless network. In at least one embodiment, the network interface 1024 may include a radio frequency front end for baseband-to-radio frequency up-conversion and radio frequency-to-baseband down-conversion. In at least one embodiment, frequency conversion may be carried out in any technically feasible manner. For example, frequency conversion may be carried out through a well-known process and / or using a superheterodyne process. In at least one embodiment, the radio frequency front end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functionality for communication over LTE, WCDMA®, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0169] In at least one embodiment, the vehicle 1000 may further include one or more data stores 1028, which may include, but are not limited to, off-chip (e.g., not on one or more SoCs 1004) storage. In at least one embodiment, the data stores 1028 may include one or more storage elements, which may include, but are not limited to, RAM, SRAM, dynamic random-access memory ("DRAM"), video random-access memory ("VRAM"), flash memory, hard disks, and / or other components and / or devices capable of storing at least one bit of data.

[0170] In at least one embodiment, the vehicle 1000 may further include (one or more) GNSS sensors 1058 (e.g., GPS and / or auxiliary GPS sensors) to assist mapping, perception, occupy grid generation, and / or route planning functions. In at least one embodiment, any number of GNSS sensors 1058 may be used, including, for example, a GPS using a USB connector with an Ethernet-to-serial (e.g., RS-232) bridge.

[0171] In at least one embodiment, the vehicle 1000 may further include one or more RADAR sensors 1060. In at least one embodiment, one or more RADAR sensors 1060 may be used by the vehicle 1000 for long-range vehicle detection, even in darkness and / or severe weather conditions. In at least one embodiment, the functional safety level of the RADAR may be ASIL B. In at least one embodiment, one or more RADAR sensors 1060 may, in some examples, use a CAN bus and / or bus 1002 for control (e.g., to transmit data generated by one or more RADAR sensors 1060) and for accessing object tracking data, along with access to an Ethernet channel for accessing raw data. In at least one embodiment, a wide variety of RADAR sensor types may be used. For example, but not limited to, one or more RADAR sensors 1060 may be suitable for forward, rear, and side RADAR use. In at least one embodiment, one or more of the (one or more) RADAR sensors 1060 are pulsed Doppler RADAR sensors.

[0172] In at least one embodiment, the (one or more) RADAR sensors 1060 may include different configurations, such as narrow-field long-range, wide-field short-range, and short-range lateral coverage. In at least one embodiment, the long-range RADAR may be used for adaptive driving control functionality. In at least one embodiment, the long-range RADAR system may provide a wide field of view achieved by two or more independent scans, such as within a 250 m (meter) range. In at least one embodiment, the (one or more) RADAR sensors 1060 may help distinguish between static and moving objects and may be used by the ADAS system 1038 for emergency braking assistance and forward collision warning. In at least one embodiment, the (one or more) sensors 1060 included in the long-range RADAR system may include, but are not limited to, multiple (e.g., six or more) fixed RADAR antennas, as well as monostatic and multimodal RADARs with high-speed CAN and FlexRay interfaces. In at least one embodiment, if there are six antennas, the four central antennas may create a focused beam pattern designed to record the area around vehicle 1000 at a faster speed with minimal interference from traffic in adjacent lanes. In at least one embodiment, two additional antennas may expand the field of view, which may allow for the rapid detection of vehicles entering or leaving the lane of vehicle 1000.

[0173] In at least one embodiment, the medium-range RADAR system may, as an example, include a range of up to 160 m (forward) or 80 m (rearward) and a field of view of up to 42 degrees (forward) or 150 degrees (rearward). In at least one embodiment, the short-range RADAR system may include, but not limited to, any number of RADAR sensors 1060 designed to be mounted on both ends of the rear bumper. When mounted on both ends of the rear bumper, in at least one embodiment, the RADAR sensor system may create two beams that constantly monitor blind spots in the rearward and adjacent to the vehicle. In at least one embodiment, the short-range RADAR system may be used in an ADAS system 1038 for blind spot detection and / or lane change assistance.

[0174] In at least one embodiment, the vehicle 1000 may further include one or more ultrasonic sensors 1062. In at least one embodiment, one or more ultrasonic sensors 1062, which can be positioned in front of, behind, and / or to the side of the vehicle 1000, may be used for parking assistance and / or to create and update the occupancy grid. In at least one embodiment, a wide variety of one or more ultrasonic sensors 1062 may be used, and different ultrasonic sensors 1062 may be used for different detection ranges (e.g., 2.5m, 4m). In at least one embodiment, one or more ultrasonic sensors 1062 may operate at functional safety level ASIL B.

[0175] In at least one embodiment, the vehicle 1000 may include (one or more) LiDAR sensors 1064. In at least one embodiment, (one or more) LiDAR sensors 1064 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, (one or more) LiDAR sensors 1064 may operate at functional safety level ASIL B. In at least one embodiment, the vehicle 1000 may include multiple LiDAR sensors 1064 (e.g., two, four, six, etc.), and those LiDAR sensors 1064 may use an Ethernet channel (e.g., to provide data to a Gigabit Ethernet switch).

[0176] In at least one embodiment, one or more LiDAR sensors 1064 may be capable of providing a list of objects and their distances over a 360-degree field of view. In at least one embodiment, one or more commercially available LiDAR sensors 1064 may have an advertised range of approximately 100m, for example, with an accuracy of 2cm to 3cm and support for a 100Mbps Ethernet connection. In at least one embodiment, one or more non-protruding LiDAR sensors may be used. In such embodiments, one or more LiDAR sensors 1064 may include small devices that can be incorporated into the front, rear, side, and / or corner locations of a vehicle 1000. In at least one embodiment, one or more LiDAR sensors 1064 may, in such embodiments, provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees over a range of 200m, even for low-reflectivity objects. In at least one embodiment, one or more front-mounted LiDAR sensors 1064 may be configured for a horizontal field of view between 45 and 135 degrees.

[0177] In at least one embodiment, LiDAR technology such as 3D flash LiDAR may also be used. In at least one embodiment, the 3D flash LiDAR uses a laser flash as a transmission source to illuminate the area around the vehicle 1000 up to approximately 200m. In at least one embodiment, the flash LiDAR unit includes, but is not limited to, a receptor which records the transit time of the laser pulse and the reflected light on each pixel, which corresponds to the range from the vehicle 1000 to the object. In at least one embodiment, the flash LiDAR enables the generation of highly accurate and distortion-free ambient images with each laser flash. In at least one embodiment, four flash LiDAR sensors may be introduced, one on each side of the vehicle 1000. In at least one embodiment, the 3D flash LiDAR system includes, but is not limited to, a solid-state 3D staring array LiDAR camera (e.g., a non-scanning LiDAR device) with no moving parts other than a fan. In at least one embodiment, a flash LiDAR device may use a Class I (eye-safe) laser pulse of 5 nanoseconds per frame and capture reflected laser light as a 3D-range point cloud and position-synchronized (co-registered) intensity data.

[0178] In at least one embodiment, the vehicle 1000 may further include one or more IMU sensors 1066. In at least one embodiment, one or more IMU sensors 1066 may be located in the center of the rear axle of the vehicle 1000. In at least one embodiment, one or more IMU sensors 1066 may include, for example, one or more accelerometers, one or more magnetometers, one or more gyroscopes, magnetic compasses, multiple magnetic compasses, and / or other sensor types. In at least one embodiment, such as in a 6-axis application, one or more IMU sensors 1066 may include, for example, an accelerometer and a gyroscope. In at least one embodiment, such as in a 9-axis application, one or more IMU sensors 1066 may include, for example, an accelerometer, a gyroscope, and a magnetometer.

[0179] In at least one embodiment, the (one or more) IMU sensors 1066 may be implemented as a small, high-performance GPS-Aided Inertial Navigation System ("GPS / INS") that combines micro-electro-mechanical systems ("MEMS") inertial sensors, a high-sensitivity GPS receiver, and an advanced Kalman filtering algorithm to provide estimates of position, velocity, and attitude. In at least one embodiment, the (one or more) IMU sensors 1066 enable the vehicle 1000 to estimate its bearing without requiring input from magnetic sensors by directly observing changes in velocity and correlating them from GPS to the (one or more) IMU sensors 1066. In at least one embodiment, the (one or more) IMU sensors 1066 and the (one or more) GNSS sensors 1058 may be combined in a single integrated unit.

[0180] In at least one embodiment, the vehicle 1000 may include one or more microphones 1096 placed inside and / or around the vehicle 1000. In at least one embodiment, one or more microphones 1096 may, among other things, be used for emergency vehicle detection and identification.

[0181] In at least one embodiment, the vehicle 1000 may further include any number of camera types, including (one or more) stereo cameras 1068, (one or more) wide-angle cameras 1070, (one or more) infrared cameras 1072, (one or more) ambient cameras 1074, (one or more) long-range cameras 1098, (one or more) medium-range cameras 1076, and / or other camera types. In at least one embodiment, cameras may be used to capture image data around the entire periphery of the vehicle 1000. In at least one embodiment, the type of camera used depends on the vehicle 1000. In at least one embodiment, any combination of camera types may be used to provide the required coverage around the vehicle 1000. In at least one embodiment, the number of cameras introduced may vary depending on the embodiment. For example, in at least one embodiment, the vehicle 1000 may include six cameras, seven cameras, ten cameras, twelve cameras, or any other number of cameras. In at least one embodiment, the camera may, as an example, support Gigabit Multimedia Serial Link ("GMSL") and / or Gigabit Ethernet communication, though not limited to these. In at least one embodiment, each camera may be as described previously in more detail herein with respect to Figures 10A and 10B.

[0182] In at least one embodiment, the vehicle 1000 may further include one or more vibration sensors 1042. In at least one embodiment, one or more vibration sensors 1042 may measure vibrations of components of the vehicle 1000, such as one or more axles. For example, in at least one embodiment, a change in vibration may indicate a change in the road surface. In at least one embodiment, when two or more vibration sensors 1042 are used, the difference in vibration may be used to determine the amount of friction or slip of the road surface (for example, when the difference in vibration is between a power-driven axle and a free-rotating axle).

[0183] In at least one embodiment, the vehicle 1000 may include an ADAS system 1038. In at least one embodiment, the ADAS system 1038 may include a SoC in some examples, but is not limited to. In at least one embodiment, the ADAS system 1038 may include, but not limited to, any number and combinations of autonomous / adaptive / automatic cruise control ("ACC") systems, cooperative adaptive cruise control ("CACC") systems, forward crash warning ("FCW") systems, automatic emergency braking ("AEB") systems, lane departure warning ("LDW") systems, lane keep assist ("LKA") systems, blind spot warning ("BSW") systems, rear cross-traffic warning ("RCTW") systems, collision warning ("CW") systems, lane centering ("LC") systems, and / or other systems, features, and / or functionalities.

[0184] In at least one embodiment, the ACC system may use (one or more) RADAR sensors 1060, (one or more) LIDAR sensors 1064, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance of vehicle 1000 to another vehicle directly in front and automatically adjusts the speed of vehicle 1000 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system enforces distance maintenance and advises vehicle 1000 to change lanes when necessary. In at least one embodiment, the lateral ACC is relevant to other ADAS applications such as LC and CW.

[0185] In at least one embodiment, the CACC system uses information from other vehicles, which may be received from other vehicles via a network interface 1024 and / or (one or more) wireless antennas 1026, either wirelessly or indirectly via a network connection (e.g., via the Internet). In at least one embodiment, direct links may be provided by vehicle-to-vehicle ("V2V") communication links, and indirect links may be provided by infrastructure-to-vehicle ("I2V") communication links. Generally, V2V communication provides information about the immediately preceding vehicle (e.g., a vehicle in the same lane immediately before vehicle 1000), and I2V communication provides information about traffic further ahead. In at least one embodiment, the CACC system may include either or both I2V and V2V information sources. In at least one embodiment, if information about the vehicle in front of vehicle 1000 is available, the CACC system may become more reliable, which could improve the smoothness of traffic flow and reduce congestion on the road.

[0186] In at least one embodiment, the FCW system is designed to alert the driver about hazardous materials so that such a driver can take corrective action. In at least one embodiment, the FCW system uses a front camera and / or (one or more) radar sensors 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration components. In at least one embodiment, the FCW system may provide warnings in the form of sound, visual warnings, vibration, and / or quick brake pulses.

[0187] In at least one embodiment, the AEB system may detect an impending forward collision with another vehicle or other object and automatically apply the brakes if the driver does not take corrective action within a specified time or distance parameter. In at least one embodiment, the AEB system may use one or more front cameras and / or one or more RADAR sensors 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, the AEB system may first alert the driver to take corrective action to avoid a collision, and if the driver does not take corrective action, the AEB system may automatically apply the brakes to prevent the anticipated collision or at least mitigate its impact. In at least one embodiment, the AEB system may include techniques such as dynamic brake support and / or pre-crash braking.

[0188] In at least one embodiment, the LDW system provides visual, auditory, and / or tactile warnings, such as vibration of the steering wheel or seat, to alert the driver when vehicle 1000 crosses a lane marker. In at least one embodiment, the LDW system does not activate when the driver indicates an intentional lane departure, such as by activating the turn signal. In at least one embodiment, the LDW system may use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration component. In at least one embodiment, the LKA system is a variation of the LDW system. In at least one embodiment, the LKA system provides steering input or brake control to correct vehicle 1000 if vehicle 1000 begins to move out of its lane.

[0189] In at least one embodiment, the BSW system detects vehicles in the vehicle's blind spot and warns the driver about those vehicles. In at least one embodiment, the BSW system may provide visual, auditory, and / or tactile alerts to indicate that merging or changing lanes is not safe. In at least one embodiment, the BSW system may provide additional warnings when the driver uses the turn signal. In at least one embodiment, the BSW system may use one or more rear-facing cameras and / or one or more RADAR sensors 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to driver feedback, such as a display, speaker, and / or vibration component.

[0190] In at least one embodiment, the RCTW system may provide visual, auditory, and / or tactile notifications when an object is detected outside the range of the rear camera while the vehicle 1000 is reversing. In at least one embodiment, the RCTW system includes an AEB system to ensure that the vehicle brakes are applied to avoid a crash. In at least one embodiment, the RCTW system may use one or more rear-facing radar sensors 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration components.

[0191] In at least one embodiment, conventional ADAS systems may be prone to producing false positive results, which can be annoying and distracting to the driver, but this is usually not a major issue as conventional ADAS systems alert the driver, allowing the driver to determine whether safety conditions truly exist and act accordingly. In at least one embodiment, the vehicle 1000 itself determines, in the event of conflicting results, whether to follow the result from a primary computer (e.g., a first controller among controllers 1036) or a secondary computer (e.g., a second controller among controllers 836). For example, in at least one embodiment, the ADAS system 1038 may be a backup and / or secondary computer for providing perceptual information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor may run redundant and varied software on hardware components to detect failures in perceptual and dynamic driving tasks. In at least one embodiment, the output from the ADAS system 1038 may be provided to a supervisory MCU. In at least one embodiment, if the output from the primary computer and the output from the secondary computer are inconsistent, the supervising MCU determines how to reconcile the inconsistency to ensure safe operation.

[0192] In at least one embodiment, the primary computer may be configured to provide the supervising MCU with a reliability score indicating the reliability of the primary computer in the selected outcome. In at least one embodiment, if the reliability score exceeds a threshold, the supervising MCU may follow the instructions of the primary computer, regardless of whether the secondary computer provides contradictory or inconsistent results. In at least one embodiment, if the reliability score does not meet the threshold, and the primary and secondary computers produce different results (e.g., contradictory), the supervising MCU may mediate between the computers to determine an appropriate outcome.

[0193] In at least one embodiment, the supervising MCU may be configured to operate one or more neural networks trained and configured to determine, at least in part, the conditions under which a secondary computer provides a false alarm, based on the output from the primary computer and the output from the secondary computer. In at least one embodiment, one or more neural networks in the supervising MCU may learn when the output from the secondary computer can be trusted and when it cannot. For example, in at least one embodiment, when the secondary computer is a radar-based FCW system, one or more neural networks in the supervising MCU may learn when the FCW system identifies a metallic object that is not actually a hazard, such as a drain grate or manhole cover, which triggers an alarm. In at least one embodiment, when the secondary computer is a camera-based LDW system, the neural network in the supervising MCU may learn to disable the LDW when a cyclist or pedestrian is present and lane departure is actually the safest operation. In at least one embodiment, the supervisor MCU may include at least one DLA or GPU suitable for operating (one or more) neural networks together with associated memory. In at least one embodiment, the supervisor MCU may comprise and / or be included as a component of (one or more) SoC1004.

[0194] In at least one embodiment, the ADAS system 1038 may include a secondary computer that implements ADAS functionality using conventional computer vision rules. In at least one embodiment, the secondary computer may use conventional computer vision rules (if-then), and the presence of (one or more) neural networks in the supervising MCU may improve reliability, safety, and performance. For example, in at least one embodiment, diverse implementations and intentional non-identities make the entire system more fault-tolerant, particularly against failures caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if there is a software bug or error in the software running on the primary computer, and non-identical software code running on the secondary computer provides a consistent overall result, the supervising MCU may have greater confidence that the overall result is correct and that the bug in the software or hardware on the primary computer has not caused a critical error.

[0195] In at least one embodiment, the output of the ADAS system 1038 may be fed to a perception block and / or a dynamic driving task block of the primary computer. For example, in at least one embodiment, if the ADAS system 1038 indicates a forward crash warning due to an object immediately preceding, the perception block may use this information when identifying the object. In at least one embodiment, the secondary computer may have its own trained, and therefore false-positive-reducing, neural network, as described herein.

[0196] In at least one embodiment, the vehicle 1000 may further include an infotainment SoC 1030 (for example, an in-vehicle infotainment system (IVI)). Although shown and described as an SoC, the infotainment system SoC 1030 may not be an SoC in at least one embodiment and may include, but not limited to, two or more separate components. In at least one embodiment, the infotainment SoC 1030 may include, but is not limited to, a combination of hardware and software which may be used to provide the vehicle 1000 with audio (e.g., music, personal digital assistant, navigation commands, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), telephone (e.g., hands-free calling), network connectivity (e.g., LTE, Wi-Fi, etc.), and / or information services (e.g., a navigation system, rear parking assist, wireless data system, vehicle-related information such as fuel level, total mileage, brake fuel level, oil level, door open / closed, air filter information, etc.). For example, the infotainment SoC 1030 may include a radio, disc player, navigation system, video player, USB and Bluetooth connectivity, car computer, in-car entertainment, Wi-Fi, steering wheel audio control, hands-free voice control, heads-up display ("HUD"), HMI display 1034, telematics device, control panel (for example, for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, the infotainment SoC 1030 may be further used to provide (one or more) users of the vehicle 1000 with (for example, visual and / or auditory) information, such as information from the ADAS system 1038, autonomous driving information such as planned vehicle operation and trajectory, ambient information (for example, intersection information, vehicle information, road information, etc.), and / or other information.

[0197] In at least one embodiment, the infotainment SoC 1030 may include any amount and type of GPU functionality. In at least one embodiment, the infotainment SoC 1030 may communicate with other devices, systems, and / or components of the vehicle 1000 via bus 1002. In at least one embodiment, the infotainment SoC 1030 may be coupled to a supervisory MCU so that if one or more primary controllers 1036 (e.g., the primary and / or backup computers of the vehicle 1000) fail, the GPU of the infotainment system may perform some self-driving functions. In at least one embodiment, the infotainment SoC 1030 may put the vehicle 1000 into driver-safe stop mode as described herein.

[0198] In at least one embodiment, the vehicle 1000 may further include an instrument cluster 1032 (e.g., a digital dashboard, electronic instrument cluster, digital instrument panel, etc.). In at least one embodiment, the instrument cluster 1032 may include, but is not limited to, a controller and / or supercomputer (e.g., a separate controller or supercomputer). In at least one embodiment, the instrument cluster 1032 may include, but is not limited to, any number and combination of instrumentation sets, such as a speedometer, fuel level, oil pressure, tachometer, odometer, direction indicator, shift lever position indicator, (one or more) seat belt warning lights, (one or more) parking brake warning lights, (one or more) engine fault lights, auxiliary restraint system (e.g., airbag) information, light control, safety system control, navigation information, etc. In some examples, the information may be displayed and / or shared between the infotainment SoC 1030 and the instrument cluster 1032. In at least one embodiment, the instrument cluster 1032 may be included as part of the infotainment SoC 1030, and vice versa.

[0199] The inference and / or training logic 715 is used to perform inference and / or training operations related to one or more embodiments. Details relating to the inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, the inference and / or training logic 715 may be used in the system of Figure 10C for inference or prediction operations, at least in part, based on weight parameters calculated using the neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0200] Figure 10D is a diagram of a system for communication between one or more cloud-based servers and the autonomous vehicle 1000 of Figure 10A, according to at least one embodiment. In at least one embodiment, the system may include, but is not limited to, one or more servers 1078, one or more networks 1090, and any number and types of vehicles, including vehicle 1000. In at least one embodiment, the one or more servers 1078 may include, but is not limited to, a plurality of GPUs 1084(A) to 1084(H) (collectively referred to herein as GPU 1084), PCIe switches 1082(A) to 1082(D) (collectively referred to herein as PCIe switches 1082), and / or CPUs 1080(A) to 1080(B) (collectively referred to herein as CPU 1080). In at least one embodiment, the GPU 1084, the CPU 1080, and the PCIe switch 1082 may be interconnected by a high-speed interconnect, such as, for example, an NVLink interface 1088 and / or PCIe connection 1086 developed by NVIDIA. In at least one embodiment, the GPU 1084 is connected via an NVLink and / or NVSwitch SoC, and the GPU 1084 and PCIe switch 1082 are connected via a PCIe interconnect. Eight GPUs 1084, two CPUs 1080, and four PCIe switches 1082 are shown, but this is not limited to them. In at least one embodiment, each of (one or more) servers 1078 may include, but not limited to, any number of GPUs 1084, CPUs 1080, and / or PCIe switches 1082 in any combination. For example, in at least one embodiment, one or more servers 1078 may each include 8, 16, 32, and / or more GPUs 1084.

[0201] In at least one embodiment, one or more servers 1078 may receive from a vehicle via one or more networks 1090 image data representing images showing unexpected or altered road conditions, such as recently started road construction. In at least one embodiment, one or more servers 1078 may transmit to a vehicle via one or more networks 1090 map information 1094, which includes updated or unupdated neural networks 1092 and / or, but not limited to, information about traffic and road conditions. In at least one embodiment, updates to the map information 1094 may include updates to the HD map 1022, which includes, but not limited to, information about construction sites, potholes, detours, floods, and / or other obstacles. In at least one embodiment, the neural network 1092 and / or the map information 1094 may arise from new training and / or experience represented in data received from any number of vehicles in the environment, and / or from training performed in a data center (for example, using one or more servers 1078 and / or other servers).

[0202] In at least one embodiment, one or more servers 1078 may be used to train a machine learning model (e.g., a neural network) based at least in part on training data. In at least one embodiment, the training data may be generated by the vehicle and / or generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data may be tagged and / or otherwise preprocessed (e.g., if the relevant neural network benefits from supervised learning). In at least one embodiment, any amount of training data may not be tagged and / or preprocessed (e.g., if the relevant neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model may be used by the vehicle (e.g., transmitted to the vehicle via one or more networks 1090) and / or the machine learning model may be used by one or more servers 1078 to remotely monitor the vehicle.

[0203] In at least one embodiment, one or more servers 1078 may receive data from a vehicle and apply the data to a state-of-the-art real-time neural network for real-time intelligent inference. In at least one embodiment, one or more servers 1078 may include one or more deep learning supercomputers and / or dedicated AI computers powered by GPUs 1084, such as DGX and DGX Station Machines developed by NVIDIA. However, in at least one embodiment, one or more servers 1078 may include a deep learning infrastructure using a CPU-powered data center.

[0204] In at least one embodiment, the deep learning infrastructure of one or more servers 1078 may be capable of high-speed real-time inference and may use that capability to assess and verify the health of the processor, software, and / or associated hardware in the vehicle 1000. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from the vehicle 1000, such as a series of images and / or objects located in that series of images (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may operate its own neural network to identify objects and compare them to objects identified by the vehicle 1000. If the results do not match and the deep learning infrastructure concludes that the AI ​​in the vehicle 1000 is malfunctioning, the one or more servers 1078 may send a signal to the vehicle 1000 instructing the vehicle 1000's fail-safe computer to take control, notify passengers, and complete a safe parking operation.

[0205] In at least one embodiment, one or more servers 1078 may include one or more GPUs 1084 and one or more programmable inference accelerators (e.g., NVIDIA TensorRT3 devices). In at least one embodiment, a combination of a server powered by a GPU and inference acceleration may enable real-time response. In at least one embodiment, a server powered by a CPU, FPGA, and other processors may be used for inference, for example, when performance is not critical. In at least one embodiment, one or more hardware structures 715 are used to carry out one or more embodiments. Details relating to hardware structure(x)715 are provided herein in conjunction with Figures 7A and / or 7B.

[0206] In at least one embodiment, one or more systems shown in Figures 10A to 10D are used to implement a system for action recognition as described with respect to Figures 1 to 6. In at least one embodiment, one or more systems shown in Figures 10A to 10D are used to perform one or more quantization and pruning processes on one or more neural networks. In at least one embodiment, one or more systems shown in Figures 10A to 10D are used to perform action recognition using a hardware accelerator and / or one or more neural networks processed through one or more quantization and pruning processes.

[0207] Computer system Figure 11 is a block diagram showing an exemplary computer system, which may be a system having interconnected devices and components, a system-on-a-chip (SOC), or any combination thereof, formed together with a processor that may include an execution unit for executing instructions, according to at least one embodiment. In at least one embodiment, computer system 1100 may include components such as a processor 1102 for employing an execution unit including logic for implementing algorithms for process data, as described herein, but not limited to embodiments described herein. In at least one embodiment, computer system 1100 may include a processor such as the PENTIUM® processor family, Xeon®, Itanium®, XScale®, and / or StrongARM®, Intel® Core®, or Intel® Nervana® microprocessors, available from Intel Corporation in Santa Clara, California, but other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, the computer system 1100 may run a version of the WINDOWS® operating system available from Microsoft Corporation in Redmond, Washington, but other operating systems (e.g., UNIX® and Linux®), embedded software, and / or graphical user interfaces may also be used.

[0208] The embodiments may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor ("DSP"), a system-on-a-chip, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system capable of implementing one or more instructions according to at least one embodiment.

[0209] In at least one embodiment, the computer system 1100 may include, but is not limited to, a processor 1102, which may include, but is not limited to, one or more execution units 1108 for performing machine learning model training and / or inference by the techniques described herein. In at least one embodiment, the computer system 1100 is a single-processor desktop or server system, while in another embodiment, the computer system 1100 may be a multi-processor system. In at least one embodiment, the processor 1102 may include, but is not limited to, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor implementing a combination of instruction sets, or any other processor device such as a digital signal processor. In at least one embodiment, the processor 1102 may be coupled to a processor bus 1110, and the processor bus 1110 may transmit data signals between the processor 1102 and other components in the computer system 1100.

[0210] In at least one embodiment, the processor 1102 may include, but is not limited to, a level 1 ("L1") internal cache memory ("cache") 1104. In at least one embodiment, the processor 1102 may have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory may reside outside the processor 1102. Other embodiments may also include a combination of both internal and external caches, depending on the specific implementation and requirements. In at least one embodiment, the register file 1106 may store different types of data in various registers, including, but is not limited to, integer registers, floating-point registers, status registers, and instruction pointer registers.

[0211] In at least one embodiment, but not limited to, an execution unit 1108 containing logic for performing integer and floating-point arithmetic may also be present in the processor 1102. In at least one embodiment, the processor 1102 may also include a microcode ("u-code") read-only memory ("ROM") for storing microcode for several macro instructions. In at least one embodiment, the execution unit 1108 may include logic for handling a packed instruction set 1109. In at least one embodiment, by including the packed instruction set 1109, along with the associated circuit elements for executing the instructions, in the instruction set of a general-purpose processor, arithmetic used by many multimedia applications can be performed using packed data in the processor 1102. In at least one embodiment, many multimedia applications may be accelerated and run more efficiently by using the full width of the processor's data bus to perform arithmetic on packed data, which may eliminate the need to transfer smaller units of data across the processor's data bus to perform one or more arithmetic operations, one data element at a time.

[0212] In at least one embodiment, the execution unit 1108 may also be used in a microcontroller, embedded processor, graphics device, DSP, and other types of logic circuits. In at least one embodiment, the computer system 1100 may include, but is not limited to, memory 1120. In at least one embodiment, memory 1120 may be a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other memory device. In at least one embodiment, memory 1120 may store (one or more) instructions 1119 and / or data 1121, which are represented by data signals that can be executed by the processor 1102.

[0213] In at least one embodiment, a system logic chip may be coupled to the processor bus 1110 and memory 1120. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub ("MCH") 1116, and the processor 1102 may communicate with the MCH 1116 via the processor bus 1110. In at least one embodiment, the MCH 1116 may provide a high-bandwidth memory path 1118 to memory 1120 for instruction and data storage, as well as for the storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1116 may direct data signals between the processor 1102, memory 1120, and other components in the computer system 1100, and bridge data signals between the processor bus 1110, memory 1120, and system I / O interface 1122. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH1116 may be coupled to memory 1120 through a high-bandwidth memory path 1118, and the graphics / video card 1112 may be coupled to the MCH1116 via an Accelerated Graphics Port ("AGP") interconnect 1114.

[0214] In at least one embodiment, the computer system 1100 may use the system I / O interface 1122 as a proprietary hub interface bus for coupling the MCH 1116 to the I / O controller hub ("ICH") 1130. In at least one embodiment, the ICH 1130 may provide direct connectivity to several I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripherals to memory 1120, the chipset, and the processor 1102. Examples may include, but are not limited to, an audio controller 1129, a firmware hub ("Flash BIOS") 1128, a wireless transceiver 1126, data storage 1124, a legacy I / O controller 1123 including a user input and keyboard interface 1125, a serial expansion port 1127 such as a Universal Serial Bus ("USB") port, and a network controller 1134. In at least one embodiment, the data storage 1124 may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0215] In at least one embodiment, Figure 11 shows a system including interconnected hardware devices or “chips,” while in other embodiments, Figure 11 may show an exemplary SoC. In at least one embodiment, the devices shown in Figure 11 may be interconnected by proprietary interconnects, standard interconnects (e.g., PCIe), or any combination thereof. In at least one embodiment, one or more components of the computer system 1100 are interconnected using a compute express link (CXL) interconnect.

[0216] The inference and / or training logic 715 is used to perform inference and / or training operations related to one or more embodiments. Details relating to the inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, the inference and / or training logic 715 may be used in the system of Figure 11 for inference or prediction operations, at least in part, based on weight parameters calculated using the neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0217] In at least one embodiment, one or more systems shown in Figure 11 are used to implement a system for action recognition as described with respect to Figures 1 to 6. In at least one embodiment, one or more systems shown in Figure 11 are used to perform one or more quantization and pruning processes on one or more neural networks. In at least one embodiment, one or more systems shown in Figure 11 are used to perform action recognition using a hardware accelerator and / or one or more neural networks processed through one or more quantization and pruning processes.

[0218] Figure 12 is a block diagram showing an electronic device 1200 for utilizing the processor 1210 according to at least one embodiment. In at least one embodiment, the electronic device 1200 may be, for example, a notebook, a tower server, a rack server, a blade server, a laptop, a desktop, a tablet, a mobile device, a telephone, an embedded computer, or any other suitable electronic device, for example, but not limited to.

[0219] In at least one embodiment, the electronic device 1200 may include a processor 1210 communicably coupled to any preferred number or type of components, peripherals, modules, or devices, but is not limited to. In at least one embodiment, the processor 1210 is I 2 The devices are coupled using buses or interfaces such as the C-bus, System Management Bus ("SMBus"), Low Pin Count (LPC) bus, Serial Peripheral Interface ("SPI"), High Definition Audio ("HDA") bus, Serial Advance Technology Attachment ("SATA") bus, Universal Serial Bus ("USB") (versions 1, 2, 3, etc.), or Universal Asynchronous Receiver / Transmitter ("UART") bus. In at least one embodiment, Figure 12 shows a system including interconnected hardware devices or "chips," while in other embodiments, Figure 12 may show an exemplary SoC. In at least one embodiment, the devices shown in Figure 12 may be interconnected by proprietary interconnects, standard interconnects (e.g., PCIe), or any combination thereof. In at least one embodiment, one or more components of Figure 12 are interconnected using a Compute Express Link (CXL) interconnect.

[0220] In at least one embodiment, Figure 12 shows a display 1224, a touchscreen 1225, a touchpad 1230, a Near Field Communication ("NFC") unit 1245, a sensor hub 1240, a thermal sensor 1246, an Express Chipset ("EC") 1235, a Trusted Platform Module ("TPM") 1238, a BIOS / firmware / flash memory ("BIOS,FW flash") 1222, a DSP 1260, a drive 1220 such as a Solid State Disk ("SSD") or Hard Disk Drive ("HDD"), a Wireless Local Area Network ("WLAN") unit 1250, a Bluetooth unit 1252, and a Wireless Wide Area Network ("WWAN") unit. The components may include a network (1256), a Global Positioning System (GPS) unit (1255), a camera such as a USB 3.0 camera ("USB 3.0 camera") (1254), and / or a Low Power Double Data Rate ("LPDDR") memory unit ("LPDDR3") (1215) implemented, for example, in the LPDDR3 standard. Each of these components may be implemented in any preferred manner.

[0221] In at least one embodiment, other components may be communicatively coupled to the processor 1210 through components described herein. In at least one embodiment, an accelerometer 1241, an ambient light sensor ("ALS") 1242, a compass 1243, and a gyroscope 1244 may be communicatively coupled to a sensor hub 1240. In at least one embodiment, a thermal sensor 1239, a fan 1237, a keyboard 1236, and a touchpad 1230 may be communicatively coupled to the EC 1235. In at least one embodiment, a speaker 1263, headphones 1264, and a microphone ("mic") 1265 may be communicatively coupled to an audio unit ("audio codec and Class D amplifier") 1262, and the audio unit 1262 may be communicatively coupled to a DSP 1260. In at least one embodiment, the audio unit 1262 may include, for example, an audio coder / decoder ("codec") and a Class D amplifier. In at least one embodiment, a SIM card ("SIM") 1257 may be communicatively coupled to the WWAN unit 1256. In at least one embodiment, components such as the WLAN unit 1250 and the Bluetooth unit 1252, as well as the WWAN unit 1256, may be implemented in a Next Generation Form Factor ("NGFF").

[0222] The inference and / or training logic 715 is used to perform inference and / or training operations related to one or more embodiments. Details relating to the inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, the inference and / or training logic 715 may be used in the system of Figure 12 for inference or prediction operations, at least in part, based on weight parameters calculated using the neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0223] In at least one embodiment, one or more systems shown in Figure 12 are used to implement a system for action recognition as described with respect to Figures 1 to 6. In at least one embodiment, one or more systems shown in Figure 12 are used to perform one or more quantization and pruning processes on one or more neural networks. In at least one embodiment, one or more systems shown in Figure 12 are used to perform action recognition using a hardware accelerator and / or one or more neural networks processed through one or more quantization and pruning processes.

[0224] Figure 13 shows a computer system 1300 according to at least one embodiment. In at least one embodiment, the computer system 1300 is configured to implement various processes and methods described throughout this disclosure.

[0225] In at least one embodiment, the computer system 1300 includes, but is not limited to, at least one central processing unit ("CPU") 1302, which is connected to a communications bus 1310 implemented using any preferred protocol, such as PCI ("Peripheral Component Interconnect"), Peripheral Component Interconnect Express ("PCI-Express"), AGP ("Accelerated Graphics Port"), Hypertransport, or any other bus or point-to-point communication protocol (one or more). In at least one embodiment, the computer system 1300 includes, but is not limited to, main memory 1304 and control logic (implemented, for example, as hardware, software, or a combination thereof), where data is stored in the main memory 1304, which may take the form of random access memory ("RAM"). In at least one embodiment, the network interface subsystem ("Network Interface") 1322 provides an interface to other computing devices and networks for receiving data from other systems and transmitting data to other systems, together with the computer system 1300.

[0226] In at least one embodiment, the computer system 1300 includes, in at least one embodiment, an input device 1308, a parallel processing system 1312, and a display device 1306, the display device 1306 of which may be implemented using a conventional cathode ray tube ("CRT"), a liquid crystal display ("LCD"), a light-emitting diode ("LED") display, a plasma display, or other suitable display technology. In at least one embodiment, user input is received from the input device 1308, such as a keyboard, mouse, touchpad, or microphone. In at least one embodiment, each module described herein may be on a single semiconductor platform to form a processing system.

[0227] The inference and / or training logic 715 is used to perform inference and / or training operations related to one or more embodiments. Details relating to the inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, the inference and / or training logic 715 may be used in the system of Figure 13 for inference or prediction operations, at least in part, based on weight parameters calculated using the neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0228] In at least one embodiment, one or more systems shown in Figure 13 are used to implement a system for action recognition as described with respect to Figures 1 to 6. In at least one embodiment, one or more systems shown in Figure 13 are used to perform one or more quantization and pruning processes on one or more neural networks. In at least one embodiment, one or more systems shown in Figure 13 are used to perform action recognition using a hardware accelerator and / or one or more neural networks processed through one or more quantization and pruning processes.

[0229] Figure 14 shows a computer system 1400 according to at least one embodiment. In at least one embodiment, the computer system 1400 may include, but is not limited to, a computer 1410 and a USB stick 1420. In at least one embodiment, the computer 1410 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, the computer 1410 may include, but is not limited to, a server, a cloud instance, a laptop, and a desktop computer.

[0230] In at least one embodiment, the USB stick 1420 includes, but is not limited to, a processing unit 1430, a USB interface 1440, and a USB interface logic 1450. In at least one embodiment, the processing unit 1430 may be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, the processing unit 1430 may include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing unit 1430 comprises an application-specific integrated circuit ("ASIC") optimized to perform any amount and type of operations related to machine learning. For example, in at least one embodiment, the processing unit 1430 is a tensor processing unit ("TPC") optimized to perform machine learning inference operations. In at least one embodiment, the processing unit 1430 is a vision processing unit ("VPU") optimized to perform machine vision and machine learning inference operations. In at least one embodiment, the processing unit 1430 may include a data processing unit ("DPU") optimized for processing a stream of data (e.g., data received over a network) and for directly directing that data to one or more other processors (e.g., but not limited to, the memory of a GPU). In one or more embodiments, the DPU may be integrated with a network interface device.

[0231] In at least one embodiment, the USB interface 1440 may be any type of USB connector or USB socket. For example, in at least one embodiment, the USB interface 1440 is a USB 3.0 Type-C socket for data and power. In at least one embodiment, the USB interface 1440 is a USB 3.0 Type-A connector. In at least one embodiment, the USB interface logic 1450 may include any amount and type of logic that enables the processing unit 1430 to interface with a device (e.g., a computer 1410) via the USB connector 1440.

[0232] The inference and / or training logic 715 is used to perform inference and / or training operations related to one or more embodiments. Details relating to the inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, the inference and / or training logic 715 may be used in the system of Figure 14 for inference or prediction operations, at least in part, based on weight parameters calculated using the neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0233] In at least one embodiment, one or more systems shown in Figure 14 are used to implement a system for action recognition as described with respect to Figures 1 to 6. In at least one embodiment, one or more systems shown in Figure 14 are used to perform one or more quantization and pruning processes on one or more neural networks. In at least one embodiment, one or more systems shown in Figure 14 are used to perform action recognition using a hardware accelerator and / or one or more neural networks processed through one or more quantization and pruning processes.

[0234] Figure 15A shows an exemplary architecture in which multiple GPUs 1510(1)–1510(N) are communicably coupled to multiple multi-core processors 1505(1)–1505(M) via high-speed links 1540(1)–1540(N) (e.g., bus, point-to-point interconnect). In at least one embodiment, the high-speed links 1540(1)–1540(N) support communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or higher. In at least one embodiment, but not limited to, various interconnect protocols may be used, including PCIe 4.0 or 5.0 and NVLink 2.0. In various figures, "N" and "M" represent positive integers whose values ​​may differ from figure to figure.

[0235] Furthermore, in at least one embodiment, two or more of the GPUs 1510 are interconnected via high-speed links 1529(1)–1529(2), which may be implemented using a protocol / link similar to or different from that used for high-speed links 1540(1)–1540(N). Similarly, two or more of the multicore processors 1505 may be connected via high-speed link 1528, which may be a symmetric multi-processor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, all communication between the various system components shown in Figure 15A may be achieved using similar protocols / links (e.g., via a common interconnection fabric).

[0236] In at least one embodiment, each multicore processor 1505 is communicatively coupled to processor memory 1501(1)-1501(M) via memory interconnects 1526(1)-1526(M), and each GPU 1510(1)-1510(N) is communicatively coupled to GPU memory 1520(1)-1520(N) via GPU memory interconnects 1550(1)-1550(N). In at least one embodiment, memory interconnects 1526 and 1550 may utilize similar or different memory access techniques. For example, but not limited to, the processor memory 1501(1) to 1501(M) and the GPU memory 1520 may be volatile memory such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high-bandwidth memory (HBM), and / or non-volatile memory such as 3D XPoint or Nano-Ram. In at least one embodiment, some portion of the processor memory 1501 may be volatile memory, and other portions may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0237] As described herein, various multicore processors 1505 and GPUs 1510 may be physically coupled to specific memories 1501, 1520, respectively, and / or a unified memory architecture may be implemented in which a virtual system address space (also called the “effective address” space) is distributed across various physical memories. For example, processor memories 1501(1) to 1501(M) may each have a system memory address space of 64GB, and GPU memories 1520(1) to 1520(N) may each have a system memory address space of 32GB, resulting in a total of 256GB of addressable memory when M=2 and N=4. Other values ​​for N and M are possible.

[0238] Figure 15B provides additional details about the interconnection between the multicore processor 1507 and the graphics acceleration module 1546 in one exemplary embodiment. In at least one embodiment, the graphics acceleration module 1546 may include one or more GPU chips integrated on a line card coupled to the processor 1507 via a high-speed link 1540 (e.g., PCIe bus, NVLink, etc.). In at least one embodiment, the graphics acceleration module 1546 may alternatively be integrated on a package or chip with the processor 1507.

[0239] In at least one embodiment, the processor 1507 includes a plurality of cores 1560A–1560D, each having translation lookaside buffers ("TLBs") 1561A–1561D and one or more caches 1562A–1562D. In at least one embodiment, the cores 1560A–1560D may include various other components not shown for executing instructions and processing data. In at least one embodiment, the caches 1562A–1562D may comprise a Level 1 (L1) cache and a Level 2 (L2) cache. Furthermore, one or more shared caches 1556 may be included in the caches 1562A–1562D and shared by the set of cores 1560A–1560D. For example, one embodiment of the processor 1507 includes 24 cores, each having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one or more L2 and L3 caches are shared by two adjacent cores. In at least one embodiment, the processor 1507 and the graphics acceleration module 1546 are connected to system memory 1514, which may include processor memories 1501(1) to 1501(M) in Figure 15A.

[0240] In at least one embodiment, coherence is maintained over data and instructions stored in various caches 1562A-1562D, 1556 and system memory 1514 via inter-core communication over coherence bus 1564. In at least one embodiment, for example, each cache may have associated cache coherence logic / circuit elements to communicate over coherence bus 1564 in response to detected reads or writes to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented over coherence bus 1564 to snoop cache accesses.

[0241] In at least one embodiment, the proxy circuit 1525 connects the graphics acceleration module 1546 to the coherence bus 1564 in a communicative manner, enabling the graphics acceleration module 1546 to participate in the cache coherence protocol as a peer of cores 1560A-1560D. In particular, in at least one embodiment, interface 1535 provides connectivity to the proxy circuit 1525 via high-speed link 1540, and interface 1537 connects the graphics acceleration module 1546 to high-speed link 1540.

[0242] In at least one embodiment, the accelerator integration circuit 1536 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 1531(1) to 1531(N) of the graphics acceleration module 1546. In at least one embodiment, each of the graphics processing engines 1531(1) to 1531(N) may comprise a separate graphics processing unit (GPU). In at least one embodiment, the graphics processing engines 1531(1) to 1531(N) may alternatively comprise different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module 1546 may be a GPU having multiple graphics processing engines 1531(1) to 1531(N), or the graphics processing engines 1531(1) to 1531(N) may be individual GPUs integrated on a common package, line card, or chip.

[0243] In at least one embodiment, the accelerator integration circuit 1536 includes a memory management unit (MMU) 1539 for performing various memory management functions, such as virtual-physical memory translation (also known as effective-to-real memory translation), and a memory access protocol for accessing system memory 1514. In at least one embodiment, the MMU 1539 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective-physical / real address translations. In at least one embodiment, the cache 1538 can store commands and data for efficient access by graphics processing engines 1531(1) to 1531(N). In at least one embodiment, data stored in cache 1538 and graphics memory 1533(1)-1533(M) is kept coherent with core caches 1562A-1562D, 1556 and system memory 1514, possibly using a fetch unit 1544. As stated, this can be achieved via a proxy circuit 1525 instead of cache 1538 and memory 1533(1)-1533(M) (for example, by sending updates related to modification / access of cache lines on processor caches 1562A-1562D, 1556 to cache 1538 and receiving updates from cache 1538).

[0244] In at least one embodiment, a set of registers 1545 stores context data for threads executed by graphics processing engines 1531(1) to 1531(N), and a context management circuit 1548 manages thread contexts. For example, the context management circuit 1548 may perform save and restore operations to save and restore the contexts of various threads during context switching (for example, the first thread is saved and the second thread is stored so that a second thread can be executed by the graphics processing engine). For example, during context switching, the context management circuit 1548 may store the current register values ​​in a specified area of ​​memory (for example, identified by a context pointer). The context management circuit 1548 may then restore the register values ​​when returning to the context. In at least one embodiment, an interrupt management circuit 1547 receives and processes interrupts received from system devices.

[0245] In at least one embodiment, virtual / effective addresses from the graphics processing engine 1531 are translated by the MMU 1539 to real / physical addresses in system memory 1514. In at least one embodiment, the accelerator integration circuit 1536 supports multiple (e.g., 4, 8, or 16) graphics accelerator modules 1546 and / or other accelerator devices. In at least one embodiment, the graphics accelerator module 1546 may be dedicated to a single application running on the processor 1507 or may be shared among multiple applications. In at least one embodiment, there exists a virtualized graphics execution environment in which the resources of the graphics processing engines 1531(1) to 1531(N) are shared among multiple applications or virtual machines (VMs). In at least one embodiment, the resources may be subdivided into "slices," which are allocated to different VMs and / or applications based on processing requirements and priorities related to the VMs and / or applications.

[0246] In at least one embodiment, the accelerator integration circuit 1536 acts as a bridge to the system for the graphics acceleration module 1546 and provides address translation and system memory cache services. Furthermore, in at least one embodiment, the accelerator integration circuit 1536 may provide virtualization facilities for the host processor to manage the virtualization, interrupts, and memory management of the graphics processing engines 1531(1) to 1531(N).

[0247] In at least one embodiment, the hardware resources of the graphics processing engines 1531(1) to 1531(N) are explicitly mapped to the real address space visible to the host processor 1507, so that any host processor can directly address these resources using effective address values. In at least one embodiment, one function of the accelerator integration circuit 1536 is to physically isolate the graphics processing engines 1531(1) to 1531(N) so that they appear as independent units to the system.

[0248] In at least one embodiment, one or more graphics memories 1533(1) to 1533(M) are each coupled to each of the graphics processing engines 1531(1) to 1531(N), where N=M. In at least one embodiment, the graphics memories 1533(1) to 1533(M) store instructions and data being processed by each of the graphics processing engines 1531(1) to 1531(N). In at least one embodiment, the graphics memories 1533(1) to 1533(M) may be volatile memory such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or non-volatile memory such as 3D XPoint or Nano-Ram.

[0249] In at least one embodiment, biasing techniques may be used to reduce data traffic over the high-speed link 1540, ensuring that the data stored in graphics memory 1533(1)-1533(M) is most frequently used by the graphics processing engines 1531(1)-1531(N) and preferably not used (or at least not frequently used) by the cores 1560A-1560D. Similarly, in at least one embodiment, the biasing mechanism attempts to keep data required by the cores (preferably not required by the graphics processing engines 1531(1)-1531(N)) in caches 1562A-1562D, 1556 and system memory 1514.

[0250] Figure 15C shows another exemplary embodiment in which the accelerator integration circuit 1536 is incorporated within the processor 1507. In this embodiment, the graphics processing engines 1531(1) to 1531(N) communicate directly over the high-speed link 1540 to the accelerator integration circuit 1536 via interfaces 1537 and 1535 (which may again be any form of bus or interface protocol). In at least one embodiment, the accelerator integration circuit 1536 may perform operations similar to those described with respect to Figure 15B, but potentially at higher throughput given its proximity to the coherence bus 1564 and caches 1562A to 1562D, 1556. In at least one embodiment, the accelerator integration circuit supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), and these programming models may include a programming model controlled by the accelerator integration circuit 1536 and a programming model controlled by the graphics acceleration module 1546.

[0251] In at least one embodiment, the graphics processing engines 1531(1) to 1531(N) may be dedicated to a single application or process under a single operating system. In at least one embodiment, a single application may direct other application requests to the graphics processing engines 1531(1) to 1531(N) to provide virtualization within a VM / partition.

[0252] In at least one embodiment, the graphics processing engines 1531(1) to 1531(N) may be shared by multiple VM / application partitions. In at least one embodiment, the sharing model may use a system hypervisor to virtualize the graphics processing engines 1531(1) to 1531(N) to allow access by each operating system. In at least one embodiment, for a single-partition system without a hypervisor, the graphics processing engines 1531(1) to 1531(N) are owned by the operating system. In at least one embodiment, the operating system may virtualize the graphics processing engines 1531(1) to 1531(N) to provide access to each process or application.

[0253] In at least one embodiment, the graphics acceleration module 1546 or individual graphics processing engines 1531(1)-1531(N) select process elements using a process handle. In at least one embodiment, the process elements are stored in the system memory 1514 and are addressable using the effective address - physical address translation techniques described herein. In at least one embodiment, the process handle may be an implementation-specific value provided to the host process when registering the context of the host process with the graphics processing engines 1531(1)-1531(N) (i.e., calling system software to add a process element to the process element link list). In at least one embodiment, the lower 16 bits of the process handle may be the offset of the process element within the process element link list.

[0254] FIG. 15D shows an exemplary accelerator integration slice 1590. In at least one embodiment, a "slice" comprises a designated portion of the processing resources of the accelerator integration circuit 1536. In at least one embodiment, the effective address space 1582 of an application within the system memory 1514 stores a process element 1583. In at least one embodiment, the process element 1583 is stored in response to a GPU call 1581 from an application 1580 executing on the processor 1507. In at least one embodiment, the process element 1583 includes the process state of the corresponding application 1580. In at least one embodiment, the work descriptor (WD) 1584 included in the process element 1583 may be a single job requested by the application or may include a pointer to a queue of jobs. In at least one embodiment, the WD 1584 is a pointer to a job request queue in the effective address space 1582 of the application.

[0255] In at least one embodiment, the graphics acceleration module 1546 and / or the individual graphics processing engines 1531(1)-1531(N) can be shared by all or a subset of the processes in the system. In at least one embodiment, an infrastructure for setting the process state and sending the WD1584 to the graphics acceleration module 1546 to start a job in a virtualized environment can be included.

[0256] In at least one embodiment, the dedicated process programming model is implementation specific. In at least one embodiment, in this model, a single process owns the graphics acceleration module 1546 or an individual graphics processing engine 1531. In at least one embodiment, when the graphics acceleration module 1546 is owned by a single process, the hypervisor initializes the accelerator integration circuit 1536 for the owning partition, and when the graphics acceleration module 1546 is assigned, the operating system initializes the accelerator integration circuit 1536 for the owning process.

[0257] In at least one embodiment, during operation, the WD fetch unit 1591 in the accelerator integrated slice 1590 fetches the next WD 1584 containing instructions for work to be performed by one or more graphics processing engines of the graphics acceleration module 1546. In at least one embodiment, as shown, the data from WD 1584 is stored in register 1545 and may be used by the MMU 1539, interrupt management circuit 1547, and / or context management circuit 1548. For example, one embodiment of the MMU 1539 includes a segment / page walk circuit element for accessing the segment / page table 1586 in the OS virtual address space 1585. In at least one embodiment, the interrupt management circuit 1547 may process an interrupt event 1592 received from the graphics acceleration module 1546. In at least one embodiment, when performing graphics operations, the effective address 1593 generated by the graphics processing engines 1531(1) to 1531(N) is translated to a real address by the MMU 1539.

[0258] In at least one embodiment, register 1545 may be duplicated for each graphics processing engine 1531(1)–1531(N) and / or graphics acceleration module 1546 and initialized by the hypervisor or operating system. In at least one embodiment, each of these duplicated registers may be included in the accelerator integration slice 1590. Exemplary registers that may be initialized by the hypervisor are shown in Table 1. [Table 1]

[0259] Table 2 shows exemplary registers that can be initialized by the operating system. [Table 2]

[0260] In at least one embodiment, each WD1584 is specific to a particular graphics acceleration module 1546 and / or graphics processing engines 1531(1) to 1531(N). In at least one embodiment, WD1584 may contain all the information required by the graphics processing engines 1531(1) to 1531(N) to perform the work, or it may be a pointer to a memory location set up by the application for a command queue of work to be completed.

[0261] Figure 15E provides additional details of an exemplary embodiment of the shared model. This embodiment includes a hypervisor real address space 1598 in which the process element list 1599 is stored. In at least one embodiment, the hypervisor real address space 1598 is accessible via a hypervisor 1596 that virtualizes a graphics acceleration module engine for the operating system 1595.

[0262] In at least one embodiment, a shared programming model allows all or a subset of processes from all or a subset of partitions in the system to use the graphics acceleration module 1546. In at least one embodiment, there are two programming models in which the graphics acceleration module 1546 is shared by multiple processes and partitions: time-slice sharing and graphics-directed sharing.

[0263] In at least one embodiment, in this model, the system hypervisor 1596 owns the graphics acceleration module 1546 and makes its functionality available to all operating systems 1595. In at least one embodiment, for the graphics acceleration module 1546 to support virtualization by the system hypervisor 1596, the graphics acceleration module 1546 may be subject to several requirements, including (1) application job requests must be autonomous (i.e., no state needs to be maintained between jobs) or the graphics acceleration module 1546 must provide a context saving and restoration mechanism; (2) the graphics acceleration module 1546 must guarantee that application job requests will be completed within a specified amount of time, including any translation failures, or the graphics acceleration module 1546 must provide the ability to preempt job processing; and (3) when the graphics acceleration module 1546 is operating in a specified shared programming model, fairness between processes must be guaranteed.

[0264] In at least one embodiment, application 1580 is required to make a system call to operating system 1595, accompanied by a graphics acceleration module type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore area pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes the acceleration function of the system call. In at least one embodiment, the graphics acceleration module type may be a system-specific value. In at least one embodiment, the WD is specifically formatted for graphics acceleration module 1546 and may be in the form of a command for graphics acceleration module 1546, an effective address pointer to a user-defined structure, an effective address pointer to a queue of commands, or any other data structure for describing the work to be performed by graphics acceleration module 1546.

[0265] In at least one embodiment, the AMR value is the AMR state to be used for the current process. In at least one embodiment, the value passed to the operating system is the same as that of the application setting the AMR. In at least one embodiment, if the accelerator integration circuit 1536 (not shown) implementation and the graphics acceleration module 1546 implementation do not support the User Authority Mask Override Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in a hypervisor call. In at least one embodiment, the hypervisor 1596 may optionally apply the current Authority Mask Override Register (AMOR) value before putting the AMR into process element 1583. In at least one embodiment, CSRP is one of the registers 1545 that contains the effective addresses of areas in the application's effective address space 1582 for the graphics acceleration module 1546 to save and restore context state. In at least one embodiment, this pointer is optional when no state needs to be saved between jobs or when a job is preempted. In at least one embodiment, the context save / restore area may be pinned system memory.

[0266] Upon receiving a system call, the operating system 1595 may verify that application 1580 is registered and authorized to use the graphics acceleration module 1546. In at least one embodiment, the operating system 1595 then calls the hypervisor 1596 with the information shown in Table 3. [Table 3]

[0267] In at least one embodiment, upon receiving a hypervisor call, the hypervisor 1596 verifies that the operating system 1595 is registered and authorized to use the graphics acceleration module 1546. In at least one embodiment, the hypervisor 1596 then places the process element 1583 into the process element link list for the corresponding graphics acceleration module 1546 type. In at least one embodiment, the process element may include the information shown in Table 4. [Table 4]

[0268] In at least one embodiment, the hypervisor initializes multiple accelerator integration slice 1590 registers 1545.

[0269] As shown in Figure 15F, in at least one embodiment, a unified memory addressable via a common virtual memory address space is used to access physical processor memories 1501(1) to 1501(N) and GPU memories 1520(1) to 1520(N). In this implementation, operations performed on GPUs 1510(1) to 1510(N) utilize the same virtual / effective memory address space to access processor memories 1501(1) to 1501(M), and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1501(1), a second portion to a second processor memory 1501(N), a third portion to GPU memory 1520(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes called the effective address space) is distributed across processor memory 1501 and GPU memory 1520, respectively, allowing either processor or GPU to access either physical memory, where virtual addresses are mapped to physical memory.

[0270] In at least one embodiment, the bias / coherence management circuit elements 1594A-1594E within one or more of MMUs 1539A-1539E ensure cache coherence between the cache of one or more host processors (e.g., 1505) and the cache of GPU 1510, and implement a bias technique to indicate the physical memory in which some types of data should be stored. In at least one embodiment, multiple instances of the bias / coherence management circuit elements 1594A-1594E are shown in FIG. 15F, but the bias / coherence circuit elements may be implemented within the MMU of one or more host processors 1505 and / or within the accelerator integration circuit 1536.

[0271] In one embodiment, GPU memory 1520 is mapped as part of system memory and can be accessed using shared virtual memory (SVM) technology, but without incurring the performance drawbacks associated with full system cache coherence. In at least one embodiment, the ability of GPU memory 1520 to be accessed as system memory without cumbersome cache coherence overhead provides a beneficial operating environment for GPU offloading. In at least one embodiment, this mechanism allows software on the host processor 1505 to set operands and access computation results without the overhead of conventional I / O DMA data copying. In at least one embodiment, such conventional copying involves driver calls, interrupts, and memory-mapped I / O (MMIO) access, all of which are inefficient compared to simple memory access. In at least one embodiment, the ability to access GPU memory 1520 without cache coherence overhead may be essential for the execution time of offloaded computations. In at least one embodiment, for example, when there is significant streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by the GPU1510. In at least one embodiment, the efficiency of operand configuration, the efficiency of result access, and the efficiency of GPU computation can be helpful in determining the effectiveness of GPU offloading.

[0272] In at least one embodiment, the selection between GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, for example, a bias table may be used, which may be a page-granular structure containing 1 or 2 bits per GPU-enabled memory page (for example, it may be controlled at the memory page granularity). In at least one embodiment, the bias table may be implemented in a stolen memory range of one or more GPU memories 1520, with or without a bias cache (for example, for caching frequently used / recently used entries in the bias table) in the GPU 1510. Alternatively, in at least one embodiment, the entire bias table may be maintained within the GPU.

[0273] In at least one embodiment, a bias table entry associated with each access to the GPU-biased memory 1520 is accessed before the actual access to the GPU memory, causing the following behavior: In at least one embodiment, a local request from GPU 1510 finding its page in GPU bias is forwarded directly to the corresponding GPU memory 1520. In at least one embodiment, a local request from a GPU finding its page in host bias is forwarded to processor 1505 (for example, via the fast link described above). In at least one embodiment, a request from processor 1505 finding the requested page in host processor bias completes the request like a normal memory read. Alternatively, a request targeting a GPU-biased page may be forwarded to GPU 1510. In at least one embodiment, the GPU may then move the page to host processor bias if the page is not currently in use. In at least one embodiment, the bias state of a page can be modified by either a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of cases, simply by a hardware-based mechanism.

[0274] In at least one embodiment, one mechanism for changing the bias state employs an API call (e.g., OpenCL), the API call calls the GPU's device driver, the GPU's device driver changes the bias state and sends a message to the GPU (or queues a command descriptor) instructing the GPU to perform a cache flushing operation on the host for some transitions. In at least one embodiment, the cache flushing operation is used for transitions from host processor bias to GPU bias, but not for transitions in the opposite direction.

[0275] In at least one embodiment, cache coherency is maintained by temporarily rendering GPU-biased pages that cannot be cached by the host processor 1505. In at least one embodiment, to access these pages, processor 1505 may request access from GPU 1510, which may or may not immediately grant access. In at least one embodiment, it is therefore beneficial to ensure that GPU-biased pages are those that are required by the GPU but not by the host processor 1505, and vice versa, in order to reduce communication between processor 1505 and GPU 1510.

[0276] One or more hardware structures 715 are used to carry out one or more embodiments. Details relating to one or more hardware structures 715 may be provided herein in conjunction with Figures 7A and / or 7B.

[0277] In at least one embodiment, one or more systems shown in Figures 15A to 15F are used to implement a system for action recognition as described with respect to Figures 1 to 6. In at least one embodiment, one or more systems shown in Figures 15A to 15F are used to perform one or more quantization and pruning processes on one or more neural networks. In at least one embodiment, one or more systems shown in Figures 15A to 15F are used to perform action recognition using a hardware accelerator and / or one or more neural networks processed through one or more quantization and pruning processes.

[0278] Figure 16 shows exemplary integrated circuits and associated graphics processors that can be fabricated using one or more IP cores according to various embodiments described herein. In addition to those shown, at least one embodiment may include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0279] Figure 16 is a block diagram showing an exemplary system-on-chip integrated circuit 1600 that may be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 1600 includes one or more application processors 1605 (e.g., CPUs), at least one graphics processor 1610, and additionally, an image processor 1615 and / or a video processor 1620, any of which may be modular IP cores. In at least one embodiment, the integrated circuit 1600 includes a USB controller 1625, a UART controller 1630, an SPI / SDIO controller 1635, and I 2 2S / I 2 The integrated circuit includes peripherals or bus logic, including a 2C controller 1640. In at least one embodiment, the integrated circuit 1600 may include a display device 1645 coupled to one or more of the following: a High-Definition Multimedia Interface (HDMI®) controller 1650 and a Mobile Industry Processor Interface (MIPI) display interface 1655. In at least one embodiment, storage may be provided by a flash memory subsystem 1660, which includes flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1665 for access to SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits may additionally include an embedded security engine 1670.

[0280] The inference and / or training logic 715 is used to perform inference and / or training operations related to one or more embodiments. Details relating to the inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, the inference and / or training logic 715 may be used in the integrated circuit 1600 for inference or prediction operations, at least in part, based on weight parameters calculated using the neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0281] In at least one embodiment, one or more systems shown in Figure 16 are used to implement a system for action recognition as described with respect to Figures 1 to 6. In at least one embodiment, one or more systems shown in Figure 16 are used to perform one or more quantization and pruning processes on one or more neural networks. In at least one embodiment, one or more systems shown in Figure 16 are used to perform action recognition using a hardware accelerator and / or one or more neural networks processed through one or more quantization and pruning processes.

[0282] Figures 17A to 17B show exemplary integrated circuits and associated graphics processors that can be fabricated using one or more IP cores according to various embodiments described herein. In addition to those shown, at least one embodiment may include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0283] Figures 17A and 17B are block diagrams illustrating exemplary graphics processors for use in a SoC according to embodiments described herein. Figure 17A shows an exemplary graphics processor 1710 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores, according to at least one embodiment. Figure 17B shows an additional exemplary graphics processor 1740 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, the graphics processor 1710 of Figure 17A is a low-power graphics processor core. In at least one embodiment, the graphics processor 1740 of Figure 17B is a higher-performance graphics processor core. In at least one embodiment, each of the graphics processors 1710 and 1740 may be a variation of the graphics processor 1610 of Figure 16.

[0284] In at least one embodiment, the graphics processor 1710 includes a vertex processor 1705 and one or more fragment processors 1715A-1715N (e.g., 1715A, 1715B, 1715C, 1715D-1715N-1, and 1715N). In at least one embodiment, the graphics processor 1710 can execute different shader programs via separate logic, thereby optimizing the vertex processor 1705 to perform operations for a vertex shader program, and the one or more fragment processors 1715A-1715N to perform fragment (e.g., pixel) shading operations for a fragment or pixel shader program. In at least one embodiment, the vertex processor 1705 performs the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. In at least one embodiment, one or more fragment processors 1715A–1715N use primitive and vertex data generated by the vertex processor 1705 to create a frame buffer that is displayed on the display device. In at least one embodiment, one or more fragment processors 1715A–1715N are optimized to execute fragment shader programs such as those provided in the OpenGL API, and the OpenGL API may be used to perform operations similar to those of pixel shader programs such as those provided in the Direct 3D API.

[0285] In at least one embodiment, the graphics processor 1710 additionally includes one or more memory management units (MMUs) 1720A-1720B, one or more caches 1725A-1725B, and one or more circuit interconnects 1730A-1730B. In at least one embodiment, one or more MMUs 1720A-1720B provide virtual-physical address mappings for the graphics processor 1710, including vertex processors 1705 and / or one or more fragment processors 1715A-1715N, which may reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more caches 1725A-1725B. In at least one embodiment, one or more MMUs 1720A-1720B may be synchronized with other MMUs in the system, including one or more MMUs associated with one or more application processors 1605, image processor 1615, and / or video processor 1620 in Figure 16, thereby allowing each processor 1605-1620 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1730A-1730B enable the graphics processor 1710 to interface with other IP cores in the SoC, either via the SoC's internal bus or via a direct connection.

[0286] In at least one embodiment, as shown in Figure 17B, the graphics processor 1740 includes one or more shader cores 1755A-1755N (e.g., 1755A, 1755B, 1755C, 1755D, 1755E, 1755F-1755N-1, and 1755N), and one or more shader cores 1755A-1755N provide a unified shader core architecture in which a single core, or type, or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1740 includes an intercore task manager 1745 that acts as a thread dispatcher for dispatching execution threads to one or more shader cores 1755A-1755N, and a tiling unit 1758 for accelerating tiling operations for tile-based rendering, where rendering operations for a scene are subdivided in image space, for example, to take advantage of local space coherence within the scene or to optimize the use of an internal cache.

[0287] The inference and / or training logic 715 is used to perform inference and / or training operations related to one or more embodiments. Details relating to the inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, the inference and / or training logic 715 may be used in integrated circuits 17A and / or 17B for inference or prediction operations, at least in part, based on weight parameters calculated using the neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0288] In at least one embodiment, one or more systems shown in Figures 17A to 17B are used to implement a system for action recognition as described with respect to Figures 1 to 6. In at least one embodiment, one or more systems shown in Figures 17A to 17B are used to perform one or more quantization and pruning processes on one or more neural networks. In at least one embodiment, one or more systems shown in Figures 17A to 17B are used to perform action recognition using a hardware accelerator and / or one or more neural networks processed through one or more quantization and pruning processes.

[0289] Figures 18A and 18B illustrate additional exemplary graphics processor logic according to embodiments described herein. Figure 18A shows a graphics core 1800, which in at least one embodiment may be included within the graphics processor 1610 of Figure 16, and in at least one embodiment may be unified shader cores 1755A to 1755N, as in the case of Figure 17B. Figure 18B shows a highly parallel general-purpose graphics processing unit ("GPGPU") 1830, which in at least one embodiment is suitable for deployment on a multi-chip module.

[0290] In at least one embodiment, the graphics core 1800 includes a shared instruction cache 1802, a texture unit 1818, and a cache / shared memory 1820, which are common to the execution resources within the graphics core 1800. In at least one embodiment, the graphics core 1800 may include multiple slices 1801A-1801N, or partitions for each core, and the graphics processor may include multiple instances of the graphics core 1800. In at least one embodiment, slices 1801A-1801N may include support logic including local instruction caches 1804A-1804N, thread schedulers 1806A-1806N, thread dispatchers 1808A-1808N, and sets of registers 1810A-1810N. In at least one embodiment, slices 1801A to 1801N may include a set of additional function units (AFUs) 1812A to 1812N, floating-point units (FPUs) 1814A to 1814N, integer arithmetic logic units (ALUs) 1816A to 1816N, address computational units (ACUs) 1813A to 1813N, double-precision floating-point units (DPFPUs) 1815A to 1815N, and matrix processing units (MPUs) 1817A to 1817N.

[0291] In at least one embodiment, the FPU1814A-1814N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, and the DPFPU1815A-1815N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU1816A-1816N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision and may be configured for mixed-precision operations. In at least one embodiment, the MPU1817A-1817N may also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPU1817-1817N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general-purpose matrix-to-matrix multiplication (GEMM). In at least one embodiment, AFU1812A~1812N can perform additional logical operations not supported by the floating-point unit or integer unit, including trigonometric function operations (e.g., sine, cosine, etc.).

[0292] The inference and / or training logic 715 is used to perform inference and / or training operations related to one or more embodiments. Details relating to the inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, the inference and / or training logic 715 may be used in the graphics core 1800 for inference or prediction operations, at least in part, based on weight parameters calculated using the neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0293] Figure 18B shows a general-purpose processing unit (GPGPU) 1830, which in at least one embodiment may be configured to enable highly parallel compute operations to be performed by an array of graphics processing units. In at least one embodiment, the GPGPU 1830 may be directly linked to other instances of the GPGPU 1830 to create a multi-GPU cluster to improve training speed for deep neural networks. In at least one embodiment, the GPGPU 1830 includes a host interface 1832 for enabling connectivity with a host processor. In at least one embodiment, the host interface 1832 is a PCI Express interface. In at least one embodiment, the host interface 1832 may be a vendor-specific communication interface or communication fabric. In at least one embodiment, the GPGPU 1830 receives commands from the host processor and uses the global scheduler 1834 to distribute the execution threads associated with those commands across a set of compute clusters 1836A-1836H. In at least one embodiment, the compute clusters 1836A-1836H share a cache memory 1838. In at least one embodiment, the cache memory 1838 can act as a higher-level cache for the cache memory within the compute clusters 1836A-1836H.

[0294] In at least one embodiment, the GPGPU 1830 includes memory 1844A-1844B coupled to compute clusters 1836A-1836H via a set of memory controllers 1842A-1842B. In at least one embodiment, the memory 1844A-1844B may include various types of memory devices, including graphics random access memory such as dynamic random access memory (DRAM) or synchronous graphics random access memory (SGRAM) including graphics double data rate (GDDR) memory.

[0295] In at least one embodiment, each compute cluster 1836A–1836H includes a set of graphics cores, such as the graphics core 1800 in Figure 18A, and the set of graphics cores may include multiple types of integer and floating-point logic units capable of performing computational operations at varying precisions, including those suitable for machine learning computations. For example, in at least one embodiment, at least a subset of floating-point units in each compute cluster 1836A–1836H may be configured to perform 16-bit or 32-bit floating-point operations, and different subsets of floating-point units may be configured to perform 64-bit floating-point operations.

[0296] In at least one embodiment, multiple instances of GPGPU 1830 may be configured to operate as a compute cluster. In at least one embodiment, the communication used for synchronization and data exchange by compute clusters 1836A-1836H varies across embodiments. In at least one embodiment, multiple instances of GPGPU 1830 communicate via a host interface 1832. In at least one embodiment, GPGPU 1830 includes an I / O hub 1839, which couples GPGPU 1830 with a GPU link 1840 that enables direct connections to other instances of GPGPU 1830. In at least one embodiment, the GPU link 1840 is coupled with a dedicated GPU-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1830. In at least one embodiment, the GPU link 1840 is coupled with a high-speed interconnect to send and receive data to and from other GPGPUs or parallel processors. In at least one embodiment, multiple instances of the GPGPU 1830 are located on separate data processing systems and communicate via a network device accessible through the host interface 1832. In at least one embodiment, the GPU link 1840 may be configured to enable connection to a host processor in addition to, or as an alternative to, the host interface 1832.

[0297] In at least one embodiment, the GPGPU1830 may be configured to train a neural network. In at least one embodiment, the GPGPU1830 may be used within an inference platform. In at least one embodiment where the GPGPU1830 is used for inference, the GPGPU1830 may include fewer compute clusters 1836A-1836H compared to when the GPGPU1830 is used to train a neural network. In at least one embodiment, the memory technology associated with memory 1844A-1844B may differ between the inference configuration and the training configuration, with higher bandwidth memory technology allocated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU1830 may support inference-specific instructions. For example, in at least one embodiment, the inference configuration may provide support for one or more 8-bit integer dot product instructions, which may be used during inference operations for the introduced neural network.

[0298] The inference and / or training logic 715 is used to perform inference and / or training operations related to one or more embodiments. Details relating to the inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, the inference and / or training logic 715 may be used in the GPGPU 1830 for inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0299] In at least one embodiment, one or more systems shown in Figures 18A to 18B are used to implement a system for action recognition as described with respect to Figures 1 to 6. In at least one embodiment, one or more systems shown in Figures 18A to 18B are used to perform one or more quantization and pruning processes on one or more neural networks. In at least one embodiment, one or more systems shown in Figures 18A to 18B are used to perform action recognition using a hardware accelerator and / or one or more neural networks processed through one or more quantization and pruning processes.

[0300] Figure 19 is a block diagram of a computing system 1900 according to at least one embodiment. In at least one embodiment, the computing system 1900 includes a processing subsystem 1901 having one or more processors 1902 and system memory 1904 communicating via an interconnection path which may include a memory hub 1905. In at least one embodiment, the memory hub 1905 may be a separate component within a chipset component or may be incorporated within one or more processors 1902. In at least one embodiment, the memory hub 1905 is coupled to an I / O subsystem 1911 via a communication link 1906. In at least one embodiment, the I / O subsystem 1911 includes an I / O hub 1907 which can enable the computing system 1900 to receive input from one or more input devices 1908. In at least one embodiment, the I / O hub 1907 can enable a display controller, which may be included in one or more processors 1902, to provide output to one or more display devices 1910A. In at least one embodiment, one or more display devices 1910A coupled with the I / O hub 1907 may include local, internal, or embedded display devices.

[0301] In at least one embodiment, the processing subsystem 1901 includes one or more parallel processors 1912 coupled to a memory hub 1905 via a bus or other communication link 1913. In at least one embodiment, the communication link 1913 may use any number of standards-based communication link technologies or protocols, such as PCI Express, or it may be a vendor-specific communication interface or communication fabric. In at least one embodiment, one or more parallel processors 1912 may form a computation-focused parallel or vector processing system that may include a large number of processing cores and / or processing clusters, such as a many integrated core (MIC) processor. In at least one embodiment, some or all of the (one or more) parallel processors 1912 may form a graphics processing subsystem, which may output pixels to one of one or more display devices 1910A coupled via an I / O hub 1907. In at least one embodiment, the (one or more) parallel processors 1912 may also include a display controller and a display interface (not shown) for enabling direct connection to one or more display devices 1910B.

[0302] In at least one embodiment, the system storage unit 1914 can be connected to the I / O hub 1907 to provide storage functionality for the computing system 1900. In at least one embodiment, an I / O switch 1916 may be used to provide an interface mechanism for enabling connections between the I / O hub 1907 and other components such as a network adapter 1918 and / or a wireless network adapter 1919 that may be incorporated into the platform, as well as various other devices that may be added via one or more add-in devices 1920. In at least one embodiment, the network adapter 1918 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 1919 may include one or more other network devices, including Wi-Fi, Bluetooth, near-field communication (NFC), or one or more wireless radios.

[0303] In at least one embodiment, the computing system 1900 may include other components not explicitly shown, such as USB or other port connections, optical storage drives, and video capture devices, and may also be connected to the I / O hub 1907. In at least one embodiment, the communication paths interconnecting the various components in Figure 19 may be implemented using any preferred protocol, such as a PCI (Peripheral Component Interconnection) based protocol (e.g., PCI-Express), or other bus or point-to-point communication interfaces and / or protocols, such as NV-Link High-Speed ​​Interconnection, or one or more protocols, or interconnection protocols.

[0304] In at least one embodiment, one or more parallel processors 1912 incorporate circuit elements optimized for graphics and video processing, such as video output circuit elements, to constitute a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 1912 incorporate circuit elements optimized for general-purpose processing. In at least one embodiment, components of the computing system 1900 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1912, a memory hub 1905, one or more processors 1902, and an I / O hub 1907 may be incorporated into a system-on-a-chip (SoC) integrated circuit. In at least one embodiment, components of the computing system 1900 may be incorporated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computing system 1900 may be incorporated into a multi-chip module (MCM), and the multi-chip module may be interconnected with other multi-chip modules to form a modular computing system.

[0305] The inference and / or training logic 715 is used to perform inference and / or training operations related to one or more embodiments. Details relating to the inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, the inference and / or training logic 715 may be used in the system of Figure 1900 for inference or prediction operations, at least in part, based on weight parameters calculated using the neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0306] In at least one embodiment, one or more systems shown in Figure 19 are used to implement a system for action recognition as described with respect to Figures 1 to 6. In at least one embodiment, one or more systems shown in Figure 19 are used to perform one or more quantization and pruning processes on one or more neural networks. In at least one embodiment, one or more systems shown in Figure 19 are used to perform action recognition using a hardware accelerator and / or one or more neural networks processed through one or more quantization and pruning processes.

[0307] Processor Figure 20A shows a parallel processor 2000 according to at least one embodiment. In at least one embodiment, various components of the parallel processor 2000 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA). In at least one embodiment, the parallel processor 2000 shown is a variation of one or more parallel processors 1912 shown in Figure 19, according to an exemplary embodiment.

[0308] In at least one embodiment, the parallel processor 2000 includes a parallel processing unit 2002. In at least one embodiment, the parallel processing unit 2002 includes an I / O unit 2004 that enables communication with other devices, including other instances of the parallel processing unit 2002. In at least one embodiment, the I / O unit 2004 may be directly connected to other devices. In at least one embodiment, the I / O unit 2004 connects to other devices via the use of a hub or switch interface, such as a memory hub 2005. In at least one embodiment, the connection between the memory hub 2005 and the I / O unit 2004 forms a communication link 2013. In at least one embodiment, the I / O unit 2004 connects to a host interface 2006 and a memory crossbar 2016, the host interface 2006 receiving commands intended to perform processing operations and the memory crossbar 2016 receiving commands intended to perform memory operations.

[0309] In at least one embodiment, when the host interface 2006 receives a command buffer via the I / O unit 2004, the host interface 2006 can direct work operations to the front end 2008 to execute those commands. In at least one embodiment, the front end 2008 is coupled with a scheduler 2010, which is configured to distribute commands or other work items to the processing cluster array 2012. In at least one embodiment, the scheduler 2010 ensures that the processing cluster array 2012 is properly configured and enabled before tasks are distributed to the clusters of the processing cluster array 2012. In at least one embodiment, the scheduler 2010 is implemented via firmware logic running on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2010 can be configured to perform complex scheduling and work distribution operations at both coarse and fine granularity, enabling rapid preemption and context switching of threads running on the processing array 2012. In at least one embodiment, the host software can prove the workload for scheduling on the processing cluster array 2012 via one of several graphics processing paths. In at least one embodiment, the workload can then be automatically distributed across the processing array cluster 2012 by the scheduler 2010 logic within the microcontroller, which includes the scheduler 2010.

[0310] In at least one embodiment, the processing cluster array 2012 may contain up to "N" processing clusters (e.g., cluster 2014A, cluster 2014B to cluster 2014N), where "N" represents a positive integer (which may be a different integer "N" than that used in other figures). In at least one embodiment, each cluster 2014A to 2014N of the processing cluster array 2012 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 2010 may allocate work to clusters 2014A to 2014N of the processing cluster array 2012 using various scheduling and / or work distribution algorithms, which may vary depending on the workload arising for each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by the scheduler 2010 or partially assisted by compiler logic during the compilation of program logic configured for execution by the processing cluster array 2012. In at least one embodiment, different clusters 2014A to 2014N of the processing cluster array 2012 may be allocated to process different types of programs or to perform different types of calculations.

[0311] In at least one embodiment, the processing cluster array 2012 may be configured to perform various types of parallel processing operations. In at least one embodiment, the processing cluster array 2012 is configured to perform general-purpose parallel compute operations. For example, in at least one embodiment, the processing cluster array 2012 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations including physical operations, and performing data transformations.

[0312] In at least one embodiment, the processing cluster array 2012 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2012 may include additional logic to support the execution of such graphics processing operations, including, but not limited to, texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2012 may be configured to execute graphics processing-related shader programs, such as vertex shaders, tessellation shaders, geometry shaders, and pixel shaders, but not limited to these. In at least one embodiment, the parallel processing unit 2002 may transfer data from system memory via the I / O unit 2004 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2022) during processing and then written back to system memory.

[0313] In at least one embodiment, when a parallel processing unit 2002 is used to perform graphics processing, the scheduler 2010 may be configured to divide the processing workload into tasks of approximately equal size in order to better enable the distribution of graphics processing operations across multiple clusters 2014A to 2014N of the processing cluster array 2012. In at least one embodiment, parts of the processing cluster array 2012 may be configured to perform different types of processing. For example, in at least one embodiment, to produce a rendered image for display, a first part may be configured to perform vertex shading and topology generation, a second part may be configured to perform tessellation and geometry shading, and a third part may be configured to perform pixel shading or other screen-space operations. In at least one embodiment, intermediate data produced by one or more of the clusters 2014A to 2014N may be stored in a buffer to enable the intermediate data to be transmitted between clusters 2014A to 2014N for further processing.

[0314] In at least one embodiment, the processing cluster array 2012 may receive processing tasks to be executed via the scheduler 2010, which receives commands defining the processing tasks from the front-end 2008. In at least one embodiment, the processing task may include an index of the data to be processed, e.g., surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data should be processed (e.g., which program should be executed). In at least one embodiment, the scheduler 2010 may be configured to fetch the index corresponding to the task or to receive the index from the front-end 2008. In at least one embodiment, the front-end 2008 may be configured to ensure that the processing cluster array 2012 is configured to a valid state before the workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is started.

[0315] In at least one embodiment, each of one or more instances of the parallel processing unit 2002 can be coupled to a parallel processor memory 2022. In at least one embodiment, the parallel processor memory 2022 may be accessed via a memory crossbar 2016, which can receive memory requests from the processing cluster array 2012 and the I / O unit 2004. In at least one embodiment, the memory crossbar 2016 can access the parallel processor memory 2022 via a memory interface 2018. In at least one embodiment, the memory interface 2018 may include a plurality of partition units (e.g., partition unit 2020A, partition unit 2020B to partition unit 2020N), each of which can be coupled to a portion of the parallel processor memory 2022 (e.g., a memory unit). In at least one embodiment, the number of partition units 2020A to 2020N is configured to be equal to the number of memory units, such that the first partition unit 2020A has a corresponding first memory unit 2024A, the second partition unit 2020B has a corresponding memory unit 2024B, and the nth partition unit 2020N has a corresponding nth memory unit 2024N. In at least one embodiment, the number of partition units 2020A to 2020N may not be equal to the number of memory devices.

[0316] In at least one embodiment, memory units 2024A to 2024N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM) including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 2024A to 2024N may also include 3D stacked memory, including but not limited to high-bandwidth memory (HBM). In at least one embodiment, to efficiently use the available bandwidth of parallel processor memory 2022, render targets such as frame buffers or texture maps may be stored across memory units 2024A to 2024N, allowing partition units 2020A to 2020N to write portions of each render target in parallel. In at least one embodiment, local instances of parallel processor memory 2022 may be excluded to favor a unified memory design that utilizes system memory in conjunction with local cache memory.

[0317] In at least one embodiment, one of the clusters 2014A to 2014N of the processing cluster array 2012 can process data that will be written to one of the memory units 2024A to 2024N in the parallel processor memory 2022. In at least one embodiment, the memory crossbar 2016 may be configured to forward the output of each cluster 2014A to 2014N to any partition unit 2020A to 2020N that can perform additional processing operations on the output, or to another cluster 2014A to 2014N. In at least one embodiment, each cluster 2014A to 2014N can communicate with the memory interface 2018 through the memory crossbar 2016 to read from or write to various external memory devices. In at least one embodiment, the memory crossbar 2016 has connections to a memory interface 2018 for communicating with the I / O unit 2004, as well as to a local instance of the parallel processor memory 2022, which allows processing units in different processing clusters 2014A-2014N to communicate with system memory or other memory that is not local to the parallel processing unit 2002. In at least one embodiment, the memory crossbar 2016 can use virtual channels to isolate traffic streams between clusters 2014A-2014N and partition units 2020A-2020N.

[0318] In at least one embodiment, multiple instances of the parallel processing unit 2002 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of the parallel processing unit 2002 may be configured to interoperate even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 2002 may include higher-precision floating-point units than other instances. In at least one embodiment, a system incorporating one or more instances of the parallel processing unit 2002 or parallel processor 2000 may be implemented in a variety of configurations and form factors, including, but not limited to, desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0319] Figure 20B is a block diagram of partition unit 2020 according to at least one embodiment. In at least one embodiment, partition unit 2020 is one instance of partition units 2020A to 2020N in Figure 20A. In at least one embodiment, partition unit 2020 includes an L2 cache 2021, a frame buffer interface 2025, and a ROP 2026 (raster arithmetic unit). In at least one embodiment, L2 cache 2021 is a read / write cache configured to perform load and store operations received from memory crossbar 2016 and ROP 2026. In at least one embodiment, read misses and urgent write-back requests are output to the frame buffer interface 2025 by L2 cache 2021 for processing. In at least one embodiment, updates may also be sent to the frame buffer via the frame buffer interface 2025 for processing. In at least one embodiment, the frame buffer interface 2025 interfaces with one of the memory units in the parallel processor memory, such as memory units 2024A to 2024N (for example, in the parallel processor memory 2022) in Figure 20.

[0320] In at least one embodiment, ROP2026 is a processing unit that performs raster operations such as stenciling, z-testing, and blending. In at least one embodiment, ROP2026 then outputs the processed graphics data, which is stored in graphics memory. In at least one embodiment, ROP2026 includes compression logic for compressing depth or color data written to memory and for decompressing depth or color data read from memory. In at least one embodiment, the compression logic may be lossless compression logic that utilizes one or more of a plurality of compression algorithms. In at least one embodiment, the type of compression performed by ROP2026 may vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, delta color compression is performed on a tile-by-tile basis for depth and color data.

[0321] In at least one embodiment, ROP2026 is contained within each processing cluster (for example, clusters 2014A-2014N in Figure 20A) rather than within a partition unit 2020. In at least one embodiment, read and write requests for pixel data, rather than pixel fragment data, are transmitted via the memory crossbar 2016. In at least one embodiment, the processed graphics data may be displayed on a display device, such as one of the one or more display devices 1910 in Figure 19, and routed for further processing by one or more processors 1902, or for further processing by one of the processing entities in the parallel processors 2000 in Figure 20A.

[0322] Figure 20C is a block diagram of a processing cluster 2014 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is one instance of processing clusters 2014A to 2014N in Figure 20A. In at least one embodiment, processing cluster 2014 may be configured to run many threads in parallel, where “thread” refers to an instance of a particular program running on a particular set of input data. In at least one embodiment, a single-instruction, multiple-data (SIMD) instruction issuing technique is used to support the parallel execution of many threads without providing multiple independent instruction units. In at least one embodiment, a single-instruction, multiple-thread (SIMT) technique is used to support the parallel execution of many threads with a total synchronization, using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster of the processing cluster.

[0323] In at least one embodiment, the operation of the processing cluster 2014 may be controlled via a pipeline manager 2032 that distributes processing tasks to SIMT parallel processors. In at least one embodiment, the pipeline manager 2032 receives instructions from the scheduler 2010 in Figure 20A and manages the execution of those instructions via the graphics multiprocessor 2034 and / or texture unit 2036. In at least one embodiment, the graphics multiprocessor 2034 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of different architectures may be included within the processing cluster 2014. In at least one embodiment, one or more instances of the graphics multiprocessor 2034 may be included within the processing cluster 2014. In at least one embodiment, the graphics multiprocessor 2034 may process data, and a data crossbar 2040 may be used to distribute the processed data to one of several possible destinations, including other shader units. In at least one embodiment, the pipeline manager 2032 can facilitate the distribution of processed data by specifying destinations for the processed data that will be distributed via the data crossbar 2040.

[0324] In at least one embodiment, each graphics multiprocessor 2034 within the processing cluster 2014 may contain an identical set of function execution logic (e.g., arithmetic logic units, load-store units, etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, where a new instruction can be issued before the previous instruction is completed. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifts, and the computation of various algebraic functions. In at least one embodiment, the same function unit hardware may be utilized to perform different operations, and any combination of function units may exist.

[0325] In at least one embodiment, instructions sent to processing cluster 2014 constitute a thread. In at least one embodiment, a set of threads running across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a common program for different input data. In at least one embodiment, each thread in a thread group may be assigned to a different processing engine in the graphics multiprocessor 2034. In at least one embodiment, a thread group may contain fewer threads than the number of processing engines in the graphics multiprocessor 2034. In at least one embodiment, when a thread group contains fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycle in which the thread group is being processed. In at least one embodiment, a thread group may also contain more threads than the number of processing engines in the graphics multiprocessor 2034. In at least one embodiment, when a thread group contains more threads than the number of processing engines in the graphics multiprocessor 2034, processing may be performed over consecutive clock cycles. In at least one embodiment, multiple thread groups may run simultaneously on the graphics multiprocessor 2034.

[0326] In at least one embodiment, the graphics multiprocessor 2034 includes internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2034 may omit the internal cache and use cache memory within the processing cluster 2014 (e.g., L1 cache 2048). In at least one embodiment, each graphics multiprocessor 2034 also has access to L2 caches within partition units (e.g., partition units 2020A-2020N in Figure 20A), which are shared among all processing clusters 2014 and may be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 2034 may also have access to off-chip global memory, which may include one or more of the local parallel processor memory and / or system memory. In at least one embodiment, any memory outside of the parallel processing unit 2002 may be used as global memory. In at least one embodiment, the processing cluster 2014 includes multiple instances of the graphics multiprocessor 2034, which can share common instructions and data, and the common instructions and data can be stored in the L1 cache 2048.

[0327] In at least one embodiment, each processing cluster 2014 may include an MMU 2045 (Memory Management Unit) configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 2045 may reside within the memory interface 2018 in Figure 20A. In at least one embodiment, the MMU 2045 includes a set of page table entries (PTEs) used to map virtual addresses to physical addresses of tiles and optionally cache line indices. In at least one embodiment, the MMU 2045 may include an address translation lookaside buffer (TLB) or cache, which may reside within the graphics multiprocessor 2034 or L1 2048 cache or processing cluster 2014. In at least one embodiment, physical addresses are processed to distribute surface data access locally and enable efficient request interleaving between partition units. In at least one embodiment, a cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0328] In at least one embodiment, the processing cluster 2014 may be configured such that each graphics multiprocessor 2034 is coupled to a texture unit 2036 for performing texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2034 and, if necessary, fetched from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 2034 outputs the processed tasks to a data crossbar 2040 to provide the processed tasks to another processing cluster 2014 for further processing, or stores the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 2016. In at least one embodiment, a pre-ROP2042 (pre-raster arithmetic unit) is configured to receive data from a graphics multiprocessor 2034 and direct the data to an ROP unit, which may be located together with partition units as described herein (for example, partition units 2020A-2020N in Figure 20A). In at least one embodiment, the pre-ROP2042 unit can perform optimizations for color blending to organize pixel color data and perform address translation.

[0329] The inference and / or training logic 715 is used to perform inference and / or training operations related to one or more embodiments. Details relating to the inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, the inference and / or training logic 715 may be used in the graphics processing cluster 2014 for inference or prediction operations, at least in part, based on weight parameters calculated using the neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0330] Figure 20D shows a graphics multiprocessor 2034 according to at least one embodiment. In at least one embodiment, the graphics multiprocessor 2034 is coupled with a pipeline manager 2032 of a processing cluster 2014. In at least one embodiment, the graphics multiprocessor 2034 has an execution pipeline that includes, but is not limited to, an instruction cache 2052, an instruction unit 2054, an address mapping unit 2056, a register file 2058, one or more general-purpose graphics processing unit (GPGPU) cores 2062, and one or more load / store units 2066. In at least one embodiment, the GPGPU core 2062 and the load / store unit 2066 are coupled with cache memory 2072 and shared memory 2070 via a memory and cache interconnect 2068.

[0331] In at least one embodiment, the instruction cache 2052 receives a stream of instructions to be executed from the pipeline manager 2032. In at least one embodiment, the instructions are cached in the instruction cache 2052 and dispatched for execution by the instruction unit 2054. In at least one embodiment, the instruction unit 2054 may dispatch the instructions as a thread group (e.g., a warp), where each thread in the thread group is assigned to a different execution unit within the GPGPU core 2062. In at least one embodiment, the instructions may access a local, shared, or global address space by specifying an address in the unified address space. In at least one embodiment, the address mapping unit 2056 may be used to translate addresses in the unified address space to individual memory addresses that can be accessed by the load / store unit 2066.

[0332] In at least one embodiment, register file 2058 provides a set of registers to the functional units of the graphics multiprocessor 2034. In at least one embodiment, register file 2058 provides temporary storage for operands connected to the data paths of the functional units of the graphics multiprocessor 2034 (e.g., GPGPU core 2062, load / store unit 2066). In at least one embodiment, register file 2058 is divided among each of the functional units so that each functional unit is allocated a dedicated portion of register file 2058. In one embodiment, register file 2058 is divided among different warps being executed by the graphics multiprocessor 2034.

[0333] In at least one embodiment, each GPGPU core 2062 may include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) used to execute instructions of the graphics multiprocessor 2034. In at least one embodiment, the GPGPU core 2062 may have a similar architecture or a different architecture. In at least one embodiment, a first part of the GPGPU core 2062 includes a single-precision FPU and an integer ALU, and a second part of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement IEEE 754-2008 standard floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 2034 may additionally include one or more fixed-function units or special-function units for performing specific functions such as rectangular copy operations or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 2062 may also include fixed or special function logic.

[0334] In at least one embodiment, the GPGPU core 2062 includes SIMD logic capable of executing a single instruction for multiple sets of data. In at least one embodiment, the GPGPU core 2062 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for the GPGPU core may be generated at compile time by the shader compiler or automatically generated when running a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model may be executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operation may be executed in parallel via a single SIMD8 logic unit.

[0335] In at least one embodiment, the memory and cache interconnect 2068 is an interconnect network connecting each functional unit of the graphics multiprocessor 2034 to the register file 2058 and shared memory 2070. In at least one embodiment, the memory and cache interconnect 2068 is a crossbar interconnect that enables the load / store unit 2066 to implement load and store operations between the shared memory 2070 and the register file 2058. In at least one embodiment, the register file 2058 can operate at the same frequency as the GPGPU core 2062, and therefore data transfer between the GPGPU core 2062 and the register file 2058 can have very low latency. In at least one embodiment, the shared memory 2070 may be used to enable communication between threads running on functional units within the graphics multiprocessor 2034. In at least one embodiment, the cache memory 2072 may be used as a data cache to cache texture data communicated between functional units and the texture unit 2036, for example. In at least one embodiment, shared memory 2070 may also be used as a program-managed cache. In at least one embodiment, a thread running on the GPGPU core 2062 may programmatically store data in shared memory in addition to automatically cached data stored in cache memory 2072.

[0336] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to a host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one em...

Claims

1. A method performed by a system for action recognition, The steps include receiving multiple frames of a video, The steps include determining one or more objects represented in the aforementioned plurality of frames, The steps include generating a set of bounding boxes corresponding to one or more objects represented in the aforementioned multiple frames, A step of calculating the movement of one or more objects represented in one or more pixels between frames of the plurality of frames, A step of cropping the movement based on the set of bounding boxes, The steps include: cropping at least one of the plurality of frames based on the set of bounding boxes; A step of classifying one or more actions performed by the one or more objects and represented in the multiple frames, based at least partially on the cropped movement and the cropped at least one frame. Methods that include...

2. The method according to claim 1, wherein the set of bounding boxes is generated using a first neural network.

3. The method according to claim 2, wherein the one or more actions are classified using a second neural network.

4. The steps of determining one or more values ​​based at least partially on one or more kernels of the first neural network and the second neural network, The steps of removing a set of kernels from the first neural network and the second neural network based at least partially on one or more of the aforementioned values. The method according to claim 3, further comprising:

5. The method according to claim 1, wherein the one or more actions include at least the action of sitting, walking, running, or climbing stairs.

6. The method according to claim 3, wherein the first neural network and the second neural network each include one or more quantized weights.

7. From video data, identify one or more objects shown in one or more frames, Using one or more frames of the video data, calculate one or more flow fields and one or more bounding boxes corresponding to the one or more objects: Based on the one or more bounding boxes, the one or more flow fields are cropped. Based on the one or more bounding boxes, crop at least one of the one or more frames, Based on the cropped flow field of one or more objects and the cropped at least one frame, one or more classifications are determined for one or more actions performed by the one or more objects. A processor comprising one or more circuits.

8. The aforementioned one or more circuits may further A first neural network is used to compute one or more bounding boxes. The processor according to claim 7, which uses a second neural network to determine the one or more classifications.

9. The aforementioned one or more circuits may further The L1 norm values ​​of one or more kernels of the first neural network and the second neural network are calculated. The processor according to claim 8, wherein a set of kernels is removed from the first neural network and the second neural network based at least in part on the one or more L1 norm values.

10. The processor according to claim 9, wherein the set of kernels corresponds to one or more kernels having an L1 norm value above a threshold.

11. The processor according to claim 7, wherein one or more circuits further use one or more hardware accelerators to compute the one or more flow fields.

12. The processor according to claim 8, wherein the first neural network and the second neural network include sets of quantized weights.

13. The processor according to claim 7, wherein the video data is captured from one or more autonomous vehicle systems.

14. Hardware accelerators and Memory equipped with instructions A computing device comprising, wherein the instruction is at least, Receive multiple frames, Using the aforementioned hardware accelerator, one or more vector fields corresponding to the plurality of frames are determined. Using a first neural network, determine the set of bounding boxes corresponding to one or more objects represented in the multiple frames. Based on the set of bounding boxes, one or more vector fields are cropped. Based on the set of bounding boxes, at least one of the plurality of frames is cropped. A second neural network is used to classify one or more actions represented in the multiple frames based at least partially on the cropped one or more vector fields and the cropped at least one frame. A computing device that can be executed by one or more processors of the computing device.

15. The computing device according to claim 14, wherein the first neural network and the second neural network each include one or more weights processed through one or more quantization processes.

16. The computing device according to claim 15, wherein the one or more quantization processes include the conversion of the one or more weights from a first representation to a second representation.

17. The computing device according to claim 15, wherein the one or more quantization processes are at least partially based on one or more Kullback-Leibler divergence values.

18. The computing device according to claim 16, wherein the first representation is a 32-bit floating-point representation and the second representation is an 8-bit integer representation.

19. The computing device according to claim 14, wherein the instructions further include instructions that can be executed by the one or more processors to acquire at least the plurality of frames from one or more image capture hardware of the computing device.

20. The computing device according to claim 14, wherein the hardware accelerator comprises one or more parallel processing units.

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