electronic machinery

Abstract

An electronic device (1) according to the present disclosure is provided with a semiconductor substrate (2), a chip (3), bumps (4, 4a), and a side wall portion (5, 5a). The bumps (4, 4a) connect a plurality of connection pads (21, 31) provided on opposite main surfaces of the semiconductor substrate (2) and the chip (4, 4a). The side wall portion (5, 5a) includes a porous metal layer (41, 51) annularly surrounding a region in which a plurality of bumps (4, 4a) are provided, and connects the semiconductor substrate (2) and the chip (3). The chip (3) has a thermal expansion coefficient differing from that of the semiconductor substrate by 0.1 ppm / ℃ or more. The chip (3) comprises a semiconductor laser, and the semiconductor substrate (2) includes a drive circuit for driving the semiconductor laser.

Description

Technical Field

[0001] The present disclosure relates to an electronic device.

Background Art

[0002] An electronic device that flip-chip connects an electronic circuit element onto a substrate is sealed with, for example, resin in order to prevent the intrusion of cutting water used when individualizing each electronic device from a semiconductor wafer.

[0003] However, when an electronic device is sealed with resin, there are problems such as contamination of electrodes by the resin, lengthening of the working time due to injecting resin for each electronic device, and an increase in the amount of resin discarded due to the lengthening of the working time.

[0004] For this reason, there is an electronic device in which the electrodes between the electronic circuit element and the substrate are connected by a gold-tin bond, a gold-silver bond, a gold-aluminum bond, or a gold-gold bond, and the peripheral portion of the electronic circuit element and the opposing substrate are joined and sealed by the same joining method as the inter-electrode connection (see, for example, Patent Document 1). An electronic device characterized in that the chip electrode of the electronic circuit element and the internal electrode of the substrate are connected by a gold-tin (Au-Sn) bond, a gold-silver (Au-Ag) bond, a gold-aluminum (Au-Al) bond, or a gold-gold (Au-Au) bond, and the peripheral portion of the electronic circuit element or the portion that requires sealing and the substrate facing this are joined and sealed by the same joining method as described above.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] However, in the conventional technology described above, if there are variations in thickness or warping in the electronic circuit elements or substrates, gaps may form in the metal sealing portion, reducing the airtightness of the electronic device. Therefore, this disclosure proposes an electronic device that can improve airtightness. [Means for solving the problem]

[0007] This disclosure provides an electronic device. The electronic device comprises a semiconductor substrate, a chip, bumps, and a side wall. The bumps connect a plurality of connection pads provided on opposing main surfaces of the semiconductor substrate and the chip. The side wall includes a porous metal layer that annularly surrounds the region where the plurality of bumps are provided, and connects the semiconductor substrate and the chip. [Brief explanation of the drawing]

[0008] [Figure 1] This is a cross-sectional diagram illustrating an electronic device according to an embodiment of the present disclosure. [Figure 2] Figure 1 is a cross-sectional diagram illustrating the lines AA and AA. [Figure 3] This is an explanatory diagram showing the process of forming bumps and sidewalls on a semiconductor substrate according to this disclosure. [Figure 4] This is an explanatory diagram showing the process of forming bumps and sidewalls on a semiconductor substrate according to this disclosure. [Figure 5] This is an explanatory diagram showing the process of forming bumps and sidewalls on a semiconductor substrate according to this disclosure. [Figure 6] This is an explanatory diagram showing the process of forming bumps and sidewalls on a semiconductor substrate according to this disclosure. [Figure 7] This is an explanatory diagram showing the process of forming bumps and sidewalls on the chip according to this disclosure. [Figure 8] This is an explanatory diagram showing the process of forming bumps and sidewalls on the chip according to this disclosure. [Figure 9] This is an explanatory diagram showing the process of forming bumps and sidewalls on the chip according to this disclosure. [Figure 10]This is an explanatory diagram showing the process of forming bumps and sidewalls on the chip according to this disclosure. [Modes for carrying out the invention]

[0009] Embodiments of the present disclosure will be described in detail below with reference to the drawings. In each of the following embodiments, the same parts will be denoted by the same reference numerals and the same hatching to avoid redundant explanations.

[0010] [1. Cross-sectional structure of electronic devices] Figure 1 is a cross-sectional diagram illustrating an electronic device according to an embodiment of the present disclosure. Figure 2 is a cross-sectional diagram illustrating the line AA shown in Figure 1. As shown in Figure 1, the electronic device 1 according to the present disclosure comprises a semiconductor substrate 2, a chip 3, and bumps 4 that connect connection pads 21 and 31 provided on opposing main surfaces of the semiconductor substrate 2 and the chip 3.

[0011] Furthermore, as shown in Figures 1 and 2, the electronic device 1 includes a porous metal layer 51 that surrounds the region where the multiple bumps 4 are provided in an annular shape, and has a side wall portion 5 that connects the semiconductor substrate 2 and the chip 3. In addition, the electronic device 1 also has a connection pad 21 between the side wall portion 5 and the semiconductor substrate 2. The connection pad 21 provided between the side wall portion 5 and the semiconductor substrate 2 is not connected to the circuit inside the semiconductor substrate 2.

[0012] Chip 3 is, for example, a semiconductor laser and has a plurality of connection pads 31 on one main surface of a GaAs (gallium arsenide) substrate. Chip 3 also has a light-emitting section for the semiconductor laser inside the substrate. The light-emitting section has a plurality of light-emitting elements arranged in two dimensions that emit laser light. The light-emitting elements are connected to the connection pads 31 within Chip 3.

[0013] Furthermore, the electronic components included in chip 3 may be any electronic components other than the light-emitting part of the semiconductor laser. Also, the substrate of chip 3 may be a semi-insulating substrate such as InP (indium phosphide).

[0014] The semiconductor substrate 2 is, for example, a Si (silicon) substrate, and includes a drive circuit for driving a semiconductor laser inside. The semiconductor substrate 2 includes a plurality of connection pads 21 on one main surface. The connection pads 21 are connected to the drive circuit inside the semiconductor substrate 2. Note that the electronic circuit included in the semiconductor substrate 2 may be any electronic circuit other than the drive circuit of the semiconductor laser.

[0015] In the electronic device 1, the chip 3 is flip-chip mounted on the semiconductor substrate 2, and the drive circuit in the semiconductor substrate 2 and the chip 3, which is a semiconductor laser, are electrically connected by the bumps 4. Further, in the electronic device 1, the space where the connection pads 21, 31 and the bumps 4 are provided is sealed by the side wall portion 5.

[0016] Here, for example, when manufacturing an electronic device by flip-chip mounting a chip 3 having a semiconductor laser on a semiconductor substrate 2 including a drive circuit of the semiconductor laser, in a general manufacturing method, first, a plurality of drive circuits are formed on a Si wafer.

[0017] Thereafter, the chip 3 is laminated via bulk metal bumps on each drive circuit, and the connection pads 21, 31 provided on the opposing main surfaces of the drive circuit and the chip 3 are connected by the bumps. Then, the Si wafer is diced into individual pieces for each electronic device.

[0018] In the process of dicing the Si wafer into individual pieces for each electronic device, dicing is performed while supplying cutting water to the Si wafer. At this time, if the cutting water intrudes between the semiconductor substrate 2 and the chip 3, it will have an adverse effect on the electronic device. For this reason, generally, after each electronic device is resin-sealed, the Si wafer is diced into individual pieces for each electronic device.

[0019] However, when the electronic device is sealed with resin, there are problems such as contamination of the electrodes by the resin, prolongation of the working time due to injecting resin for each electronic device, and increase in the amount of resin that is discarded after the expiration of the service life due to the prolongation of the working time.

[0020] Therefore, there is a technique in which connection pads 21 and 31 provided on the opposing main surfaces of the semiconductor substrate 2 and the chip 3 are connected by bumps, and the areas where the connection pads 21 and 31 and bumps that require sealing are provided are joined and sealed using the same connection method as the connection between the connection pads 21 and 31.

[0021] In addition, in typical flip-chip mounting, the chip 3 is mounted onto the semiconductor substrate 2 by heating while pressing down on bulk metal bumps such as Au (gold), Cu (copper), and solder, which are provided on the opposing main surfaces of the semiconductor substrate 2 or the chip 3.

[0022] However, if the thermal expansion coefficients of the semiconductor substrate 2 and the chip 3 differ by, for example, 0.1 ppm / °C or more, the following problems arise when bulk materials such as Au, Cu, and solder are used as bump materials.

[0023] For example, when using bulk Au as the material for the bumps, in order to stably connect the semiconductor substrate 2 and the chip 3, which have different coefficients of thermal expansion, by the bumps, it is necessary to heat them to a high temperature of 300°C or higher and apply a high pressure of 100 MPa or higher between the semiconductor substrate 2 and the chip 3.

[0024] Furthermore, when bulk copper is used as the bump material, heating to over 380°C is required. Thus, when bulk gold or copper is used as the bump material, the bump connection must be made at high temperature and pressure, and such high temperature and pressure can damage chip 3, potentially reducing the reliability of the electronic device.

[0025] On the other hand, when solder is used as the material for the bumps, it is possible to make bump connections at low temperatures and low pressures compared to Au or Cu, but solder has inferior heat resistance and connection strength compared to Au or Cu. For this reason, if solder bumps are used, for example, when chip 3 expands due to heat generated by electronic components such as semiconductor lasers mounted on chip 3, an open fault may occur due to the difference in thermal expansion rates between the semiconductor substrate 2 and chip 3, potentially reducing the reliability of the electronic device.

[0026] Furthermore, as described above, the semiconductor substrate 2 in this disclosure is a Si substrate with a thermal expansion coefficient of 5.7 ppm / °C. On the other hand, the base material of the chip 3 in this disclosure is GaAs with a thermal expansion coefficient of 2.6 ppm / °C.

[0027] Thus, in electronic device 1, the difference in thermal expansion coefficients between the semiconductor substrate 2 and the chip 3 is much greater than 0.1 ppm / °C. For this reason, if the bump material of electronic device 1 is bulk Au, Cu, or solder, the above-mentioned problems may occur, potentially reducing its reliability.

[0028] Furthermore, when the peripheral area of ​​the region requiring sealing between the semiconductor substrate 2 and the chip 3 is surrounded and sealed with a bulk metal whose surface has been plated, if the thermal expansion coefficients of the semiconductor substrate 2 and the chip 3 differ by, for example, 0.1 ppm / °C or more, cracks will occur in the sealed portion. As a result, the airtightness of the electronic device will decrease.

[0029] Furthermore, if there are variations in thickness or warping in the semiconductor substrate 2 or chip 3, when the semiconductor substrate 2 and chip 3 are stacked, the sealing portion can only be bonded to the semiconductor substrate 2 and chip 3 by the convex protrusions of the plating film.

[0030] As a result, the electronic device will have gaps scattered throughout the sealed area, reducing its airtightness. Furthermore, if the semiconductor substrate 2 and chip 3 are joined by increasing the temperature and pressure to prevent the formation of gaps in the sealed area, the electronic device may experience short-circuit failures between adjacent minute bumps.

[0031] Therefore, the bump 4 of the electronic device 1 includes, for example, a porous metal layer 41 made of Au. The porous metal layer 41 contains Au particles with a particle size of 0.005 μm to 1.0 μm and a purity of 99.9% by weight or more. The components of the porous metal layer 41 may also be, for example, Cu, Ag (silver), or Pt (platinum) with a purity of 99.9% by weight or more.

[0032] A porous metal layer 41 containing metal particles with a particle size of 0.005 μm to 1.0 μm can be bonded at a temperature lower than the melting point of bulk metal due to the size effect of the particle size. For example, the porous metal layer 41 can bond the semiconductor substrate 2 and the chip 3 at temperatures of approximately 100°C if the component is Au, approximately 250°C if it is Ag, and approximately 150°C if it is Cu. As a result, the electronic device 1 can reduce heat-induced damage to the chip 3, thereby improving its reliability.

[0033] Furthermore, because the porous metal layer 41 is elastic, even if the chip 3 expands with a different coefficient of thermal expansion than the semiconductor substrate 2 due to the heat generated by the semiconductor laser, for example, it will undergo elastic deformation, thereby suppressing the occurrence of open faults. As a result, the reliability of the electronic device 1 can be improved compared to, for example, using solder bumps.

[0034] Such electronic device 1 is manufactured by stacking chips 3 on a semiconductor substrate 2 having bumps 4 on its upper surface, and by flip-chip mounting the chips 3 on the semiconductor substrate 2 by connecting them to connection pads 31 without melting the porous metal layer 41 of the bumps 4.

[0035] Alternatively, the electronic device 1 may be manufactured by stacking chips 3, each having a bump 4 containing a porous metal layer 41 on its lower surface, onto a semiconductor substrate 2, and then flip-chip mounting the chip 3 onto the semiconductor substrate 2 by connecting the porous metal layer 41 of the bump 4 to a connecting pad 21 without melting it. Note that the bumps 4 containing the porous metal layer 41 may be provided on both the semiconductor substrate 2 and the chip 3 before stacking.

[0036] When the bump 4 is provided on the semiconductor substrate 2 side, a metal film 42 is provided between the porous metal layer 41 and the connection pad 21 on the semiconductor substrate 2 side. When the bump 4 is provided on the chip 3 side, a metal film 42 is provided between the porous metal layer 41 and the connection pad 31 on the chip 3 side. The metal film 42 may be provided in at least one of the following locations: between the porous metal layer 41 and the connection pad 21 on the semiconductor substrate 2 side, or between the porous metal layer 41 and the connection pad 31 on the chip 3 side.

[0037] In this disclosure, by making the ratio of the thickness of the metal film 42 to the thickness in the direction perpendicular to the main surface of the semiconductor substrate 2 in the bump 4 less than 10%, it is possible to fine-pitch the bump 4 to a pitch of 20 μm or less. This fine-pitch process will be described later in conjunction with the bump 4 formation process.

[0038] Furthermore, the bump 4 also has a metal film 42 on the side surface (side circumferential surface) of the porous metal layer 41. It is desirable that the material of the metal film 42 be the same as that of the porous metal layer 41. For example, if the material of the porous metal layer 41 is Au, it is desirable that the metal film 42 be an Au film.

[0039] As a result, the sides of the porous metal layer 41 of the bump 4 are coated with the metal film 42, which prevents the particles of the porous metal layer 41 from crumbling and scattering. Therefore, the bump 4 can prevent adjacent bumps 4 from short-circuiting due to the scattering of particles of the porous metal layer 41.

[0040] Furthermore, if a metal film 42 is not provided on the side surface of the porous metal layer 41, surface roughness will occur on the relatively soft side surface of the porous metal layer 41, resulting in variations in shape between the bumps 4.

[0041] In contrast, since the bump 4 has a metal film 42 that is harder than the porous metal layer 41 on its side surface, variations in shape between the bumps 4 are suppressed, resulting in a uniform shape for all of them. Moreover, since the sides of the bump 4 are coated with a relatively hard metal film 42, further miniaturization becomes possible, enabling even finer pitches.

[0042] Furthermore, when the chip 3 is flip-chip mounted on the semiconductor substrate 2, the bump 4 is slightly compressed in the thickness direction, but it prevents the particles of the porous metal layer 41 from leaking out of the metal film 42. As a result, the bump 4 increases the particle density of the porous metal layer 41 inside the metal film 42, thereby reducing the connection resistance.

[0043] Furthermore, the side wall portion 5 of the electronic device 1 has a structure similar to that of the bump 4. Specifically, the side wall portion 5 includes a porous metal layer 51 of Au. The porous metal layer 51 contains Au particles with a particle size of 0.005 μm to 1.0 μm and a purity of 99.9% by weight or more. The components of the porous metal layer 51 may also be, for example, Cu, Ag (silver), or Pt (platinum) with a purity of 99.9% by weight or more.

[0044] As mentioned above, the porous metal layer 51 can be bonded at a temperature lower than the melting point of the bulk metal due to the size effect of the particle size. This allows the electronic device 1 to reduce damage to the chip 3 caused by heat during the formation of the porous metal layer 51, thereby improving reliability.

[0045] Furthermore, because the porous metal layer 51 is elastic, even if the chip 3 expands with a different coefficient of thermal expansion than the semiconductor substrate 2 due to the heat generated by the semiconductor laser, for example, it will undergo elastic deformation, thus suppressing the occurrence of cracks in the sidewall portion 5. As a result, the electronic device 1 can improve the airtightness of the areas where the connection pads 21, 31 and bumps 4 that require sealing are provided.

[0046] Furthermore, since the porous metal layer 51 is elastically deformable, even if there are variations in thickness or warping in the semiconductor substrate 2 or chip 3, for example, when joining the semiconductor substrate 2 and chip 3, the porous metal layer 51 deforms to follow the surface shape of the semiconductor substrate 2 or chip 3.

[0047] As a result, the electronic device 1 can suppress the formation of gaps at the connection between the side wall 5 and the semiconductor substrate 2, and at the connection between the side wall 5 and the chip 3, thereby improving airtightness.

[0048] Furthermore, as shown in Figure 2, the side wall portion 5 is provided in an annular shape to surround the area where the connection pads 21, 31 and bumps 4 that require sealing are provided. This allows the electronic device 1 to alleviate the mechanical stress on the bumps 4 provided at the corners when the semiconductor substrate 2 or chip 3 undergoes thermal expansion.

[0049] Specifically, when the semiconductor substrate 2 or chip 3 undergoes thermal expansion, the amount of expansion and contraction due to temperature changes increases from the center of the main surface of the semiconductor substrate 2 or chip 3 towards the periphery. Therefore, if the side wall portion 5 is absent, mechanical stress will be applied to the bumps 4 provided at the corners.

[0050] In contrast, in the electronic device 1, the peripheral edges of the semiconductor substrate 2 and chip 3 are sealed by the side wall portion 5, so that expansion and contraction at the peripheral edges of the semiconductor substrate 2 and chip 3 due to temperature changes can be suppressed by the side wall portion 5. As a result, the electronic device 1 can alleviate the mechanical stress on the bumps 4 provided at the corners.

[0051] When the side wall portion 5 is provided on the semiconductor substrate 2 side, a metal film 52 is provided between the porous metal layer 51 and the connection pad 21 on the main surface of the semiconductor substrate 2. When the side wall portion 5 is provided on the chip 3 side, a metal film 52 is provided between the porous metal layer 51 and the connection pad on the main surface of the chip 3. The metal film 52 may be provided in at least one of the following locations: between the porous metal layer 51 and the connection pad 21 on the main surface of the semiconductor substrate 2, and between the porous metal layer 51 and the connection pad on the main surface of the chip 3.

[0052] In this disclosure, by making the ratio of the thickness of the metal film 52 to the thickness in the direction perpendicular to the main surface of the semiconductor substrate 2 in the side wall portion 5 less than 10%, it is possible to fine-pitch the bump 4 to a pitch of 20 μm or less in the process of simultaneously forming the side wall portion 5 and the bump 4.

[0053] Furthermore, the side wall portion 5 also includes a metal film 52 on the side surface (side circumferential surface) of the porous metal layer 51. It is desirable that the material of the metal film 52 be the same as that of the porous metal layer 51. For example, if the material of the porous metal layer 51 is Au, it is desirable that the metal film 52 be an Au film.

[0054] As a result, the side surface of the porous metal layer 51 of the side wall portion 5 is coated with the metal film 52, which prevents the particles of the porous metal layer 51 from crumbling and scattering. Therefore, the side wall portion 5 can prevent adjacent bumps 4 from short-circuiting due to the scattering of particles of the porous metal layer 51.

[0055] Furthermore, if a metal film 52 is not provided on the side surface of the porous metal layer 51, surface roughness will occur on the relatively soft side surface of the porous metal layer 51, resulting in variations in the side shape of the side wall portion 5.

[0056] In contrast, the sidewall portion 5 has a metal film 52 that is harder than the porous metal layer 51 on its side surface, which suppresses variations in the side shape and results in a uniform surface shape across the entire side. Moreover, since the sidewall portion 5 is coated with a relatively hard metal film 52, further miniaturization becomes possible.

[0057] Such electronic device 1 is manufactured by stacking chips 3, which do not have bumps 4a (see Figure 10), on a semiconductor substrate 2 having bumps 4 on its upper surface, and then flip-chip mounting the chips 3 onto the semiconductor substrate 2 by connecting them to connection pads 31 without melting the porous metal layer 41 of the bumps 4.

[0058] Alternatively, the electronic device 1 may be manufactured by stacking a chip 3, which has a bump 4a (see Figure 10) containing a porous metal layer 41 on its lower surface, onto a semiconductor substrate 2 that does not have a bump 4, and then flip-chip mounting the chip 3 onto the semiconductor substrate 2 by connecting the porous metal layer 41 of the bump 4a to a connecting pad 21 without melting it. Note that the bumps 4 and 4a containing the porous metal layer 41 may be provided on both the semiconductor substrate 2 and the chip 3 before stacking.

[0059] [2. Process for forming bumps and side walls] Next, the process for forming bumps and sidewalls according to this disclosure will be described with reference to Figures 3 to 10. Figures 3 to 6 are explanatory diagrams showing the process for forming bumps and sidewalls on a semiconductor substrate according to this disclosure. Figures 7 to 10 are explanatory diagrams showing the process for forming bumps and sidewalls on a chip according to this disclosure.

[0060] As shown in Figure 3, when forming bumps 4 and sidewalls 5 on the semiconductor substrate 2, first, a metal film 22 is formed on the upper surface of a connecting pad 21 located on the semiconductor substrate 2 where the bumps 4 will be formed later. At the same time, a metal film 32 is also formed on the upper surface of a connecting pad 21 located where the sidewalls 5 will be formed later, that is, on the upper surface of a connecting pad 21 located in a ring-shaped area on the main surface of the semiconductor substrate 2 where the bumps 4 will be formed later. As the material for the metal film 22, a metal with the same composition as the metal film 64 (see Figure 4) that will be laminated later is selected. In this case, a gold metal film 22 is formed.

[0061] Subsequently, a photoresist layer 61 is formed on the surface of the semiconductor substrate 2 on the side where the connection pads 21 and the metal film 22 are provided. Then, using photolithography technology, through holes 62 are formed in the photoresist layer 61 at the locations where the bumps 4 will be formed, exposing the surface of the metal film 22. At the same time, grooves 63 are formed at the locations where the side walls 5 will be formed, exposing the surface of the metal film 22.

[0062] At this time, the through-holes 62 are formed such that the distance between the centers of adjacent through-holes 62 is 20 μm (20 μm pitch). These through-holes 62 will be filled with paste 50 containing metal particles that will become the material for the porous metal layer 41 in a later process. However, because of the fine structure with a 20 μm pitch, if the paste 50 is filled in this state, the fine structure may be damaged and collapse.

[0063] Therefore, as shown in Figure 4, a metal film 64 is formed on the upper surface of the photoresist layer 61, the side surface of the through-hole 62, the side surface of the groove 63, and the upper surface of the metal film 22, for example, by sputtering. As the material for the metal film 64, a metal with the same component as the metal particles contained in the paste 50 that will later fill the through-hole 62 is selected. In this case, an Au metal film 64 is formed.

[0064] As a result, the photoresist layer 61 hardens when its surface is coated with a metal film 64, which prevents the fine structure from collapsing when the paste 50 containing metal particles is filled into the through-holes 62.

[0065] Furthermore, if the thickness of the metal film 64 formed here is too thick, the opening of the through hole 62 will become narrow, making it difficult to fill the through hole 62 with paste 50 containing metal particles. Therefore, a thin metal film 64 (for example, less than 1 μm thick) is formed here, such that the ratio of the thickness d1 of the metal film 64 to the depth D1 of the through hole 62, or in other words, the thickness in the direction perpendicular to the main surface of the semiconductor substrate 2 in the bump 4 that is formed later (height D1 of the bump 4), is less than 10%.

[0066] For example, when forming bumps 4 with a height of 10 μm arranged at a pitch of 20 μm, the thickness of the metal film 64 is set to 0.2 μm. This prevents the opening of the through-holes 62 from narrowing even when the metal film 64 is formed, so that the paste 50 containing metal particles can be sufficiently filled into the through-holes 62 in a later step.

[0067] As a result, the ratio of the thickness d1 of the metal film 64 to the depth D2 of the groove 63, or in other words, the thickness in the direction perpendicular to the main surface of the semiconductor substrate 2 in the side wall portion 5 that is formed later (height D2 of the side wall portion 5), becomes less than 10%.

[0068] Next, as shown in Figure 5, the through-holes 62 and grooves 63 formed in the photoresist layer 61 are filled with a paste 50 containing, for example, Au particles with a purity of 99.9% by weight or more and a particle size of 0.005 μm to 1.0 μm. Any method can be used to fill the through-holes 62 and grooves 63 with the paste 50, such as screen printing or spreading the dropped paste 50 with a spatula.

[0069] Subsequently, after drying and sintering the paste 50, the photoresist layer 61 is peeled off by lift-off using a stripping solution or the like. As a result, as shown in Figure 6, a bump 4 is completed on the surface of the connecting pad 21, with an Au metal film 22, an Au metal film 42, and a porous metal layer 41 containing Au particles with a particle size of 0.005 μm to 1.0 μm sequentially laminated, and an Au metal film 42 also formed on the sides of the porous metal layer 41.

[0070] Simultaneously, a metal film 22 made of Au, a metal film 52 made of Au, and a porous metal layer 51 containing Au particles with a particle size of 0.005 μm to 1.0 μm are sequentially laminated around the region where the bump 4 is formed, completing a side wall portion 5 in which a metal film 52 made of Au is also formed on the side surface of the porous metal layer 51.

[0071] Thus, the bump 4 has a metal film 42 between the metal film 22 on the connecting pad 21 and the porous metal layer 41, with a film thickness ratio of less than 10% to the height D1 of the bump 4. Furthermore, the bump 4 also has a metal film 42 on the sides of the porous metal layer 41.

[0072] Furthermore, the side wall portion 5 is provided with a metal film 52 between the metal film 22 on the connecting pad 21 and the porous metal layer 51, with a film thickness ratio of less than 10% to the height D2 of the side wall portion 5. In addition, the side wall portion 5 is also provided with a metal film 52 on the side surface of the porous metal layer 51.

[0073] These metal films 42 and 52 are formed on the upper surface of the photoresist layer 61, on the sides of the through holes 62 and grooves 63 formed in the photoresist layer 61, and on the surface of the metal film 22, in order to prevent the collapse of the fine structure of the bumps 4 and sidewalls 5 that are patterned on the photoresist layer 61. As a result, it is possible to make the bumps 4 finer, with a pitch of 20 μm or less.

[0074] Furthermore, since the metal film 22 is formed on the surface of the connecting pad 21 by sputtering, even if the connecting pad 21 is made of a metal with a different composition than the metal film 22, it will be firmly bonded to the connecting pad 21.

[0075] Furthermore, the metal films 42 and 52 may be formed from metals with different components than those of the porous metal layers 41 and 51. However, if they are formed from Au of the same component, the porous metal layers 41 and 51 will be bonded to the metal films 42 and 52 with stronger bonding force than when they are provided on other metal films with different components. Note that if the porous metal layers 41 and 51 are made from a component other than Au (for example, Cu, Ag (silver), or Pt (platinum)), the metal films 42 and 52 may also be made from the same metal as the porous metal layers 41 and 51 (for example, Cu, Ag (silver), or Pt (platinum)).

[0076] Next, the process of forming the bumps 4a and sidewalls 5a shown in Figure 10 on the chip 3 will be described. As shown in Figure 7, when forming the bumps 4a and sidewalls 5 on the chip 3, first, a metal film 32 is formed on the upper surface of the connection pad 31 located on the chip 3 where the bumps 4a will be formed later. At the same time, a metal film 32 is also formed on the upper surface of the connection pad 31 located where the sidewalls 5a will be formed later, that is, the upper surface of the connection pad 31 located in a ring-shaped area on the main surface of the chip 3 where the bumps 4a will be formed later. As the material for the metal film 32, a metal with the same composition as the metal film 74 (see Figure 8) that will be laminated later is selected. In this case, an Au metal film 32 is formed. Note that the connection pad 31 located where the sidewalls 5a will be formed later is not connected to the circuit inside the chip 3.

[0077] Subsequently, a photoresist layer 71 is formed on the surface of the chip 3 on the side where the connection pad 31 and the metal film 32 are provided. Then, using photolithography technology, through holes 72 are formed in the photoresist layer 71 at the locations where the bumps 4a will be formed, exposing the surface of the metal film 32. At the same time, grooves 73 are formed at the locations where the side wall portions 5a will be formed, exposing the surface of the metal film 32.

[0078] Subsequently, as shown in Figure 8, a metal film 74 is formed on the upper surface of the photoresist layer 71, the side surfaces of the through holes 72, the side surfaces of the grooves 73, and the upper surface of the metal film 32, for example, by sputtering. As the material for the metal film 74, Au with the same component as the Au particles contained in the paste 50 that will later fill the through holes 72 is selected.

[0079] As a result, the photoresist layer 71 hardens when its surface is coated with the metal film 43, which prevents the fine structure from collapsing when the paste 50 containing Au particles is filled into the through-holes 72.

[0080] Here as well, a thin metal film 74 (for example, less than 1 μm thick) is formed such that the ratio of the thickness d1 of the metal film 74 to the depth D1 of the through hole 72, or in other words, the thickness in the direction perpendicular to the main surface of the chip 3 in the bump 4a that is later formed (height D1 of the bump 4a), is less than 10%.

[0081] For example, when forming bumps 4 with a height of 10 μm arranged at a pitch of 20 μm, the thickness of the metal film 74 is set to 0.2 μm. This prevents the opening of the through-holes 72 from narrowing even when the metal film 74 is formed, so that the paste 50 containing metal particles can be sufficiently filled into the through-holes 72 in a later step.

[0082] As a result, the ratio of the thickness d1 of the metal film 74 to the depth D2 of the groove 73, or in other words, the thickness in the direction perpendicular to the main surface of the chip 3 in the side wall portion 5a that is formed later (height D2 of the side wall portion 5a), becomes less than 10%.

[0083] Next, as shown in Figure 9, the through holes 72 and grooves 73 formed in the photoresist layer 71 are filled with a paste 50 containing, for example, Au particles with a purity of 99.9% by weight or more and a particle size of 0.005 μm to 1.0 μm.

[0084] Afterward, the paste 50 is dried and sintered, and then the photoresist layer 71 is peeled off by lift-off using a stripping solution or the like. As a result, as shown in Figure 10, a bump 4a is completed on the surface of the connecting pad 31, with an Au metal film 32, an Au metal film 42, and a porous metal layer 41 containing Au particles with a particle size of 0.005 μm to 1.0 μm sequentially laminated, and an Au metal film 42 also formed on the side surface of the porous metal layer 41.

[0085] Simultaneously, a metal film 32 of Au, a metal film 52 of Au, and a porous metal layer 51 containing Au particles with a particle size of 0.005 μm to 1.0 μm are sequentially laminated around the region where the bump 4a is formed, completing a side wall portion 5a in which a metal film 52 of Au is also formed on the side surface of the porous metal layer 51.

[0086] Thus, the bump 4a has a metal film 42 between the metal film 22 on the connecting pad 31 and the porous metal layer 41, with a film thickness ratio of less than 10% to the height D1 of the bump 4a. Furthermore, the bump 4a also has a metal film 42 on the side surface of the porous metal layer 41.

[0087] Furthermore, the side wall portion 5a is provided with a metal film 52 between the metal film 32 on the connecting pad 31 and the porous metal layer 51, with a ratio of film thickness to height D2 of the side wall portion 5a of less than 10%. In addition, the side wall portion 5a is also provided with a metal film 52 on the side surface of the porous metal layer 51.

[0088] These metal films 42 and 52 are formed on the upper surface of the photoresist layer 71, on the sides of the through holes 72 and grooves 73 formed in the photoresist layer 71, and on the surface of the metal film 22, in order to prevent the collapse of the fine structure of the bumps 4a and sidewalls 5a that are patterned on the photoresist layer 71. As a result, the bumps 4a can be made into a fine pitch of 20 μm or less, similar to the bumps 4 on the semiconductor substrate 2 side.

[0089] In the embodiments described above, we explained the case in which a chip 3 without bumps 4a and sidewalls 5a is mounted on a semiconductor substrate 2 provided with bumps 4 and sidewalls 5, and the case in which a chip 3 provided with bumps 4a and sidewalls 5a is mounted on a semiconductor substrate 2 without bumps 4 and sidewalls 5. However, this is just one example.

[0090] The electronic device according to this disclosure may have a configuration in which a chip 3 having bumps 4a and sidewalls 5a is mounted on a semiconductor substrate 2 having bumps 4 and sidewalls 5. In such a configuration, the ratio of the thickness of the metal films 42, 52 to half the thickness in the direction perpendicular to the main surface of the semiconductor substrate 2 and the chip 3 in the bumps 4, 4a and sidewalls 5, 5a is less than 10%, preferably less than 5%.

[0091] Furthermore, although the above-described embodiment described a case where the substrate of the chip 3 is a substrate other than Si, the substrate of the chip 3 may be Si doped with impurities, as long as its coefficient of thermal expansion is different from that of the semiconductor substrate 2.

[0092] The chip 3, which includes the semiconductor laser light-emitting section described above, and the semiconductor substrate 2, which includes the semiconductor laser drive circuit, are mounted on, for example, distance measuring devices such as ToF sensors and structured lights. When mounted on a distance measuring device, the semiconductor laser light-emitting section functions, for example, as a light source for a ToF sensor or a structured light.

[0093] [3. Effects] The electronic device 1 comprises a semiconductor substrate 2, a chip 3, bumps 4, and a side wall portion 5. The bumps 4 connect multiple connection pads 21 and 31 provided on the opposing main surfaces of the semiconductor substrate 2 and the chip 3. The side wall portion 5 includes a porous metal layer 51 that surrounds the area where the multiple bumps 4 are provided in an annular shape, and connects the semiconductor substrate 2 and the chip 3. This allows the electronic device 1 to have improved airtightness.

[0094] The thermal expansion coefficient of the chip 3 differs from that of the semiconductor substrate 2 by 0.1 ppm / °C or more. As a result, even if the chip 3 generates heat and expands with a different thermal expansion coefficient than the semiconductor substrate 2, the porous metal layer 51 of the sidewall portion 5 undergoes elastic deformation, thus suppressing the occurrence of cracks or gaps in the sidewall portion 5. Furthermore, even if there are variations in thickness or warping in the chip 3 or the semiconductor substrate 2, the sidewall portion 5 elastically deforms to follow the shape of the chip 3 or the semiconductor substrate 2, thereby improving airtightness.

[0095] Chip 3 is a semiconductor laser. The semiconductor substrate 2 has a drive circuit that drives the semiconductor laser. As a result, even if the chip 3 expands at a different thermal expansion coefficient than the semiconductor substrate 2 due to the heat generated by the emission of light from the semiconductor laser, the porous metal layer 51 of the side wall 5 undergoes elastic deformation, thereby improving the airtightness of the electronic device 1.

[0096] The porous metal layer 51 contains metal particles with a particle size of 0.005 μm to 1.0 μm. Due to the size effect of the metal particles, this porous metal layer 51 can be bonded at a temperature lower than the melting point of the bulk metal. As a result, in the peripheral areas of the region where the connection pads 21, 31 and bumps 4 are provided, the semiconductor substrate 2 and the chip 3 are connected by the porous metal layer 51, which allows for metal bonding at a relatively low temperature. This reduces thermal damage and improves airtightness.

[0097] The side wall portion 5 has a metal film 52 provided on at least one of the following: between the porous metal layer 51 and the connection pad 21 provided on the semiconductor substrate 2, and between the porous metal layer 51 and the connection pad 31 provided on the chip 3, as well as on the side surface of the porous metal layer 51. As a result, the electronic device 1 can improve airtightness by preventing the porous metal layer 51 from collapsing with the metal film 52 provided on the side surface of the porous metal layer 51.

[0098] The metal film 52 provided between the porous metal layer 51 and the connecting pad 21 provided on the semiconductor substrate 2, and between the porous metal layer 51 and the connecting pad 31 provided on the chip 3, has a film thickness ratio of less than 10% to the thickness in the direction perpendicular to the main surface of the sidewall portions 5, 5a. This prevents the grooves 63, 73 for forming the sidewall portions 5, 5a, which are patterned in the photoresist layers 61, 71, from being narrowed by the formation of the metal film 52. As a result, the grooves 63, 73 patterned in the photoresist layers 61, 71 can be properly filled with paste 50 containing metal particles that will form the sidewall portions 5, 5a.

[0099] The metal film 52 provided between the porous metal layer 51 and the connecting pad 21 provided on the semiconductor substrate 2, and between the porous metal layer 51 and the connecting pad 31 provided on the chip 3, has a film thickness ratio of less than 10% to half the thickness in the direction perpendicular to the main surface of the sidewall portions 5, 5a. This prevents the grooves 63, 73 for forming the sidewall portions 5, 5a, which are patterned in the photoresist layers 71, 71, from being narrowed by the formation of the metal film 52 in the case of electronic equipment in which the semiconductor substrate 2 and the chip 3 are connected by the sidewall portions 5, 5a. As a result, the grooves 63, 73 patterned in the photoresist layers 61, 71 can be properly filled with paste 50 containing metal particles that will form the sidewall portions 5, 5a.

[0100] The bumps 4 and 4a have a porous metal layer 41 and a metal film 42. The porous metal layer 41 is formed from the same material as the porous metal layer 51 of the sidewalls 5 and 5a. The metal film 42 is provided between the porous metal layer 41 and the connecting pad 21 provided on the semiconductor substrate 2, and between the porous metal layer 41 and the connecting pad 31 provided on the chip 3, at least one of these, and on the side surface of the porous metal layer 41. As a result, the bumps 4 and 4a and the sidewalls 5 and 5a can be formed simultaneously, so the semiconductor substrate 2 and the chip 3 can be joined and sealed by forming the sidewalls 5 and 5a without adding any new steps for bonding and sealing.

[0101] The metal film 42 provided between the porous metal layer 41 and the connecting pads 21 and 31 has a film thickness ratio of less than 10% to the thickness in the direction perpendicular to the main surface of the semiconductor substrate 2 in the bumps 4 and 4a. This prevents the through holes 62 and 72 for forming the bumps 4 and 4a, which are patterned in the photoresist layers 61 and 71, from being narrowed by the formation of the metal film 42. As a result, the paste 50 containing metal particles that will form the bumps 4 and 4a can be properly filled into the through holes 62 and 72 patterned in the photoresist layers 61 and 71.

[0102] The metal film 42 provided between the porous metal layer 41 and the connecting pads 21 and 31 has a film thickness ratio of less than 10% to half the thickness of the bumps 4 and 4a in the direction perpendicular to the main surface of the semiconductor substrate 2. This prevents the through holes 62 and 72 for forming the bumps 4 and 4a, which are patterned in the photoresist layers 61 and 71, from being narrowed by the formation of the metal film 42 in the case of electronic devices in which the semiconductor substrate 2 and chip 3 are connected by bumps 4 and 4a. As a result, the paste 50 containing metal particles that will form the bumps 4 and 4a can be properly filled into the through holes 62 and 72 patterned in the photoresist layers 61 and 71.

[0103] The porous metal layers 41, 51 and the metal films 42, 43 are made of the same type of metal. This increases the bonding strength between the porous metal layers 41, 51 and the metal films 42, 43.

[0104] The porous metal layers 41 and 51 are made of porous metal containing gold, silver, platinum, or copper with a purity of 99.9% by weight or higher. This makes it possible to keep the connection resistance between the connection pad 21 of the semiconductor substrate 2 and the connection pad 31 of the chip 3 low.

[0105] Furthermore, the effects described herein are merely illustrative and not limiting, and other effects may also occur.

[0106] Furthermore, this technology can also be configured as follows. (1) Semiconductor substrate and Tips and, Bumps that connect a plurality of connection pads provided on the opposing main surfaces of the semiconductor substrate and the chip, The region in which the multiple bumps are provided is surrounded in an annular shape by a porous metal layer, and the side wall portion connects the semiconductor substrate and the chip. A powerful electronic device. (2) The aforementioned chip is The coefficient of thermal expansion differs from that of the semiconductor substrate by 0.1 ppm / °C or more. The electronic device described in (1) above. (3) The aforementioned chip is It is a semiconductor laser, The aforementioned semiconductor substrate is The semiconductor laser has a drive circuit for driving the aforementioned semiconductor laser. The electronic device described in (1) or (2) above. (4) The porous metal layer is Contains metal particles with a particle size of 0.005 μm to 1.0 μm. The electronic device described in any of (1) to (3) above. (5) The aforementioned side wall portion is A metal film is provided between the porous metal layer and the connecting pad provided on the semiconductor substrate, and between the porous metal layer and the connecting pad provided on the chip, at least one of these, and on the side surface of the porous metal layer. An electronic device according to any one of (1) to (4) above, having the following: (6) The metal film provided between the porous metal layer and the connecting pad provided on the semiconductor substrate, and between the porous metal layer and the connecting pad provided on the chip, has a film thickness ratio of less than 10% to the thickness of the side wall portion in the direction perpendicular to the main surface. The electronic equipment described in (5) above. (7) The metal film provided between the porous metal layer and the connecting pad provided on the semiconductor substrate, and between the porous metal layer and the connecting pad provided on the chip, has a film thickness ratio of less than 10% to half the thickness of the side wall portion in the direction perpendicular to the main surface. The electronic equipment described in (5) above. (8) The aforementioned bump is, A porous metal layer formed from the same material as the porous metal layer of the side wall portion, A metal film is provided between the porous metal layer and the connecting pad provided on the semiconductor substrate, and between the porous metal layer and the connecting pad provided on the chip, at least one of these, and on the side surface of the porous metal layer. An electronic device according to any one of (1) to (7) above, having the above. (9) The metal film provided between the porous metal layer and the connecting pad has a film thickness ratio of less than 10% to the thickness in the direction perpendicular to the main surface of the bump. The electronic equipment described in (8) above. (10) The metal film provided between the porous metal layer and the connecting pad has a film thickness ratio of less than 10% to half the thickness in the direction perpendicular to the main surface of the bump. The electronic equipment described in (8) above. (11) The materials of the porous metal layer and the metal film are They are the same type of metal. The electronic device described in any of (5) to (10) above. (12) The material of the porous metal layer is A porous metal containing gold, silver, platinum, or copper with a purity of 99.9% by weight or higher. The electronic device described in any of (1) to (11) above. [Explanation of Symbols]

[0107] 1 Electronic equipment 2 Semiconductor substrates 3 chips 4,4a Bump 5,5a Side wall part 50 Paste 21,31 Connection pads 41,51 Porous metal layer 22, 32, 42, 52, 64, 74 Metal film 61,71 Photoresist layer 62,72 Through holes 63,73 groove

Claims

1. Semiconductor substrate and Tips and, Bumps that connect a plurality of connection pads provided on the opposing main surfaces of the semiconductor substrate and the chip, The region in which the multiple bumps are provided is surrounded in an annular shape by a porous metal layer, and the side wall portion connects the semiconductor substrate and the chip. It has, The side wall portion has a metal film that is harder than the porous metal layer. The metal film covers the inner surface of the side wall portion facing the region where the plurality of bumps are provided, and the outer surface of the side wall portion located on the opposite side of the porous metal layer from the inner surface, in an electronic device.

2. The aforementioned chip is The coefficient of thermal expansion differs from that of the semiconductor substrate by 0.1 ppm / °C or more. The electronic device according to claim 1.

3. The aforementioned chip is It is a semiconductor laser, The aforementioned semiconductor substrate is The semiconductor laser has a drive circuit for driving the aforementioned semiconductor laser. The electronic device according to claim 1.

4. The porous metal layer is Contains metal particles with a particle size of 0.005 μm to 1.0 μm. The electronic device according to claim 1.

5. The aforementioned side wall portion is A metal film is provided between the porous metal layer and the connecting pad provided on the semiconductor substrate, and between the porous metal layer and the connecting pad provided on the chip, at least one of these, and on the side surface of the porous metal layer. The electronic device according to claim 1, having the following features.

6. The metal film provided between the porous metal layer and the connecting pad provided on the semiconductor substrate, and between the porous metal layer and the connecting pad provided on the chip, has a film thickness ratio of less than 10% to the thickness of the side wall portion in the direction perpendicular to the main surface. The electronic device according to claim 5.

7. The metal film provided between the porous metal layer and the connecting pad provided on the semiconductor substrate, and between the porous metal layer and the connecting pad provided on the chip, has a film thickness ratio of less than 10% to half the thickness of the side wall portion in the direction perpendicular to the main surface. The electronic device according to claim 5.

8. The aforementioned bump is, A porous metal layer formed from the same material as the porous metal layer of the side wall portion, A metal film is provided between the porous metal layer and the connecting pad provided on the semiconductor substrate, and between the porous metal layer and the connecting pad provided on the chip, at least one of these, and on the side surface of the porous metal layer. The electronic device according to claim 1, having the following features.

9. The metal film provided between the porous metal layer and the connecting pad has a film thickness ratio of less than 10% to the thickness in the direction perpendicular to the main surface of the bump. The electronic device according to claim 8.

10. The metal film provided between the porous metal layer and the connecting pad has a film thickness ratio of less than 10% to half the thickness in the direction perpendicular to the main surface of the bump. The electronic device according to claim 8.

11. The materials of the porous metal layer and the metal film are They are the same type of metal. The electronic device according to claim 5.

12. The material of the porous metal layer is A porous metal containing gold, silver, platinum, or copper with a purity of 99.9% by weight or higher. The electronic device according to claim 1.

Images