Voltage-mode bit-line precharging for random-access memory cells

Abstract

To disclose circuits and methods for voltage-mode bit line precharge for random-access memory cells.SOLUTION: A circuit includes an array of random access memory cells; a low-impedance voltage source configured to provide a precharge voltage; and a control circuit configured to precharge a bit line of one of the random access memory cells to the precharge voltage using the low-impedance voltage source prior to reading the one of the random access memory cells.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] Cross-reference of related applications This application claims priority to U.S. Patent Application No. 16 / 670,633, entitled “VOLTAGE-MODE BIT LINE PRECHARGE FOR RANDOM-ACCESS MEMORY CELLS,” filed on 31 October 2019, and to U.S. Provisional Patent Application No. 62 / 899,211, entitled “VOLTAGE-MODE PRE-CHARGE SCHEME FOR RRAM SENSE-AMP,” filed on 12 September 2019. U.S. Patent Application No. 16 / 670,633 claims priority and benefit of U.S. Provisional Patent Application No. 62 / 899,211. The applications referenced above are incorporated herein by reference in their entirety.

[0002] This disclosure generally relates to memory cells, and more specifically to precharging random-access memory cells.

[0003] Generally, one aspect of the disclosed memory circuit comprises an array of random access memory cells, a low-impedance voltage source configured to supply a precharge voltage, and a control circuit configured to precharge one bit line of a random access memory cell to the precharge voltage using the low-impedance voltage source before reading one of the random access memory cells.

[0004] Embodiments of the method may include one or more of the following features. Some embodiments include an on / off switch positioned between a low-impedance voltage source and one bit line of a random-access memory cell, and a control circuit is configured to electrically couple the low-impedance voltage source to the bit line until the bit line reaches a precharge voltage, and to electrically disconnect the low-impedance voltage source from the bit line before reading one of the random-access memory cells. In some embodiments, the low-impedance voltage source is a high-gain feedback-loop low-impedance voltage source. In some embodiments, the low-impedance voltage source includes a unit-gain amplifier. In some embodiments, the random-access memory cell is a resistive random-access memory cell. In some embodiments, the magnitude of the precharge voltage is selected such that the read time of the memory cell when off is approximately equal to the read time of the memory cell when on. In some embodiments, each of the resistive random-access memory cells includes a three-terminal access element and a resistive random-access memory element coupled between the three-terminal access element and one of a plurality of bit lines. In some embodiments, the first terminal of a three-terminal access element is coupled to one of a plurality of word lines, the second terminal of the three-terminal access element is coupled to one of a plurality of source lines, and a resistive random-access memory element is coupled between the third terminal of the three-terminal access element and one of a plurality of bit lines. Some embodiments include a sense amplifier configured to read random-access memory cells.

[0005] Generally, one embodiment disclosed features a method for reading a random access memory cell, the method comprising supplying a precharge voltage from a low-impedance voltage source to the bit line of the random access memory cell, and reading the memory cell after the voltage on the bit line has reached the precharge voltage. Some embodiments include stopping the supply of the precharge voltage from the low-impedance voltage source to the bit line of the random access memory cell before reading the memory cell. Some embodiments include electrically coupling the low-impedance voltage source to the bit line until the bit line reaches the precharge voltage, and electrically disconnecting the low-impedance voltage source from the bit line before reading the random access memory cell. In some embodiments, the voltage source comprises a low-impedance voltage source. In some embodiments, the low-impedance voltage source comprises a unit-gain amplifier. In some embodiments, the random access memory cell is a resistive random access memory cell. In some embodiments, the magnitude of the precharge voltage is selected such that the read time of the memory cell when it is off is approximately equal to the read time of the memory cell when it is on. In some embodiments, a resistive random-access memory cell comprises a three-terminal access element and a resistive random-access memory element coupled between the three-terminal access element and a bit line. In some embodiments, the first terminal of the three-terminal access element is coupled to a word line, the second terminal of the three-terminal access element is coupled to a source line, and the resistive random-access memory element is coupled between the third terminal of the three-terminal access element and a bit line. [Background technology]

[0006] Precharging random-access memory (RAM) cells is a common technique to reduce the time required to read the state of a RAM cell. This technique involves applying a large current to the RAM cell to quickly raise its voltage to a desired value before reading its state. Without precharging, RAM cells are charged relatively slowly by a small reference current. [Overview of the Initiative]

[0007] A circuit and method for voltage-mode bit-line precharging of random-access memory cells are disclosed.

[0008] Generally, one aspect of the disclosed memory circuit comprises an array of random access memory cells, a low-impedance voltage source configured to supply a precharge voltage, and a control circuit configured to precharge one bit line of a random access memory cell to the precharge voltage using the low-impedance voltage source before reading one of the random access memory cells.

[0009] Embodiments of the memory circuit may include one or more of the following features. Some embodiments include an on / off switch positioned between a low-impedance voltage source and one bit line of a random-access memory cell, and the control circuit is configured to electrically couple the low-impedance voltage source to the bit line until the bit line reaches a precharge voltage, and to electrically disconnect the low-impedance voltage source from the bit line before reading one of the random-access memory cells. In some embodiments, the low-impedance voltage source is a high-gain low-impedance voltage source. In some embodiments, the low-impedance voltage source comprises a unit-gain amplifier. In some embodiments, the random-access memory cell is a resistive random-access memory cell. In some embodiments, the magnitude of the precharge voltage is selected such that the read time of the memory cell when it is off is approximately equal to the read time of the memory cell when it is on. In some embodiments, each of the resistive random-access memory cells comprises a three-terminal access element and a resistive random-access memory element coupled between the three-terminal access element and one of a plurality of bit lines. In some embodiments, the first terminal of a three-terminal access element is coupled to one of a plurality of word lines, the second terminal of the three-terminal access element is coupled to one of a plurality of source lines, and a resistive random-access memory element is coupled between the third terminal of the three-terminal access element and one of a plurality of bit lines. Some embodiments include a sense amplifier configured to read random-access memory cells.

[0010] Generally, one aspect of the disclosed invention features a method for reading a random-access memory cell, the method comprising supplying a precharge voltage from a low-impedance voltage source to the bit lines of the random-access memory cell, and reading the memory cell after the voltage on the bit lines has reached the precharge voltage.

[0011] Embodiments of the method may include one or more of the following features. Some embodiments include stopping the supply of a precharge voltage from a low-impedance voltage source to the bit line of a random-access memory cell before reading the memory cell. Some embodiments include electrically coupling the low-impedance voltage source to the bit line until the bit line reaches the precharge voltage, and electrically disconnecting the low-impedance voltage source from the bit line before reading the random-access memory cell. In some embodiments, the voltage source comprises a low-impedance voltage source. In some embodiments, the low-impedance voltage source comprises a unit-gain amplifier. In some embodiments, the random-access memory cell is a resistive random-access memory cell. In some embodiments, the magnitude of the precharge voltage is selected such that the read time of the memory cell when it is off is approximately equal to the read time of the memory cell when it is on. In some embodiments, the resistive random-access memory cell comprises a three-terminal access element and a resistive random-access memory element coupled between the three-terminal access element and the bit line. In some embodiments, the first terminal of a three-terminal access element is coupled to a word line, the second terminal of the three-terminal access element is coupled to a source line, and a resistive random-access memory element is coupled between the third terminal of the three-terminal access element and a bit line. [Brief explanation of the drawing]

[0012] [Figure 1] This figure shows a conventional memory circuit without precharging. [Figure 2] This figure shows a conventional memory circuit with current-mode memory cell precharging. [Figure 3] This figure shows the read operation for the memory circuit shown in Figure 2. [Figure 4] This figure shows a memory circuit according to several embodiments of the technology disclosed herein. [Figure 5]A diagram showing a read operation according to some embodiments of the technology of the present disclosure. [Figure 6] A diagram showing a read operation for the memory circuit of FIG. 4 according to some embodiments of the technology of the present disclosure. [Figure 7A] A diagram showing a read operation for a RRAM cell having a resistive change memory element in an off state using a precharge voltage of VPRE = 200 mV. [Figure 7B] A diagram showing a read operation for a RRAM cell having a resistive change memory element in an on state using a precharge voltage of VPRE = 200 mV. [Figure 7C] A diagram showing a read operation for a RRAM cell having a resistive change memory element in an on state using a precharge voltage of VPRE = 80 mV. [Figure 7D] A diagram showing a read operation for a RRAM cell having a resistive change memory element in an off state using a precharge voltage of VPRE = 80 mV.

Embodiments for Carrying Out the Invention

[0013] Embodiments of the described technology result in voltage-mode bit-line precharge for random access memory cells. The described technology provides several significant advantages compared to conventional precharging techniques, as described in detail below.

[0014] FIG. 1 shows a conventional memory circuit 100 without precharging. Referring to FIG. 1, the memory circuit 100 includes a RAM cell 102. The memory circuit 100 may include an array of RAM cells. However, for simplicity of explanation, only one RAM cell 102 is shown in FIG. 1. In the described embodiments, the RAM cell 102 is a resistive random access memory (RRAM) cell. However, the technology of the present disclosure can be applied to any RAM cell.

[0015] The RRAM cell 102 includes a resistive change memory element R and a transistor T3. The transistor T3 acts as an access element for the resistive change memory element R. The drain terminal of the transistor T3 is coupled to a source line, and the source line is coupled to an on / off switch M2. The gate of the transistor T3 is coupled to a word line, and the word line is coupled to an on / off switch M1. The source terminal of the transistor T3 is coupled to one terminal of the resistive change memory element R. The other terminal of the resistive change memory element R is coupled to a bit line, and the bit line is coupled to an on / off switch M3. A control circuit (not shown) provides access to the RRAM cell 102 by operating the on / off switches M1, M2, and M3.

[0016] The bit line of the RRAM cell 102 is precharged by a reference current source 106B. The reference current source 106B supplies a reference current I RDREF . The read current I READ is determined by the reference current I RDREF and the state of the resistive change memory element R. The precharge voltage level V READ is set by a bias circuit. The bias circuit includes a current source 106A, a transistor T1, and two unity-gain amplifiers (UGAs) 104A and 104B. The UGA 104A supplies a precharge voltage level V READ , which is stepped up by the gate-source voltage of the transistor T1. The stepped-up voltage is output as a voltage V CAS by the UGA 104B. The voltage V CAS is stepped down to the precharge voltage level V READ by the gate-source voltage of the transistor T2.

[0017] The path of the read current I READ is indicated by the dashed line at 108. As shown in FIG. 1, the read current I READThe current flows through the memory cell and transistor T5 to ground. The voltage level at the sense output Sout changes depending on the state of the resistive memory element R, and therefore indicates that state. The state of the resistive memory element R can be read at the sense output Sout by a sense amplifier (not shown).

[0018] Therefore, in the memory circuit 100 of Figure 1, the bit line of the RRAM cell 102 is read current I READ It is charged solely by this current. This current is very small for RRAM technology, and can be, for example, at the level of approximately 5 microamperes. With such a small current, a considerable amount of time is spent charging the bit lines of the RRAM cell 102 to a suitable level for read operations.

[0019] To reduce the time required for read operations, RRAM cells can be pre-charged. Figure 2 shows a conventional memory circuit 200 with current-mode memory cell precharging. The memory circuit 200 in Figure 2 is similar to the memory circuit 100 in Figure 1, except that a pre-charge circuit 202 is added. Other elements of the memory circuit 200 in Figure 2 can be the same as in Figure 1, and their descriptions are not repeated here.

[0020] The precharge circuit 202 includes transistor T4. Transistor T4 is as shown in Figure 2. PMOS A transistor can be used. A control circuit (not shown) supplies a precharge signal Pchg' to the gate of transistor T4. When enabled by the precharge signal, transistor T4 acts as a current source, supplying a large current to the bit lines of RRAM cell 102. This large current quickly precharges the bit lines, thereby reducing the read time for RRAM cell 102. However, this method has several drawbacks.

[0021] Figure 3 shows the read operation for the memory circuit 200 in Figure 2. Referring to Figure 3, the precharge signal is shown at 302. For ease of understanding, the precharge signal is shown inverted. The bit line voltage is shown at 304. The read signal is shown at 306. The control signals can operate on / off switches M1 to M5 to access RRAM cell 102.

[0022] When the precharge signal is asserted, the bit line voltage begins to rise as shown in 304. However, as previously stated, the read current I READ This is partially determined by the state of the resistive random-access memory element R. Process variations in the resistive random-access memory element R can significantly alter this current among the resistive random-access memory elements R in the memory array. Therefore, the precharge voltage rate and level in the bit line can vary significantly, as shown by the multiple curves in 304 of Figure 3.

[0023] These fluctuations result in two significant drawbacks. In some cases, the precharge voltage may overshoot, causing damage to the resistive random-access memory element R. As a result, the resistive random-access memory element may not be able to maintain its state as desired. In addition, this overshoot requires additional time to settle to the desired precharge voltage. Consequently, the read time of the RRAM cell 102 increases, leading to slower operation of the memory array.

[0024] These problems are corrected by embodiments of the technology of this disclosure. Instead of current-mode precharging, these embodiments result in voltage-mode precharging. Figure 4 shows a memory circuit 400 according to several embodiments of the technology of this disclosure. The memory circuit 400 in Figure 4 can be similar to the memory circuit 100 in Figure 1, except that a voltage-mode precharge circuit 402 and a control circuit 410 are added. Other elements of the memory circuit 100 in Figure 1 can be the same as in Figure 1, and their description is not repeated here.

[0025] The voltage-mode precharge circuit 402 in Figure 4 can be implemented as a low-impedance voltage source. The low-impedance voltage source can be implemented using a high-gain feedback loop to mitigate the effects of process variations in the resistive switching memory element R. In the example in Figure 4, the voltage source is implemented as UGA104C. UGA104A and 104C are each provided with a precharge voltage V PRE It supplies the following. In some embodiments, UGA104A and 104C may be implemented as a single UGA.

[0026] Figure 5 shows a read operation 500 according to several embodiments of the technology of the present disclosure. Referring to Figure 5, the read operation 500 includes supplying a precharge voltage from a low-impedance voltage source to the bit lines of a random-access memory cell, in 502. In the example of Figure 4, the control circuit 410 supplies the precharge voltage V to the UGA104C. PRE The on / off switch M6 is controlled to supply power to the bit line of the RRAM cell 102. One advantage of this method is that the voltage source UGA104C controls the voltage of the bit line of the RRAM cell 502, thereby preventing voltage overshoot, and consequently long read times and damage to the resistive random-access memory element R. Thus, during the precharge phase, the precharge voltage is always precharged to the precharge voltage regardless of process variations or the state of the memory cell. And during the sense phase, the bit line voltage is always set to the precharge voltage regardless of the state of the memory cell. And being a low impedance voltage source, UGA104C supplies a large current for rapid precharging of the RRAM cell 102. Furthermore, the current through the memory cell never exceeds Vbl / R, where Vbl is the bit line voltage and R is the resistance of the RRAM cell.

[0027] Referring again to Figure 5, the read operation 500, at 504, stops supplying a precharge voltage from a low-impedance voltage source to the bit lines of the random-access memory cell before reading the memory cell. In the example in Figure 4, the control circuit 410 uses the precharge signal PS to control the on / off switch M6 to electrically isolate UGA104C from the bit lines of RRAM cell 102. In some embodiments, the precharge voltage may be applied for a predetermined time interval. Other embodiments may use other techniques to limit the duration of the precharge voltage.

[0028] Referring again to Figure 5, the read operation involves reading the memory cell at 506 after the bit line voltage reaches the precharge voltage. In the example in Figure 4, the RRAM cell 102 may be read at the output terminal Sout, for example, using a sense amplifier.

[0029] Figure 6 shows the read operation of the memory circuit 400 of Figure 4 according to some embodiments of the technology of the present disclosure. Referring to Figure 6, the precharge signal PS is shown in 602. The bit line voltage is shown in 604. The read signal is shown in 606.

[0030] When the precharge signal is asserted, the bit line voltage begins to rise, as shown in 604. And since the limit voltage is controlled by the voltage source, the bit line voltage is the precharge voltage V, as shown in Figure 6. PRE It rises rapidly and consistently until it reaches the aforementioned advantages.

[0031] In the technology of this disclosure, the bit line voltage determines the read time of a memory cell. This provides an opportunity for precise control of the read time by selecting an appropriate precharge voltage. In some embodiments, the precharge voltage may be selected such that the read time of a memory cell in the off state is approximately equal to the read time of a memory cell in the on state. This technique improves the read speed performance of the entire memory array.

[0032] Another advantage of the technology of this disclosure is that the benefits described above persist regardless of the precharge voltage level used. This advantage is demonstrated in Figures 7A–7D, which show simulation results for memory circuits using the technology of this disclosure. In each of these figures, the left-hand scale is Voltage in volts The scale on the right shows the current in microamperes.

[0033] Figure 7A shows V PRE This demonstrates the read operation for an RRAM cell having an off-state resistive random-access memory element using a precharge voltage of 200mV. In this example, the resistance of the resistive random-access memory element is approximately Roff = 200 K-ohm Referring to Figure 7A, when the precharge signal PS is asserted, the current Icell flowing through the RRAM cell rises rapidly to approximately 1 microampere without overshooting. That is, as can be seen from Figure 7A, the current is V PRE It will never exceed / Roff. As a result, the bit line voltage Vbl will quickly and consistently overshoot the precharge voltage V PRE It rises to [value]. Then, when the precharge signal PS is negated and the resistive variable memory element is off, the current Icell and voltage Vbl rise, causing an increase in the voltage Vout at the output terminal Sout.

[0034] Figure 7B shows V PRE This shows the read operation for an RRAM cell with an ON-state resistive random-access memory element using a precharge voltage of 200mV. In this example, the resistance of the resistive random-access memory element is approximately Ron = 20k ohms. Referring to Figure 7B, when the precharge signal PS is asserted, the current Icell flowing through the RRAM cell rises rapidly to approximately 8 microamperes without overshooting. That is, as can be seen from Figure 7B, the current is V PRE It will never exceed / Ron. As a result, the bit line voltage Vbl will quickly and consistently overshoot the precharge voltage VPRE It rises to [value]. Then, when the precharge signal PS is negated and the resistive random-access memory element is on, the current Icell and voltage Vbl decrease, causing a decrease in the voltage Vout at the output terminal Sout.

[0035] Figure 7D V PRE This demonstrates the read operation for an RRAM cell having an off-state resistive random-access memory element using a precharge voltage of 80mV. In this example, the resistance of the resistive random-access memory element is approximately Roff = 200. K-ohm That is the case. Figure 7D Referring to this, when the precharge signal PS is asserted, the current Icell flowing through the RRAM cell is approximately without overshoot. 0.5 It rises rapidly to microamperes. That is, Figure 7D As can be seen, the current is V PRE It will never exceed / Roff. As a result, the bit line voltage Vbl will quickly and consistently overshoot the precharge voltage V PRE It rises to [value]. Then, when the precharge signal PS is negated and the resistive variable memory element is off, the current Icell and voltage Vbl rise, causing an increase in the voltage Vout at the output terminal Sout.

[0036] Figure 7C is V PRE This demonstrates the read operation for an RRAM cell having an ON-state resistive random-access memory element using a precharge voltage of 80mV. In this example, the resistance of the resistive random-access memory element is approximately Ron = 20k ohms. Figure 7C Referring to this, when the precharge signal PS is asserted, the current Icell flowing through the RRAM cell is approximately without overshoot. 4 It rises rapidly to microamperes. That is, Figure 7C As can be seen, the current is V PRE It will never exceed / Ron. As a result, the bit line voltage Vbl will quickly and consistently overshoot the precharge voltage VPRE It rises to [value]. Then, when the precharge signal PS is negated and the resistive random-access memory element is on, the current Icell and voltage Vbl are rise This causes a decrease in the voltage Vout at the output terminal Sout.

[0037] Spatially relative terms such as "under," "below," "lower," "over," and "upper" are used to facilitate descriptions of the position of one element relative to a second element. These terms encompass different orientations of the device, in addition to orientations different from those shown in the diagram. Furthermore, terms such as "first" and "second" are used to describe various elements, regions, and intervals, and are not intended to be limiting. Similar terms refer to similar elements throughout the description.

[0038] As used herein, terms such as “having,” “containing,” “including,” and “comprising” are open-ended terms indicating the existence of the element or feature being described, but do not exclude additional elements or features. The articles “a,” “an,” and “the” include both singular and plural forms unless the context clearly indicates a different interpretation.

[0039] While the present invention has been disclosed in relation to several implementations and examples, those skilled in the art will understand that the present invention extends beyond the specifically disclosed implementations to other alternative implementations and / or uses of the invention, as well as obvious modifications and equivalents thereof. Accordingly, the scope of the present invention disclosed herein is not intended to be limited to the specific disclosed implementations described above.

[0040] Furthermore, those skilled in the art will recognize the compatibility of various features from different implementations. In addition to the variations described herein, other known equivalents for each feature can be successfully combined by those skilled in the art to construct similar systems and techniques according to the principles herein.

[0041] It should be understood that not all objectives or benefits can necessarily be achieved according to any particular implementation of the present invention. Therefore, for example, those skilled in the art will recognize that the present invention can be embodied or performed in a manner that achieves or optimizes one or a group of benefits as taught herein, without necessarily achieving other objectives or benefits that can be taught or suggested herein. The inventions disclosed herein include the following: [Aspect 1] It is a memory circuit, An array of random access memory cells, A low-impedance voltage source configured to supply a precharge voltage, A control circuit configured to precharge one bit line of the random access memory cell to the precharge voltage using the low impedance voltage source before reading the one bit line of the random access memory cell, A memory circuit equipped with the following features. [Aspect 2] The system further comprises an on / off switch positioned between the low-impedance voltage source and one of the bit lines of the random-access memory cell, The memory circuit according to embodiment 1, wherein the control circuit is configured to electrically couple the low impedance voltage source to the bit line until the bit line reaches the precharge voltage, and to electrically disconnect the low impedance voltage source from the bit line before reading one of the random access memory cells. [Aspect 3] The memory circuit according to embodiment 1, wherein the low-impedance voltage source is a high-gain low-impedance voltage source. [Aspect 4] The memory circuit according to embodiment 3, wherein the low impedance voltage source comprises a unit gain amplifier. [Aspect 5] The memory circuit according to embodiment 1, wherein the random access memory cell is a resistive random access memory cell. [Aspect 6] The memory circuit according to embodiment 5, wherein the magnitude of the precharge voltage is selected such that the read time of the memory cell when it is off is approximately equal to the read time of the memory cell when it is on. [Aspect 7] Each of the resistive random access memory cells is: 3-terminal access element, A resistive random-access element is coupled between the three-terminal access element and one of the plurality of bit lines, A memory circuit according to embodiment 5, comprising the above. [Aspect 8] The first terminal of the three-terminal access element is connected to one of the word lines. The second terminal of the three-terminal access element is coupled to one of the multiple source lines. The memory circuit according to embodiment 7, wherein the resistive random-access memory element is coupled between the third terminal of the three-terminal access element and one of the plurality of bit lines. [Aspect 9] The memory circuit according to embodiment 1, further comprising a sense amplifier configured to read the random access memory cell. [Aspect 10] A method for reading random-access memory cells, A precharge voltage is supplied from a low-impedance voltage source to the bit lines of the random-access memory cell, After the voltage of the bit line reaches the precharge voltage, the memory cell is read out. A method that includes this. [Aspect 11] The method according to embodiment 10, further comprising stopping the supply of the precharge voltage from the low-impedance voltage source to the bit lines of the random-access memory cell before reading the memory cell. [Aspect 12] The low-impedance voltage source is electrically coupled to the bit line until the bit line reaches the precharge voltage. The low-impedance voltage source is electrically isolated from the bit line before reading the random-access memory cell. The method according to embodiment 10, further comprising: [Aspect 13] The method according to embodiment 10, wherein the voltage source comprises a low-impedance voltage source. [Aspect 14] The method according to embodiment 13, wherein the low impedance voltage source comprises a unit gain amplifier. [Aspect 15] The method according to embodiment 15, wherein the random access memory cell is a resistive random access memory cell. [Aspect 16] The method according to embodiment 15, wherein the magnitude of the precharge voltage is selected such that the read time of the memory cell when it is off is approximately equal to the read time of the memory cell when it is on. [Aspect 17] The resistive random-access memory cell is, 3-terminal access element, A resistive random-access element coupled between the three-terminal access element and the bit line, The method according to embodiment 16, comprising: [Aspect 18] The first terminal of the three-terminal access element is connected to the word line. The second terminal of the three-terminal access element is coupled to the source line. The method according to embodiment 17, wherein the resistive random-access memory element is coupled between the third terminal of the three-terminal access element and the bit line.

Claims

1. It is a memory circuit, An array of random access memory cells, A low-impedance voltage source configured to supply a precharge voltage, A control circuit is configured to precharge one bit line of the random access memory cell to the precharge voltage using the low impedance voltage source before reading one of the random access memory cells. An on / off switch is positioned between the low-impedance voltage source and the bit line, Equipped with, The control circuit is configured to electrically couple the low-impedance voltage source to the bit line until the bit line reaches the precharge voltage, and to electrically disconnect the low-impedance voltage source from the bit line before reading one of the random-access memory cells. A memory circuit in which the current of one of the random access memory cells does not exceed V PRE / R, where V PRE is the precharge voltage, R is the resistance of one of the random access memory cells, and the magnitude of the precharge voltage is selected such that the read time of the random access memory cell when off is approximately equal to the read time of the random access memory cell when on.

2. The memory circuit according to claim 1, wherein the low-impedance voltage source is a high-gain low-impedance voltage source.

3. The memory circuit according to claim 2, wherein the low impedance voltage source comprises a unit gain amplifier.

4. The memory circuit according to claim 1, wherein the random access memory cell is a resistive random access memory cell.

5. Each of the resistive random access memory cells is: A three-terminal access element, A resistive random-access element is coupled between the three-terminal access element and one of the plurality of bit lines, The memory circuit according to claim 4, comprising:

6. The first terminal of the three-terminal access element is connected to one of the word lines. The second terminal of the three-terminal access element is connected to one of the multiple source lines. The memory circuit according to claim 5, wherein the resistive random-access memory element is coupled between the third terminal of the three-terminal access element and one of the plurality of bit lines.

7. The memory circuit according to claim 1, further comprising a sense amplifier configured to read the random access memory cell.

8. A method for reading random-access memory cells, A precharge voltage is supplied from a low-impedance voltage source to the bit lines of the random-access memory cell, After the voltage of the bit line reaches the precharge voltage, the memory cell is read out. Before reading the memory cell, the supply of the precharge voltage from the low-impedance voltage source to the bit lines of the random-access memory cell is stopped. Includes, A method wherein the current in one of the random access memory cells does not exceed V PRE / R, where V PRE is the precharge voltage, R is the resistance of one of the random access memory cells, and the magnitude of the precharge voltage is selected such that the read time of the random access memory cell when it is off is approximately equal to the read time of the random access memory cell when it is on.

9. The low-impedance voltage source is electrically coupled to the bit line until the bit line reaches the precharge voltage. The low-impedance voltage source is electrically isolated from the bit line before reading the random-access memory cell. The method according to claim 8, further comprising:

10. The method according to claim 8, wherein the low impedance voltage source comprises a unit gain amplifier.

11. The method according to claim 8, wherein the random access memory cell is a resistive random access memory cell.

12. The aforementioned resistive random access memory cell is A three-terminal access element, A resistive random-access element coupled between the three-terminal access element and the bit line, The method according to claim 11, comprising:

13. The first terminal of the three-terminal access element is connected to the word line. The second terminal of the three-terminal access element is coupled to the source line. The method according to claim 12, wherein the resistive random-access memory element is coupled between the third terminal of the three-terminal access element and the bit line.

14. The method according to claim 8, further comprising reading the random access memory cell by a sense amplifier.

15. It is a memory circuit, Random access memory cells and, A low-impedance voltage source configured to supply a precharge voltage, A control circuit is configured to precharge the bit lines of the random access memory cell to the precharge voltage using the low-impedance voltage source before reading the random access memory cell. An on / off switch is positioned between the low-impedance voltage source and the bit line, Equipped with, The control circuit is configured to electrically couple the low-impedance voltage source to the bit line until the bit line reaches the precharge voltage, and to electrically disconnect the low-impedance voltage source from the bit line before reading one of the random-access memory cells. A memory circuit in which the current of one of the random access memory cells does not exceed V PRE / R, where V PRE is the precharge voltage, R is the resistance of one of the random access memory cells, and the magnitude of the precharge voltage is selected such that the read time of the random access memory cell when off is approximately equal to the read time of the random access memory cell when on.

16. The memory circuit according to claim 15, wherein the low impedance voltage source comprises a unit gain amplifier.

17. The memory circuit according to claim 16, wherein the random access memory cell is a resistive random access memory cell.

18. The memory circuit according to claim 15, wherein the random access memory cell is a resistive random access memory cell.

19. The aforementioned resistive random access memory cell is A three-terminal access element, A resistive random-access element is coupled between the three-terminal access element and one of the plurality of bit lines, The memory circuit according to claim 18, comprising:

20. The first terminal of the three-terminal access element is connected to one of the word lines. The second terminal of the three-terminal access element is connected to one of the multiple source lines. The memory circuit according to claim 19, wherein the resistive random-access memory element is coupled between the third terminal of the three-terminal access element and one of the plurality of bit lines.

21. The memory circuit according to claim 15, further comprising a sense amplifier configured to read the random access memory cell.

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