Sample holder and superconducting quantum computer

Abstract

To more increase a resonance frequency of resonance occurring when a signal of a specific frequency is input to a chip when the chip is mounted on a sample holder.SOLUTION: A sample holder includes a pedestal and a printed circuit board (PCB) in contact with the pedestal. The PCB includes: a dielectric 8; a front surface ground (GND) 9 formed on a front surface of the dielectric 8; a back surface GND 11 formed on a back surface of the dielectric 8; a through hole 4 that penetrates from the front surface GND 9 to the back surface GND 11 and in which a chip is stored; and a conductor 14 that conducts the front surface GND 9 and the back surface GND 11 to an end surface of the through hole 4. A cavity is provided in at least part of a lower side of the through hole 4 in the pedestal, and a support structure is provided that supports a surface of the chip and being conducted to the pedestal in the cavity.SELECTED DRAWING: Figure 11E

Description

Technical Field

[0001] The present disclosure relates to a sample holder and the like.

Background Art

[0002] Superconducting quantum circuits are formed on a substrate such as a silicon substrate using superconducting materials such as Nb (niobium) and Al (aluminum). Here, a structure in which a superconducting quantum circuit is formed on a substrate is called a chip. The superconducting quantum circuit is mounted on a sample holder and operated. There are various structures of sample holders. As a method of mounting the chip, there are a method of mounting the chip on a printed circuit board as described in Non-Patent Document 1 without turning over the circuit surface of the chip, and a method of mounting the chip on a printed circuit board by turning over the circuit surface of the chip as described in Patent Document 1 (flip chip mounting). In the following description, the former mounting method will be described on the premise.

[0003] For example, there is a structure in which a printed circuit board (Printed Circuit Board, hereinafter PCB) is installed on a metal pedestal. A through hole is provided near the center of the PCB, the chip is placed in the through hole, and the pads of the chip and the PCB, and the ground of the chip and the ground of the PCB are electrically connected by bonding wires such as Al. In such a case, the back surface of the chip is in contact with the metal pedestal.

[0004] When a chip is mounted on the sample holder as described above, resonance occurs when a signal of a specific frequency is input to the chip. Here, this resonance is referred to as chip-mode resonance. When the chip-mode resonance couples with the superconducting quantum circuit on the chip, it causes decoherence of the superconducting quantum circuit. In order to reduce the influence of this decoherence, the resonance frequency of the chip mode should be made as high as possible. For example, Non-Patent Document 1 describes that in order to suppress the influence of the chip mode, in the above-described structure, a cavity is formed directly under the chip by removing a part of the metal pedestal directly under the chip.

Prior Art Documents

[0005] [Patent Document 1] Japanese Patent Publication No. 2002-299503 [Non-patent literature]

[0006] [Non-Patent Document 1] B. Lienhard, et al., “Microwave Packaging for Superconducting Qubits,” arXiv: 1906.05425v1 [quant-ph] 12 Jun 2019. [Overview of the project] [Problems that the invention aims to solve]

[0007] When a chip is mounted on a sample holder, it is required that the resonant frequency of the resonance that occurs when a signal of a specific frequency is input to the chip be higher than that of the technology described in Non-Patent Document 1.

[0008] One example of the purpose of this disclosure is to provide a sample holder that increases the resonant frequency of the resonance that occurs when a signal of a specific frequency is input to a chip mounted on the sample holder. [Means for solving the problem]

[0009] A sample holder in one aspect of the present disclosure comprises a base and a PCB in contact with the base, wherein the PCB has a dielectric, a surface ground formed on the surface of the dielectric, a back ground formed on the back surface of the dielectric, a through hole for storing a chip that penetrates from the surface ground to the back ground, and a conductor at the end face of the through hole that conducts the surface ground and the back ground, wherein at least a portion of the base below the through hole is a cavity, and the cavity has a support structure that supports the surface of the chip and is conductive to the base, wherein at least a portion of the support structure that supports the chip is not parallel to the surface of the chip.

[0010] A superconducting quantum computer in one aspect of the present disclosure comprises a sample holder and a chip on which a superconducting quantum circuit is formed, which is stored in the sample holder, wherein the sample holder comprises a base and a PCB in contact with the base, the PCB having a dielectric, a surface ground formed on the surface of the dielectric, a back ground formed on the back surface of the dielectric, a through hole in which the chip is stored and which penetrates from the surface ground to the back ground, and a conductor on the end face of the through hole that conducts the surface ground and the back ground, wherein at least a portion of the base below the through hole is a cavity, and the cavity has a support structure that supports the surface of the chip and is conductive to the base, wherein at least a portion of the support structure that supports the chip is not parallel to the surface of the chip. [Effects of the Invention]

[0011] According to this disclosure, when a chip is mounted on a sample holder, the resonant frequency of the resonance that occurs when a signal of a specific frequency is input to the chip is increased. [Brief explanation of the drawing]

[0012] [Figure 1A] This is an explanatory diagram showing an example of a sample holder for storing chips on which superconducting quantum circuits are formed. [Figure 1B]It is a side view of the sample holder shown in FIG. 1A. [Figure 2A] It is a top view of the PCB. [Figure 2B] It is a bottom view of the PCB. [Figure 2C] It is a side view of the PCB. [Figure 2D] It is a perspective view of the PCB. [Figure 2E] It is an enlarged view of the vicinity of the through-hole of the PCB. [Figure 3A] It is a perspective view showing the configuration when a chip of a superconducting quantum circuit is mounted on the sample holder shown in FIGS. 1A and 1B. [Figure 3B] It is an end view in which the configuration when a chip of a superconducting quantum circuit is mounted on the sample holder shown in FIGS. 1A and 1B is cut along a plane parallel to the xz plane including the cutting line A-AA shown in FIG. 3A. [Figure 4A] It is a top view of the chip used in the simulation. [Figure 4B] It is an enlarged view of the vicinity of the tip of the first coplanar waveguide. [Figure 5A] It is a perspective view showing an example in which the chips shown in FIGS. 4A and 4B are mounted on the sample holder shown in FIGS. 1A and 1B. [Figure 5B] It is an enlarged view of the vicinity of the chip. [Figure 6A] It is an explanatory diagram showing the reflection (S11) at Port 1 when a high-frequency signal is input from Port 1 shown in FIG. 5A. [Figure 6B] It is an explanatory diagram showing the transmission (S21) to Port 2 when a high-frequency signal is input from Port 1 shown in FIG. 5A. [Figure 7A] It is a perspective view of the sample holder in which a cavity is formed in the pedestal. 3] [Figure 7B] It is a top view of the sample holder in which a cavity is formed in the pedestal. [Figure 7C] It is an end view in which the sample holder in which a cavity is formed in the pedestal is cut along a plane parallel to the xz plane including the cutting line B-BB shown in FIG. 7B. [Figure 8]Explanatory drawing showing the simulation result of reflection (S11) to Port1 when a high-frequency signal is input to Port1 shown in Fig. 5A when the chips shown in Figs. 4A and 4B are mounted on the sample holder shown in Figs. 7A, 7B, and 7C. [Figure 9] Explanatory drawing showing the sample holder according to the first embodiment. [Figure 10A] Perspective view showing the sample holder of the first embodiment. [Figure 10B] Top view of the sample holder of the first embodiment. [Figure 10C] End view of the sample holder of the first embodiment cut along a plane parallel to the xz plane including the cutting line C-CC shown in Fig. 10B. [Figure 11A] Top view of the PCB used for the sample holder of the first embodiment. [Figure 11B] Bottom view of the PCB used for the sample holder of the first embodiment. [Figure 11C] Side view of the PCB used for the sample holder of the first embodiment. [Figure 11D] Perspective view of the PCB used for the sample holder of the first embodiment. [Figure 11E] Enlarged view near the through hole of the PCB used for the sample holder of the first embodiment. [Figure 12] Explanatory drawing showing the simulation result of S11 when a chip is mounted on the sample holder according to the first embodiment with bonding wires. [Figure 13A] Top view showing the structure of the PCB according to a modification of the first embodiment. [Figure 13B] Cross-sectional view of the PCB according to a modification of the first embodiment cut along a plane parallel to the xy plane so that the core wires formed in the region sandwiched between the surface GND and the back surface GND can be seen. [Figure 13C] Enlarged view near the core wires of the cross section of the PCB according to a modification of the first embodiment cut along a plane parallel to the xz plane including the cutting line D-DD shown in Fig. 13A. [Figure 13D]This is a bottom view showing the structure of a PCB according to a modified example of the first embodiment. [Figure 13E] This is a perspective view of a PCB according to a modified example of the first embodiment. [Figure 13F] This is an enlarged view of the area near the through-hole in the PCB according to a modified example of the first embodiment. [Figure 14] This is a magnified view of the area near the through-hole of the PCB used in the sample holder of the second embodiment. [Figure 15] This is an explanatory diagram showing the simulation results of S11 when a chip is mounted on the sample holder of the second embodiment using bonding wire. [Figure 16] This is a magnified view of the area near the through-hole of the PCB used in the sample holder of the second embodiment. [Figure 17A] This is a perspective view of the sample holder according to the third embodiment. [Figure 17B] This is a top view of the sample holder according to the third embodiment. [Figure 17C] The sample holder according to the third embodiment is an end view cut by a plane parallel to the xz plane, including the cutting line E-EE shown in Figure 17B. [Figure 18] This is an explanatory diagram showing the simulation results of S11 according to the third embodiment. [Figure 19A] This is a perspective view of a sample holder according to another example of the third embodiment. [Figure 19B] This is a top view of a sample holder according to another example of the third embodiment. [Figure 19C] Figure 19B shows an end view of a sample holder according to another example of the third embodiment, cut by a plane parallel to the xz plane including the cutting line F-FF. [Figure 20] This is an explanatory diagram showing the simulation results of S11 according to another example of the third embodiment. [Figure 21A] This is a perspective view of a sample holder according to a modified example of the third embodiment. [Figure 21B] This is a top view of a sample holder according to a modification of the third embodiment. [Figure 21C] Figure 21B shows an end view of a sample holder according to a modification of the third embodiment, cut by a plane parallel to the xz plane including the cutting line G-GG. [Figure 22] Figures 21A to 21C are explanatory diagrams showing the simulation results of S11 when a chip is mounted with bonding wire on a sample holder using a base with a cavity formed therein. [Figure 23A] This is a perspective view of a sample holder according to the fourth embodiment. [Figure 23B] This is a top view of a sample holder according to the fourth embodiment. [Figure 23C] Figure 23B shows an end view of the sample holder according to the fourth embodiment, cut by a plane parallel to the xz plane, including the cutting line H-HH. [Figure 24] This is an explanatory diagram showing the simulation results of S11 when a chip is mounted on the sample holder according to the fourth embodiment using bonding wire. [Figure 25A] This is a perspective view of a sample holder according to a modified example of the fourth embodiment. [Figure 25B] This is a top view of a sample holder according to a modification of the fourth embodiment. [Figure 25C] Figure 25B shows an end view of a sample holder according to a modification of the fourth embodiment, cut by a plane parallel to the xz plane including the cutting line I-II. [Figure 26] Figures 25A to 25C are explanatory diagrams showing the simulation results of S11 when a chip is mounted on a sample holder using a base with a cavity formed therein. [Figure 27A] This is a perspective view of the sample holder of the fifth embodiment. [Figure 27B] This is a top view of the sample holder according to the fifth embodiment. [Figure 27C] The sample holder of the fifth embodiment is a cross-sectional view taken by a plane parallel to the xz plane, including the cutting line J-JJ shown in Figure 27B. [Figure 28A] This is a perspective view showing example 1 of the cavity shape of the sample holder in the fifth embodiment. [Figure 28B] This is a top view showing example 1 of the shape of the cavity in the sample holder of the fifth embodiment. [Figure 28C] In the fifth embodiment, example 1 of the sample holder cavity shape, the area near the sample holder cavity is a cross-section view taken by a plane parallel to the xz plane, including the cutting line K-KK shown in Figure 28B. [Figure 29A] This is a perspective view showing example 2 of the cavity shape of the sample holder in the fifth embodiment. [Figure 29B] This is a top view showing example 2 of the cavity shape of the sample holder in the fifth embodiment. [Figure 29C] In the second example of the cavity shape of the sample holder in the fifth embodiment, the sample holder is a cross-sectional view taken by a plane parallel to the xz plane, including the cutting line L-LL shown in Figure 29B. [Figure 30] This is an explanatory diagram showing the simulation results of S11 of the system in which a chip is mounted on the sample holder of the fifth embodiment. [Figure 31A] This is a perspective view of a sample holder of a modified example of the fifth embodiment. [Figure 31B] This is a top view of a sample holder of a modified example of the fifth embodiment. [Figure 31C] A sample holder of a modified example of the fifth embodiment is a cross-sectional view taken from a plane parallel to the xz plane, including the cutting line M-MM shown in Figure 31B. [Figure 32A] This is a perspective view showing example 1 of the shape of the cavity in the sample holder of a modified example of the fifth embodiment. [Figure 32B] This is a top view showing example 1 of the shape of the cavity in the sample holder of a modified example of the fifth embodiment. [Figure 32C] In the example of the shape of the cavity in the sample holder of the fifth embodiment, the area near the cavity in the sample holder is a cross-section view taken by a plane parallel to the xz plane containing the cutting line N-NN shown in Figure 32B. [Figure 33A] This is a perspective view showing example 2 of the shape of the cavity in the sample holder of a modified example of the fifth embodiment. [Figure 33B]This is a top view showing example 2 of the shape of the cavity in the sample holder, a modified example of the fifth embodiment. [Figure 33C] In the second example of the shape of the cavity in the sample holder, a modified example of the fifth embodiment, the sample holder is a cross-sectional view taken by a plane parallel to the xz plane, which includes the cutting line O-OO shown in Figure 33B. [Figure 34] This is an explanatory diagram showing the simulation results of S11 in a system where a chip is mounted on a sample holder with bonding wires, which is a modified example of the fifth embodiment. [Modes for carrying out the invention]

[0013] Embodiments of the sample holder and superconducting quantum computer according to this disclosure will be described in detail below with reference to the drawings. However, the drawings are schematic representations of the configuration in the embodiments of this disclosure. Furthermore, the embodiments of this disclosure described below are examples and can be modified as appropriate to the extent that they are essentially the same. In the following drawings, identical or similar parts are denoted by the same or similar reference numerals. In the following drawings, elements not used in the description are omitted as appropriate. Also, in the following description, ground may be represented as GND. For example, surface ground will be represented as surface GND. For example, back surface ground will be represented as back surface GND.

[0014] To clarify the effects of the sample holders in each embodiment, we will compare the simulation results of a modeled sample holder with a cavity formed in the base directly beneath the chip with the simulation results of a modeled sample holder in each embodiment. Therefore, before describing each embodiment in detail, we will first explain the chip mode problem in superconducting quantum circuits in more detail. Then, we will describe the simulation results of a modeled sample holder that will be used for comparison with the sample holders in each embodiment. The sample holder used for comparison has a PCB placed on a metal base. Furthermore, this sample holder has a through hole near the center of the PCB. In addition, this sample holder has a part of the metal base directly beneath the chip hollowed out, forming a cavity directly beneath the chip.

[0015] Furthermore, in order to clearly indicate the orientation in each drawing, we will use a three-dimensional coordinate system with x, y, and z axes for explanation.

[0016] Figure 1A is an explanatory diagram showing an example of a sample holder for storing a chip on which a superconducting quantum circuit is formed. Figure 1B is a side view of the sample holder 101 shown in Figure 1A. As shown in Figure 1A, the sample holder 101 has a configuration in which a PCB 103 is placed on a metal base 102. In Figure 1A, the shape of the base 102 is a rectangular parallelepiped or a cube. A through-hole 104 is provided near the center of the PCB 103, penetrating the PCB 103.

[0017] An example of PCB103 is shown in Figures 2A to 2E. Figure 2A is a top view of PCB103. Figure 2B is a bottom view of PCB103. Figure 2C is a side view of PCB103. Figure 2D is a perspective view of PCB103. Figure 2E is a magnified view of the area around the through-hole 104 of PCB103.

[0018] As shown in Figures 2A to 2E, the PCB 103 has a structure in which, for example, a surface GND 109 and a core wire 110 of a coplanar waveguide are formed on one side of a plate-shaped dielectric 108 extending parallel to the xy plane, and a back surface GND 111 is formed on the other side of the dielectric 108. The core wire 110, surface GND 109, and back surface GND 111 are conductors, such as metal. Here, a coplanar waveguide is a waveguide composed of a central conductor (hereinafter abbreviated as the central conductor) and two GND planes arranged on both sides of the central conductor with a gap between them in the xy plane, and the central conductor and the two GND planes are arranged substantially on the same plane. The two GND planes of the coplanar waveguide shown in Figures 2A and 2E are formed by the surface GND 109. In the PCB 103 shown in Figures 2A to 2E, the core wire 110 corresponds to the central conductor. In the PCB 103 shown in Figures 2A to 2E, a coplanar waveguide is formed by creating a surface GND 109 with a gap in the xy plane on both sides of the core wire 110. In the example shown in Figures 2A to 2E, eight coplanar waveguides are formed in the PCB 103. As shown in Figure 2D, the PCB 103 is provided with multiple through-holes 112. These through-holes 112 penetrate the dielectric 108 and electrically connect the surface GND 109 and the back surface GND 111. For example, through-holes 112 are created by forming holes that penetrate the dielectric 108, the surface GND 109, and the back surface GND 111, and then plating the inside of the holes with metal. In Figures 1A and 1B, the back surface GND 111 of the PCB 103 is in contact with the base 102. Therefore, the metal base 102 and the GND 111 on the back of PCB 103, the through-hole 112 of PCB 103, and the GND 109 on the front of PCB 103 are electrically connected. Also, the through-hole 104 located near the center of PCB 103 has the same shape as, for example, the chip of the superconducting quantum circuit mounted on the sample holder 101, i.e., it is rectangular or square. Furthermore, the area of ​​the through-hole 104 is larger than the area of ​​the chip so that the chip fits inside the through-hole 104.

[0019] Next, Figures 3A and 3B show the configuration when the superconducting quantum circuit chip 107 is mounted on the sample holder 101 shown in Figures 1A and 1B. Figure 3A is a perspective view showing the configuration when the superconducting quantum circuit chip 107 is mounted on the sample holder 101 shown in Figures 1A and 1B. Figure 3B is an end view of the configuration when the superconducting quantum circuit chip 107 is mounted on the sample holder 101 shown in Figures 1A and 1B, cut by a plane parallel to the xz plane including the cutting line A-AA shown in Figure 3A. In Figures 3A and 3B, the PCB 103 shown in Figures 2A to 2E is used. As shown in Figures 3A and 3B, the chip 107 is placed inside the through-hole 104 of the PCB 103 and then placed on the base 102. The pads of the chip 107 and the core wires 110 of the PCB 103 are electrically connected with bonding wires 113 made of aluminum (Al), and the GND plane of the chip 107 and the surface GND 109 of the PCB are electrically connected with bonding wires 113 made of aluminum (Al). Here, the pads of the chip 107 refer to the terminals formed on the chip 107 for signal input and output. In the example shown in Figures 3A and 3B, the back surface of the chip 107 (the lower surface of the chip 107 in Figure 3B) is in contact with the metal base 102.

[0020] When chip 107 is mounted on the sample holder 101 shown in Figures 1A and 1B, resonance occurs when a signal of a specific frequency is input to chip 107. To identify the cause of this chip-mode resonance, a simulation using electromagnetic field analysis software is performed. Here, the simulation is performed using ANSYS® HFSS manufactured by ANSYS Japan Co., Ltd. The same tool will be used for subsequent simulations as well.

[0021] The chip is shown in Figures 4A and 4B. Figure 4A is a top view of the chip 107 used in the simulation. Figure 4B is a magnified view of the area near the tip of the first coplanar waveguide 71. As shown in Figure 4A, the chip 107 has a rectangular or square shape, with the lengths of each side of the chip 107 being v and w, respectively. In the simulation described below, the shape of the chip 107 is assumed to be square, and the lengths of each side of the chip 107 are set to v=w=5 [mm] (millimeters). The chip 107 used in the simulation has a 200 [nm] (nanometer) thick metal film laminated on a 380 [μm] (micrometer) thick silicon substrate, and the circuit pattern is formed by removing a predetermined portion of the metal film. The chip 107 shown in Figures 4A and 4B has a first coplanar waveguide 71 and a second coplanar waveguide 72 formed on it. The first coplanar waveguide 71 and the second coplanar waveguide 72 have the same shape. The characteristic impedance of the first coplanar waveguide 71 and the second coplanar waveguide 72 are designed to be 50 ohms, and their length is 1 mm. Figure 4B shows a magnified view of the area near the tip of the first coplanar waveguide 71. As shown in Figure 4B, the tip of the first coplanar waveguide 71 is not in contact with the GND plane 73. As shown in Figure 4A, the first coplanar waveguide 71 and the second coplanar waveguide 72 are not connected. Similarly, the tip of the second coplanar waveguide 72 is not in contact with the GND plane 73. One end of the first core wire 74 is connected to the first pad 76, and one end of the second core wire 75 is connected to the second pad 77.

[0022] Figures 5A and 5B show an example of the chip 107 shown in Figures 4A and 4B mounted on the sample holder 101 shown in Figures 1A and 1B. Figure 5A is a perspective view showing an example of the chip 107 shown in Figures 4A and 4B mounted on the sample holder 101 shown in Figures 1A and 1B. Figure 5B is a magnified view of the area around the chip 107. As shown in Figures 5A and 5B, the first pad 76 of the chip 107 is electrically connected to the first core wire 110a of the PCB 103 by an Al bonding wire 113. The second pad 77 of the chip 107 is electrically connected to the second core wire 110b of the PCB 103 by an Al bonding wire 113, and the GND plane 73 of the chip 107 is electrically connected to the surface GND 109 of the PCB 103 by an Al bonding wire 113. As shown in Figure 5A, the end of the first core wire 110a of PCB103 that is not connected to the first pad 76 of chip 107 is designated as Port1. On the other hand, the end of the second core wire 110b of PCB103 that is not connected to the second pad 77 of chip 107 is designated as Port2. In the simulation, for example, when a high-frequency signal is input from Port1, the reflection to Port1 and transmission to Port2 are calculated. Here, the reflection to Port1 is denoted as S11, and the transmission to Port2 is denoted as S21.

[0023] Figures 6A and 6B show the simulation results when a high-frequency signal is input from Port 1, as shown in Figure 5A. Figure 6A is an explanatory diagram showing the reflection (S11) to Port 1 when a high-frequency signal is input from Port 1, as shown in Figure 5A. Figure 6B is an explanatory diagram showing the transmission (S21) to Port 2 when a high-frequency signal is input from Port 1, as shown in Figure 5A. In Figures 6A and 6B, the horizontal axis is frequency (unit [GHz] (gigahertz)). The vertical axes S11 and S21 are displayed in decibels ([dB]). That is, the vertical axes S11 and S21 are displayed logarithmically. In the following explanation of the simulation results, the horizontal axis will also be frequency (unit [GHz]), and the vertical axes S11 and S21 will be displayed in decibels ([dB]).

[0024] As shown in Figures 6A and 6B, when signals of certain specific frequencies are input, S21 becomes very large and S11 becomes very small. As shown in Figures 4A and 4B, the first coplanar waveguide 71 and the second coplanar waveguide 72 of chip 107 are not connected. Therefore, even if a signal is input to Port 1, it is expected that the signal will not pass through to Port 2. However, as the simulation results in Figure 6B show, when signals of certain specific frequencies are input from Port 1, S21 becomes very large. For example, according to the simulation results in Figure 6B, when an 8.9 [GHz] signal is input from Port 1, S21 is approximately -1.9 [dB]. That is, about 65% of the energy of the signal input from Port 1 is transmitted to Port 2. At certain frequencies where S21 becomes very large, the simulation results shown in Figure 6A show that S11 becomes very small.

[0025] From the above, the simulation results shown in Figures 6A and 6B indicate the following: In a system where the superconducting quantum circuit chip 107 is mounted on the sample holder 101, as shown in Figures 5A and 5B, the space between the GND plane 73 on the surface of the chip 107 and the metal base 102, i.e., the silicon substrate, forms a cavity resonator. The first coplanar waveguide 71 and the second coplanar waveguide 72 of the chip 107 are coupled to this cavity resonator. Therefore, when a signal with a frequency equal to the resonant frequency of this cavity resonator is input to the chip from, for example, Port 1, the resonance of the cavity resonator is excited. A standing wave is then formed in the silicon substrate, and electromagnetic field energy is accumulated. Since the second coplanar waveguide 72 of the chip 107 is also coupled to this cavity resonator, some of the electromagnetic field energy accumulated in the silicon substrate is transmitted through the second coplanar waveguide 72 of the chip 107 to Port 2.

[0026] Such phenomena can occur in the systems shown in Figures 3A and 3B, regardless of the type of circuit formed on the chip 107. This phenomenon can occur not only when coplanar waveguides 71 and 72 are formed on the chip 107 as shown in Figures 4A and 4B, but also when any superconducting quantum circuit is formed on the chip 107. In the implementation system shown in Figure 3, resonance caused by the formation of a cavity resonator in the space between the GND plane 73 on the surface of the chip 107 and the metal base 102, i.e., the silicon substrate, is referred to as chip-mode resonance in this specification.

[0027] In the simulation results of Figures 6A and 6B, several specific frequencies at which S21 becomes very large and S11 becomes very small are referred to below as the resonant frequencies of the chip modes. When a signal with a frequency equal to or close to the resonant frequency of the chip modes is input to chip 107, resonance of the chip modes occurs. According to the simulation results of Figures 6A and 6B, in the system shown in Figures 5A and 5B, the lowest resonant frequency of the chip modes is 8.9 [GHz]. In the system shown in Figures 3A and 3B, in which chip 107 with a superconducting quantum circuit is mounted on sample holder 101 shown in Figures 1A and 1B, when chip modes couple with the superconducting quantum circuit formed on chip 107, it causes decoherence of the superconducting quantum circuit. It is known that in order to reduce the effect of this decoherence, it is necessary to make the resonant frequency of the chip modes as high as possible.

[0028] Therefore, there is a need for a technology to increase the resonant frequency of the chip modes. For example, in the comparative sample holder 101, the influence of chip modes can be reduced by creating a cavity directly beneath the chip 107 by hollowing out a portion of the base 102 that is directly beneath the chip 107.

[0029] Figures 7A to 7C show enlarged views of the sample holder 101, which has a cavity formed in its base 102, near the through-hole 104 of the PCB 103. Figure 7A is a perspective view of the sample holder 101 with a cavity formed in its base. Figure 7B is a top view of the sample holder 101 with a cavity formed in its base. Figure 7C is an end view of the sample holder 101 with a cavity formed in its base, cut by a plane parallel to the xz plane including the cutting line B-BB shown in Figure 7B. As shown in Figures 7A to 7C, a cavity 105 is formed in the base 102 in the portion directly below the through-hole 104 of the PCB 103. In other words, as shown in Figures 7A to 7C, a cavity 105 is formed in the base 102 in the portion directly below the chip 107 when the chip 107 is mounted on the sample holder 101. Furthermore, in Figures 7A to 7C, the cavity 105 is a rectangular prism with a base having the same area as the chip 107. The base 102 has a structure in which pillars 106 remain at the four corners of the cavity 105. The pillars 106 are made of metal, for example. In Figure 7C, the chip 107 is mounted on the sample holder 101 with bonding wire 113.

[0030] In Figures 7A, 7B, and 7C, the columns 106 are represented with a different pattern from the base 102 to clearly indicate their presence. The metal columns 106 at the four corners are integrated with the base 102 and constitute a part of the base 102. Of the two bottom surfaces of the metal columns 106 at the four corners shown in Figures 7A to 7C, the upper bottom surface contacts the back surface of the chip 107. Also, in Figures 7A and 7B, the bottom surface of the metal column 106 is a right-angled isosceles triangle. As shown in Figure 7C, the simulation is performed for the case where the lengths of the two equal sides of the bottom surface of this column 106 are set to 1 [mm] (millimeters), and the height of the cavity 105 is set to 3 [mm], and the chip 107 shown in Figures 4A and 4B is mounted on the sample holder 101 in Figure 7.

[0031] Figure 8 is an explanatory diagram showing the simulation results of the reflection (S11) to Port 1 when a high-frequency signal is input from Port 1 shown in Figure 5A, when the chip 107 shown in Figures 4A and 4B is mounted on the sample holder 101 shown in Figures 7A, 7B, and 7C using bonding wires 113. According to the simulation results in Figure 8, when the chip 107 shown in Figures 4A and 4B is mounted on the sample holder 101 in which the cavity 105 shown in Figure 7 is formed on the base 102 using bonding wires 113, it can be seen that the lowest resonant frequency of the chip mode can be raised to 19.9 [GHz]. In the simulation results when the cavity 105 is not formed on the base 102 (Figures 6A and 6B), the lowest resonant frequency of the chip mode is 8.9 [GHz]. From this, it can be seen that by using the sample holder 101 in which the cavity 105 shown in Figures 7A, 7B, and 7C is formed on the base 102, the resonant frequency of the chip mode can be significantly increased.

[0032] The reason why forming a cavity 105 in the base 102 can increase the resonant frequency of the chip mode is that, when a cavity 105 is formed directly beneath the chip 107, the inside of the cavity resonator formed by the space between the GND plane 73 on the surface of the chip 107 and the base 102 (in this case, the bottom of the cavity 105) is presumed to consist of silicon (380 μm thick in the simulation) and vacuum (3 mm thick in the simulation). This is presumed to be because the effective dielectric constant inside the cavity resonator is lower than when a cavity 105 is not formed in the base 102 (i.e., when the inside of the cavity resonator is almost entirely silicon). Note that the relative permittivity of vacuum is 1, while the relative permittivity of silicon is very high at 11.9. In addition, the resonant frequency of a cavity resonator generally increases as the dielectric constant of the medium filling the inside of the cavity resonator decreases.

[0033] Thus, by using a sample holder 101 with a cavity 105 formed on the base 102, the resonant frequency of the chip modes can be increased. However, in order to reduce the influence of chip modes on superconducting quantum circuits, it is necessary to make the resonant frequency of the chip modes as high as possible. Furthermore, as the number of qubits integrated on the chip 107 increases toward the practical application of quantum computers, it is predicted that a chip 107 with an area larger than 5 [mm] × 5 [mm] will be required. The larger the area of ​​the chip 107, the lower the resonant frequency of the chip modes. This is because as the area of ​​the chip 107 increases, the dimensions of the bottom surface of the cavity resonator formed by the space sandwiched between the GND plane 73 on the surface of the chip 107 and the base 102 increase. Therefore, even when using a sample holder 101 with a cavity 105 formed on the base 102 as shown in Figures 7A to 7C, it is predicted that as the area of ​​the chip 107 increases, the resonant frequency of the chip modes will decrease and the influence on the quantum circuit will increase. Therefore, it is necessary to develop a technology that can raise the resonant frequency of the chip modes as much as possible, compared to the case where a sample holder 101 with a cavity 105 formed in the base 102 is used.

[0034] Therefore, we will now describe various embodiments that can increase the resonant frequency of the chip mode.

[0035] (First embodiment) In the first embodiment, we describe an example in which the PCB in contact with the base has a dielectric, a surface GND formed on the surface of the dielectric, a back GND formed on the back surface of the dielectric, a through hole that penetrates from the surface GND to the back GND in which the chip is housed, and a conductor that conducts the surface GND and the back GND at the end face of the through hole. Furthermore, in the first embodiment, we describe an example in which there is a cavity in at least a part of the base below the through hole, and the cavity has a support structure that supports the surface of the chip and is conductive to the base.

[0036] Figure 9 is an explanatory diagram showing a sample holder according to the first embodiment. The sample holder 1 of the first embodiment has a configuration in which a PCB 3 is placed on a metal base 2, as shown in Figure 9. A through hole 4 is provided near the center of the PCB 3, penetrating the PCB 3. The shape of the base 2 is not particularly limited. For example, the shape of the base 2 may be a rectangular parallelepiped or a cube. The sample holder 1 has a cavity 5 in the base 2, in the portion directly below the through hole 4 in the PCB 3.

[0037] By making the height of the circuit surface of the chip and the surface of the PCB3 as close as possible, wire bonding can be made easier, and the bonding wires can be shortened. The shorter the bonding wires, the better the electrical characteristics. In addition, by forming through holes 4 in the PCB3, the resonant frequency of the chip modes can be increased. If dielectric or conductive material is present on the back surface of the chip (the surface opposite the circuit surface), the resonant frequency of the chip modes will decrease. Therefore, in order to increase the resonant frequency of the chip modes, the back surface of the chip should be in contact with the vacuum as much as possible. If the chip is placed on the PCB3 without forming through holes 4 in the PCB3, the dielectric or conductive material of the PCB3 will come into contact with the back surface of the chip, so the resonant frequency of the chip modes cannot be increased. Therefore, in the first embodiment, through holes 4 are formed in the PCB3, the chip is placed in the through holes 4, and a cavity 5 is formed in the base 2 directly below the chip, so that the largest possible area of ​​the back surface of the chip is in contact with the vacuum.

[0038] Figures 10A to 10C show enlarged views of the area near the through-hole 4 of the PCB 3 in the sample holder 1 of the first embodiment. Figure 10A is a perspective view of the sample holder 1 of the first embodiment. Figure 10B is a top view of the sample holder 1 of the first embodiment. Figure 10C is an end view of the sample holder 1 of the first embodiment, cut by a plane parallel to the xz plane including the cutting line C-CC shown in Figure 10B. In Figure 10C, the chip 7 is mounted on the sample holder 1 of the first embodiment with bonding wire 13.

[0039] The sample holder 1 has a cavity 5 in at least a portion of the base 2 below the through hole 4. In Figures 10A to 10C, the sample holder 1 has a cavity 5 in the base 2, in the portion directly below the through hole 4 of the PCB 3. In other words, in Figures 10A to 10C, the sample holder 1 has a cavity 5 in the base 2, in the portion directly below the chip 7 when the chip 7 is mounted on the sample holder 1 with bonding wires 13. The shape of the cavity 5 is not particularly limited. For example, the bottom surface of the cavity 5 may be flat or not. The sides of the cavity 5 may be flat or not. For example, there may be indentations on the sides or bottom surface of the cavity 5. In Figures 10A to 10C, the cavity 5 is in the shape of a rectangular prism. More specifically, in Figures 10A to 10C, the cavity 5 is a rectangular prism with a base that is a rectangle with sides of length a and b, and a height of d. Furthermore, the cavity 5 has a support structure that is electrically connected to a base and supports the surface of the chip 7. The material of the support structure is, for example, metal. Specifically, the material of the support structure may be, for example, a metal-containing mixture such as a resin mixed with metal particles or fillers.

[0040] Furthermore, the shape of the support structure is not particularly limited. For example, in Figures 10A to 10C, the support structure may be a column 6. Although not shown, the support structure may be, for example, a protrusion extending from the side of the cavity 5. Alternatively, although not shown, the support structure may be, for example, three non-linear support points. Alternatively, although not shown, the support structure may be a structure extending from the bottom of the cavity 5 like a pincushion.

[0041] Here, as a support structure, we will explain using the columns 6 shown in Figures 10A to 10C as an example. The number and shape of the columns 6 are not particularly limited. The same applies to subsequent embodiments. In Figures 10A to 10C, multiple columns 6 are provided in the cavity 5. More specifically, conductive columns 6 are arranged at the four corners of the cavity 5.

[0042] In Figures 10A to 10C, the pillars 6 are shown in a different pattern from the base 2 to clearly indicate their presence. Note that the cavity 5 in Figures 10A to 10C has the same structure as the cavity 105 shown in Figures 7A to 7C. That is, the base of the four corner pillars 6 is in the shape of a right-angled isosceles triangle. The length of two equal sides (equal sides) on the base of this pillar 6 is s. The height of the pillar 6 is d. The four corner conductive pillars 6 are in electrical contact with the base 2. The four conductive pillars 6 shown in Figures 10A to 10C may be separate from the base 2. Alternatively, the pillars 6 shown in Figures 10A to 10C may be made of the same material as the base 2. That is, the base 2 and the pillars 6 may be integrated. When the chip 7 is mounted on the sample holder 1 with bonding wires 13, the upper bottom surfaces of the four corner pillars 6 contact the back surface of the chip 7.

[0043] Here, we will explain the effects of using column 6. Without column 6, there is a concern that the chip 7 may fall into the cavity 5. The chip 7 and PCB 3 are connected by bonding wires. Therefore, even without column 6, there is a possibility that the chip 7 may not fall into the cavity 5, but there is a risk that the chip 7 may fall into the cavity 5 due to vibration or if some of the bonding wires come loose. Therefore, by providing metal column 6, it is possible to prevent the chip 7 from falling into the cavity 5 and to prevent the bonding wires from coming loose. In addition, the metal column 6 can strengthen the thermal path between the chip 7 and the base 2. The chip 7 of the superconducting quantum circuit is cooled to about 10 [mK] (millikelvin) in a refrigerator and operated, but generally, the base 2 is in thermal contact with the cold stage (the coldest part) of the refrigerator. That is, the temperature of the base 2 becomes very low. The stronger the thermal path between the base 2 and the chip 7, in other words, the smaller the thermal resistance between the base 2 and the chip 7, the better the chip 7 cools. If chip 7 is not cooled properly, the quantum circuit formed on chip 7 cannot be brought out to its full potential. Therefore, it is desirable to cool chip 7 to the lowest possible temperature. For this reason, it is preferable that the thermal resistance between the base 2 and chip 7 be as small as possible. The metal pillar 6 can reduce the thermal resistance between the base 2 and chip 7.

[0044] For example, a structure in which no cavity 5 is formed in the base 2 can be considered in order to best enhance the heat path between the chip 7 and the base 2. However, if no cavity 5 is formed in the base 2, there is a problem with chip mode. Therefore, when a cavity 5 is formed in the base 2 to resolve the chip mode problem, a part of the upper surface of the column 6 is made parallel to the back surface of the chip 7. That is, at least a part of the part of the support structure that supports the chip 7 is parallel to the back surface of the chip 7. This makes it possible to reduce thermal resistance.

[0045] Figure 11A is a top view of the PCB3 used in the sample holder 1 of the first embodiment. Figure 11B is a bottom view of the PCB3 used in the sample holder 1 of the first embodiment. Figure 11C is a side view of the PCB3 used in the sample holder 1 of the first embodiment. Figure 11D is a perspective view of the PCB3 used in the sample holder 1 of the first embodiment. Figure 11E is an enlarged view of the area near the through hole 4 of the PCB3 used in the sample holder 1 of the first embodiment.

[0046] As shown in Figures 11A and 11E, PCB3 has a dielectric 8 in the shape of a plate, for example, extending parallel to the xy plane. PCB3 has a structure in which a surface GND 9 and a core wire 10 of a coplanar waveguide are formed on one surface (front) of the dielectric 8. PCB3 has a structure in which a back surface GND 11 is formed on the other surface (back) of the dielectric 8. The core wire 10, surface GND 9, and back surface GND 11 are conductors, such as metals. Examples of such metals include Cu (copper) and Cu with Au plating (gold plating). In Figure 11A, eight coplanar waveguides are formed on PCB3. The coplanar waveguides are as described in Figure 2A. However, the number of coplanar waveguides formed on PCB3 is not particularly limited and may be any number. As shown in Figure 11D, a plurality of through holes 12 are provided on PCB3. These through-holes 12 penetrate the dielectric 8 and electrically connect the surface GND 9 and the back GND 11. The through-holes 12 are fabricated, for example, by forming holes that penetrate the dielectric 8, the surface GND 9, and the back GND 11, and then plating the inside of the holes with metal.

[0047] In Figure 9, the GND11 on the back of PCB3 is in contact with the base 2. Therefore, the metal base 2, the GND11 on the back of PCB3, the through-hole 12 of PCB3, and the GND9 on the front of PCB3 are electrically connected. A through-hole 4 is also provided near the center of PCB3. This through-hole 4 may have the same shape as the chip 7 of the superconducting quantum circuit mounted on the sample holder 1, for example, i.e., it may be rectangular or square. Also, the area of ​​the through-hole 4 is larger than the area of ​​the chip 7 so that the chip 7 fits inside the through-hole 4.

[0048] Furthermore, the PCB 3 used in the sample holder 1 of the first embodiment has a conductor on the end face of the through-hole 4 that conducts to the surface GND 9 and the back surface GND 11. In Figure 11E, this conductor is a conductive material 14. More specifically, a feature of the PCB 3 used in the sample holder 1 of the first embodiment is that, as shown in Figure 11E, the surface GND 9 and the back surface GND 11 of the PCB 3 are electrically connected by forming a conductive material 14 on the end face of the through-hole 4 of the PCB 3. That is, the conductive material 14 is not formed on the end face of the PCB 3 near the core wire 10 of the PCB 3. Therefore, the conductive material 14 is provided on the end face of the through-hole 4, excluding the end face of the PCB 3 near the core wire 10. This prevents the core wire 10 of the PCB 3 from making electrical contact with each of the GNDs of the PCB 3. The conductive material 14 formed on the end face of the through-hole 4 is, for example, a metal. More specifically, the conductive material 14 is Cu or Au-plated Cu. Furthermore, the conductor 14 may be a material that becomes a superconductor in an extremely low-temperature environment of about 10 mK (millikelvin) where the superconducting quantum circuit operates, such as lead (Pb).

[0049] Figure 12 shows the simulation results of S11 for a system in which the chip 7 is mounted on the sample holder 1 of the first embodiment shown in Figure 9 using bonding wires 13. Here, S11 is the reflection to Port 1 when a high-frequency signal is input from Port 1 as shown in Figure 11A, as described above. Figure 12 is an explanatory diagram showing the simulation results of S11 when the chip 7 is mounted on the sample holder 1 of the first embodiment using bonding wires 13. In the simulation in Figure 12, a=5[mm], b=5[mm], d=3[mm], and s=1[mm] were set.

[0050] As shown in Figure 12, the lowest resonant frequency of the chip mode is 36.6 GHz. Therefore, as shown in Figure 12, the lowest resonant frequency of the chip mode can be made higher than the simulation result shown in Figure 8, which was simulated using the sample holder 101 shown in Figures 7A to 7C. The reason why the resonant frequency of the chip mode could be made higher by using the sample holder 1 of the first embodiment is thought to be as follows. In the example of the sample holder 101 shown in Figures 7A to 7C, the electric field of the standing wave generated when chip mode resonance occurs does not remain within the silicon substrate of the chip 107, but spreads through the end face of the through hole 104 of the PCB 103 into the interior of the dielectric 108. In contrast, in the case of the sample holder 1 of the first embodiment, by forming a conductor 14 on the end face of the through hole 4 of the PCB 3 and electrically connecting the surface GND 9 and back GND 11 of the PCB 3, it is possible to suppress the electric field of the standing wave generated when chip mode resonance occurs from spreading into the interior of the dielectric 8 of the PCB 3. Therefore, according to the first embodiment, it is considered that the dimensions of the cavity resonator can be substantially reduced.

[0051] In the first embodiment, for example, the chip 7 mounted on the sample holder 1 has a rectangular shape. Let the length of the short side of the chip 7 be v, and the length of the long side of the chip 7 be w. In such a case, in the cavity 5 shown in FIGS. 10A to 10C, it is preferable that a < b, and a is preferably equal to or greater than v, and b is preferably equal to or greater than w. If not, the contact area between the back surface of the chip 7 and the pedestal 2 increases, and the resonance frequency of the chip mode decreases.

[0052] Also, in this case, the shape of the through-hole 4 of the PCB 3 of the first embodiment is not particularly limited, but a rectangular shape is more preferable. As shown in FIGS. 11A and 11B, when the length of the short side of the through-hole 4 of the PCB 3 is x1 and the length of the long side of the through-hole 4 is y1, the chip 7 must enter the inside of the through-hole 4. For this reason, it is necessary that v < x1 and w < y1. Furthermore, the shorter x1 and y1 are, the smaller the substantial dimensions of the cavity resonator can be, and thus the resonance frequency of the chip mode can be increased. Thus, x1 is preferably 1.2v or less, and more preferably 1.1v or less. For the same reason, b is preferably 1.2w or less, and more preferably 1.1w or less.

[0053] On the other hand, when the chip 7 has a square shape and the length of one side of the chip 7 is v, in the cavity 5 shown in FIGS. 10A to 10C, it is preferable that a = b, and a is preferably equal to or greater than v. Also, in this case, the through-hole 4 of the PCB 3 according to the first embodiment is preferably square. When the length of one side of the through-hole 4 of the PCB 3 is x1, since the chip 7 must enter the inside of the through-hole 4, it is necessary that v < x1. Furthermore, since the resonance frequency of the chip mode can be increased as x1 becomes shorter, x1 is preferably 1.2v or less, and more preferably 1.1v or less.

[0054] Furthermore, simulations show that increasing the height d of the cavity 5 increases the resonant frequency of the chip modes, but beyond a certain point, increasing d further does not significantly change the resonant frequency of the chip modes. Therefore, in the first embodiment, if the thickness of the chip 7 mounted on the sample holder 1 is t, the height d of the cavity 5 shown in Figures 10A to 10C is preferably 2t or more, more preferably 3t or more, and even more preferably 5t or more.

[0055] Furthermore, in the first embodiment, the smaller the base area of ​​the four corner pillars 6 shown in Figures 10A to 10C, the less the contact area between the back surface of the chip 7 and the base 2, thereby increasing the resonant frequency of the chip mode. For this reason, if the chip 7 mounted on the sample holder 1 is rectangular and the length of the shorter side of the chip 7 is v, it is preferable that s is 0.5v or less. Furthermore, it is preferable that s is 0.3v or less, and more preferably 0.2v or less. On the other hand, if the chip 7 mounted on the sample holder 1 is square and the length of one side of the chip 7 is v, it is preferable that s is 0.5v or less. Furthermore, it is preferable that s is 0.3v or less, and more preferably 0.2v or less.

[0056] [Modified example of the first embodiment] In the first embodiment, an example was described in which PCB3 has two metal layers. The number of metal layers in PCB3 is not limited to two, but may be three or more. A modification of the first embodiment will describe the case in which PCB3 has three or more metal layers.

[0057] Figure 13A is a top view showing the structure of PCB3 according to a modification of the first embodiment. Figure 13B is a cross-sectional view of PCB3 according to a modification of the first embodiment, cut by a plane parallel to the xy plane so that the core wire formed in the region sandwiched between the surface GND9 and the back surface GND11 is visible. Note that the cross-sectional view shown in Figure 13B is a cross-sectional view of PCB3 cut near the plane parallel to the xy plane including the cutting line P-PP shown in Figure 13C. Figure 13C is an enlarged view of the area around the core wire 10 in the cross-section of PCB3 according to a modification of the first embodiment, cut by a plane parallel to the xz plane including the cutting line D-DD shown in Figure 13A. Figure 13D is a bottom view showing the structure of PCB3 according to a modification of the first embodiment. Figure 13E is a perspective view of PCB3 according to a modification of the first embodiment. Figure 13F is an enlarged view of the area around the through hole 4 of PCB3 according to a modification of the first embodiment. The sample holder 1 of the modification of the first embodiment has a configuration in which PCB3 is placed on a metal base 2, as shown in Figure 9. A cavity 5 with the same shape as that in Figures 10A to 10C is formed in the base 2. As mentioned above, the sample holder 1 of the first embodiment uses the PCB 3 shown in Figures 11A to 11E. The PCB 3 shown in Figures 11A to 11E has two metal layers. Specifically, the PCB 3 shown in Figures 11A to 11E has a total of two metal layers: a metal layer on which the surface GND 9 and core wire 10 are formed, and a metal layer on which the back surface GND 11 is formed. On the other hand, a modified version of the first embodiment uses a PCB 3 having three or more metal layers.

[0058] As shown in Figure 13C, PCB3 has a structure in which, for example, a plate-shaped dielectric 8 extending parallel to the xy-plane has a surface GND 9 formed on one side. PCB3 also has a structure in which a back surface GND 11 is formed on the other side of the dielectric 8. Furthermore, PCB3 has a structure in which a core wire 10 is formed inside the dielectric 8, that is, in the region sandwiched between the surface GND 9 and the back surface GND 11. A transmission line with such a structure is generally called a stripline.

[0059] As shown in Figure 13A, the upper surface of PCB3 has a surface GND9, input / output pads 15, and bonding pads 16. The input / output pads 15 are used to connect the core wires 10 of PCB3 to external measuring instruments, etc., for signal input and output. The bonding pads 16 are used to connect the core wires 10 of PCB3 to the pads of chip 7 with bonding wires 13, etc. The input / output pads 15 and bonding pads 16 formed on the upper surface of PCB3 are electrically connected to the core wires 10 formed in the area between the surface GND9 and the back surface GND11. Note that in the top view of Figure 13A, the core wires 10 are hidden by the surface GND9 and are therefore not visible. On the other hand, Figure 13B shows a cross-sectional view taken near the core wires 10 by a plane parallel to the xy plane. In Figures 13A to 13F, four striplines are formed on PCB3. However, the number of striplines formed on PCB3 is not particularly limited and can be any number. As shown in Figures 13B, 13C, and 13E, the PCB 3 has multiple through-holes 12. These through-holes 12 penetrate the dielectric 8 and electrically connect the surface GND 9 and the back surface GND 11. In addition, a through-hole 4 is provided near the center of the PCB 3. As shown in Figure 13F, a conductor 14 is formed on the end face of the through-hole 4 in the PCB 3, thereby electrically connecting the surface GND 9 and the back surface GND 11 of the PCB 3.

[0060] Even with a PCB 3 having three or more metal layers, as shown in Figure 13F, by forming a conductor 14 on the end face of the through hole 4, the sample holder 1 with the PCB 3 placed on a base 2 similar to that in Figures 10A to 10C will have the same effect as in the first embodiment.

[0061] In the first embodiment and its modifications, the shape of the column 6 was a triangular prism with a right-angled isosceles triangle as its base, but the shape of the column 6 does not have to be a triangular prism. The shape of the column 6 may be, for example, a rectangular prism with a polygonal base, or the base of the column may not be polygonal. Regardless of the shape of the column, the effects described in the first embodiment and its modifications are achieved.

[0062] (Second Embodiment) The second embodiment will be described in detail with reference to the drawings. To the extent that the description of the second embodiment remains clear, any information that overlaps with the previous description will be omitted.

[0063] The sample holder 1 of the second embodiment has a configuration in which the PCB 3 is placed on a base 2, as shown in Figure 9 described in the first embodiment. The base 2 has a cavity 5 with the same shape as the cavity 5 shown in Figures 10A to 10C.

[0064] Figure 14 is an enlarged view of the area near the through-hole 4 of the PCB 3 used in the sample holder 1 of the second embodiment. The difference between the PCB 3 used in the first embodiment and the PCB 3 used in the second embodiment is as follows. In the PCB 3 described in the first embodiment, as shown in Figure 11E, a conductor 14 is formed on the end face of the through-hole 4 of the PCB 3, but the conductor 14 is not formed on the end face of the PCB 3 near the core wire 10 of the PCB 3. This prevents the core wire 10 of the PCB 3 from making electrical contact with the GND of the PCB 3. In contrast, in the PCB 3 of Figure 14 used in the second embodiment, the core wire 10 of the PCB 3 is made slightly shorter than in the first embodiment so that the core wire 10 of the PCB 3 does not come into contact with the end face of the through-hole 4. That is, the core wire 10 of the PCB 3 is formed on the surface of the dielectric with a length that does not come into contact with the end face of the through-hole 4. Then, the PCB 3 has a conductor 14 formed over the entire end face of the through-hole 4 of the PCB 3. This electrically connects the surface GND9 and the back GND11 of PCB3. By using this structure, it is possible to form a conductor 14 over the entire end face of the through hole 4 of PCB3 while preventing electrical contact between the core wire 10 of PCB3 and the GND of PCB3.

[0065] Here, the effects of the second embodiment will be explained. In the first embodiment, there is an effect of suppressing the spread of the standing wave electric field generated when chip mode resonance occurs into the dielectric 8 of PCB3. However, since the conductor 14 was not formed on the end face of PCB3 near the core wire 10 of PCB3, it is conceivable that a portion of the electric field leaks into the dielectric 8 of PCB3 through the portion where the conductor 14 is not formed on the end face of PCB3, that is, the portion where the dielectric 8 on the end face of the through hole 4 of PCB3 is exposed. On the other hand, in the second embodiment, since the conductor 14 is formed on the entire end face of the through hole 4 of PCB3, the spread of the standing wave electric field generated when chip mode resonance occurs into the dielectric 8 of PCB3 can be suppressed even more than in the first embodiment, and the resonant frequency of the chip mode can be made even higher.

[0066] Figure 15 is an explanatory diagram showing the simulation results of S11 when the chip 7 is mounted on the sample holder 1 of the second embodiment using bonding wires 13. As shown in Figure 15, the lowest resonant frequency of the chip mode can be increased to 36.8 [GHz], which is higher than in the first embodiment. Thus, the sample holder 1 of the second embodiment has the effect of being able to raise the resonant frequency of the chip mode more than the sample holder 1 of the first embodiment.

[0067] [Modified version of the second embodiment] The sample holder 1 of the modified second embodiment has a configuration in which the PCB 3 is placed on a metal base 2, as shown in Figure 9. The base 2 has a cavity 5 with the same shape as the example shown in Figures 10A to 10C. In the modified second embodiment, a PCB 3 having three or more metal layers is used. As an example of a PCB 3 having three or more metal layers, an example of the configuration of a PCB 3 having three metal layers is shown in Figure 16.

[0068] Figure 16 is an enlarged view of the area near the through-hole 4 of PCB3 used in the sample holder 1 of the modified version of the second embodiment. The difference between PCB3 described in the modified version of the first embodiment (Figure 13) and PCB3 in Figure 16 described in the modified version of the second embodiment is as follows. In PCB3 described in the modified version of the first embodiment, as shown in Figure 13F, a conductor 14 is formed on the end face of the through-hole 4 of PCB3, but the conductor 14 is not formed on the end face of PCB3 near the bonding pad 16 of PCB3. This prevents the bonding pad 16 and the GND of PCB3 from making electrical contact. In contrast, in PCB3 in Figure 16 used in the modified version of the second embodiment, the tip of the bonding pad 16 is slightly separated from the through-hole so that the bonding pad 16 does not come into contact with the end face of the through-hole 4, and a conductor 14 is formed over the entire end face of the through-hole 4 of PCB3, electrically connecting the surface GND 9 and the back GND 11 of PCB3. This structure prevents the bonding pad 16 from making electrical contact with the GND of the PCB 3, while allowing the conductor 14 to be formed across the entire end face of the through-hole 4 of the PCB 3.

[0069] In the modified version of the first embodiment, there is an effect of suppressing the spread of the standing wave electric field generated when chip mode resonance occurs into the dielectric 8 of PCB 3. However, since the conductor 14 was not formed on the end face of PCB 3 near the bonding pad 16, it is conceivable that some of the electric field may leak into the dielectric 8 of PCB 3 through the portion of the end face of PCB 3 where the conductor 14 is not formed, that is, the portion of the end face of the through hole 4 of PCB 3 where the dielectric 8 is exposed. On the other hand, in the modified version of the second embodiment, since the conductor 14 is formed on the entire end face of the through hole 4 of PCB 3, it is expected that the spread of the standing wave electric field generated when chip mode resonance occurs into the dielectric 8 of PCB 3 can be suppressed even more than in the modified version of the first embodiment, and the resonant frequency of the chip mode can be made even higher.

[0070] As described above, even with a PCB 3 having three or more metal layers, by forming a conductor 14 over the entire end face of the through hole 4 as shown in Figure 16, a sample holder 1 with such a PCB 3 placed on a base 2 similar to that in Figures 10A to 10C will achieve the same effects as in the second embodiment.

[0071] In the second embodiment and its modifications, the shape of the column 6 is a triangular prism with a right-angled isosceles triangle as its base, as described in the first embodiment. However, the shape of the column 6 does not have to be a triangular prism. The shape of the column 6 may be, for example, a rectangular prism with a polygonal base, or the base of the column 6 may not be polygonal. Regardless of the shape of the column 6, the effects described in the second embodiment and its modifications are achieved.

[0072] (Third embodiment) A third embodiment will be described in detail with reference to the drawings. To the extent that the description of the third embodiment remains clear, any content that overlaps with the previous description will be omitted. In the third embodiment, similar to the first embodiment, the sample holder 1 comprises a base 2 and a PCB 3 in contact with the base 2. Furthermore, in the third embodiment, similar to the first two embodiments, the PCB 3 has a through hole 4, and at least a portion of the base 2 below the through hole 4 has a cavity 5. The cavity 5 contains a support structure that supports the surface of the chip 7 and is electrically connected to the base 2. Hereinafter, in the third embodiment, at least a portion of the support structure that supports the chip 7 is not parallel to the back surface of the chip 7.

[0073] Figure 17A is a perspective view of the sample holder 1 according to the third embodiment. Figure 17B is a top view of the sample holder 1 according to the third embodiment. Figure 17C is an end view of the sample holder 1 according to the third embodiment, cut by a plane parallel to the xz plane including the cutting line E-EE shown in Figure 17B. In Figure 17C, a chip 7 is mounted on the sample holder 1.

[0074] The sample holder 1 according to the third embodiment comprises a base 2 and a PCB 3. That is, the sample holder 1 of the third embodiment has a configuration in which the PCB 3 is placed on a metal base 2, as shown in Figure 9. In the third embodiment, the same PCB 3 structure as in the first and second embodiments, as shown in Figure 11, is used. In the third embodiment, a cavity 5 with the structure shown in Figures 17A to 17C is formed in the base 2. The PCB 3 has through holes 4. The cavity 5 is in at least a portion of the base 2 below the through holes 4. As with the first and second embodiments, the shape of the cavity 5 is not particularly limited. For example, the bottom surface of the cavity 5 may be flat or not. The sides of the cavity 5 may be flat or not. For example, there may be indentations on the sides or bottom surface of the cavity 5. In Figures 17A to 17C, the sample holder 1 has a cavity 5 in the base 2, in the portion directly below the through holes 4 of the PCB 3. In other words, as shown in Figures 17A to 17C, the sample holder 1 has a cavity 5 in the base 2, in the portion directly beneath the chip 7 when the chip 7 is mounted on the sample holder 1 with bonding wires 13. As shown in Figures 17A to 17C, the cavity 5 is a rectangular prism with a height d, and a rectangular base with sides of lengths a and b.

[0075] The cavity 5 has a support structure that supports the surface of the chip 7 and is electrically connected to the base 2. Here, the surface of the chip 7 is the back surface of the chip 7 opposite to the circuit surface of the chip 7. As mentioned above, a feature of the third embodiment is that at least a part of the portion of the support structure that supports the chip 7 is not parallel to the back surface of the chip 7. In the third embodiment, as with the first embodiment, the support structure is not particularly limited. Here, the support structure will be explained using the example of a column 6. The explanation will be given using an example in which the columns 6 are arranged at the four corners of the cavity 5. The lower bottom surface of the column 6 at the four corners has the shape of a right-angled isosceles triangle, the length of the two equal sides of this bottom surface is s, and the height of the column 6 is d. The conductive column 6 at the four corners is in electrical contact with the base 2. The four conductive column 6 shown in Figures 17A to 17C may be separate from the base 2. Alternatively, the column 6 may be made of the same material as the base 2, that is, the base 2 and the four column 6 may be integrated.

[0076] As mentioned above, the difference between the structure of the cavity 5 in the first embodiment shown in Figures 10A to 10C and the third embodiment is that, in the third embodiment, at least a portion of the upper surfaces of the four corner pillars 6, that is, the surfaces facing the back surface of the chip 7 when the chip 7 is mounted on the sample holder 1, is not parallel to the back surface of the chip 7. In other words, at least a portion of the upper surfaces of the four corner pillars 6 is not parallel to the upper surface of the base 2. As shown in Figure 17C, the pillars 6 used in the sample holder 1 of the third embodiment have a structure in which the upper part 61 and the lower part 62 are connected. The shapes of the upper part 61 and the lower part 62 are not particularly limited. The lower part 62 is in the shape of a triangular prism, and the base of the lower part 62 is in the shape of a right-angled isosceles triangle, with the lengths of the two equal sides of this base being s, and the height of the lower part 62 being d1. The upper part 61 is in the shape of a triangular pyramid, and the base of the upper part 61 is in the shape of a right-angled isosceles triangle, and the height of the upper part 61 is d2. Here, d1 + d2 = d. Furthermore, for example, the bottom surface of the upper part 61 and the bottom surface of the lower part 62 have the same shape and dimensions. In this structure, when the chip 7 is mounted on the sample holder 1, at least a portion of each of the four corner pillars 6 contacts the back surface of the chip 7. This structure makes it possible to reduce the contact area between the back surface of the chip 7 and the conductive pillars 6 compared to the first embodiment.

[0077] Figure 18 shows the simulation results of S11 when the chip 7 is mounted on the sample holder 1 of the third embodiment using bonding wires 13. Figure 18 is an explanatory diagram showing the simulation results of S11 according to the third embodiment. In the simulation in Figure 18, a=5[mm], b=5[mm], d=3[mm], d1=2[mm], d2=1[mm], and s=1[mm]. As shown in Figure 18, the lowest resonant frequency of the chip mode can be increased to 37.5[GHz], which is higher than in the first embodiment.

[0078] Thus, the sample holder 1 of the third embodiment has the effect of being able to raise the resonant frequency of the chip modes compared to the sample holder 1 of the first embodiment. In the case of the first embodiment described above, the electric field of the standing wave generated when the chip modes resonate mainly spreads within the silicon substrate and into the cavity 5 (vacuum) provided in the base 2. However, in the portion directly above the four corner pillars 6, the space between the GND plane 73 on the surface of the chip 7 and the pillars 6 consists only of silicon, and the electric field cannot spread into the vacuum, so the effective dielectric constant is high in the portion directly above the four corner pillars 6. In contrast, in the case of the third embodiment, by making at least a part of the upper surface of the four corner pillars 6 not parallel to the back surface of the chip 7, the space between the GND plane 73 on the surface of the chip 7 and the pillars 6 in the portion directly above the four corner pillars 6 consists of silicon and vacuum, so the electric field can spread into the vacuum in this portion. For this reason, in the third embodiment, the effective dielectric constant in the portion directly above the four corner pillars 6 is lower than in the first embodiment, so it is thought that the resonant frequency of the chip modes can be raised even higher.

[0079] As another example of the third embodiment, Figures 19A to 19C show a case where the thickness s of the four corner pillars 6 is larger than that shown in Figures 17A to 17C. Figure 19A is a perspective view of the sample holder 1 according to another example of the third embodiment. Figure 19B is a top view of the sample holder 1 according to another example of the third embodiment. Figure 19C is an end view of the sample holder according to another example of the third embodiment, cut by a plane parallel to the xz plane including the cutting line F-FF shown in Figure 19B. In Figure 19C, a chip 7 is mounted on the sample holder 1 according to another example of the third embodiment.

[0080] Figure 20 shows the simulation results of S11 when a chip 7 is mounted on a sample holder 1 using a base 2 with a cavity 5 formed in Figures 19A to 19C, with bonding wires 13.

[0081] Figure 20 is an explanatory diagram showing the simulation results of S11 according to another example of the third embodiment. In the simulation, a=5[mm], b=5[mm], d=3[mm], d1=0.5[mm], d2=2.5[mm], and s=2.5[mm] were set. As shown in Figure 20, the lowest resonant frequency of the chip mode can be further increased to 38.1[GHz]. Thus, in the third embodiment, the resonant frequency can be further increased by changing the thickness s of the four corner pillars 6, the height d1 of the lower part 62 and the height d2 of the upper part 61 of the pillars 6, the height d of the cavity 5, the thickness t of the chip 7, etc.

[0082] [Modified version of the third embodiment] In a modified version of the third embodiment, the upper surfaces of the upper parts 61 of the pillars 6 at the four corners of the cavity 5, that is, the surfaces facing the back surface of the chip 7 when the chip 7 is mounted on the sample holder 1, are not parallel to the back surface of the chip 7, but a portion of them are parallel to the back surface of the chip 7.

[0083] Figure 21A is a perspective view of a modified sample holder 1 according to the third embodiment. Figure 21B is a top view of the modified sample holder 1 according to the third embodiment. Figure 21C is an end view of the modified sample holder 1 according to the third embodiment, cut by a plane parallel to the xz plane containing the cutting line G-GG shown in Figure 21B. In Figure 21C, a chip 7 is mounted on the modified sample holder 1 according to the third embodiment. In Figures 21A, 21B, and 21C, the upper surfaces of the upper parts 61 of the four corner pillars 6 of the cavity 5, that is, when the chip 7 is mounted on the sample holder 1, a portion of the surface of the base 2 forming the cavity 5 that faces the back surface of the chip 7 is not parallel to the back surface of the chip 7, but a portion is parallel to the back surface of the chip 7. In other words, at least a portion of the upper surfaces of the upper parts 61 of the four corner pillars 6 is not parallel to the upper surface of the base 2, but a portion is parallel to the upper surface of the base 2. The lower part 62 of column 6 has the shape of a triangular prism, as in Figures 17A, 17B, 17C and Figures 19A, 19B, 19C, and the base of the lower part 62 is a right-angled isosceles triangle with two equal sides of length s1.

[0084] On the other hand, the upper part 61 of the column 6 is shaped like a truncated triangular pyramid, and the lower base of the upper part 61 is a right-angled isosceles triangle with two equal sides of length s1, while the upper base of the upper part 61 is also a right-angled isosceles triangle with two equal sides of length s2, where s1 > s2. The height of the lower part 62 of the column 6 is d1, and the height of the upper part 61 is d2. In this structure, when the chip 7 is mounted on the sample holder 1, at least a portion of each of the four corner columns 6 will contact the back surface of the chip 7. This structure allows the contact area between the back surface of the chip 7 and the conductive column 6 to be reduced compared to the first embodiment. However, the contact area between the back surface of the chip 7 and the conductive column 6 is larger than in the cases of Figures 17A to 17C and Figures 19A to 19C.

[0085] FIG. 22 is an explanatory diagram showing the simulation result of S11 when the chip 7 is mounted on the sample holder 1 using the pedestal 2 with the cavity 5 shown in FIGS. 21A to 21C by the bonding wire 13. In the simulation in FIG. 22, a = 5 [mm], b = 5 [mm], d = 3 [mm], d1 = 2 [mm], d2 = 1 [mm], s1 = 1 [mm], and s2 = 0.5 [mm]. As shown in FIG. 22, the lowest resonance frequency of the chip mode is 37.5 [GHz]. This is almost equal to the resonance frequency in the simulation results in the case of FIGS. 17A to 17C described in the third embodiment. Thus, in the third embodiment, even if a part of the upper surface of the upper part 61 of the four-corner columns 6 is parallel to the back surface of the chip 7, the effect that the resonance frequency of the chip mode can be made higher can be obtained.

[0086] In the third embodiment and its modification, for example, the chip 7 mounted on the sample holder 1 has a rectangular shape, and the length of the short side of the chip 7 is v, and the length of the long side of the chip 7 is w. In such a case, in the cavities 5 shown in FIGS. 17A to 17C, the cavities 5 shown in FIGS. 19A to 19C, and the cavities 5 shown in FIGS. 21A to 21C, it is preferable that a < b, and it is preferable that a is not less than v and b is not less than w. If not, the contact area between the back surface of the chip 7 and the pedestal 2 will increase, and the resonance frequency of the chip mode may decrease. Also, in this case, the through-hole 4 of the PCB 3 used in the third embodiment and its modification is preferably rectangular. When the length of the short side of the through-hole 4 of the PCB 3 is x1 and the length of the long side of the through-hole 4 is y1, since the chip 7 must enter the inside of the through-hole 4, it is necessary that v < x1 and w < y1. And since the resonance frequency of the chip mode can be increased as x1 and y1 are shorter, it is preferable that x1 is not more than 1.2v, and more preferably not more than 1.1v. For the same reason, it is preferable that b is not more than 1.2w, and more preferably not more than 1.1w.

[0087] On the one hand, when the chip 7 mounted on the sample holder 1 has a square shape and the length of one side of the chip 7 is v, it is preferable that a = b in the cavities 5 of FIGS. 17A to 17C, FIGS. 19A to 19C, and FIGS. 21A to 21C, and it is preferable that a is not less than v. Also, in this case, the through-hole 4 of the PCB 3 used in the third embodiment and its modifications is preferably square. When the length of one side of the through-hole 4 of the PCB 3 is x1, since the chip 7 must fit inside the through-hole 4, it is necessary that v < x1. And since the resonance frequency of the chip mode can be increased as x1 becomes shorter, it is preferable that x1 is not more than 1.2v, and more preferably not more than 1.1v.

[0088] Also, in the third embodiment and its modifications, when the thickness of the chip 7 mounted on the sample holder 1 is t, the height d of the cavities 5 of FIGS. 17A to 17C, FIGS. 19A to 19C, and FIGS. 21A to 21C is preferably not less than 2t, more preferably not less than 3t, and still more preferably not less than 5t.

[0089] Also, in the third embodiment, when the chip 7 mounted on the sample holder 1 is rectangular and the length of the short side of the chip 7 is v, it is preferable that s is not less than 0.1v and not more than 0.5v. Also, when the chip 7 mounted on the sample holder 1 is square and the length of one side of the chip 7 is v, it is preferable that s is not less than 0.1v and not more than 0.5v. Similarly, in the modification of the third embodiment, when the chip 7 mounted on the sample holder 1 is rectangular and the length of the short side of the chip 7 is v, it is preferable that s1 is not less than 0.1v and not more than 0.5v. Also, when the chip 7 mounted on the sample holder 1 is square and the length of one side of the chip 7 is v, it is preferable that s1 is not less than 0.1v and not more than 0.5v. Note that in the modification of the third embodiment, s2 only needs to satisfy s2 < s1.

[0090] Furthermore, in the third embodiment and its modified form, if d2 is greater than 0, it has the effect of increasing the chip mode. Therefore, it is preferable that d2 is greater than 0 and less than or equal to d. Note that if d2=d, then d1=0, and in that case, the column 6 is composed only of the upper part 61.

[0091] In the third embodiment and its modified versions, the PCB3 of the first embodiment (Figures 11A to 11E) was used. Similar effects can be obtained by using a sample holder 1 on a base 2 with a cavity 5 formed as shown in Figures 17A to 17C, 19A to 19C, and 21A to 21C, on which a modified version of the PCB3 of the first embodiment (Figures 13A to 13F), the PCB3 of the second embodiment (Figure 14), or a modified version of the PCB3 of the second embodiment (Figure 16) is placed.

[0092] In the third embodiment and its modifications, the shape of the lower part 62 of the column 6 is a triangular prism with a right-angled isosceles triangle as its base, and the shape of the upper part 61 is a triangular pyramid. However, the shapes of the lower part 62 and upper part 61 of the column 6 are not particularly limited. The effects described in the third embodiment and its modifications are achieved as long as at least a portion of the upper surface of the upper part 61, that is, the surface of the upper part 61 facing the back surface of the chip 7, is not parallel to the back surface of the chip 7 or the upper surface of the base 2.

[0093] (Fourth embodiment) The fourth embodiment will be described in detail with reference to the drawings. To the extent that the description of the fourth embodiment remains clear, any information that overlaps with the previous descriptions will be omitted.

[0094] The sample holder 1 of the fourth embodiment has a configuration in which a PCB 3 is placed on a metal base 2, as shown in Figure 9. In the fourth embodiment, the same PCB 3 shown in Figures 11A to 11E is used as in the first embodiment. In the fourth embodiment, the sample holder 1 has a cavity 5 in the base 2, in the part directly below the through hole 4 of the PCB 3. In other words, the sample holder 1 has a cavity 5 in the base 2, in the part directly below the chip 7 when a chip 7 is mounted on the sample holder 1. In the fourth embodiment, the cavity 5 has a shape that combines a column and a frustum, and the narrower base of the frustum and the upper base of the column have the same shape. For example, the wider base of the frustum is on the side of the through hole 4. As an example of a frustum of the cavity 5, a truncated pyramid will be used as an example. As an example of a column of the cavity 5, a rectangular prism will be used as an example.

[0095] A sample holder 1 according to the fourth embodiment is shown in Figures 23A to 23C. Figure 23A is a perspective view of the sample holder 1 according to the fourth embodiment. Figure 23B is a top view of the sample holder 1 according to the fourth embodiment. Figure 23C is an end view of the sample holder 1 according to the fourth embodiment, cut by a plane parallel to the xz plane containing the cutting line H-HH shown in Figure 23B. In Figure 23C, a chip 7 is mounted on the sample holder 1 according to the fourth embodiment with bonding wire 13.

[0096] As shown in Figures 23B and 23C, in the fourth embodiment, the cavity 5 formed in the base 2 has a structure connecting a prism portion 51, which is a rectangular prism, and a truncated pyramidal portion 52, which is a truncated pyramidal pyramid. In Figures 23B and 23C, the bottom surface of the prism portion 51 and the smaller bottom surface of the truncated pyramidal portion 52 are connected. Therefore, the bottom surface of the prism portion 51 and the smaller bottom surface of the truncated pyramidal portion 52 have the same shape and the same area.

[0097] In Figures 23A to 23C, the prism portion 51 is a rectangular prism with a base that is the length of a1 and b1 sides and a height of d1. In Figures 23A to 23C, the truncated pyramidal portion 52 is a truncated pyramidal pyramid.

[0098] Here, the lengths of the sides of the chip 7 and the prism portion 51 when the chip 7 mounted on the sample holder 1 has a rectangular shape will be described. When the length of the short side of the chip 7 is v and the length of the long side of the chip 7 is w, it is preferable that a1 < b1 in the prism portion 51, and it is preferable that a1 is smaller than v and b1 is smaller than w.

[0099] On the other hand, when the chip 7 mounted on the sample holder 1 has a square shape and the length of one side of the chip 7 is v, it is preferable that a1 = b1 in the prism portion 51, and it is preferable that a1 is smaller than v.

[0100] In FIGS. 23A to 23C, the frustum pyramid portion 52 has a shape of a quadrilateral with the smaller bottom area of the two bottom surfaces having side lengths a1 and b1. In FIGS. 23A to 23C, the frustum pyramid portion 52 has a shape of a quadrilateral with the larger bottom area having side lengths a2 and b2.

[0101] Here, for example, assume that the chip 7 mounted on the sample holder 1 has a rectangular shape, the length of the short side of the chip 7 is v, and the length of the long side of the chip 7 is w. In such a case, it is preferable that a2 < b2 in the frustum pyramid portion 52, and it is preferable that a2 is not less than v and not more than 1.5v, and b2 is not less than w and not more than 1.5w.

[0102] On the other hand, when the chip 7 mounted on the sample holder 1 has a square shape and the length of one side of the chip 7 is v, it is preferable that a2 = b2 in the frustum pyramid portion 52, and it is preferable that a2 is not less than v and not more than 1.5v. Also, the height of the frustum pyramid portion 52 is d2. The cavity 5 formed in the pedestal 2 of the sample holder 1 of the present embodiment has a structure in which the frustum pyramid portion 52 is connected on the prism portion 51, and the upper bottom surface of the prism portion 51 and the lower bottom surface of the frustum pyramid portion 52 are the same plane. Here, the lower bottom surface of the frustum pyramid portion 52 is the smaller bottom surface of the two bottom surfaces of the frustum pyramid portion 52.

[0103] A feature of the sample holder 1 in the fourth embodiment is that a frustum-shaped pyramidal portion 52 is provided on the upper side of the cavity 5, so that at least a portion of the surface of the base 2 facing the back surface of the chip 7 when the chip 7 is mounted on the sample holder 1 is not parallel to the back surface of the chip 7. In Figures 23A to 23C, this portion is the side surface of the frustum-shaped pyramidal portion 52. As shown in Figure 23C, let θ be the angle between the side surface of the frustum-shaped pyramidal portion 52, that is, the portion of the surface that is not parallel to the back surface of the chip 7 when the chip 7 is mounted on the sample holder 1, and the back surface of the chip 7. In other words, let θ be the angle between the side surface of the frustum-shaped pyramidal portion 52 and the upper surface of the base 2. θ is the range in which a portion of the side surface of the frustum-shaped pyramidal portion 52 is not parallel to the back surface of the chip 7. For example, θ is less than 90 degrees. In the structure of the sample holder 1 of the fourth embodiment, when a chip 7 is mounted on the sample holder 1, at least a portion of the base 2 contacts the back surface of the chip 7. This structure allows the contact area between the back surface of the chip 7 and the base 2 to be reduced compared to the first embodiment.

[0104] Figure 24 is an explanatory diagram showing the simulation results of S11 when the chip 7 is mounted on the sample holder 1 according to the fourth embodiment using bonding wires 13. In the simulation in Figure 24, a1=4[mm], b1=4[mm], d1=2.5[mm], a2=5[mm], b2=5[mm], and d2=0.5[mm]. In this case, θ is 45 degrees. As shown in Figure 24, the lowest resonant frequency of the chip mode can be increased to 38.6[GHz], which is higher than in the first embodiment.

[0105] Thus, the sample holder 1 of the fourth embodiment has the effect of being able to raise the resonant frequency of the chip modes compared to the sample holder 1 of the first embodiment. The reason why the resonant frequency of the chip modes could be raised in the fourth embodiment compared to the first embodiment will be explained. In the case of the first embodiment, the electric field of the standing wave generated when the chip mode resonance occurs spreads mainly within the silicon substrate and into the cavity 5 (vacuum) provided in the base 2. However, in the case of the first embodiment, in the parts directly above the pillars 6 at the four corners, in other words, at the four corners of the chip 7, the space between the GND plane 73 on the surface of the chip 7 and the pillars 6 is only silicon, and the electric field cannot spread into the vacuum. For this reason, in the case of the first embodiment, the effective dielectric constant is high at these four corners of the chip 7. In contrast, in the case of the fourth embodiment, by providing a frustum-shaped pyramidal section 52 in the cavity 5, even at the four corners of the chip 7, the space between the GND plane 73 on the surface of the chip 7 and the base 2 becomes silicon and vacuum, so the electric field can spread into the vacuum in this part as well. Therefore, in the fourth embodiment, the effective dielectric constant at the four corners of the chip 7 is lower than in the first embodiment, which is thought to allow for a higher resonant frequency of the chip modes.

[0106] [Modified version of the fourth embodiment] As a modification of the fourth embodiment, Figures 25A to 25C show a sample holder 1 in which the prism portion 51 of the cavity 5 is eliminated, leaving only the truncated pyramidal portion 52. Figure 25A is a perspective view of the sample holder 1 according to the modification of the fourth embodiment. Figure 25B is a top view of the sample holder 1 according to the modification of the fourth embodiment. Figure 25C is an end view of the sample holder 1 according to the modification of the fourth embodiment, cut by a plane parallel to the xz plane including the cutting line I-II shown in Figure 25B. In Figure 25C, the chip 7 according to the modification of the fourth embodiment is mounted with bonding wire 13. As shown in Figures 25A to 25C, the cavity 5 does not have a prism portion 51, but has a truncated pyramidal portion 52. In Figures 25A to 25C, the truncated pyramidal portion 52 is a square truncated pyramid. Also, θ is the range in which the side surface of the truncated pyramidal portion 52 is not parallel to the back surface of the chip 7. For example, if the frustum of the pyramid 52 is a frustum of a square pyramid, then θ is less than 90 degrees.

[0107] Figure 26 is an explanatory diagram showing the simulation results of S11 when a chip 7 is mounted with bonding wire 13 on a sample holder 1 using a base 2 with a cavity 5 formed therein as shown in Figures 25A to 25C. In the simulation in Figure 26, a1=2[mm], b1=2[mm], a2=5[mm], b2=5[mm], d1=0[mm], and d2=5[mm] were set. In this case, θ is approximately 73.3 degrees. As shown in Figure 26, the lowest resonant frequency of the chip mode can be further increased to 39.0[GHz]. Thus, in the fourth embodiment, the resonant frequency can be further increased by changing the dimensions a1, b1, d1, a2, b2, d2 of the prismatic portion 51 and the frustum portion 52 of the cavity 5, as well as the thickness t of the chip 7.

[0108] In the fourth embodiment and its modified form, if the thickness of the chip 7 mounted on the sample holder 1 is t, the height d1+d2 of the cavity 5 in Figures 23A to 23C and 25A to 25C is preferably 2t or more, more preferably 3t or more, and even more preferably 5t or more.

[0109] Furthermore, in the fourth embodiment and its modified form, if d2 is greater than 0, it has the effect of increasing the chip mode. Therefore, it is preferable that d2 is greater than 0. On the other hand, since d1 may be 0, it is preferable that d2 is 0 or greater. Note that when d1=0, the cavity 5 is composed only of the truncated pyramidal portion 52.

[0110] In the fourth embodiment and its modified versions, the PCB3 of the first embodiment (Figures 11A to 11E) was used. Similar effects can be obtained by using a sample holder 1 on a base 2 with a cavity 5 formed as shown in Figures 23A to 23C and Figures 25A to 25C, on which a modified version of the PCB3 of the first embodiment (Figures 13A to 13F), the PCB3 of the second embodiment (Figure 14), or a modified version of the PCB3 of the second embodiment (Figure 16) is placed.

[0111] In the fourth embodiment and its modified form, the cavity 5 is a structure in which a prism portion 51 and a frustum portion 52 are connected, or a structure consisting only of the frustum portion 52. However, the frustum portion 52 does not have to be in the shape of a frustum. For example, the side surface of the frustum portion 52 may be curved instead of flat. In other words, as long as at least a part of the surface of the base 2 that forms the cavity 5, the surface facing the back surface of the tip 7 is not parallel to the back surface of the tip 7 or the upper surface of the base 2, the effects described in the fourth embodiment and its modified form will be achieved. Also, a pyramidal shape may be used instead of the frustum shape of the frustum portion 52. Therefore, the cavity 5 may be a structure in which a prism portion 51 and a pyramidal portion are connected, or a structure consisting only of the pyramidal portion.

[0112] (Fifth embodiment) The fifth embodiment will be described in detail with reference to the drawings. To the extent that the description of the fifth embodiment remains clear, any information that overlaps with the previous descriptions will be omitted.

[0113] The sample holder 1 of the fifth embodiment has a configuration in which a PCB 3 is placed on a metal pedestal 2 as shown in FIG. 9. In the fifth embodiment, the PCB 3 having the structure shown in FIGS. 11A to 11E, which is the same as that of the first embodiment, is used. And in the fifth embodiment, the sample holder 1 has a cavity 5 in a portion of the pedestal 2 that corresponds directly below the through-hole 4 of the PCB 3, that is, in a portion that corresponds directly below the chip 7 when the chip 7 is mounted on the sample holder 1. The cavity 5 has a shape that combines a prism and a frustum of a pyramid, similar to the fourth embodiment, and is a shape in which the smaller bottom surface of the frustum of the pyramid and the upper bottom surface of the prism are connected. Furthermore, in the fifth embodiment, unlike the fourth embodiment, the frustum of the pyramid may be deformed. Thereby, in the fifth embodiment, when the chip 7 is mounted on the sample holder 1, at least a part of the surface of the pedestal 2 that forms the cavity 5 and faces the back surface of the chip 7 is not parallel to the back surface of the chip 7.

[0114] FIG. 27A is a perspective view of the sample holder 1 of the fifth embodiment. FIG. 27B is a top view of the sample holder 1 of the fifth embodiment. FIG. 27C is a cross-sectional view of the sample holder of the fifth embodiment cut along a plane parallel to the xz plane including the cutting line J-JJ shown in FIG. 27B. In FIG. 27C, the chip 7 is mounted on the sample holder 1 according to the fifth embodiment with bonding wires 13. As shown in FIGS. 27A to 27C, the cavity 5 formed in the pedestal 2 in the fifth embodiment has a structure connecting a prism portion 51 and a frustum of a pyramid deformed portion 53.

[0115] The prism portion 51 has a bottom surface in the shape of a quadrilateral with side lengths a1 and b1, and has the shape of a quadrangular prism with a height of d1.

[0116] Here, for example, the chip 7 mounted on the sample holder 1 has a rectangular shape, and let the length of the short side of the chip 7 be v and the length of the long side of the chip 7 be w. In such a case, it is preferable that a1 < b1 in the prism portion 51, and it is preferable that a1 is smaller than v and b1 is smaller than w.

[0117] On the one hand, when the chip 7 mounted on the sample holder 1 has a square shape and the length of one side of the chip 7 is v, it is preferable that a1 = b1 in the prism portion 51, and it is preferable that a1 is smaller than v.

[0118] The frustum pyramid-shaped deformation portion 53 has a shape of a quadrilateral with the lengths of each side being a1 and b1 for the smaller-bottom surface of the two bottom surfaces, and a shape of an octagon with the corners of the quadrilateral with the lengths of each side being a2 and b2 for the larger-bottom surface being cut diagonally.

[0119] Here, for example, when the chip 7 mounted on the sample holder 1 has a rectangular shape, let the length of the short side of the chip 7 be v and the length of the long side of the chip 7 be w. In such a case, it is preferable that a2 < b2 in the frustum pyramid-shaped deformation portion 53, and it is preferable that a2 is not less than v and not more than 1.5v, and b2 is not less than w and not more than 1.5w.

[0120] On the one hand, when the chip 7 mounted on the sample holder 1 has a square shape and the length of one side of the chip 7 is v, it is preferable that a2 = b2 in the frustum pyramid-shaped deformation portion 53, and it is preferable that a2 is not less than v and not more than 1.5v.

[0121] Also, the height of the frustum pyramid-shaped deformation portion 53 is d2. The cavity 5 formed in the pedestal 2 of the sample holder 1 of the present embodiment has a structure in which the frustum pyramid-shaped deformation portion 53 is connected on the prism portion 51, and the upper bottom surface of the prism portion 51 and the lower bottom surface of the frustum pyramid-shaped deformation portion 53 are the same plane. Here, the lower bottom surface of the frustum pyramid-shaped deformation portion 53 is the smaller-bottom surface of the two bottom surfaces of the frustum pyramid-shaped deformation portion 53. In order to accurately describe the shape of the cavity 5 in FIGS. 27A to 27C of the fifth embodiment, FIGS. 28A to 28C and FIGS. 29A to 29C are used for explanation.

[0122] Figure 28A is a perspective view showing example 1 of the shape of the cavity 5 in the sample holder 1 of the fifth embodiment. Figure 28B is a top view showing example 1 of the shape of the cavity 5 in the sample holder 1 of the fifth embodiment. Figure 28C is an end view of example 1 of the shape of the cavity 5 in the sample holder 1 of the fifth embodiment, where the area around the cavity 5 of the sample holder 1 is cut by a plane parallel to the xz plane containing the cutting line K-KK shown in Figure 28B. In Figure 28C, a chip 7 is mounted on the sample holder 1 according to the fifth embodiment with bonding wire 13.

[0123] Figure 29A is a perspective view showing example 2 of the shape of the cavity 5 in the sample holder 1 of the fifth embodiment. Figure 29B is a top view showing example 2 of the shape of the cavity 5 in the sample holder 1 of the fifth embodiment. Figure 29C is a cross-sectional view of the sample holder 1 in example 2 of the shape of the cavity in the sample holder of the fifth embodiment, cut by a plane parallel to the xz plane including the cutting line L-LL shown in Figure 29B. In the cross-sectional view shown in Figure 29C, there are no columns 6 on the cut surface, but a pattern has been added to the columns 6 to make them visible. In Figure 29C, a chip 7 is mounted on the sample holder 1 according to the fifth embodiment with bonding wire 13.

[0124] The cavity 5 shown in Figures 28A to 28C has the same structure as the cavity 5 shown in Figures 23A to 23C of the fourth embodiment. That is, the cavity 5 is configured by connecting a prism portion 51 and a truncated pyramidal portion 52. In the fifth embodiment, four conductive pillars 6 shown in Figures 29A to 29C are added to the four corners of the cavity 5 shown in Figures 28A to 28C, which is similar to that of the fourth embodiment. This allows a cavity 5 with the structure shown in Figures 27A to 27C to be formed in the base 2. As shown in Figures 29A to 29C, in this embodiment the conductive pillars 6 at the four corners are triangular prisms, and the base of the triangular prism is in the shape of a right-angled isosceles triangle, with the lengths of the two equal sides of this base being s, and the height of the triangular prism being d1 + d2. The conductive pillars 6 at the four corners are in electrical contact with the base 2. The four conductive pillars 6 shown in Figures 29A to 29C may be separate from the base 2, or they may be made of the same material as the base 2; in other words, the base 2 and the four pillars 6 may be integrated into a single unit.

[0125] A feature of the sample holder 1 in the fifth embodiment is that a frustum pyramidal deformation section 53 is provided on the upper side of the cavity 5, so that when a chip 7 is mounted on the sample holder 1, at least a portion of the surface facing the back surface of the chip 7 is not parallel to the back surface of the chip 7. As shown in Figure 27C, let θ be the angle between the side surface of the frustum pyramidal deformation section 53, that is, the portion of the surface facing the back surface of the chip 7 when the chip 7 is mounted on the sample holder 1 that is not parallel to the back surface of the chip 7, and the back surface of the chip 7. In other words, θ is the angle between the side surface of the frustum pyramidal deformation section 53 and the upper surface of the base 2. θ is the range in which the side surface of the frustum pyramidal deformation section 53 is not parallel to the back surface of the chip 7. For example, if the frustum pyramidal deformation section 53 is created based on a frustum pyramidal section 52 which is a square frustum, then θ is less than 90 degrees. In the structure of the sample holder 1 of the fifth embodiment, when the chip 7 is mounted on the sample holder 1, at least a portion of the base 2 comes into contact with the back surface of the chip 7.

[0126] Figure 30 shows the simulation results of S11 when a chip 7 is mounted on a sample holder 1 using a base 2 with a cavity 5 formed in Figures 27A to 27C, with bonding wire 13. Figure 30 is an explanatory diagram showing the simulation results of S11 for a system in which a chip 7 is mounted on a sample holder 1 with bonding wire 13 according to the fifth embodiment. In the simulation in Figure 30, a1=3[mm], b1=3[mm], a2=5[mm], b2=5[mm], d1=1[mm], d2=2[mm], and s=1[mm] were set. In this case, θ is approximately 63.4 degrees.

[0127] As shown in Figure 30, the lowest resonant frequency of the chip mode can be increased to 37.4 GHz, which is higher than in the first embodiment.

[0128] Thus, the sample holder 1 of the fifth embodiment has the effect of being able to raise the resonant frequency of the chip mode compared to the sample holder 1 of the first embodiment. In the sample holder 1 of the fifth embodiment shown in Figures 27A to 27C, the upper surfaces of the four corner pillars 6 are in contact with the back surface of the chip 7. In the simulation shown in Figure 30, s=1[mm] was set, and in this case, the contact area between the upper surfaces of the four corner pillars 6 and the back surface of the chip 7 in the sample holder 1 of this embodiment is the same as when analyzed in the simulation of Figure 12 of the first embodiment. Note that in the simulation of Figure 12, the resonant frequency of the chip mode in Figure 12 for the first embodiment with s=1[mm] is 36.6[GHz], and in Figure 30 for the fifth embodiment, the resonant frequency of the chip mode is 37.4[GHz]. Therefore, the resonant frequency of the chip mode is higher in the fifth embodiment than in the first embodiment. The reason why the fifth embodiment can raise the resonant frequency of the chip mode than in the first embodiment is thought to be the following reason. In the fifth embodiment, the dimensions of the cavity 5 are smaller than those of the cavity 5 in the first embodiment (a and b), which is thought to be why the resonant frequency of the cavity 5 itself is higher than in the first embodiment. Specifically, in the fifth embodiment, the dimensions of the cavity 5 directly below the chip 7 decrease as you go down, and at the very bottom of the cavity 5, the dimensions of the cavity 5 (a1 and b1) are smaller than those of the first embodiment (a and b). This structure is thought to result in a higher resonant frequency of the cavity 5 itself in the fifth embodiment than in the first embodiment. As a result, even if the contact area between the back surface of the chip 7 and the column 6 is the same, the fifth embodiment is thought to have the effect of being able to achieve a higher resonant frequency of the chip mode than the first embodiment.

[0129] [Modified version of the fifth embodiment] As a modification of the fifth embodiment, Figures 31A to 31C show a sample holder in which the prism portion 51 of the cavity 5 is removed, leaving only the truncated pyramidal portion 53. Figure 31A is a perspective view of the sample holder 1 of the modification of the fifth embodiment. Figure 31B is a top view of the sample holder 1 of the modification of the fifth embodiment. Figure 31C is a cross-sectional view of the sample holder of the modification of the fifth embodiment, cut by a plane parallel to the xz plane including the cutting line M-MM shown in Figure 31B. In Figure 31C, a chip 7 is mounted on the sample holder 1 according to the fifth embodiment with bonding wire 13. Furthermore, in order to explain in more detail the shape of the cavity 5 shown in Figures 31A, 31B, and 31C of the modification of the fifth embodiment, we will use Figures 32A to 32C and Figures 33A to 33C for further explanation.

[0130] Figure 32A is a perspective view showing example 1 of the shape of the cavity 5 in the sample holder 1 of a modified example of the fifth embodiment. Figure 32B is a top view showing example 1 of the shape of the cavity 5 in the sample holder 1 of a modified example of the fifth embodiment. Figure 32C is an end view of example 1 of the shape of the cavity 5 in the sample holder 1 of a modified example of the fifth embodiment, where the vicinity of the cavity 5 in the sample holder 1 is cut by a plane parallel to the xz plane containing the cutting line N-NN shown in Figure 32B. In Figure 32C, a chip 7 is mounted on the sample holder 1 according to the modified example of the fifth embodiment with bonding wire 13.

[0131] Figure 33A is a perspective view showing example 2 of the shape of the cavity 5 in the sample holder 1 of the modified fifth embodiment. Figure 33B is a top view showing example 2 of the shape of the cavity 5 in the sample holder 1 of the modified fifth embodiment. Figure 33C is a cross-sectional view of the sample holder in example 2 of the shape of the cavity in the sample holder of the modified fifth embodiment, cut by a plane parallel to the xz plane including the cutting line O-OO shown in Figure 33B. In Figure 33C, a chip 7 is mounted on the sample holder 1 according to the modified fifth embodiment with bonding wire 13.

[0132] The cavity 5 shown in Figures 32A to 32C has the same structure as the cavity 5 shown in Figures 25A to 25C of the modified version of the fourth embodiment. That is, the cavity 5 shown in Figures 32A to 32C is composed of a frustum pyramidal portion 52. In the modified version of the fifth embodiment, similar to the modified version of the fourth embodiment, four conductive pillars 6 shown in Figures 33A to 33C are added to the four corners of the cavity 5 shown in Figures 32A to 32C. This allows the cavity 5 shown in Figures 31A to 31C to be formed in the base 2. θ is the range in which a portion of the side surface of the cavity 5 (frustum pyramidal portion 52) shown in Figures 32A to 32C is not parallel to the back surface of the tip 7. For example, if the cavity 5 shown in Figures 32A to 32C is a square frustum pyramidal portion, θ is less than 90 degrees.

[0133] Figure 34 shows the simulation results of S11 when a chip 7 is mounted with bonding wire 13 on a sample holder 1 using a base 2 with a cavity 5 formed therein, as shown in Figures 31A to 31C. Figure 34 is an explanatory diagram showing the simulation results of S11 for a system in which a chip 7 is mounted with bonding wire 13 on a sample holder 1 of a modified example of the fifth embodiment. In the simulation in Figure 34, a1=2[mm], b1=2[mm], a2=5[mm], b2=5[mm], d2=5[mm], and s=1[mm] were set. In this case, θ is approximately 73.3 degrees. As shown in Figure 34, the lowest resonant frequency of the chip mode can be raised to 37.5[GHz], which is higher than in the first embodiment. Thus, in the fifth embodiment, the resonant frequency can be further increased by changing the dimensions a1, b1, d1, a2, b2, d2 of the prismatic portion 51 and the frustum-shaped portion 53 of the cavity 5, as well as the thickness t of the chip 7.

[0134] In the fifth embodiment and its modified form, the thickness of the chip 7 mounted on the sample holder 1 is denoted as t. In this case, the sum of the height d1 of the prism portion 51 and the height d2 of the truncated pyramidal portion 53 of the cavity 5 shown in Figures 27A to 27C and 31A to 31C (d1+d2) is preferably 2t or more, more preferably 3t or more, and even more preferably 5t or more.

[0135] Furthermore, in the fifth embodiment and its modified form, if d2 is greater than 0, it has the effect of increasing the chip mode. Therefore, it is preferable that d2 is greater than 0. On the other hand, since d1 may be 0, it is preferable that d2 is 0 or greater. Note that when d1=0, the cavity 5 is composed only of the frustum pyramidal deformation portion 53.

[0136] Furthermore, in the fifth embodiment and its modified form, the smaller the base area of ​​the pillars 6 at the four corners in Figures 29A to 29C and 33A to 33C, the less the contact area between the back surface of the chip 7 and the base 2, thereby increasing the resonant frequency of the chip mode. For this reason, if the chip 7 mounted on the sample holder 1 is rectangular and the length of the shorter side of the chip 7 is v, then s must be 0.5v or less, preferably 0.3v or less, and more preferably 0.2v or less. On the other hand, if the chip 7 mounted on the sample holder 1 is square and the length of one side of the chip 7 is v, then s must be 0.5v or less, preferably 0.3v or less, and more preferably 0.2v or less.

[0137] In the fifth embodiment and its modified versions, the PCB3 of the first embodiment (Figures 11A to 11E) was used. Similar effects can be obtained by using a sample holder 1 on a base 2 that has a cavity 5 formed as shown in Figures 27A to 27C and Figures 31A to 31C, on which a modified version of the PCB3 of the first embodiment (Figures 13A to 13F), the PCB3 of the second embodiment (Figure 14), or a modified version of the PCB3 of the second embodiment (Figure 16) is placed.

[0138] In the fifth embodiment and its modifications, the cavity 5 is a structure in which a prism portion and a frustopyramidal deformed portion are connected, or a structure consisting only of a frustopyramidal deformed portion. However, the shape of the cavity 5 may be other shapes. For example, the side surface of the frustopyramidal deformed portion may be curved instead of flat. In other words, as long as at least a portion of the surface of the base 2 forming the cavity 5 that faces the back surface of the chip 7 is not parallel to the back surface of the chip 7 or the upper surface of the base 2, the effects described in the fifth embodiment and its modifications will be achieved.

[0139] [Other embodiments] In the first to fifth embodiments and their variations, a configuration in which the superconducting quantum circuit chip 7 is directly placed on a metal base 2 was described as a mounting method for the chip 7, but the mounting method is not limited to this. For example, even in a mounting configuration in which a resin material such as varnish is applied to the metal base 2 and then the chip 7 is placed on the resin material such as varnish, the effects of each embodiment, namely the effect of being able to raise the resonant frequency of the chip mode, can be obtained.

[0140] Furthermore, in the first to fifth embodiments and their variations, a configuration in which the PCB 3 is placed directly on a metal base 2 was described for the sample holder 1. However, the effects of each embodiment can also be obtained with a sample holder 1 in which a metal sheet such as In (indium) is placed on the metal base 2, and the PCB 3 is placed on the metal sheet such as In. By sandwiching a soft metal sheet such as In between the base 2 and the PCB 3, it is possible to make it less likely for a gap to form between the GND 11 on the back of the PCB 3 and the base 2. This can improve the high-frequency characteristics of the sample holder 1. Specifically, if there is a gap between the PCB 3 and the base 2, that gap may form a new cavity resonator, which may cause resonance when a signal of a specific frequency is input to the chip 7. For this reason, it is preferable to prevent a gap from forming between the GND 11 on the back of the PCB 3 and the base 2.

[0141] Furthermore, in the first to fifth embodiments and their variations, the sample holder 1 was described in which the PCB 3 is placed on a metal base 2. In addition, a metal lid may be placed on top of the PCB 3. Even when a lid is placed, the effects of each embodiment can be obtained. In such a sample holder 1, the metal lid is in electrical contact with the surface GND 9 of the PCB 3. However, the lid should not come into contact with the core wires 10 or chips 7 of the PCB 3. This is to prevent the circuits and wiring of the core wires 10 and chips 7 of the PCB 3 from coming into contact with GND. For the same reasons as above, it is preferable that there is no gap between the lid and the surface GND 9 of the PCB 3, so a sheet such as In may be placed between the lid and the surface GND 9 of the PCB 3.

[0142] Furthermore, in the first to fifth embodiments and their variations, the shape of the sample holder 1 is shown as a rectangular parallelepiped or a cube for the base 2. However, the effects of each embodiment can be obtained even if the shape of the base 2 is a different shape, such as a cylinder. Similarly, the effects of each embodiment can be obtained even if the shape of the PCB 3 is a shape other than a rectangle or square, such as a circle.

[0143] (Sixth Embodiment) In the sixth embodiment, the basic configuration of the contents described in the first to fifth embodiments will be explained. Here, the sixth embodiment will be explained using Figures 9 and 11E, which were used in the first embodiment.

[0144] As shown in Figure 9, the sample holder 1 comprises a base 2 and a PCB 3 in contact with the base 2. As shown in Figure 11E, the PCB 3 comprises a dielectric 8, a surface GND 9 formed on the surface of the dielectric 8, a back surface GND 11 formed on the back surface of the dielectric 8, a through hole 4 that penetrates from the surface GND 9 to the back surface GND 11 and houses the chip 7, and a conductor 14 that conducts the surface GND 9 and the back surface GND 11 at the end face of the through hole 4.

[0145] As shown in Figure 9, there is a cavity 5 in at least a portion of the base 2 below the through hole 4. The shape of the cavity 5 is not particularly limited. For example, the bottom surface of the cavity 5 may be flat or not. The sides of the cavity 5 may be flat or not. For example, there may be indentations or depressions on the sides or bottom surface of the cavity 5.

[0146] Next, the cavity 5 contains a support structure that supports the surface of the chip 7 and is electrically connected to the base 2. The shape of the support structure is not particularly limited. The support structure may be a column or the like. The support structure may be integrated with the base. For this reason, the support structure may be formed by the shape of the cavity 5.

[0147] In the sixth embodiment, a cavity 5 is formed in the base 2, and a conductor 14 that conducts the surface GND 9 and the back GND 11 is provided on the end face of the through hole 4 of the PCB 3, thereby increasing the resonant frequency of the chip mode.

[0148] This concludes the description of the sample holder 1 according to each embodiment. Furthermore, the superconducting quantum computer according to each embodiment comprises the sample holder 1 according to each embodiment and a chip on which a superconducting quantum circuit is formed, which is stored in the sample holder 1.

[0149] The present disclosure has been described above with reference to the embodiments described herein, but the present disclosure is not limited to the embodiments described above. The structure and details of each disclosure may include embodiments that apply various modifications that can be grasped by those skilled in the art within the scope of the present disclosure. The present disclosure may include embodiments that combine or substitute the matters described herein as appropriate. For example, matters described using a particular embodiment may also apply to other embodiments, to the extent that they do not cause a contradiction.

[0150] Some or all of the above embodiments may also be described as follows. However, some or all of the above embodiments are not limited to the following.

[0151] (Note 1) The base and The PCB in contact with the aforementioned base and Equipped with, The PCB comprises a dielectric, a surface ground formed on the surface of the dielectric, a back ground formed on the back surface of the dielectric, a through hole that penetrates from the surface ground to the back ground and houses a chip, and a conductor that conducts the surface ground and the back ground at the end face of the through hole. At least a portion of the base below the through hole has a cavity, The cavity contains a support structure that supports the surface of the chip and is electrically connected to the base. Sample holder.

[0152] (Note 2) In the support structure, at least a portion of the part that supports the chip is parallel to the surface of the chip. The sample holder described in Appendix 1.

[0153] (Note 3) The aforementioned support structure is a column, The sample holder described in Appendix 1 or 2.

[0154] (Note 4) The support structure is a plurality of columns provided in the cavity. The sample holder described in Appendix 3.

[0155] (Note 5) The aforementioned multiple columns are provided at the four corners of the cavity, The sample holder described in Appendix 4.

[0156] (Note 6) If each of the aforementioned multiple columns is a triangular prism, The lengths of the equal sides of the isosceles triangle faces of the triangular prism are shorter than half the length of the shorter side of the face of the chip. The sample holder described in Appendix 5.

[0157] (Note 7) The PCB has a core wire of a coplanar waveguide on the surface of the dielectric, A sample holder as described in any of the appendices 1 to 6.

[0158] (Note 8) The conductor is provided on the end face of the through hole, excluding the end face of the PCB near the core wire. The sample holder described in Appendix 7.

[0159] (Note 9) The core wire is of a length such that it does not come into contact with the end face of the through hole. The conductor is formed on the entire end face of the through hole, The sample holder described in Appendix 7.

[0160] (Note 10) The PCB further has a core wire in the region of the dielectric sandwiched between the surface ground and the back ground, On the surface of the dielectric, in addition to the surface ground, there is a pad that electrically connects the chip and the core wire, and the pad is electrically connected to the core wire. A sample holder as described in any of the appendices 1 to 6.

[0161] (Note 11) The support structure is made of metal or a mixture containing metal. A sample holder as described in any of the appendices 1 through 10.

[0162] (Note 12) The base is made of metal. A sample holder as described in any of the appendices 1 through 11.

[0163] (Note 13) The height of the cavity is greater than the thickness of the chip. A sample holder as described in any of the appendices 1 to 12.

[0164] (Note 14) The height of the cavity is at least twice the thickness of the chip. The sample holder described in Appendix 13.

[0165] (Note 15) Sample holder and, A chip on which a superconducting quantum circuit is formed is stored in the aforementioned sample holder, Equipped with, The aforementioned sample holder is The base and The PCB in contact with the base, Equipped with, The PCB comprises a dielectric, a surface ground formed on the surface of the dielectric, a back ground formed on the back surface of the dielectric, a through hole in which the chip is housed, extending from the surface ground to the back ground, and a conductor at the end face of the through hole that conducts the surface ground and the back ground. At least a portion of the base below the through hole has a cavity, The cavity contains a support structure that supports the surface of the chip and is electrically connected to the base. Superconducting quantum computer. [Explanation of Symbols]

[0166] 1. Sample holder 2 bases 3 PCB 4 through holes 5 hollow 6 pillars 7 chips 8 Dielectrics 9 Surface GND 10 core wires 11 Backside GND 12 through-holes 13 Bonding wire 14 Conductors 15 Input / Output Pads 16 Bonding Pads 51. Corner prism section 52 truncated pyramid part 53. Deformed part of a truncated pyramid 61 Top 62 Lower part 71 First Coplanar Waveguide 72 Second Coplanar Waveguide 73 GND plane 74 First core wire 75 Second core wire 76 First pad 77 Second pad 101 Sample Holder 102 Pedestal 103 PCB 104 Through hole 105 Cavity 106 pillars 107 chips 108 dielectric 109 Surface GND 110 core wire 110a First core wire 110b Second core wire 111 Backside GND 112 Through-holes 113 Bonding wire

Claims

1. The base and The PCB (Printed Circuit Board) in contact with the aforementioned base and Equipped with, The PCB comprises a dielectric, a surface ground formed on the surface of the dielectric, a back ground formed on the back surface of the dielectric, a through hole that penetrates from the surface ground to the back ground and houses a chip, and a conductor that conducts the surface ground and the back ground at the end face of the through hole. At least a portion of the base below the through hole has a cavity, The cavity contains a support structure that supports the surface of the chip and is electrically connected to the base. In the support structure, at least a portion of the part that supports the chip is not parallel to the surface of the chip. Sample holder.

2. The aforementioned support structure is a column of conductors, The sample holder according to claim 1.

3. The aforementioned column has a shape that combines a truncated pyramid and a rectangular prism. The narrower side of the frustum is the side with the through hole. The larger base of the frustum and the upper base of the prism are the same shape and connected. The sample holder according to claim 2.

4. The aforementioned columns are a plurality of columns provided in the aforementioned cavity. The sample holder according to claim 2 or 3.

5. The aforementioned multiple columns are provided at the four corners of the cavity, The sample holder according to claim 4.

6. The aforementioned cavity has the shape of a frustum, The larger base of the frustum is the side with the through hole. The sample holder according to claim 1.

7. The aforementioned cavity has a shape that combines the frustum and the prism. The narrower base of the frustum and the upper base of the prism are the same shape and connected. The sample holder according to claim 6.

8. The aforementioned prism is a rectangular prism. The aforementioned frustum is a truncated square pyramid. The sample holder according to claim 7.

9. The cavity is further provided with a rectangular prism of a conductive material. The upper bottom surface of the rectangular prism of the conductor is parallel to the upper surface of the base. A sample holder according to any one of claims 6 to 8.

10. Sample holder and, A chip on which a superconducting quantum circuit is formed is stored in the aforementioned sample holder, Equipped with, The aforementioned sample holder is The base and The PCB in contact with the base, Equipped with, The PCB comprises a dielectric, a surface ground formed on the surface of the dielectric, a back ground formed on the back surface of the dielectric, a through hole in which the chip is housed, extending from the surface ground to the back ground, and a conductor at the end face of the through hole that conducts the surface ground and the back ground. At least a portion of the base below the through hole has a cavity, The cavity contains a support structure that supports the surface of the chip and is electrically connected to the base. In the support structure, at least a portion of the part that supports the chip is not parallel to the surface of the chip. Superconducting quantum computer.

Images