Electron source and method for manufacturing the electron source

Abstract

To provide a field emission type electron source formed to form a curved surface.SOLUTION: An electron source of the present invention has: an etch-stop layer with a first region supported by a substrate and a second region not supported by the substrate; and an electron emission structure formed at least above the second region. Nothing may be formed, arranged, etc., in a lower portion of the second region. In the second region, the etch-stop layer and the electron emission structure naturally form a convex or concave surface. Thus, the electron beam is aggregated or diverged.SELECTED DRAWING: Figure 1

Description

Technical Field

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[0001] The present invention relates to a field emission type electron source and a method for manufacturing the same.

Background Art

[0002] For example, in Patent Document 1, for the purpose of focusing an electron beam emitted from an electron source used in a traveling wave tube (TWT) or the like to a single point, it is disclosed that the surface of the electron source (also called a cathode) is processed into a part of a concave spherical surface. Such a technique uses a so-called thermionic electron source (hot cathode) or a photoelectron electron source that emits electrons into a vacuum by applying energy of heat or light to the electrons.

[0003] On the other hand, regarding an electron source that emits electrons into a vacuum by tunneling only by an electric field, for example, in Patent Documents 2 and 3, it is disclosed that the electron sources are arranged on a part of a concave spherical surface.

[0004] However, in these methods, a field emission type electron source manufactured on a flat substrate is attached to a concave spherical surface, and the electron source itself is not spherical, and there is a limit to the focused electron beam.

[0005] On the other hand, it is difficult to manufacture a field emission type electron source array on a concave surface. Usually, since a field emission type electron source array is manufactured on a flat silicon substrate or a glass substrate using semiconductor microfabrication technology, the manufacturing process includes processes such as photolithography and dry etching. In photolithography, the process of applying a photoresist is indispensable, and when a resist is applied to a curved concave surface, it is inevitable that a film thickness distribution occurs in the plane, such as the photoresist becoming thick at the bottom of the curved surface. That is, it is impossible to fabricate a field emission type electron source array of uniform size on a curved concave surface.

Prior Art Documents

Patent Documents

[0006] [Patent Document 1] Patent No. 4134000 [Patent Document 2] Japanese Patent Publication No. 2005-261502 [Patent Document 3] Patent No. 5424098 [Overview of the project] [Problems that the invention aims to solve]

[0007] Therefore, one aspect of the present invention is to provide a field emission type electron source formed to have a curved surface, and a method for manufacturing said electron source. [Means for solving the problem]

[0008] The electron source of the present invention comprises an etch stop layer having a first region supported by a substrate and a second region not supported by the substrate, and an electron emission structure formed on at least the second region.

[0009] The present invention provides a method for manufacturing an electron source, comprising the steps of forming an electron emission structure on at least a portion of the etch stop layer on a substrate, and removing the substrate by etching below at least a portion of the above region. [Effects of the Invention]

[0010] From one perspective, this makes it possible to provide a field emission type electron source that forms a curved surface. [Brief explanation of the drawing]

[0011] [Figure 1] Figure 1 shows an example of the configuration of an electron source according to the first embodiment. [Figure 2] Figure 2 shows an example of the general shape of an electron emission area. [Figure 3] Figure 3 is a diagram illustrating a method for manufacturing an electron source according to the first embodiment. [Figure 4] FIG. 4 is a diagram showing an example of the schematic shape of an electron emission area. [Figure 5] FIG. 5 is a diagram showing a configuration example of an electron source when a stress adjustment layer is added. [Figure 6] FIG. 6 is a diagram showing an example of adjustment of internal stress. [Figure 7] FIG. 7 is a diagram showing a configuration example of an electron source when a convex curved surface is formed. [Figure 8] FIG. 8 is a diagram showing a configuration example of an electron source according to Modification 1 of the First Embodiment. [Figure 9] FIG. 9 is a diagram for explaining a method of manufacturing an electron source when using a SOI wafer. [Figure 10] FIG. 10 is a diagram showing a configuration example of an electron source according to the Second Embodiment. [Figure 11] FIG. 11 is a diagram for explaining a method of manufacturing an electron source according to the Second Embodiment. [Figure 12] FIG. 12 is a diagram showing a configuration example of an electron source according to Modification 1 of the Second Embodiment.

BEST MODE FOR CARRYING OUT THE INVENTION

[0012] [Embodiment 1] [Configuration] An example of a field emission type electron source according to the present embodiment is shown in FIG. 1. The electron source according to the present embodiment includes an emitter array (70) in which a plurality of emitters (80) having sharp electron emission ends are formed in an array. In the present embodiment, this emitter array (70) forms a concave curved surface. Since the emitter array (70) forms a concave curved surface in this way, it becomes easier to focus the electrons emitted from the tips of the respective emitters (80).

[0013] In this electron source, an opening 60 is formed in the substrate 100 at the lower part (i.e., the opposite side) of the emitter array 70. The membrane including the etch stop layer 40 formed on the opening 60 and the conductive layer 30 formed further above is not supported by the substrate 100. Therefore, the membrane naturally forms a concave curved surface due to its own stress. Note that the substrate 100 remains in the parts other than the opening 60, and the etch stop layer 40 and the like formed above the substrate 100 are supported by the substrate 100.

[0014] As shown in FIG. 2, the shape of the opening 60 is preferably circular, for example, in terms of both performance and manufacturing. In the case of a rectangle, stress concentrates at the corner portions, so it is likely that a preferable concave curved surface cannot be formed or it may break.

[0015] A conductive layer 30 is formed for the emitter array 70 formed on the etch stop layer 40. On the conductive layer 30, an insulating layer 20 having a plurality of small openings and a gate electrode 10 are formed, and an emitter 80 is formed in each of these small openings.

[0016] In such an electron source, electrons are emitted from the emitter 80 by applying a predetermined voltage to the gate electrode and the conductive layer 30.

[0017] [Manufacturing Method of Embodiment 1] The manufacturing method of the electron source according to this embodiment will be described with reference to FIGS. 3(a) to (d).

[0018] As shown in Figure 3(a), an etch-stop layer 40 is formed on the substrate 100 so as not to be etched when the opening 60 is later formed on the back surface. The material of the substrate 100 is not particularly limited, but a silicon substrate is suitable as it is easy to form the opening 60 on the back surface. The material of the etch-stop layer 40 is selected by the etching method for the opening 60 on the back surface. When a silicon substrate is selected as the substrate 100 and a Bosch process using SF6 gas and CF-based gases such as C4F8, which are commonly used to deeply etch silicon substrates, a material that will not be etched by SF6 or CF-based gases should be selected. For example, silicon oxide (SiO2), aluminum, or chromium can be used. Alternatively, a multilayer film of these materials may also be used.

[0019] A conductive layer 30 for supplying current to the emitter is formed on top of the etch-stop layer 40. If a conductive film is chosen for the etch-stop layer 40, it is possible to omit the conductive layer. However, generally, the conductive layer is often patterned to the required shape, so providing it separately from the etch-stop layer offers greater design flexibility.

[0020] Next, as shown in Figure 3(b), there are many methods for forming the insulating layer 20, gate electrode 30, and emitter 80 on the conductive layer 30, so any method can be chosen. For example, a method for manufacturing a spint-type emitter described in Japanese Patent Publication No. 6093968, CA Spindt, et al., “Physical Properties of thin-film field emission cathode with molybdenum cones”, Journal of applied Physics, vol. 47, (1976) p.5248, may be adopted. As well as well-known methods, a detailed explanation will be omitted here.

[0021] Next, as shown in Figure 3(c), after forming the emitter array 70 as shown in Figure 3(b), the silicon substrate on the back side of the emitter array 70 is etched using a so-called deep etching method such as the Bosch process. To do this, first, the surface on which the emitter array 70 is formed is protected with a coating-type protective film 200. A photoresist or resin film that can be applied thicker than the height of structures such as the emitter 80 is suitable for the protective film 200. In addition, a photoresist is applied to the back side of the silicon substrate to form a mask 300 according to the pattern to be deep-etched. As for the Bosch process, for example, a method in which etching is repeated by alternately introducing SF6 gas and C4F8 gas can be used.

[0022] While it is possible to etch silicon substrates using alkaline liquids such as tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH), the etching rate differs depending on the silicon crystal orientation, resulting in etching proceeding in a way that leaves the (111) plane intact. As a result, the shape of the etched holes becomes rectangular regardless of the original mask shape. When the holes formed by etching are rectangular, as mentioned above, there is a high possibility of tearing occurring from the corners of the rectangle. Furthermore, even if etching is successful without tearing, there is a high possibility of wrinkles (bending) occurring when the substrate is bent, which is undesirable.

[0023] The shape of the aperture 60 is selected according to the desired shape of the final focused electron beam. For example, when focusing the electron beam to a point, it is preferable that the concave surface formed by the membrane has a structure like a part cut out of a sphere, so the shape of the hole to be etched is preferably circular, as shown in Figure 2. Also, when the goal is to focus the electron beam in a line, it is preferable to have a shape like a rectangle with the shorter side made into a semicircle, that is, a shape that is covered by moving a circle in a straight line, as shown in Figure 4.

[0024] Then, as shown in Figure 3(d), after deep etching, the unnecessary protective film 200 and mask 300 are removed using oxygen plasma or a stripping solution. With the silicon substrate on the back removed, the emitter array 70 becomes curved due to the stress of the stacked thin films (i.e., membranes). Whether the curved surface is convex or concave depends on whether the total stress of the stacked thin films (i.e., membranes) is tensile or compressive stress.

[0025] The degree of curvature (radius of curvature (R)) of an electron-emitting membrane is determined by the distance between the electron source and the electron beam's focus point. To achieve this R, the stress of the membrane is adjusted. For this purpose, as shown in Figure 5, a stress adjustment layer 400 (also called a curvature adjustment layer that adjusts the degree of curvature) may be inserted between the etch-stop layer 40 and the conductive layer 30. Since the purpose of the stress adjustment layer 400 is to adjust the degree of curvature by its stress, a film that allows for stress adjustment is desirable. For example, an SiO2 film deposited by plasma CVD (Chemical Vapor Deposition) using tetraethoxysilane (TEOS) gas, as shown in Figure 6, allows for some control of stress from tensile stress (the portion above 0 on the vertical axis) to compressive stress (the portion below 0 on the vertical axis) by adjusting the ratio of TEOS gas and oxygen gas introduced during deposition (horizontal axis) and the substrate temperature Ts, making it suitable for use as a stress adjustment layer.

[0026] Furthermore, when the stress on the membrane is tensile stress, the membrane will form a convex surface, as shown in Figure 7. Such a convex membrane can be used in light-emitting devices like light bulbs by diverging, rather than focusing, the electron beam.

[0027] [Modification 1 of Embodiment 1] Instead of the spint-type emitter described above, an emitter array with an integrated volcanic focusing electrode may be formed, as shown in Figure 8. A method for manufacturing this emitter array with an integrated volcanic focusing electrode is described, for example, in Japanese Patent Application Publication No. 2021-018846, so a detailed explanation is omitted here. Briefly describing the structure, an emitter 80 is formed at the opening of the extraction gate electrode 94, and a focusing electrode 92 for focusing electrons emitted from the emitter 80 is also formed. In the case of an electron source like the one in Figure 1, it is said that electrons emitted from each emitter 80 are emitted with a spread angle of about 30 degrees, and with only the configuration in Figure 1, it may not be possible to easily focus the electron beam. On the other hand, in this configuration, since the focusing electrode 92 can be formed integrally with each emitter 80, an electron beam aligned perpendicular to the emitter 80 from the beginning can be emitted, making it easy to focus it to a single point.

[0028] [Modification 2 of Embodiment 1] Furthermore, a method of etching silicon or other materials to form a sharp emitter may also be applied. In this case, an SOI (Silicon on Insulator) wafer may be used. For example, as shown in Figure 9(a), the SOI wafer 80 has a so-called BOX layer (SiO2 layer) 80b on the upper side of the silicon substrate 80c, and a silicon layer 80a on top of that. First, a circular mask 81 made of SiO2 is formed on the silicon layer 80. Then, as shown in Figure 9(b), the general shape of the emitter is formed by reactive etching. The reactive etching conditions can be adjusted by changing the type of gas, etc., to create conditions that cause side etching, thereby forming the general shape of the emitter. However, if etching is continued until the tip is completely sharp, the mask will come off, and the emitter tip will be rapidly etched thereafter, resulting in a poor shape. Therefore, etching is stopped just before it becomes sharp. In Figure 9(b), it can be seen that a silicon layer 82 containing an emitter with a flat tip has been formed.

[0029] Subsequently, as shown in Figure 9(c), the emitter tip is formed by thermal oxidation. During the thermal oxidation process, stress is generated in areas that are not flat, such as near the emitter tip, causing the oxidation rate to be slower compared to flat areas. By utilizing this phenomenon, a very sharp tip can be formed. That is, a film of SiO2 82' is formed on the surface of the silicon layer 82 containing the emitter with a flat tip, and a silicon layer 84 containing the emitter 83 with a pointed tip is formed below it. Then, as shown in Figure 9(d), the SiO2 remaining on top of the emitter 83 is treated with buffered hydrofluoric acid ( Buffered Etching is performed using hydrofluoric acid.

[0030] When forming an emitter in this manner, the BOX layer 80b of the SOI wafer acts as the etch stop layer. The thickness of the top silicon layer 80a of the SOI wafer 80 is set according to the height of the emitter to be fabricated. If the emitter height is 1 micron, then an SOI wafer 80 with a silicon layer thicker than 1 μm is used.

[0031] [Embodiment 2] Figure 10 shows an example configuration of an MIS (Metal / Insulator / Semiconductor) type electron source according to the second embodiment. This is also referred to as a MIM (Metal / Insulator / Metal) type electron source.

[0032] In this electron source, an etch-stop layer 40 and a conductive layer 30 are provided on the substrate 100, and further on, an insulating layer 20 for accelerating electrons and a gate electrode 10 for applying voltage are formed. In this embodiment, the insulating layer 20 is thinner only in the electron emission area 700, and an opening 60 is formed in the substrate 100 on the lower side (i.e., the opposite side) of the electron emission area 700. That is, the lower part of the electron emission area 700 is not supported by the substrate 100, and the emblem including the gate electrode 10, insulating layer 20, conductive layer 30 and etch-stop layer 40 in the electron emission area 700 naturally forms a concave curved surface. Note that the substrate 100 remains in place of the opening 60, and the etch-stop layer 40 and other components formed above the substrate 100 are supported by the substrate 100. Since electrons are emitted perpendicular to the surface, a focusing electrode is not required. If the emblem in the electron emission area 700 forms a concave curved surface, the electron beam can be focused to a single point by applying a predetermined voltage between the conductive layer 30 and the gate electrode.

[0033] Furthermore, if the etch-stop layer 40 is conductive, it may also be a film that serves as the conductive layer 30, similar to the first embodiment.

[0034] The conductive layer 30 can be made of any material as long as it is conductive, but it is preferable that it emits electrons perpendicular to the substrate, so it is preferable that it be as flat as possible. In the case of a metal film, it is generally polycrystalline and surface irregularities occur, so in that case it is preferable to flatten it using a method such as CMP (Chemical-Mechanical Polishing). Alternatively, it is also possible to use an SOI (Silicon On Insulator) wafer, in which case the SOI BOX layer (SiO2) becomes the etch stop layer 40 and the SOI layer becomes the conductive layer 30.

[0035] The thickness of the insulating layer 20 within the electron emission area 700 is preferably 4 nm to 20 nm, and more preferably 4 nm to 10 nm.700 The thickness of the other areas is preferably about 100 nm to 1000 nm. Electron emission area 700 The insulating layer 20 in this device is formed thinly, which helps prevent electrons emitted from the conductive layer 30 from being scattered in the insulating layer 20, and also has the advantage of reducing the operating voltage. However, if it is too thin, it will not be possible to apply the voltage necessary to accelerate the electrons, so it is kept within the range described above.

[0036] Suitable materials for the insulating layer 20 include those with good insulating properties, such as boron nitride (BN), SiO2, and Al2O3. However, since electrons tunnel through this material and travel along the conductive band of the insulating layer 20, a material with low interaction with electrons is desirable, and it is even more preferable that it is composed of light elements. Therefore, BN is more preferable, and among these, hexagonal boron nitride (h-BN), which can be formed into a layered film, is the most preferable.

[0037] Since electrons pass through the gate electrode 10 and are released into the vacuum, it is desirable that the interaction with electrons be as small as possible, and therefore the film thickness is preferably 7 nm or less, and even more desirable if it is a single atomic layer. The material is also preferably conductive, can form a continuous film, is composed of light elements, and can be made thin. For this reason, a layered carbon film, i.e., graphene, is preferred. If it is difficult to form a single layer film, a multilayer graphene can be used, but as mentioned above, the film thickness is preferably 7 nm or less. Furthermore, in order to properly cover parts of the insulating layer 20 with different film thicknesses, single-crystal graphene is unsuitable because its structure is made up of hexagons arranged in a grid, so it can only be flat. It is preferable that the graphene be polycrystalline.

[0038] [Manufacturing method of Embodiment 2] The method for manufacturing the electron source according to this embodiment will be explained with reference to Figures 11(a) to (d).

[0039] First, as shown in Figure 11(a), an etch-stop layer 40, a conductive layer 30, and an insulating layer 20 are deposited on a silicon substrate 100. When using an SOI wafer, the etch-stop layer 40 corresponds to the BOX layer and the conductive layer 30 corresponds to the SOI layer (silicon layer). The insulating layer 20 ultimately defines the electron emission area 700 (it is removed from the electron emission area 700, and this insulating layer 20 is left in the areas where electron emission is not desired). As long as good insulation is maintained, it can be selected from a variety of materials. Commonly used materials include SiO2 and Al2O3. Its thickness can be freely selected from a film thickness of 100 nm to 10 μm. A thickness that is usually easy to use is around 300 nm to 1 μm. In some cases, a stress adjustment layer 400 may be formed between the etch-stop layer 40 and the conductive layer 30.

[0040] Next, as shown in Figure 11(b), the insulating layer 20 is removed from the electron emission area 700 in order to define the electron emission area 700. At this point, since it is formed on a flat substrate, this can be done using conventional photolithography and dry etching or wet etching.

[0041] Furthermore, as shown in Figure 11(c), a thin insulating layer 21 is formed on the electron emission area 700 to tunnel and accelerate electrons. The quality of the insulating layer 21 greatly affects the characteristics of this electron source. For example, when single-crystal silicon is used as the conductive layer 30, cleaning such as RCA cleaning is performed to reduce defects as much as possible, followed by thermal oxidation, and the insulating layer 21 is formed on the exposed portion of the conductive layer 30. In addition, h-BN can also be used as the insulating layer 21. h-BN is composed only of light elements, nitrogen and boron, and has little interaction with electrons, so an improvement in electron emission efficiency can be expected, making it one of the most desirable forms.

[0042] It is preferable to adjust the thickness of the insulating layer 21 to approximately 4 nm to 20 nm. If the insulating layer 21 is thinner than 4 nm, a tunnel current will flow between the conductive layer 30 and the gate electrode 10 formed thereafter, before a sufficient voltage is applied. Even if a tunnel current flows when the potential of the gate electrode 10 is lower than the work function, the electrons have low energy and cannot penetrate the gate electrode 10, so electron emission cannot be obtained. Therefore, it is preferable that the insulating layer 21 is 4 nm or thicker. If the insulating layer 21 is thicker than 20 nm, the distance traveled by the tunneled electrons within the insulating layer 21 becomes longer, and they lose energy due to scattering caused by lattice vibrations during their movement. Therefore, in this case as well, the number of electrons with energy greater than or equal to the work function decreases, and the electron emission efficiency deteriorates. As a result of research conducted by the inventors of this invention, it is preferable that the thickness of the insulating layer 21 be 20 nm or less, and more preferable that it be 10 nm or less.

[0043] Next, the gate electrode 10 is formed. While metals or semiconductors can be used for the gate electrode 10, electrons that have passed through the insulating layer 21 must also pass through the gate electrode 10 to be released into a vacuum. Therefore, a material that allows electrons to pass through easily is preferable. General metals have large atoms, and a film thickness of 10 nm or more is required to obtain a continuous film. A conductive material made of light elements is preferred for the gate electrode 10, and it is desirable that it be a continuous film that is as thin as possible. Therefore, the most preferred material is graphene, which consists of a single layer of carbon atoms. As a method for directly depositing graphene on the insulating layer 21, the inventors of this application can employ a CVD method involving exposure to a mixed atmosphere of gallium vapor and methane gas, for example, as described in Japanese Patent Publication No. 6983404.

[0044] As shown in Figure 11(d), finally, the substrate 100 on the opposite side of the electron emission area 700 is etched. During the etching of the substrate 100, the electron emission area 700 on the surface is protected, as in the first embodiment.

[0045] [Modified version of Embodiment 2] Figure 12 shows an electron source according to a modified example of the second embodiment. Here, the electron emission area 750 is array-shaped, unlike the electron emission area 700 of the electron source shown in Figure 10. This ensures that even if there is a defect in one part, only that part will not function, while the other parts will continue to function. Note that, apart from the etch stop layer 40 and the opening 60 at the bottom of the substrate 100, the rest is described in publications such as Japanese Patent No. 7057972, so a detailed explanation is omitted here.

[0046] In this way, by introducing an etch stop layer and providing an opening on the back surface of the substrate, the electron emission area not supported by the substrate will form a convex or concave surface in response to the stress caused by the etch stop layer, allowing electrons to be focused or diverged and emitted. Various forms can be used for the electron emission structure formed above the etch stop layer in the electron emission area, and structures other than those described above may also be used. Even when the etch stop layer is used as a conductive layer, some structure that contributes to electron emission is formed above the etch stop layer, so this structure is a type of electron emission structure.

[0047] Furthermore, when using SOI wafers, an etch stop layer is not formed during the manufacturing of the electron source, but an electron emission structure that contributes to electron emission is formed.

[0048] Although embodiments of the present invention have been described above, the present invention is not limited to these. For example, it is possible to delete any technical matters from each embodiment or to combine any technical matters from any embodiment.

[0049] Furthermore, when a large current is discharged from the electron source, the temperature of the electron source becomes high due to Joule heating. In the structure according to this embodiment, the lower part of the electron source is not supported by the substrate, so the heat dissipation characteristics are poor, and thermal damage may occur when operating at high current. Therefore, in order to improve the heat dissipation characteristics, a heat dissipation layer may be inserted between the etch stop layer and the conductive layer. The heat dissipation layer is preferably made of a metal such as copper or aluminum, which has good thermal conductivity.

[0050] The embodiments described above can be summarized as follows:

[0051] The electron source according to this embodiment includes an etch-stop layer having a first region supported by a substrate and a second region not supported by the substrate, and an electron emission structure formed on at least the second region. The electron emission structure for electron emission, formed in the second region not supported by the substrate, naturally forms a curved surface.

[0052] More specifically, the lower part of the second region of the etch stop layer may be hollow. In other words, nothing needs to be formed or placed in the lower part of the second region. Also, the etch stop layer and electron emission structure in the second region may form a convex or concave curved surface. This is to concentrate or diverge the electron beam. Furthermore, the second region may be circular in shape, or covered by moving a circle along a straight line or curve. The shape should match the convergence or divergence shape of the electron beam, but a shape that can be manufactured without problems is preferable. In some cases, it may be elliptical.

[0053] The electron source described above may further include a stress adjustment layer formed between the etch-stop layer and the layer containing the electron emission structure. This controls the degree of curvature of the curved surface (including whether it is uneven or not).

[0054] A method for manufacturing an electron source according to an embodiment includes the steps of forming an electron emission structure on at least a portion of the etch stop layer on a substrate, and removing the substrate by etching below at least a portion of the said region. In this way, the layers above the etch stop layer are divided into a region supported by the substrate and a region not supported by the substrate, and the region not supported by the substrate naturally becomes an appropriate curved surface.

[0055] The above manufacturing method may further include the step of forming a stress adjustment layer between the etch stop layer and the layer containing the electron emission structure. substrate This allows for control over the degree of curvature in areas not supported by the system.

[0056] Furthermore, the above manufacturing method may further include the step of forming an etch stop layer on the substrate. In the case of SOI wafers, the BOX layer can be used as an etch stop layer, so it is not necessary to form one. However, when using a silicon substrate, forming an etch stop layer in this way makes it possible to stop the effects of etching from the back surface of the substrate with the etch stop layer. [Explanation of symbols]

[0057] 10 Gate electrode 20 Insulating film 30 Conductive layer 40 Etch stop layer 60 Aperture 80 Emitter 100 Silicon Substrate 70,700,750 electron emission area 80 SOI wafer 80a Silicon layer 80b Box layer 80c Silicon substrate

Claims

1. An etch stop layer having a first region supported by a substrate and a second region not supported by the substrate, An electron emission structure formed on at least the second region, An electron source having [a certain characteristic].

2. The lower portion of the second region of the etch stop layer is hollow. The electron source according to claim 1.

3. In the second region, the etch stop layer forms a convex or concave surface. The electron source according to claim 1.

4. The second region is a circular shape, or a shape covered by moving a circle along a straight line or curve. The electron source according to claim 1.

5. A stress adjustment layer formed between the etch stop layer and the layer containing the electron emission structure. The electron source according to claim 1, further comprising:

6. The steps include forming an electron emission structure on at least a portion of the etch stop layer on a substrate, The steps include removing the substrate by etching in at least a portion of the lower part of the aforementioned region, A method for manufacturing an electron source containing [the specified element].

7. The step of forming a stress adjustment layer between the etch stop layer and the layer containing the electron emission structure. The manufacturing method according to claim 6, further comprising:

8. The step of forming the etch stop layer on the substrate. The manufacturing method according to claim 6, further comprising:

9. In the aforementioned electron emission structure, An array of openings is formed in the insulating layer and the gate electrode. Each of the aforementioned openings is formed with an emitter having a sharp electron-emitting edge. The electron source according to any one of claims 1 to 5.

10. In the aforementioned electron emission structure, An array of openings is formed in the gate electrode. An emitter having a sharp electron-emitting edge is formed in each of the aforementioned openings. Furthermore, a focusing electrode is formed to focus the electrons emitted from the emitter. The electron source according to any one of claims 1 to 5.

11. The aforementioned electron emission structure is It has a flat structure in which an insulating layer for accelerating electrons and a gate electrode are stacked. The electron source according to any one of claims 1 to 5.

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