Switched-capacitor amplifiers and AD converters

Abstract

To provide a switched capacitor type amplifier which does not need a reference voltage source.SOLUTION: A switched capacitor type amplifier comprises: an operational amplifier including two input and output terminals of a positive polarity and a negative polarity; a first capacitive element connected between a voltage input terminal and the input terminal of the negative polarity of the operational amplifier; a second capacitive element connected between the input terminal and the output terminal of the negative polarity of the operational amplifier; a switch element for accumulating electric charge corresponding to a voltage of the voltage input terminal in the first capacitive element in a first phase; and a switch element for moving the electric charge accumulated in the first capacitive element to the second capacitive element in the second phase. In the switched capacitor type amplifier, the operational amplifier includes a pair of differential input transistors and a pair of load elements connected in series with the pair of differential input transistors. The input terminal of the positive polarity is connected to a reference potential point, and the pair of load elements is set to be different resistance values.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a switched-capacitor amplifier having a positive input offset voltage and an AD converter provided with the same.

Background Art

[0002] In a switched-capacitor amplifier, an input offset voltage always occurs in the operational amplifier constituting the amplifier due to variations in the manufacturing process. Therefore, in a switched-capacitor amplifier configured as shown in Fig. 4(A), when the operational amplifier AMP has a negative input offset voltage, if a ground potential is applied to the non-inverting input terminal IN(+) of the operational amplifier AMP, the inverting input terminal IN(-) becomes a negative value. Thus, regardless of the voltage value of the input voltage VIN on the inverting input terminal IN(-) side, as shown in Fig. 5(A), the output VOUT of the operational amplifier always becomes the ground potential.

[0003] Therefore, as shown in Fig. 4(B), by applying a reference voltage VREF greater than the input offset voltage of the operational amplifier to the non-inverting input terminal IN(+) of the operational amplifier AMP to raise the operating point, as shown in Fig. 5(B), there is a technique to make the output VOUT of the operational amplifier a voltage proportional to the voltage value of the input voltage VIN.

[0004] Conventionally, there is an invention of a switched-capacitor amplifier in which a capacitor is provided between the inverting input terminal of the operational amplifier and the reference voltage, and the capacitor becomes the load of the operational amplifier only during offset cancellation to suppress the oscillation phenomenon (Patent Document 1).

[0005] Also, in a differential-input switched-capacitor amplifier, there is an invention in which, in addition to the reference voltage (ground potential), a reference voltage is used to control the difference between the reference voltage and the reference voltage, thereby canceling the offset voltage included in the input voltage (Patent Document 2). Incidentally, in the amplifier of Patent Document 2, a reference voltage is also provided on the inverting input terminal side of the operational amplifier. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 6-45875 [Patent Document 2] Japanese Patent Publication No. 2004-222018 [Patent Document 3] Japanese Patent Publication No. 2016-111499 [Overview of the project] [Problems that the invention aims to solve]

[0007] Switched-capacitor amplifiers with configurations like the one shown in Figure 4(B) and those described in Patent Documents 1 and 2 use a reference voltage separate from the reference voltage (ground potential). Therefore, they have the problem of requiring a reference voltage generation circuit, such as a reference voltage circuit, to generate the reference voltage.

[0008] Furthermore, in conventional amplifiers equipped with operational amplifiers, it is common practice to measure and trim the resistance value of the load resistor connected in series with the differential input transistor during the final inspection stage of the manufacturing process in order to reduce the input offset voltage (see, for example, Patent Document 3). This presents the problem of increasing the time required for the inspection process.

[0009] This invention was made in view of the above-mentioned problems, and its objective is to provide a switched-capacitor type amplifier that does not require a reference voltage circuit (reference voltage source) and an AD converter equipped therewith. Another object of the present invention is to provide a switched-capacitor type amplifier and an AD converter equipped therewith, which eliminate the need to trim the resistance value of the load resistor and shorten the testing time. [Means for solving the problem]

[0010] To achieve the above objective, the present invention A switched-capacitor amplifier comprising: an operational amplifier having two input terminals and an output terminal, one for positive polarity and one for negative polarity; a first capacitor element connected between a voltage input terminal and the negative polarity input terminal of the operational amplifier; a second capacitor element connected between the negative polarity input terminal and the output terminal of the operational amplifier; a switch element for accumulating charge in the first capacitor element in accordance with the voltage of the voltage input terminal in the first phase; and a switch element for transferring the charge accumulated in the first capacitor element to the second capacitor element in the second phase, The operational amplifier comprises a pair of differential input transistors and a pair of load elements connected in series with each of the pair of differential input transistors, and the positive input terminal is connected to a reference potential point. The pair of load elements but , Without trimming Set to have different resistance values This allows the operational amplifier to have a positive input offset voltage that is larger than the maximum value of the input offset voltage that is predetermined. It is structured in this way.

[0011] With a switched-capacitor amplifier having the above configuration, by pre-equipping the operational amplifier with a positive input offset voltage, it can be used even when the non-inverting input terminal of the operational amplifier is directly connected to ground, thus eliminating the need for a reference voltage circuit (reference voltage source). Furthermore, trimming of the load resistor's resistance value is unnecessary, which shortens the time required for the testing process, i.e., the testing time. [Effects of the Invention]

[0012] The switched-capacitor type amplifier according to the present invention eliminates the need for a reference voltage source. Furthermore, it eliminates the need to trim the resistance value of the load resistor, thus shortening the testing time. [Brief explanation of the drawing]

[0013] [Figure 1] This is a circuit diagram showing one embodiment of a switched-capacitor type amplifier to which the present invention is applied. [Figure 2]It is a circuit diagram showing a circuit configuration example of a differential input stage of an operational amplifier constituting a switch capacitor type amplifier according to an embodiment. [Figure 3] It is a waveform diagram showing an output voltage waveform of a switch capacitor type amplifier according to an embodiment. [Figure 4] (A) is a circuit configuration diagram showing a configuration example of a conventional general switch capacitor type amplifier, and (B) is a circuit configuration diagram showing a switch capacitor type amplifier to which a reference voltage circuit is added. [Figure 5] (A) is a waveform diagram showing an output voltage waveform of a switch capacitor type amplifier using an operational amplifier having a negative input offset voltage, and (B) is a waveform diagram showing an output voltage waveform of a switch capacitor type amplifier when a reference voltage is applied to the non-inverting input terminal of the operational amplifier.

Mode for Carrying Out the Invention

[0014] Hereinafter, preferred embodiments of the present invention will be described based on the drawings. FIG. 1 shows a circuit diagram of an embodiment of a switch capacitor type amplifier according to the present invention. As shown in FIG. 1, the switch capacitor type amplifier (hereinafter abbreviated as amplifier) of the present embodiment includes an operational amplifier (operational amplifier) AMP whose non-inverting input terminal is connected to a ground point (reference potential point), an input terminal IN to which an input signal VIN is input, a first switch element SW1 and a first capacitor element C1 connected in series between the inverting input terminal (-) of the operational amplifier AMP, and a second switch element SW2 connected between a connection node N1 between the first switch element SW1 and the first capacitor element C1 and the ground point.

[0015] Further, the amplifier of the present embodiment includes a third switch element SW3 connected between the inverting input terminal (-) and the output terminal OUT of the operational amplifier AMP, a second capacitor element C2 and a fourth switch element SW4 connected in series between the inverting input terminal (-) and the output terminal OUT of the operational amplifier AMP in parallel with the switch element SW3, and a third capacitor element C3 connected between the inverting input terminal (-) of the operational amplifier AMP and the ground point. SecondThe capacitive element C2 It includes a fifth switch element SW5 connected between the connection node N2 between the C2 and the fourth switch element SW4 and the ground point.

[0016] Among the above switch elements, the switch elements SW2 and SW4 with even signs are turned on and off by the sampling / hold clock signal φ, and the switch elements SW1, SW3, and SW5 with odd signs are turned on and off complementarily to the switch elements SW2 and SW4 by the signal / φ obtained by inverting the clock signal φ by the inverter INV. Specifically, during the sampling period (the first phase), as shown in FIG. 1(A), when the switch element SW1 is turned on and the switch element SW2 is turned off, the charge corresponding to the input signal VIN is accumulated in the first capacitive element C1. At this time, the operational amplifier AMP operates as a voltage follower when the switch element SW3 is turned on and the inverting input terminal (-) and the output terminal OUT are connected.

[0017] Then, during the hold period (the second phase), as shown in FIG. 1(B), when the switch elements SW1 and SW3 are turned off and the switch elements SW2 and SW4 are turned on, the stored charge in the first capacitive element C1 is transferred to the second capacitive element C2, and thus the signal VOUT obtained by amplifying the input signal VIN is output by the operational amplifier AMP. Note that the amplification factor (gain) of the circuit at this time is represented by the capacitance ratio C1 / C2 of the capacitive elements C1 and C2. The output voltage VOUT of the operational amplifier AMP that amplifies the input signal VIN is sampled by a subsequent circuit (for example, an A / D converter) not shown during the hold period (the second phase). Also, the charge transferred to the second capacitive element C2 is reset when the switch elements SW3 and SW5 are turned on during the next sampling period (the first phase).

[0018] Furthermore, in the amplifier of the present embodiment, the operational amplifier AMP is configured to have a positive input offset voltage even with manufacturing variations. Hereinafter, a specific example of an operational amplifier having such characteristics will be described. Figure 2 shows a specific circuit example of an operational amplifier (AMP). The operational amplifier AMP shown in Figure 2 comprises a P-channel type MOS transistor (insulated-gate field-effect transistor) M1 whose gate terminal is connected to the non-inverting input terminal IN+, and a MOS transistor M2 whose gate terminal is connected to the inverting input terminal IN-. The source terminals of transistors M1 and M2 are coupled to each other, and they operate as differential input transistors.

[0019] Furthermore, a MOS transistor M3 is connected between the common source terminals of differential input transistors M1 and M2 and the circuit's power supply voltage terminal VCC, and load resistors R1 and R2 are connected between the drain terminals of differential input transistors M1 and M2 and the ground point, respectively. Transistor M3 is a P-channel type and is configured to operate as a constant current source when a ground potential is applied to its gate terminal.

[0020] Furthermore, in the circuit shown in Figure 2, the resistance values ​​of the load resistors R1 and R2 are pre-set so that the operational amplifier will have a positive input offset voltage even if the maximum input offset voltage expected due to manufacturing variations occurs. Specifically, the resistance ratio of resistors R1 and R2 is designed to be 9 / 10. Now, let's explain why the resistance ratio of resistors R1 and R2 is set to 9 / 10.

[0021] First, the inventors empirically knew that the maximum input offset voltage that can be expected due to manufacturing variations differs depending on the process and power supply voltage used, but in the case of an operational amplifier manufactured using a general MOS manufacturing process with a power supply voltage of 1.8 to 5V, the maximum input offset voltage is 5mV. Also, in the case of an operational amplifier with a circuit configuration as shown in Figure 2, the resistance values ​​of the load resistors R1 and R2 are generally several tens of kΩ.

[0022] On the other hand, although Figure 2 shows load resistors R1 and R2 as single elements, it is also possible to use multiple resistor elements (unit resistance elements) connected in series, each having a predetermined resistance value. By adopting this method of arranging multiple unit resistance elements to form a single resistor with a desired resistance value, although the possible resistance values ​​are limited, there are advantages such as easier element layout design and greater layout flexibility when forming circuits on semiconductor chips.

[0023] Therefore, in the operational amplifier AMP shown in Figure 2, the load resistors R1 and R2 are constructed using multiple unit resistance elements with the design method described above. We investigated the conditions under which the input offset voltage would be positive even if the maximum input offset of 5mV, which is expected when R1 and R2 have the same resistance value, occurs. As a result, we derived that if the resistance ratio of resistors R1 and R2 is set to (9 / 10) or less, the input offset voltage will be positive. For example, to set the resistance ratio to 9 / 10, resistors R1 and R2 should be constructed by connecting 9 and 10 unit resistors in series, respectively.

[0024] Next, the operation of the switched-capacitor type amplifier 10 shown in Figure 1, which is equipped with the operational amplifier configuration shown in Figure 2, will be explained using the waveform diagram shown in Figure 3. In the amplifier of this embodiment, as described above, the operational amplifier AMP is set to have a positive input offset voltage that is larger than the maximum value of the input offset voltage that is assumed in advance. Therefore, during the sampling period (first phase) when the switch elements SW2 and SW4 are off and SW1, SW3 and SW5 are on, a charge corresponding to the input voltage VIN is accumulated in the capacitive element C1.

[0025] Furthermore, when the switch element SW3 is turned on, the operational amplifier AMP operates as a voltage follower, so as shown in Figure 3, during the sampling period, the output voltage VOUT is at the same potential as the apparent input offset voltage Voff (always positive). Here, the apparent input offset voltage is the difference or sum of the positive input offset voltage intentionally added due to the imbalance of load resistors R1 and R2 and the input offset voltage actually generated due to variations in the manufacturing process. If the input offset voltage varies in the negative direction during the manufacturing process, it becomes a difference; if the input offset voltage varies in the positive direction, it becomes a sum.

[0026] Next, during the hold period (second phase) when switch elements SW1, SW3, and SW5 are in the off state and SW2 and SW4 are in the on state, the charge accumulated in capacitive element C1 is transferred to capacitive element C2, causing the output voltage VOUT to increase to (C1 / C2) times the input voltage VIN. VOUT = VIN × C1 / C2 This is the result. Furthermore, during this hold period, the charge transfer occurs relative to the ground potential due to the switching element SW2 being turned on, so the input offset voltage of the operational amplifier AMP is not involved. In other words, the output voltage VOUT is not affected by the input offset voltage Voff.

[0027] As explained above, the switched-capacitor amplifier of this embodiment has a positive input offset voltage pre-installed in the operational amplifier AMP, eliminating the need for post-manufacturing adjustment (trimming) of the load resistors R1 and R2, thus shortening the time required for the inspection process. Furthermore, because the input offset voltage of the operational amplifier AMP is always positive, it can be used even when the non-inverting input terminal of the operational amplifier AMP is connected to ground. This eliminates the need for the reference voltage VREF and reference voltages VREF1 and VREF2 required by the switched-capacitor type amplifier described in Figure 4(B) and Patent Document 2. As a result, there is no need to provide a reference voltage circuit (reference voltage source), and if the amplifier is formed as a semiconductor integrated circuit on a semiconductor chip, it has the advantage of reducing the chip size.

[0028] Although the present inventors' invention has been described in detail above based on embodiments, the present invention is not limited to the above embodiments. For example, in the above embodiments, it was described that a plurality of resistor elements having a unit resistance value are connected in series as the load resistors R1 and R2 constituting the operational amplifier AMP, but a plurality of resistor elements having a unit resistance value may be connected in parallel to constitute load resistors R1 and R2 with a desired resistance value. Alternatively, instead of composing the load resistors R1 and R2 with a plurality of unit resistance elements, they may be formed as single resistor elements having a predetermined resistance ratio (9 / 10) or less.

[0029] Furthermore, although the above embodiment described a standalone switched-capacitor amplifier circuit, the switched-capacitor amplifier of this embodiment can be used, for example, in an AD converter. In that case, the AD conversion circuit section of the AD converter may also be configured as a switched-capacitor circuit. [Explanation of Symbols]

[0030] AMP... Operational amplifier (op-amp), SW1~SW5... Switching elements, C1~C4... Capacitors, M1, M2... Differential input transistors, M3... Constant current transistor, R1, R2... Load resistors

Claims

1. A switched-capacitor amplifier comprising: an operational amplifier having two input terminals and an output terminal, one for positive polarity and one for negative polarity; a first capacitor element connected between a voltage input terminal and the negative polarity input terminal of the operational amplifier; a second capacitor element connected between the negative polarity input terminal and the output terminal of the operational amplifier; a switch element for accumulating charge in the first capacitor element in accordance with the voltage of the voltage input terminal in the first phase; and a switch element for transferring the charge accumulated in the first capacitor element to the second capacitor element in the second phase, The operational amplifier comprises a pair of differential input transistors and a pair of load elements connected in series with each of the pair of differential input transistors, and the positive input terminal is connected to a reference potential point. A switched-capacitor amplifier characterized in that the pair of load elements are set to have different resistance values ​​without trimming, thereby providing the operational amplifier with a positive input offset voltage that is larger than the maximum value of the input offset voltage that is predetermined.

2. The switched-capacitor amplifier according to claim 1, characterized in that one input terminal of the operational amplifier is configured such that a reference voltage source does not need to be connected.

3. The switched-capacitor amplifier according to claim 1 or 2, characterized in that the ratio of the resistance value of the load element connected to the differential input transistor on the positive input terminal side to the resistance value of the load element connected to the differential input transistor on the negative input terminal side is set to (9 / 10) or less.

4. The switched-capacitor type amplifier according to any one of claims 1 to 3, characterized in that the pair of load elements are configured by connecting a plurality of unit resistance elements, each having a predetermined resistance value, in series or in parallel.

5. An AD converter characterized by comprising a switched-capacitor type amplifier according to any one of claims 1 to 4.

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