SAR ADC circuit for temperature sensor

Abstract

Disclosed in the present invention is a SAR ADC circuit for a temperature sensor. The circuit comprises a CDAC array, a comparator, an SAR logic module, and a temperature mode switching circuit. A front-end temperature sensor utilizes the temperature characteristics of a base-emitter voltage of a triode to generate a dual-ended voltage, a voltage difference of which varies linearly with temperature. In the present invention, by means of a SAR ADC structure, an inherent offset voltage of the temperature-sensing front-end circuit is first compensated for, and then the difference of the dual-ended voltage, generated by the front-end temperature sensor and varying with temperature, is converted into an 8-bit binary digital signal. A temperature signal is represented by the quantized digital signal. In the present invention, a temperature range quantized by the ADC is changed by switching a reference voltage module of the ADC. In the present invention, for every 1°C change in temperature, the difference of the dual-ended output voltage of the temperature sensor changes by 0.0039V; and one LSB value of the SAR ADC is also 0.0039V. That is, a unit output digital signal change of the SAR ADC corresponds to a 1°C temperature change, effectively improving the efficiency of temperature quantization.

Description

A SAR ADC circuit for temperature sensors Technical Field

[0001] This invention relates to the field of analog-to-digital converter technology, and more specifically, to a SAR ADC circuit for temperature sensors. Background Technology

[0002] An analog-to-digital converter (ADC) is an electronic device that converts analog signals into digital signals. This conversion is crucial for modern electronic systems because digital electronic devices (such as computers, smartphones, and digital signal processors) can only process digital signals. ADC technology has continuously advanced with the development of electronic technology. Early ADCs had slow conversion speeds and low accuracy. With the development of semiconductor technology, modern ADCs can perform conversions very quickly and accurately. The classification and advantages / disadvantages of ADCs are as follows: Successive approximation (SAR), integrating, and voltage-to-frequency conversion ADCs are mainly used in medium-speed or low-speed, medium-precision data acquisition and intelligent instruments. Hierarchical and pipelined ADCs are mainly used in high-speed transient signal processing, fast waveform storage and recording, high-speed data acquisition, video signal quantization, and high-speed digital communication technologies.

[0003] Temperature, as one of the most important physical quantities in daily life, is closely related to human production and life, and accurate temperature measurement is of great significance. Uneven temperature distribution within a chip can lead to overall chip malfunctions, making it essential to place a temperature sensor within the chip to monitor temperature. The ADC (Analog Converter) is responsible for processing the analog voltage signal generated by the temperature sensor that changes with temperature. Since various temperature sensors differ, and the signals they generate also differ, existing ADCs cannot adequately meet the output voltage requirements of temperature sensor applications. Furthermore, most chips operate within a range of -40℃ to 125℃. How to design a system with sufficient margin so that even if the temperature deviates from this range, a relatively accurate temperature value can still be read by the ADC is also a problem that ADCs designed for temperature sensors need to solve. Summary of the Invention

[0004] The purpose of this invention is to design a SAR ADC circuit for temperature sensors. This circuit can process and quantify the temperature-related two-terminal signal generated by the temperature sensor, thereby outputting temperature values ​​over a wider temperature range with greater accuracy, and better meeting the needs of practical applications.

[0005] This invention provides a SAR ADC circuit for temperature sensors, comprising: 1. a SAR ADC circuit for temperature sensors, characterized in that it includes:

[0006] A CDAC array is used to receive differential input signals from a temperature sensor, including 8-bit capacitance values ​​configured based on binary weights, namely C0, C0, 2C0, 4C0, 8C0, 16C0, 32C0, and 64C0; where each capacitance value corresponds to a CDAC unit module; and C0 is the unit capacitance.

[0007] A comparator, including a preamplifier and a latch, is used to compare voltage signals from the CDAC array and output the comparison result;

[0008] SAR logic is used to control the CDAC array and the comparator to perform a successive approximation process to generate a digital output representing temperature; the SAR logic includes: a sampling signal generation module, a timing generation module, and a result transmission module;

[0009] A temperature mode switching circuit is used to select different operating modes based on the output signal of the temperature sensor, wherein the different operating modes are used to adapt to different temperature ranges.

[0010] As an optional implementation, the CDAC array consists of two identical 8-bit capacitor arrays, respectively connected to both ends of the comparator;

[0011] Each bit capacitor of the CDAC array is set to an initial state by a preset voltage during the conversion stage, which reduces the number of successive approximation comparison steps and the number of capacitors required.

[0012] Applying a preset voltage to the highest bit capacitor is equivalent to setting the highest bit to 1, and applying preset voltages to the remaining bits of the capacitor sequentially until the lowest bit.

[0013] During the least significant bit comparison, a partial preset voltage is applied to the corresponding capacitor.

[0014] As an optional implementation, the SAR logic is further used for:

[0015] It generates the clock and control signals required by the circuit to control the operation of the CDAC array during the sampling and conversion process;

[0016] Perform an initial comparison to determine the value of the most significant bit;

[0017] Based on the comparator's output, the reference voltage is switched, and the remaining bits are compared and assigned values ​​sequentially.

[0018] As an optional implementation, the timing generation module includes:

[0019] Multiple D flip-flops connected in sequence, each D flip-flop having a data input terminal, a clock input terminal, a data output terminal, an inverted output terminal, and a reset terminal;

[0020] The reset terminal is connected to the inverse signal of the sampling control signal. When the inverse signal is low, the D flip-flop is reset and no data transmission is performed; when the inverse signal is high, the D flip-flop operates normally.

[0021] Under normal operating conditions, the rising edge of the clock signal sequentially triggers each D flip-flop, causing:

[0022] The first D flip-flop transmits a high level to the first control signal output on the first rising edge of the clock signal and maintains a high level state.

[0023] On each subsequent rising edge of the clock, the following D flip-flops sequentially pass the high level of the previous control signal output to the next control signal output, until all control signal outputs are high, until the next reset signal arrives;

[0024] Through the above steps, the timing generation module generates control signals that are triggered sequentially, which are used for comparison and assignment of each bit during the successive approximation process.

[0025] As an optional implementation, the result transmission module includes:

[0026] Multiple independent D flip-flops, each with a data input, clock input, data output, inverted output, and reset terminal;

[0027] The reset terminal is connected to the inverse signal of the sampling control signal. When the inverse signal is low, the D flip-flop is reset and no data transmission is performed; when the inverse signal is high, the D flip-flop operates normally.

[0028] During the period when the inverse signal is high, the clock signals generated during the successive approximation process are sequentially connected to the clock inputs of each D flip-flop, such that:

[0029] As the rising edge of the clock signal arrives sequentially, the data signal input terminal of the D flip-flop reads the output signal of the comparator in sequence, which is used to realize the transmission and storage of SAR ADC results.

[0030] As an optional implementation, the temperature mode switching circuit comprises: two modules that generate different reference voltages, wherein each module generating the reference voltage includes:

[0031] The enable signal input terminal is used to control the working status of the module;

[0032] When the enable signal is at the first level, the module works normally and generates the corresponding reference voltage; when the enable signal is at the second level, the module stops working.

[0033] An operational amplifier is used to clamp the voltage at the positive input terminal to a preset reference voltage.

[0034] A control switch is used to control the activation of two reference voltage generation modules based on the mode selection signal, so as to provide different reference voltages to adapt to different temperature measurement ranges.

[0035] As an optional implementation, the temperature mode switching switch includes:

[0036] The comparator has a non-inverting input connected to a preset reference voltage and an inverting input connected to the output signal of a temperature sensor. It also has an enable input. When the enable signal is at the first level, the comparator operates normally; when the enable signal is at the second level, the comparator stops operating.

[0037] A D flip-flop, whose set terminal is connected to a fixed level and is always in normal working condition, and whose clock input terminal is connected to the clock signal generated by the logic circuit.

[0038] When the output signal of the temperature sensor is higher than the preset reference voltage, the comparator outputs the first logic level, and the D flip-flop transmits this logic level as a mode selection signal on the rising edge of the clock signal, controlling the temperature mode to the first mode; when the output signal is lower than the reference voltage, the comparator outputs the second logic level, controlling the temperature mode to the second mode.

[0039] As an optional implementation, the common-mode voltage remains constant in both temperature modes to provide a stable operating point;

[0040] The difference in the initial reference voltage is adjusted based on the selected temperature mode to compensate for the inherent offset voltage of the temperature sensor and to preset the voltage of the highest-order capacitor.

[0041] As an optional implementation, it also includes:

[0042] In the second temperature mode, the difference in the initial reference voltage is reduced by a predetermined voltage value relative to the first temperature mode, corresponding to a specific temperature range;

[0043] When the capacitor modules are connected to the adjusted reference voltage, it is equivalent to applying additional voltage compensation to the capacitors to extend the range of temperature measurement.

[0044] As an alternative implementation, during the successive approximation process, when determining the value of each bit capacitor, the preset voltage of the current bit is directly eliminated by adjusting the reference voltage to replace the initial reference voltage, and the value is assigned based on the result of the comparator.

[0045] Compared with the prior art, the beneficial effects of the present invention include:

[0046] First, this invention designs a temperature mode switching circuit with a voltage difference of 0.25V between the two modes. The voltage of 0.25V corresponds to 64℃, that is, in mode 1, -42℃ corresponds to 00000000 in an 8-bit digital signal, while in mode 2, -106℃ corresponds to 00000000 in an 8-bit digital signal. The temperature mode switching circuit contains a switch. When the temperature is less than 60℃, mode 2 is used, and when the temperature is greater than 60℃, mode 1 is used. The mode switching operation widens the operating temperature range of the chip.

[0047] Secondly, traditional 8-bit SAR ADC designs typically contain 9-bit capacitors, requiring 256 unit capacitors on one side. The first 8 bits are used for comparison and feedback reset, while the least significant bit only serves to provide voltage. In contrast, the 8-bit SAR ADC module designed in this invention uses a pre-set method, employing only 128 unit capacitors, saving half the area of ​​the capacitor array while achieving the same effect.

[0048] In summary, this invention can effectively perform temperature detection over a wider temperature range, and compared to traditional SAR ADC structures, it has a significantly smaller area, making it valuable for practical applications. Attached Figure Description

[0049] Figure 1 is a circuit structure diagram of a SAR ADC for temperature sensors provided in an embodiment of this disclosure;

[0050] Figure 2 is a CDAC array circuit diagram provided in an embodiment of this disclosure;

[0051] Figure 3 is a circuit diagram and simulation results of a timing generation module provided in an embodiment of this disclosure;

[0052] Figure 4 is a circuit diagram of a result output module provided in an embodiment of this disclosure;

[0053] Figure 5 is a circuit diagram of a module for generating different reference voltages provided in an embodiment of this disclosure;

[0054] Figure 6 is a circuit diagram of a temperature mode switching switch provided in an embodiment of this disclosure. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. The components of the embodiments of the present disclosure described and illustrated herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure is not intended to limit the scope of the present disclosure claimed, but merely represents selected embodiments of the present disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative efforts belong to the scope of protection of the present disclosure.

[0056] The present invention discloses a SAR ADC circuit for a temperature sensor. Please refer to FIG. 1, which is a structural diagram of a SAR ADC circuit for a temperature sensor provided by an embodiment of the present disclosure.

[0057] Among them, cdac is a CDAC array;

[0058] SAR_comp is a comparator in the entire SAR ADC circuit, responsible for comparing the input signal during the successive approximation process. SAR_comp includes a preamplifier and a latch to achieve high-precision and high-speed comparison functions. Among them, compp receives the voltage signal from the positive end of the CDAC array (i.e., the signal after the positive output of the temperature sensor is processed by the CDAC), and compn receives the voltage signal from the negative end of the CDAC array (i.e., the signal after the negative output of the temperature sensor is processed by the CDAC); abc_en is a control signal used to enable or disable the target module; the vcm port in the comparator is used to receive the common-mode voltage signal, provide a reference voltage for the differential input signal, and guide the signals at the comparator input terminals compp and compn to a stable operating point. By comparing the differential input signal with respect to vcm, the common-mode noise of the input signal can be effectively reduced, and the symmetry of the input signal can be maintained.

[0059] In a specific implementation, when compp > compn, the output comp_out is high, and when compp < compn, the output comp_out is low;

[0060] SAR_logic is SAR logic, including a sampling signal generation module, a timing generation module, and a result transmission module, responsible for generating the clock signals required for the entire circuit;

[0061] The system includes the following modules: **Sampling Signal Generation Module:** This module generates control signals for the CDAC array to sample. When the sampling signal is high, the CDAC array samples the differential input signal; when the sampling signal is low, sampling ends, and the capacitor maintains the sampled voltage. **Timing Generation Module:** This module generates timing signals for the successive approximation logic control based on the input clock signal. The clock signal controls the timing of each comparator's output, ensuring that the successive approximation comparison results are transmitted on time. **Result Transmission Module:** This module receives the digital signals output by the comparators and sequentially transmits the 8-bit successive approximation results to the D flip-flops for storage. After successive approximation is complete, the 8-bit digital signal is output through the `dout<7:0>` port to represent the temperature sensor's measurement results.

[0062] The input data port (d<7:0>) receives the comparison result signal output by the comparator during the successive approximation process. This port receives one bit of the comparison result at a time, ultimately forming an 8-bit digital signal representing the quantized temperature value of the temperature sensor. The control signal port (set<7:0>) controls the successive approximation logic, sequentially assigning and comparing values ​​to each bit to ensure step-by-step processing from the most significant bit to the least significant bit, ultimately determining the 8-bit digital signal. The output data port (dout<7:0>) outputs the final 8-bit digital signal after the successive approximation is complete, representing the quantized output result of the temperature sensor. The sampling control signal port controls the sampling process. When sample is high, the CDAC array samples the input signal; when sample is low, sampling ends, and the successive approximation comparison stage begins. The clock signal port (clk) controls the timing of the successive approximation process. Each time the rising edge of the clock signal arrives, the SAR_logic module controls the comparator to perform bit-level comparisons, determining the value of the digital signal bit by bit.

[0063] Vref_gen_adc_choice is a temperature mode switching circuit used in the SAR ADC circuit of this invention to generate and switch different reference voltages. This module ensures accurate temperature signal quantization by the SAR ADC across different temperature ranges by providing different reference voltages. The design of this module extends the temperature measurement range and improves measurement accuracy through mode switching.

[0064] gen_choice is a temperature mode switching switch. By comparing inn with the 1.8V reference voltage, it outputs the Vref_sel signal to the temperature mode switching circuit, and switches between the two temperature modes by the high and low values ​​of the Vref_sel signal.

[0065] Please refer to Figure 2, which is a CDAC array circuit diagram provided in an embodiment of this disclosure.

[0066] The specific structure of the CDAC array at the inn end of the receiving signal is shown in Figure 2. The structure of the CDAC array at the inp end of the receiving signal is the same as that in Figure 2, except that all the inverting input signals are switched to the non-inverting inputs. Taking C0 as the unit capacitor, the 8-bit capacitor values ​​of C0 to C7 are C0, C0, 2C0, 4C0, 8C0, 16C0, 32C0, and 64C0, respectively. The upper and lower plates of capacitors C0 to C6 are the same as those of C7. The full-scale voltage range of the capacitor array is 1V, so when the corresponding digital signal is set to 1, the voltage values ​​of C7 to C0 are 0.5V, 0.25V, 0.125V, 0.0625V, 0.03125V, 0.015625V, 0.0078125V, and 0.0078125V, respectively. Each capacitor corresponds to one CDAC unit module. When the sampling control signal sample is high, the upper plate of the capacitor is connected to the input signal V. in The lower electrode is connected to the common-mode signal V. CM When the sampling control signal goes low, the lower plate floats, and charge is conserved. The upper plate then becomes connected to V. CMN At this time, the potential of the lower plate is V. CM -V in +V CMN When the voltage difference between the two terminals of the front-end temperature sensor is 1V, the corresponding temperature is -42℃. For every 1℃ change, the voltage changes by 0.0039V. CMP The voltage is 2.5V + 0.5V + 0.25V, V CMN The voltage range is 2.5V-0.5V-0.25V. CMP -V CMN The 1V difference can offset the difference in the temperature sensor output voltage at -42℃, and the additional 0.5V can be considered equivalent to the preset highest-order capacitor being high. When comparing at this point, if the comparator output is high, i.e., V... CM -V ip +V CMP >V CM -V in +V CMN Then switch to V CMP For V refph , to V CMN For V refnl If the comparator output is low, i.e., V CM -V ip +V CMP <V CM -V in +V CMN Then switch to V CMP For V refpl , to V CMN For V refnh ;

[0067] After the above operations are completed, it is equivalent to the highest bit being set to 1 or 0. At this point, only the last seven capacitors have a preset voltage of 0.5V, which is equivalent to setting the second capacitor to 1. Then, the remaining seven capacitors are compared and assigned values ​​in sequence. In addition, after the seventh bit is assigned a value, the preset voltage of 0.5V is only applied to the last capacitor, which is equivalent to preset half of the voltage value of the last bit, that is, 0.0039V, thereby completing the comparison and assignment of the eighth bit, and thus achieving a voltage accuracy of 1°C.

[0068] Thus, compared with the traditional 8-bit SAR ADC, the present invention adopts a preset method, which requires only 128 unit capacitors at one end, saving the area of ​​the capacitor array.

[0069] Please refer to Figure 3, which is a circuit diagram and simulation results of a timing generation module provided in an embodiment of this disclosure;

[0070] As an optional implementation, the timing generation module may include eight identical D flip-flops, where the d terminal is the signal input terminal, the clk terminal is the clock input terminal, the q terminal is the data output terminal, the qn terminal is the logic opposite to the q terminal, and the nr terminal is the reset terminal of the D flip-flops;

[0071] Based on the simulation results of the clock signal in Figure 3, it can be seen that the sampleb signal is the inverted version of the sample signal. The sampleb signal is connected to the nr terminal. When the sampleb signal is low, the D flip-flop is reset and does not perform data transmission. When the sampleb signal is high, the D flip-flop works normally. Within the high-frequency range of the sampleb signal, when the rising edge of the clock clk_sar signal arrives, the first D flip-flop transmits the power supply voltage avdd to the set. <7> This makes set after this moment <7> Stay high; when the next rising edge of the clock arrives, the second D flip-flop will set. <7> The high voltage is transmitted to the set <6> until passed to set <0> The set<7:0> array is set to high until the next reset signal arrives; the logic result for generating the clock signal is shown in Figure 3.

[0072] Please refer to Figure 4, which is a circuit diagram of a result transmission module provided in an embodiment of this disclosure. As an optional implementation, the result transmission module includes eight identical and independent D flip-flops, where the d terminal is the signal input terminal, the clk terminal is the clock input terminal, the q terminal is the data output terminal, the qn terminal is the logical opposite of the q terminal, and the nr terminal is the reset terminal of the D flip-flops. The sampleb signal is the inverted version of the sample signal and is connected to the nr terminal. When the sampleb signal is low, the D flip-flops are reset and do not perform data transmission. When the sampleb signal is high, the D flip-flops can work normally. In the interval where the sampleb signal is high, as shown in Figure 3, set<7:0> are eight clock signals that arrive sequentially at the rising edge of the clock. Set<7:0> is connected to the clock signal terminals of the eight D flip-flops respectively. Therefore, as the rising edge of the clock set<7:0> arrives sequentially, d<7:0> also reads the output signal of the comparator at the rising edge of the clock sequentially, realizing the transmission of the SAR ADC result.

[0073] Please refer to Figure 5, which is a circuit diagram of a module for generating different reference voltages provided in an embodiment of this disclosure. The temperature mode switching circuit in this disclosure includes two modules for generating different reference voltages and a control switch. As an optional implementation, one of the modules for generating different reference voltages is shown in Figure 5. The en signal can control whether this module generates a reference voltage. If the en signal is high, transistor Q2 is turned off, and the circuit works normally. If the en signal is low, transistor Q2 is turned on, and the gates of transistors Q1 and Q3 are raised to Vdd, while transistors Q1 and Q3 are turned off, and the circuit does not work. When the en signal is high, the operational amplifier Vr... ef_op clamps the voltage at the positive input terminal to a reference voltage of 1.2V. At this time, the current flowing through R1 and R2 is determined by the resistance value of R2. Q1 and Q3 have the same width and length, forming a current mirror, copying the current to the Q3 branch. The resistors have the following relationship: R1+R2=R3+R4+R5+R6+R7+R8+R9+R10. The voltage division value is proportional to the resistance value. By designing the resistance values ​​of R3~R10, the desired voltages vrefph, vcmp, vrefpl, vcm, vrefnh, Vref_1p8, vcmn, and vrefnl can be obtained relatively accurately.

[0074] Furthermore, the two modules that generate reference voltages operating in different temperature ranges differ in that they produce different values ​​of vrefph, vcmp, vrefpl, vrefnh, vcmn, and vrefnl, which translates to different resistance values ​​for R3 to R10 in the circuit.

[0075] Please refer to Figure 6, which is a temperature mode switching switch circuit diagram provided in an embodiment of this disclosure. As an optional implementation, the control switch of the temperature mode switching circuit can consist of a comparator and a D flip-flop. The en terminal is connected to the en_temp signal, which is the enable terminal of the comparator. When the en_temp signal is low, the comparator does not work; when the en_temp signal is high, the comparator works normally. The non-inverting terminal of the comparator is connected to the Vref_1p8 signal, i.e., the 1.8V reference voltage, and the inverting terminal of the comparator is connected to the inn signal generated by the temperature sensor. The set terminal of the D flip-flop is always vdd, and the D flip-flop always works normally. The clk_temp signal is the clock signal generated by the logic in the circuit. The comparator will generate a rising edge after the temperature sensor output stabilizes. When the rising edge of the clk_temp signal arrives, the comparator's result is sent to Vref_sel. inn is temperature-dependent; the higher the temperature, the lower the inn signal value. Based on the properties of the pre-sensor temperature sensor, when the temperature is below 60℃, the inn signal is greater than 1.8V, and when the temperature is above 60℃, the inn signal is less than 1.8V. When the inn signal is greater than 1.8V, the comparator generates a logic low, which is then transmitted to the Vref_sel signal, thereby controlling the temperature mode to mode 1. When the inn signal is less than 1.8V, the comparator generates a logic high, which is then transmitted to the Vref_sel signal, thereby controlling the temperature mode to mode 2.

[0076] In both modes, V CM It is constantly at 2.5V, providing a stable quiescent operating point; in mode 1, V CMP -V CMN The voltage is 1.5V, so the capacitor module is connected to V respectively. CMP and V CMN At this time, it can both cancel the inherent offset voltage of 1V of the temperature sensing pre-amplifier circuit and preset the highest level capacitor to 1; Mode 2's V CMP -V CMN The voltage is 1.25V, and the voltage of Mode 2 is higher than that of Mode 1. CMP -V CMN The voltage was reduced by 0.25V. This 0.25V voltage corresponds to 64℃. In Mode 2, the capacitor module is connected to V... CMP and V CMN At the same time, in addition to canceling the inherent offset voltage of 1V of the temperature sensing pre-stage circuit and setting the highest level capacitor to 1, it is also equivalent to connecting a voltage of -0.25V to the upper plate of the single-ended 8-bit capacitor. The 0.25V voltage can quantize a temperature range of 64℃; that is, in mode 1, -42℃ corresponds to 00000000 in the 8-bit digital signal, while in mode 2, -106℃ corresponds to 00000000 in the 8-bit digital signal, thus widening the operating temperature range of the chip.

[0077] In both modes, Vrefph V CMP 0.25V high, V refpl V CMP 0.25V lower, V refnh V CMN 0.25V high, V refnl V CMN A voltage 0.25V lower, when the timing process reaches the point of determining whether a certain stage capacitor is set to 1 or 0, V... refph or V refpl Replace V CMP V refnh or V refnl Replace V CMN The preset voltage of the current stage can be directly canceled, and the current stage value can be assigned based on the comparator result. The temperature mode switching circuit contains a switch. When the temperature is less than 60℃, mode 2 is used, and when the temperature is greater than 60℃, mode 1 is used. That is, the temperature mode used in different temperature ranges can be controlled in the above way, thereby greatly expanding the temperature range that the SAR ADC can detect, which has good practical application value.

[0078] Finally, it should be noted that the above-described embodiments are merely specific implementations of this disclosure, used to illustrate the technical solutions of this disclosure, and not to limit it. The protection scope of this disclosure is not limited thereto. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this disclosure. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure, and should all be covered within the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be determined by the protection scope of the claims.

Claims

1. A SAR ADC circuit for temperature sensors, characterized in that, include: A CDAC array is used to receive differential input signals from a temperature sensor, including 8-bit capacitance values ​​configured based on binary weights, namely C0, C0, 2C0, 4C0, 8C0, 16C0, 32C0, and 64C0; where each capacitance value corresponds to a CDAC unit module; and C0 is the unit capacitance. A comparator, including a preamplifier and a latch, is used to compare voltage signals from the CDAC array and output the comparison result; SAR logic is used to control the CDAC array and the comparator to perform a successive approximation process to generate a digital output representing temperature; the SAR logic includes: a sampling signal generation module, a timing generation module, and a result transmission module; A temperature mode switching circuit is used to select different operating modes based on the output signal of the temperature sensor, wherein the different operating modes are used to adapt to different temperature ranges.

2. The SAR ADC circuit for temperature sensors according to claim 1, characterized in that, The CDAC array consists of two identical 8-bit capacitor arrays, which are connected to the two ends of the comparator respectively. Each bit capacitor of the CDAC array is set to an initial state by a preset voltage during the conversion stage, which reduces the number of successive approximation comparison steps and the number of capacitors required. Applying a preset voltage to the highest bit capacitor is equivalent to setting the highest bit to 1, and applying preset voltages to the remaining bits of the capacitor sequentially until the lowest bit. During the least significant bit comparison, a partial preset voltage is applied to the corresponding capacitor.

3. The SAR ADC circuit for temperature sensors according to claim 1, characterized in that, The SAR logic is also used for: It generates the clock and control signals required by the circuit to control the operation of the CDAC array during the sampling and conversion process; Perform an initial comparison to determine the value of the most significant bit; Based on the comparator's output, the reference voltage is switched, and the remaining bits are compared and assigned values ​​sequentially.

4. The SAR ADC circuit for temperature sensors according to claim 1, characterized in that, The timing generation module includes: Multiple D flip-flops connected in sequence, each D flip-flop having a data input terminal, a clock input terminal, a data output terminal, an inverted output terminal, and a reset terminal; The reset terminal is connected to the inverse signal of the sampling control signal. When the inverse signal is low, the D flip-flop is reset and no data transmission is performed; when the inverse signal is high, the D flip-flop operates normally. Under normal operating conditions, the rising edge of the clock signal sequentially triggers each D flip-flop, causing: The first D flip-flop transmits a high level to the first control signal output on the first rising edge of the clock signal and maintains a high level state. On each subsequent rising edge of the clock, the following D flip-flops sequentially pass the high level of the previous control signal output to the next control signal output, until all control signal outputs are high, until the next reset signal arrives; Through the above steps, the timing generation module generates control signals that are triggered sequentially, which are used for comparison and assignment of each bit during the successive approximation process.

5. The SAR ADC circuit for temperature sensors according to claim 1, characterized in that, The result transmission module includes: Multiple independent D flip-flops, each with a data input, clock input, data output, inverted output, and reset terminal; The reset terminal is connected to the inverse signal of the sampling control signal. When the inverse signal is low, the D flip-flop is reset and no data transmission is performed; when the inverse signal is high, the D flip-flop operates normally. During the period when the inverse signal is high, the clock signals generated during the successive approximation process are sequentially connected to the clock inputs of each D flip-flop, such that: As the rising edge of the clock signal arrives sequentially, the data signal input terminal of the D flip-flop reads the output signal of the comparator in sequence, which is used to realize the transmission and storage of SAR ADC results.

6. The SAR ADC circuit for temperature sensors according to any one of claims 1-5, characterized in that, The temperature mode switching circuit includes two modules that generate different reference voltages, wherein each module generating the reference voltage includes: The enable signal input terminal is used to control the working status of the module; When the enable signal is at the first level, the module works normally and generates the corresponding reference voltage; when the enable signal is at the second level, the module stops working. An operational amplifier is used to clamp the voltage at the positive input terminal to a preset reference voltage. A control switch is used to control the activation of two reference voltage generation modules based on the mode selection signal, so as to provide different reference voltages to adapt to different temperature measurement ranges.

7. The SAR ADC circuit for temperature sensors according to claim 6, characterized in that, The temperature mode switching switch includes: The comparator has a non-inverting input connected to a preset reference voltage and an inverting input connected to the output signal of a temperature sensor. It also has an enable input. When the enable signal is at the first level, the comparator operates normally; when the enable signal is at the second level, the comparator stops operating. A D flip-flop, whose set terminal is connected to a fixed level and is always in normal working condition, and whose clock input terminal is connected to the clock signal generated by the logic circuit. When the output signal of the temperature sensor is higher than the preset reference voltage, the comparator outputs the first logic level, and the D flip-flop transmits this logic level as a mode selection signal on the rising edge of the clock signal, controlling the temperature mode to the first mode; when the output signal is lower than the reference voltage, the comparator outputs the second logic level, controlling the temperature mode to the second mode.

8. The SAR ADC circuit for temperature sensors according to claim 7, characterized in that, In both temperature modes, the common-mode voltage remains constant to provide a stable operating point; The difference in the initial reference voltage is adjusted based on the selected temperature mode to compensate for the inherent offset voltage of the temperature sensor and to preset the voltage of the highest-order capacitor.

9. The SAR ADC circuit for temperature sensors according to claim 8, characterized in that, Also includes: In the second temperature mode, the difference in the initial reference voltage is reduced by a predetermined voltage value relative to the first temperature mode, corresponding to a specific temperature range; When the capacitor modules are connected to the adjusted reference voltage, it is equivalent to applying additional voltage compensation to the capacitors to extend the range of temperature measurement.

10. The SAR ADC circuit for temperature sensors according to claim 9, characterized in that, During the successive approximation process, when determining the value of the capacitance at each bit, the preset voltage of the current bit is directly eliminated by adjusting the reference voltage to replace the initial reference voltage, and the value is assigned based on the result of the comparator.

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