Gate drive device and gate drive system

Abstract

This gate drive device operates on two sides, a high side and a low side, and drives the gate of a power transistor. The gate drive device comprises: control devices that are provided in a pair to configure two sides, and that output three or more levels of switching signals including a high level, a low level, and one or more intermediate levels between the high level and the low level according to inputted control signals; and switching elements that are provided in a pair corresponding to the control devices, and that output a voltage according to the level of the switching signals inputted from the control devices to the gate of the power transistor.

Description

[Technical Field]

[0001] The present invention relates to a gate drive device and a gate drive system. [Background technology]

[0002] Power transistors such as IGBTs (Insulated Gate Bipolar Transistors) are switched by changing the gate voltage via a gate driver (also called a gate drive device). In recent years, in order to reduce the power consumption of power transistors, gate drivers that change the gate voltage using improved control methods have been developed.

[0003] Japanese Patent Publication No. 2017-135589 discloses a gate driver that variably controls the gate driver of a power transistor using multiple levels. This gate driver reduces the drive loss of the power transistor by dynamically changing the gate voltage using multiple levels to control the power transistor. [Overview of the project]

[0004] Power transistors have capacitance between each terminal, and driving the gate requires charging and discharging of this capacitance. In recent years, there has been a trend towards increasing the power output of power transistors, requiring relatively large currents to be input to the gate for charging the capacitance, for example, 40A or more. In the gate driver configuration disclosed in Japanese Patent Application Publication No. 2017-135589, increasing the output current requires more transistors to be connected in parallel, which presents the challenge of increasing the footprint of the gate driver.

[0005] This invention was made to solve these problems and aims to provide a gate drive device and a gate drive system that can variably control the output at multiple levels with a simpler configuration.

[0006] A gate drive device according to one aspect of the present invention operates on two sides, a high-side and a low-side, to drive the gate of a power transistor. The gate drive device comprises a pair of control devices arranged to constitute the two sides, which output switching signals of three or more levels, including a high level, a low level, and one or more intermediate levels between the high level and the low level, in response to an input control signal; and a pair of switching elements arranged in correspondence with the control devices, which output a voltage to the gate of the power transistor corresponding to the level of the switching signal input from the control devices.

[0007] A gate drive system according to one aspect of the present invention operates on two sides, a high side and a low side, to drive the gate of a power transistor. The gate drive system includes a controller that outputs a control signal that is variable at three or more levels, including a high level, a low level, and one or more intermediate levels; a pair of control devices provided to constitute the two sides, which output switching signals corresponding to the control signals output from the controller; and a pair of switching elements provided in correspondence with the control devices, which output a voltage to the gate of the power transistor corresponding to the level of the switching signal input from the control devices.

[0008] According to one embodiment of the present invention, the control device is capable of outputting switching signals of three or more levels in response to an input control signal. The switching element that receives the switching signal outputs a voltage to the gate of the power transistor corresponding to the level of the switching signal. With this configuration, it is possible to dynamically control the gate voltage of the power transistor at multiple levels, thereby reducing the power consumption of the power transistor. Furthermore, the gate drive device has a half-bridge configuration in which the control device and the switching element are provided in pairs, simplifying the configuration and enabling miniaturization of the gate drive device.

[0009] According to one embodiment of the present invention, the gate drive system is capable of outputting a switching signal corresponding to a control signal input from a controller that can be varied at three or more levels. The switching element that receives the switching signal outputs a voltage to the gate of the power transistor that corresponds to the level of the switching signal. With this configuration, the power consumption of the power transistor can be reduced by dynamically controlling the gate voltage of the power transistor. Furthermore, the gate drive system is a half-bridge configuration in which the control device and the switching element are provided in pairs, simplifying the configuration and enabling miniaturization of the gate drive device. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 is a circuit diagram using a gate driver according to an embodiment of the present invention. [Figure 2] Figure 2 is a detailed diagram of the IC within the gate driver. [Figure 3A] Figure 3A is a detailed circuit diagram of the DAC within the gate driver. [Figure 3B] Figure 3B shows the equivalent circuit of the DAC. [Figure 3C] Figure 3C is an explanatory diagram of the DAC output. [Figure 4] Figure 4 is a timing chart showing an example of active drive operation for a gate driver. [Figure 5A] Figure 5A is a timing chart showing the operation of a single-drive gate driver performed during characteristic evaluation. [Figure 5B] Figure 5B is a graph showing the characteristic evaluation results for the gate voltage VGSH. [Figure 5C] Figure 5C is a graph showing the characteristic evaluation results for the gate current IG. [Figure 6A] Figure 6A is a circuit diagram for a double-pulse test of a gate driver. [Figure 6B] Figure 6B is a graph showing the evaluation results for single drive and active drive in the double pulse test. [Figure 7] Figure 7 is a circuit diagram showing the gate driver of the first modified example. [Figure 8] Figure 8 is a circuit diagram showing a gate driver of the second modified example. [Modes for carrying out the invention]

[0011] Embodiments of the present invention will be described below with reference to the drawings.

[0012] Figure 1 is a circuit diagram using a gate driver according to an embodiment of the present invention.

[0013] The gate driver 10 controls the power transistor 20, and its output terminals are connected to the gate and emitter of the power transistor 20. The power transistor 20 is, for example, an IGBT (Insulated Gate Bipolar Transistor). Below, the gate voltage V is defined as the potential of the gate relative to the emitter in the power transistor 20. GE This indicates that the current input to the gate is the gate current I. G This indicates that the gate voltage V of the power transistor 20 is determined according to the output of the gate driver 10. GE The gate current I changes, and the power transistor 20 is controlled. G This must exceed a predetermined value according to the specifications of the power transistor 20.

[0014] The gate driver 10 has a half-bridge configuration and consists of two stages: the upper stage (high side) and the lower stage (low side) shown in the diagram. In the half-bridge configuration of the gate driver 10, the other does not operate while one of the high side or low side is controlled.

[0015] As described later, the gate driver 10 adjusts the gate voltage V in response to a digital control signal input from an external source. GE and gate current I GIt is dynamically variably controlled at multiple levels. By controlling such a gate, the driving loss of the power transistor 20 can be reduced. Note that the gate driver 10 is an example of a gate driving device, and a device that can variably control the gate voltage may also be referred to as a digital gate driver. In addition, the dynamic variable control at multiple levels of the gate driver 10 is referred to as active control. The control at one level (on / off) of the gate driver 10 is referred to as single-step control or single control.

[0016] The gate driver 10 includes a DAC (Digital Analog Convertor) 1 that constitutes the high side, and a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) 3, and a DAC2 that constitutes the low side, and a MOSFET 4. The two DACs 1 and 2 are integrated into an IC (Integrated Circuit) including their control circuits and are implemented as the IC 11.

[0017] Hereinafter, the voltage of the gate with respect to the source of the MOSFET 3 on the high side is represented as V GSH and the voltage of the gate with respect to the source of the MOSFET 4 on the low side is represented as V GSL . The gate voltages V GSH , V GSL of the MOSFETs 3 and 4 are controlled by the DACs 1 and 2. Therefore, the gate voltages V GSH , V GSL output from the DACs 1 and 2 are used for the switching of the MOSFETs 3 and 4 and may also be referred to as switching signals. In addition, diodes for reflux are connected to the MOSFETs 3 and 4, with the source side connected as an anode between the drain and the source, that is, connected in anti-parallel to the MOSFETs 3 and 4.

[0018] On the high side, the output terminal of the DAC 1 is connected to the gate of the MOSFET 3. A DC voltage V DD3A voltage V is supplied. In addition, one end of DAC1, which is connected to the negative terminal side of power supply 5, is electrically connected to the source of MOSFET 3. DAC1 supplies a voltage V in response to an externally input control signal. DD3 The voltage is transformed and output to the gate of MOSFET3 at the desired timing and level. Through this control of DAC1, the gate voltage V GSH The MOSFET3 operates under control.

[0019] MOSFET3 has its source connected to the gate of power transistor 20, and its drain connected to the emitter of power transistor 20 via power supply 7. Power supply 7 is a DC voltage V DD1 The gate of the power transistor 20 is supplied with a high potential relative to the emitter, i.e., the gate voltage V GE It is set so that it is at a positive potential. In the high-side control section, MOSFET3 has a gate voltage V GSH It is controlled accordingly, and as a result the gate voltage V of the power transistor 20 GE is the voltage V DD1 This becomes a stepped-down positive voltage.

[0020] The configuration on the low side is the same as the configuration on the high side. The output terminal of DAC2 is connected to the gate of MOSFET4. DAC2 receives a DC voltage V from power supply 6. DD4 A voltage V is supplied. In addition, one end of DAC2, which is connected to the negative terminal side of power supply 6, is electrically connected to the source of MOSFET4. DAC2 adjusts the supplied voltage V according to the control signal input from the outside. DD4 The voltage is transformed and output to the gate of MOSFET4 at the desired timing and level. Through this control of DAC2, the gate voltage V GSL The MOSFET4 operates under controlled conditions.

[0021] MOSFET4 has its drain connected to the gate of power transistor 20, and its source connected to the emitter of power transistor 20 via power supply 8. Power supply 8 is a DC voltage V DD2The power transistor 20 is supplied such that the emitter is at a higher potential than the gate, i.e., the gate voltage V GE It is set so that it becomes a negative potential. In the low-side control section, MOSFET4 has a gate voltage V GSL It is controlled accordingly, and as a result the gate voltage V of the power transistor 20 GE is the voltage V DD2 This becomes a stepped-down negative voltage.

[0022] In this way, the gate voltages V of MOSET3 and 4 are controlled according to the control of DAC1 and 2. GSH , V GSL This is controlled. And the gate voltage V GSH , V GSL In response to the change, the gate voltage V of the power transistor 20 changes GE , and gate current I G This is controlled. In the high-side control section, the gate voltage V of power transistor 20 is controlled. GE This is the gate voltage V of MOSET3. GSH The corresponding positive voltage occurs, and in the low-side control section, the gate voltage V of power transistor 20 is... GE This is the gate voltage V of MOSET4. GSL This results in a corresponding negative voltage. The power transistor 20 is then driven by this alternating control of the high-side and low-side.

[0023] Figure 2 is a detailed configuration diagram of IC11. IC11 contains control circuits for DAC1 and DAC2. In this diagram, power supplies 5 and 6 are shown to the right of DAC1 and DAC2.

[0024] IC11 includes shift registers 12 and 13 and an edge decoder 14, which are control circuits for DAC1 and 2. The control circuits, including the shift registers 12 and 13 and the edge decoder 14, may be implemented by any form of controller. Shift register 12 accepts a serial signal input and outputs a parallel signal. Shift register 13 accepts a parallel signal input and outputs a serial signal.

[0025] IC11 includes an input signal (IN) and an enable signal (Enable) used to control DAC1 and DAC2, an input signal (Scan IN) and a clock signal (Scan CLK) used for scan design, and the output (gate voltage V) from DAC1 and DAC2. GSH , V GSL A timing signal (Timing) indicating the timing of the change in ) is input. Note that the scan design is implemented using a shift register 12, etc., but a detailed explanation of its configuration is omitted.

[0026] The shift register 13 receives an input signal (IN) and an enable signal (Enable), as well as a timing signal (Timing) from the edge decoder 14. The shift register 13 then receives 8 bits of H_n. PMOS and H_n NMOS The control signals are output to DAC1, and each is an 8-bit L_n PMOS and L NMOS The control signal is output to DAC2. This output is updated at the timing of changes in the timing signal. In this way, DAC1 and DAC2 operate based on a digital control signal using four 8-bit signals, and the gate voltage V, which is the switching signal for MOSFET3 and 4, is output. GSH , V GSL The output is as follows. Next, the detailed configuration of DAC1 and DAC2 will be explained using Figures 3A to 3C.

[0027] Figure 3A is a detailed circuit diagram of DAC1. Figure 3B is the equivalent circuit of DAC1. Figure 3C is an explanatory diagram of the output of DAC1. As shown in Figures 3A and 3B, DAC1 includes a variable resistor section 15 at the top of the figure and a variable resistor section 16 at the bottom of the figure, so the output of DAC1 can be variably controlled as shown in Figure 3C. The details of the configuration of DAC1 will be explained below.

[0028] As shown in Figure 3A, the variable resistor section 15 has a switching element W with a resistive component. P , 2W P , 4W P , 8W P, 16W P , 32W P , 64W P , 128W P These switching elements W are connected in parallel. P On one end, there is a voltage V from power supply 5. DD3 A voltage is supplied to one end, and the other end is connected to the gate of MOSFET3.

[0029] Switching element W P The number preceding it indicates the relative size of the area of ​​the element. For example, a 2W switching element. P is a switching element W P It has a resistance value that is half the size of the other element. And the switching element W P , 2W P , 4W P , 8W P , 16W P , 32W P , 64W P , 128W P These are, respectively, H_n PMOS It is controlled by registers [0] to [7]. As a result, the resistance value of the variable resistor section 15 can be changed in 256 steps (0 to 255: 8 bits).

[0030] Similarly, the variable resistor section 16 has a switching element W having a resistive component. N , 2W N , 4W N , 8W N , 16W N , 32W N , 64W N , 128W N These switching elements W are connected in parallel. N One end of the switching element W is connected to the gate of MOSFET3, and the other end is connected to the source of MOSFET3. N , 2W N , 4W N , 8W N , 16W N , 32W N , 64W N , 128WN is controlled by registers of H_n NMOS [0] to [7], respectively. As a result, the resistance value of the variable resistor unit 16 can be changed at 256 levels (0 to 255: 8 bits).

[0031] As shown in FIG. 3B, the DAC1 is equivalent to a configuration in which a variable resistor unit 15 whose resistance value changes by being controlled by registers of H_n PMOS [0] to [7] and a variable resistor unit 16 whose resistance value changes by being controlled by registers of H_n NMOS [0] to [7] are connected in series. A voltage V DD3 is supplied to the variable resistor units 15 and 16 from the power supply 5. Also, the connection point between the variable resistor unit 15 and the variable resistor unit 16 is connected to the gate of the MOSFET3, and the terminal connected to the negative electrode side of the power supply 5 of the variable resistor units 15 and 16 is connected to the source of the MOSFET3.

[0032] In FIG. 3C, the gate voltage V GSH of the MOSFET3 controlled by the DAC1 is shown. The gate voltage V GSH is determined by降压 the voltage V DD3 of the power supply 5 according to the resistance values of the variable resistor units 15 and 16. Specifically, if the resistance value of the variable resistor unit 15 is R p and the resistance value of the variable resistor unit 16 is R N , the gate voltage V GSH is a value obtained by multiplying V DD3 by (R[[ID=​​​​​​​​​​​​​​The gate voltage V of the low-side MOSFET4 is variably controlled at multiple levels. GSL It becomes zero. At the timing of the change in the timing signal, H_n PMOS Depending on [0] to [7], the gate voltage V of MOSFET3 GSH This is controlled, and the gate current I of the power transistor 20 is controlled. G and gate voltage V GE It is controlled.

[0035] In detail, between intervals t1 and t4, the gate voltage V GSH is 0V~V DD3 Multiple levels are set between them, and in the final interval t5, V DD3 This is the result. On the other hand, in the interval t1 to t5, the gate voltage V GSL The gate voltage V remains zero. GSH Depending on the change, the gate current I G It increases and decreases within a positive range, eventually becoming zero. At the same time, the gate voltage V GE It gradually increases and eventually reaches a predetermined value of V. DD1 This is the result.

[0036] On the other hand, in the section t6~t where the IN signal is off 10 In this case, the gate voltage V of the low-side MOSFET4 GSL The gate voltage V on the high side is variably controlled at multiple levels. GSH It becomes zero. Similarly, the gate voltage V GSL Because the voltage level changes in response to the input timing signal, the gate current I of the IGBT2 G It is controlled in the negative region, and the gate voltage V GE This can be controlled within the reduction range.

[0037] In this example, the gate voltage V of the low-side MOSFET4 is as follows during the interval t6 to t9. GSL is 0V~V DD4 Multiple levels are set between them, and the final interval t 10 In V DD4 This is the result. On the other hand, the interval t6~t 10In this case, the gate voltage V GSH The gate voltage V remains zero. GSL Depending on the change, the gate current I G It increases and decreases in the negative range, eventually becoming zero. At the same time, the gate voltage V GE It gradually decreases until it reaches -V DD2 This is the result.

[0038] Such t1~t 10 Through repeated control, the gate driver 10 controls the gate current I of the power transistor 20. G and gate voltage V GE It can be controlled.

[0039] Next, we will explain the characteristic evaluation performed on the gate driver 10 using Figures 5A to 5C. In this characteristic evaluation, instead of the active control shown in Figure 4, we performed single-step control, which is a single control to a predetermined level.

[0040] Figure 5A is a timing chart showing the operation of the single-step control of the gate driver 10 during the characteristic evaluation. Figure 5B shows the gate voltage V GSH This graph shows the characteristics of the gate current I. G This graph shows the characteristics. This characteristic evaluation was performed in an environment where a 100μF film capacitor was connected to the gate driver 10, and the evaluation results shown in Figures 5B and 5C were obtained by performing the single-step control shown in Figure 5A.

[0041] As shown in Figure 5A, when the IN signal switches from off to on, H_n PMOS The value is changed from 0 to n (a predetermined value between 0 and 255), and H_n NMOS The value was changed from 255 to 60. H_n PMOS and H_n NMOS As this changes, the gate voltage V of MOSFET3 changes GSH , and the gate current I of the power transistor 20 GThis changes. And by changing n in this control from 0 to 255, the gate voltage V shown in Figures 5B and 5C changes. GSH and gate current I G It acquired the following characteristics.

[0042] Figures 5B and 5C show the measurement results for two conditions, (a) and (b). In (a), V DD1 and V DD2 The voltage is 15V, and V DD3 and V DD4 The gate voltage V as n changes when the voltage is 4V. GSH and gate current I G The results for each characteristic are shown. (b) contains V DD1 The voltage is 15V, and V DD2 V is 0V, DD3 and V DD4 The gate voltage V as n changes when the voltage is 3.5V. GSH and gate current I G The results for each characteristic are shown.

[0043] According to Figure 5B, by gradually increasing n, the gate voltage V GSH A roughly linear correlation is shown in which n increases. Figure 5C shows that as n is increased in steps, the gate current I G The correlation is shown to gradually increase from n=70 to 100. Furthermore, as shown in Figure 5C(a), the gate current I G The current has increased to about 51A. Generally, in controlling large-capacity power transistors, the gate current I G The current is required to be 40A or more, and the gate driver 10 of this embodiment exceeds this requirement. Based on these evaluation results, the gate driver 10 of this embodiment has a gate voltage V GSH It has linear characteristics, and the gate current I G It is clear that the capacity has been increased.

[0044] Next, using Figures 6A and 6B, we will explain the evaluation results of the drive performance of the gate driver 10 (DGD: Digital Gate Driver) obtained by the double pulse test. Figure 6A is a circuit diagram of the evaluation environment for the double pulse test. Figure 6B is a graph showing the drive performance of the gate driver 10 by the double pulse test.

[0045] Figure 6A shows the circuit configuration for a 600V / 200A double pulse test. In this circuit, two power transistors 31 and 32 are connected in series. The gate of power transistor 31 at the bottom of the figure accepts input from the gate driver 10. An inductor 33 is connected in parallel to power transistor 32 at the top of the figure. In this test environment, power transistors 31 and 32 were used with a maximum collector-emitter voltage of 6500V and a maximum collector current of 1000A. Also, in the gate driver 10, V DD1 The voltage is 15V, and V DD2 V is 0V, DD3 and V DD4 The voltage is 3.5V.

[0046] A power supply 34 is connected to both ends of the series-connected power transistors 31 and 32, and a capacitor 35 is also provided in parallel with the power supply 34. A voltage of 600V is supplied by the power supply 34, and a current of 200A flows through the inductor 33. In this environment, a double pulse test was performed by controlling the power transistor 31 using the gate driver 10.

[0047] Figure 6B shows the results of a double-pulse test using the environment shown in Figure 6A. In this figure, the results of the double-pulse test are shown with the overshoot current (I) of the power transistor 31 on the X axis (horizontal axis). OVERSHOOT ) is shown, and the power loss of the power transistor 31 (E) is shown on the Y axis (vertical axis). LOSS ) is shown.

[0048] The circles in Figure 5A show the correlation between overshoot current and power loss when n is varied from 94 to 255 while controlling the gate driver 10 using single-step control. From this figure, it can be seen that there is a trade-off relationship where the smaller n is, the smaller the overshoot current, and the larger n is, the smaller the power loss.

[0049] The asterisk indicates the result when the gate driver 10 is actively controlled. In active control, as shown in Figure 4, the gate voltage V of MOSFET 3 GSH , V GSL The system is controlled to pass through an intermediate level during the transition from off (low level) to on (high level). Note that the evaluation results shown in Figure 6B were obtained using an active control pattern different from that shown in Figure 4.

[0050] Comparing the results marked with a star with the results marked with a circle for n=96, we can see that the power loss was reduced by 51%, from 0.37J to 0.18J, while maintaining almost the same overshoot current. Comparing the results marked with a star with the results marked with a circle for n=105, we can see that the overshoot current was reduced by 26%, from 326A to 242A, while maintaining almost the same power loss. Thus, it can be seen that by variably controlling the gate driver 10 of this embodiment, the power transistors 31 and 32 can be driven with higher efficiency.

[0051] In this embodiment, MOSFETs 3 and 4 were used as switches controlled by DACs 1 and 2, but the invention is not limited to these. Bipolar transistors may be used instead of MOSFETs. While MOSFETs are controlled according to their gate voltage, bipolar transistors are controlled by their gate current. Therefore, by controlling the current output from DACs 1 and 2 to three or more levels, including an intermediate level, the gate voltage of the power transistor 20 connected to the bipolar transistor can be dynamically and variably controlled.

[0052] Furthermore, while DAC1 and DAC2, which are digital-to-analog converters, were used as control devices to control the switching elements, the device is not limited to these. Alternatively, a device capable of outputting signals of three or more levels, including a high level, a low level, and one or more intermediate levels between the high level and the low level, in response to the input control signal, may be used.

[0053] Furthermore, by changing MOSFETs 3 and 4 to MOSFETs with different rated currents, the gate current I of the power transistor 20 output from the gate driver 10 can be changed. G The maximum output current can be changed. Also, the voltage V of power supplies 5 and 6 that supply power to DAC1 and 2 can be changed. DD3 , V DD4 By changing the power supply to one with a different voltage, the gate current I output from the gate driver 10 can be changed. G The maximum value can be changed. MOSFETs 3 and 4, and power supplies 5 and 6 are modular and easily replaceable, so the performance of the gate driver 10 can be changed by changing these components.

[0054] Thus, the gate driver 10 of this embodiment comprises two DACs 1 and 2, and MOSFETs 3 and 4. The outputs from DACs 1 and 2 are dynamically controlled to vary levels of three or more, including a high level, a low level, and one or more intermediate levels between the high level and the low level, according to a digital control signal input from the shift register 13. The MOSFETs 3 and 4 then control the gate voltage V of the power transistor 20 to be controlled according to the output level from DACs 1 and 2. GE and gate current I G This allows for dynamic control (active control) at multiple levels. As a result, as shown in Figure 6B, both the overshoot current and power loss of the power transistor 20 can be reduced.

[0055] Furthermore, the control circuits for DAC1 and DAC2 are implemented by IC11, which includes a shift register 13. This IC11 has a single control circuit (shift registers 12 and 13, and edge decoder 14) that outputs control signals to the two DAC1 and DAC2. By configuring the two DAC1 and DAC2 to be controlled using a single control circuit in this way, the size of IC11 can be reduced. In addition, the gate driver 10 has a half-bridge configuration with two sides, a high side and a low side, so it can be operated in both turn-on and turn-off control.

[0056] Furthermore, according to this embodiment, the output of DAC1 and 2 is the gate voltage V of MOSFET3 and 4. GSH , V GSL Thus, with this configuration, the switching control of MOSFETs 3 and 4 can be directly performed. The switching control of MOSFETs 3 and 4 is performed using a gate voltage V as in this embodiment. GSH , V GSL Instead of directly controlling the gate voltage of MOSFETs 3 and 4 relative to ground, this can also be done indirectly by changing the gate voltage of MOSFETs 3 and 4 relative to ground. In contrast, in this embodiment, the control accuracy of MOSFETs 3 and 4 can be improved by changing the voltage directly rather than indirectly.

[0057] Next, other variations of the gate driver 10 will be explained using Figures 7 and 8.

[0058] Figure 7 shows a gate driver 10A of the first modified example. Compared to the gate driver 10 of the first embodiment shown in Figure 1, the gate driver 10A shown in this figure omits the power supply 5 that supplies voltage to DAC1, the power supply 6 that supplies voltage to DAC2, and the power supply 8 that constitutes the low-side output power. At the same time, DAC1 and DAC2 are configured to be supplied with a predetermined voltage from power supply 7 by changing the voltage converters 41 and 42 instead of power supplies 5 and 6.

[0059] With this configuration, DACs 1 and 2 can be driven by transforming and supplying the voltage from power supply 7 (second power supply) without needing to provide power supplies 5 and 6 (first power supplies). Furthermore, the gate driver 10A can be configured even if only one power supply 7 (second power supply) is provided for the two MOSFETs 3 and 4. This configuration reduces the number of power supplies within the gate driver 10A and simplifies the overall structure.

[0060] Figure 8 shows a second modified gate driver 10B. Compared to the gate driver 10 of the first embodiment shown in Figure 1, the gate driver 10B shown in this figure has a resistor 51 between DAC1 and MOSFET3, and a resistor 52 between DCA2 and MOSFET4. This configuration allows for smoothing of the outputs from DAC1 and DAC2, and as a result, the operation of the power transistor 20 driven by the gate driver 10B can be stabilized.

[0061] As shown in the first modified example, the number of power supplies for the gate driver 10A can be reduced, and as shown in the second modified example, the operation of the gate driver 10B can be stabilized by providing resistors 51 and 52. In addition to the configurations shown in these modified examples, the gate driver 10 can take various other modifications.

[0062] This invention allows for various embodiments and modifications without departing from the broad spirit and scope of the invention. Furthermore, the embodiments described above are for illustrative purposes only and do not limit the scope of the invention. In other words, the scope of the invention is indicated not by the embodiments, but by the claims. Various modifications made within the scope of the claims and the equivalent scope of the meaning of the invention are considered to be within the scope of the invention.

Claims

1. A gate drive device that operates on two sides, high-side and low-side, and drives the gate of a power transistor, A control device provided in pairs to constitute the two aforementioned sides, which outputs switching signals of three or more levels, including a high level, a low level, and one or more intermediate levels between the high level and the low level, in response to an input control signal. The device includes a switching element provided in a pair corresponding to the control device, which outputs a voltage to the gate of the power transistor corresponding to the level of the switching signal input from the control device, The aforementioned intermediate level is a preset value corresponding to the aforementioned control signal. The switching element is a MOSFET, The control device is a gate drive device that changes the gate voltage of the switching element to a level of 3 or more in response to the input control signal.

2. A gate drive device that operates on two sides, a high-side and a low-side, and drives the gate of a power transistor, A control device provided in pairs to constitute the two aforementioned sides, which outputs switching signals of three or more levels, including a high level, a low level, and one or more intermediate levels between the high level and the low level, in response to an input control signal. The device includes a switching element provided in a pair corresponding to the control device, which outputs a voltage to the gate of the power transistor corresponding to the level of the switching signal input from the control device, The aforementioned intermediate level is a preset value corresponding to the aforementioned control signal. The switching element is a bipolar transistor, The control device is a gate drive device that changes the gate current of the switching element to a level of 3 or more in response to the input control signal.

3. The gate drive device according to claim 1 or 2, wherein the control device is a digital-to-analog converter that converts an input voltage based on the control signal, which is an input digital signal, and outputs it as a switching signal.

4. The gate drive device according to claim 1 or 2, wherein in the operation of at least one of the two sides, the control signal is at the intermediate level during at least one of the periods between changing from the high level to the low level and between changing from the low level to the high level.

5. The gate drive device according to claim 1 or 2, wherein the maximum current that can be output from the switching element to the gate of the power transistor is determined according to the rated current of the switching element.

6. The gate drive device according to claim 1 or 2, wherein the maximum current that can be output from the switching element to the gate of the power transistor is determined according to the voltage supplied to the control device.

7. The gate drive device according to claim 1 or 2, wherein one controller is provided for each pair of control devices, which generates the control signals for the control devices.

8. The control device receives power supplied from the first power supply and outputs the switching signal. The gate drive device according to claim 1 or 2, wherein the switching element converts a voltage input from a second power supply in accordance with the switching signal, and outputs a voltage corresponding to the level of the switching signal obtained by the conversion to the gate of the power transistor.

9. The gate drive device according to claim 8, wherein the first power supply is configured by transforming the second power supply.

10. The gate drive device according to claim 8, wherein the second power supply is provided on at least one of the pair of switching elements.

11. The gate drive device according to claim 1 or 2, further comprising a resistor provided between the control device and the switching element.

12. A gate drive system that operates on two sides, high-side and low-side, and drives the gate of a power transistor, A controller that outputs a control signal that can be varied at three or more levels, including a high level, a low level, and one or more intermediate levels, A pair of control devices are provided to constitute the two sides and output a switching signal corresponding to the control signal output from the controller, The device includes a switching element provided in a pair corresponding to the control device, which outputs a voltage to the gate of the power transistor corresponding to the level of the switching signal input from the control device, The aforementioned intermediate level is a preset value corresponding to the aforementioned control signal. The switching element is a MOSFET, The control device is a gate drive system that changes the gate voltage of the switching element to a level of 3 or more in response to the input control signal.

13. A gate drive system that operates on two sides, a high-side and a low-side, and drives the gate of a power transistor, A controller that outputs a control signal that can be varied at three or more levels, including a high level, a low level, and one or more intermediate levels, A pair of control devices are provided to constitute the two sides and output a switching signal corresponding to the control signal output from the controller, The device includes a switching element provided in a pair corresponding to the control device, which outputs a voltage to the gate of the power transistor corresponding to the level of the switching signal input from the control device, The aforementioned intermediate level is a preset value corresponding to the aforementioned control signal. The switching element is a bipolar transistor, The control device is a gate drive system that changes the gate current of the switching element to a level of 3 or more in response to the input control signal.

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