Protocol controllers, protocol control methods, chiplets, systems-on-chips, and electronic devices.

Abstract

Embodiments of the present disclosure provide a protocol controller, a protocol control method, a chiplet, a system on a chip, and an electronic device, wherein the protocol controller includes: a first bus interface connected to a system bus, which implements a chip-to-chip interconnection protocol and a sub-protocol of a first part of a peripheral protocol; and a second bus interface connected to the system bus, which implements a sub-protocol of a second part of the peripheral protocol, wherein the sub-protocol of the first part and the sub-protocol of the second part are configured to be implemented by different bus interfaces, and the chiplet uses one of the chip-to-chip interconnection protocol and the peripheral protocol at the same time.

Description

Technical Field

[0001] This application claims the priority of Chinese Patent Application No. 202311459482.2 filed on November 3, 2023, and the entire content disclosed in the above Chinese patent application is incorporated herein by reference. <(

[0002] Embodiments of the present disclosure relate to a protocol controller, a protocol control method, a chiplet, a system-on-chip, and an electronic device.

Background Art

[0003] A chiplet is a unit chip that can implement a certain function, such as a processor chiplet (e.g., a CPU chiplet) that realizes data processing, etc., and a plurality of chiplets can be interconnected to form a chip such as a SOC (System On Chip).

[0004] A protocol controller is a component in a chiplet for managing and executing communication protocols. Based on the need for a chiplet to interconnect with peripheral devices (abbreviation for external devices) and other chiplets, the protocol controller in the chiplet can be divided into a peripheral device protocol controller and an inter-chip interconnect protocol controller. The peripheral device protocol controller is used to manage and execute peripheral device protocols to realize the interconnection between the chiplet and peripheral devices. The inter-chip interconnect protocol controller is used to manage and execute inter-chip interconnect protocols to realize the interconnection between the chiplet and other chiplets.

[0005] In the above background, how to provide a protocol controller to reduce the hardware resources occupied by the protocol controller has become a technical problem that those skilled in the art need to solve urgently.

Summary of the Invention

Problems to be Solved by the Invention

[0006] In view of this, embodiments of the present disclosure provide a protocol controller, a protocol control method, a chiplet, a system-on-a-chip, and electronic equipment that support peripheral device protocols and inter-chip interconnection protocols with a single protocol controller, avoiding the occupation of many hardware subprotocol parts when implementing peripheral device protocol controllers and interconnection protocol controllers respectively, and reducing the hardware resources occupied by the protocol controller. [Means for solving the problem]

[0007] To achieve the above objectives, the embodiments of this disclosure provide the following technical solutions.

[0008] In the first aspect, embodiments of the present disclosure provide a protocol controller applicable to a chiplet, the protocol controller, A first bus interface connected to the system bus implements the first part of the inter-chip interconnection protocol and peripheral device protocol subprotocols, A second bus interface connected to a system bus that implements a subprotocol of the second part of the peripheral device protocol, the second bus interface being configured such that the subprotocol of the first part and the subprotocol of the second part are implemented by different bus interfaces, The chiplet uses one of the following protocols simultaneously: the inter-chip interconnection protocol and the peripheral device protocol.

[0009] In a second aspect, embodiments of the present disclosure provide a protocol control method applicable to the protocol controller described in the first aspect, the method being: The step of determining the protocol currently being used by the protocol controller, If the protocol currently used by the protocol controller is a peripheral device protocol, the step is to close the module that has been separately configured for the inter-chip interconnection protocol within the protocol controller, If the protocol currently used by the protocol controller is an inter-chip interconnection protocol, the procedure includes the step of closing a module that has been separately configured for peripheral device protocols within the protocol controller.

[0010] In a third aspect, an embodiment of the present disclosure provides a chiplet and includes the protocol controller described in the first aspect.

[0011] In a fourth aspect, an embodiment of the present disclosure provides a system-on-a-chip comprising a plurality of interconnected chiplets, the chiplets being the chiplets described in the first aspect.

[0012] In the fifth aspect, embodiments of the present disclosure provide electronic equipment including a chiplet as described in the first aspect or a system-on-a-chip as described in the fourth aspect.

[0013] The protocol controller provided in the embodiments of this disclosure can be applied to a chiplet, and the protocol controller may include a first bus interface connected to the system bus and a second bus interface connected to the system bus. If the chiplet uses one of the protocols, the Inter-Chip Interconnection Protocol and the Peripheral Protocol, at the same time, and the subprotocols of the first and second parts of the Peripheral Protocol are configured to be implemented by different bus interfaces, then the protocol controller provided in the embodiments of this disclosure can implement the Inter-Chip Interconnection Protocol and the subprotocols of the first part of the Peripheral Protocol on the first bus interface and the subprotocols of the second part of the Peripheral Protocol on the second bus interface, thereby allowing the Inter-Chip Interconnection Protocol and the subprotocols of the first part of the Peripheral Protocol that the chiplet needs to support to share the first bus interface of the protocol controller, further reducing the hardware resources occupied by the protocol controller, and by implementing the subprotocols of the second part that need to be configured separately from the subprotocols of the first part on the second bus interface of the protocol controller, the protocol controller of the chiplet can support the Peripheral Protocol and the Inter-Chip Interconnection Protocol through two sets of interfaces, the first bus interface and the second bus interface.

[0014] As can be seen from the above, the embodiments of the present disclosure enable a single protocol controller in a chiplet to support peripheral protocols and inter-chip interconnect protocols, and the subprotocols of the first part of the inter-chip interconnect protocols and peripheral protocols can share a set of bus interfaces of the protocol controller (i.e., the first bus interface), improving the multiplexing of hardware resources. Furthermore, unlike methods of implementing peripheral protocol controllers and interconnect protocol controllers separately in a chiplet, the embodiments of the present disclosure can reduce the hardware resources occupied by the protocol controller, thereby saving hardware resources in the chiplet.

[0015] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the following drawings, which are necessary for describing the embodiments, are briefly introduced below. Obviously, the drawings described below are merely examples of the embodiments of this disclosure, and those skilled in the art can obtain other drawings based on the provided drawings without requiring any creative work. [Brief explanation of the drawing]

[0016] [Figure 1A] Figure 1A is an illustrative diagram showing how a chiplet is interconnected with peripheral devices and other chiplets. [Figure 1B] Figure 1B is another example diagram illustrating how a chiplet is interconnected with peripheral devices and other chiplets. [Figure 2A] Figure 2A is an example diagram illustrating the connection of a protocol controller according to an embodiment of this disclosure. [Figure 2B] Figure 2B is another example diagram illustrating the connection of a protocol controller according to an embodiment of this disclosure. [Figure 3] Figure 3 is an illustrative diagram showing how chiplets according to an embodiment of this disclosure are interconnected. [Figure 4] Figure 4 is an illustrative diagram of a protocol controller according to an embodiment of the present disclosure. [Figure 5]FIG. 5 is an exemplary diagram of a bus interface module according to an embodiment of the present disclosure. [Figure 6A] FIG. 6A is an exemplary diagram of a transport layer module according to an embodiment of the present disclosure. [Figure 6B] FIG. 6B is another exemplary diagram of a transport layer module according to an embodiment of the present disclosure. [Figure 6C] FIG. 6C is an exemplary diagram of an interaction process between a protocol controller and a system bus according to an embodiment of the present disclosure. [Figure 6D] FIG. 6D is another exemplary diagram of an interaction process between a protocol controller and a system bus according to an embodiment of the present disclosure. [Figure 7] FIG. 7 is an exemplary diagram of a data link layer module according to an embodiment of the present disclosure. [Figure 8] FIG. 8 is an exemplary diagram of a physical layer module according to an embodiment of the present disclosure. [Figure 9] FIG. 9 is another exemplary diagram of a protocol controller according to an embodiment of the present disclosure. [Figure 10] FIG. 10 is a flowchart of a protocol control method according to an embodiment of the present disclosure.

DETAILED DESCRIPTION OF THE INVENTION

[0017] Hereinafter, while referring to the drawings in the embodiments of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative labor shall fall within the protection scope of the present disclosure.

[0018] Limited by the process technology and cost of the chip, a plurality of chiplets can form a chip system (such as a system-on-chip) by chip-to-chip interconnect technology, and the performance improvement and function increase of the chip can be realized. The chip-to-chip interconnect technology can realize the interconnection of a plurality of chiplets based on a chip-to-chip interconnect protocol.

[0019] At the same time, in order to enable chiplets such as processor chiplets (e.g., CPU chiplets) to interconnect with peripheral devices, chiplets and peripheral devices can be interconnected via peripheral device protocols. For example, with the increasing computational power requirements of computer systems, peripheral device protocols such as the CXL (Compute Express Link) protocol have been introduced to mitigate the effects of the memory wall problem and are used to improve the efficiency of data exchange between chiplets such as CPU chiplets and peripheral devices. Therefore, chiplets such as CPU chiplets and peripheral devices can be interconnected via peripheral device protocols such as the CXL protocol. The memory wall problem refers to the problem where, when it is necessary to access a large amount of internal memory data, the performance of the computer system cannot be effectively improved due to limitations such as the bandwidth, latency, or cache consistency of the internal memory. The occurrence of the memory wall problem is accompanied by a bottleneck in the bandwidth of the internal memory.

[0020] As can be seen from the above, there is a need for chiplets to interconnect with peripheral devices and other chiplets. Therefore, when designing chiplets, it is necessary to ensure that they support peripheral device protocols and inter-chip interconnection protocols. This allows chiplets to interconnect with peripheral devices via peripheral device protocols and with other chiplets via inter-chip interconnection protocols.

[0021] For ease of understanding, Figure 1A illustrates an example of how a chiplet is interconnected with peripherals and other chiplets. As shown in Figure 1A, chiplet 111 and chiplet 112 may be interconnected via an inter-chip interconnection protocol, and chiplet 111 and peripheral 120 may be interconnected via a peripheral protocol.

[0022] Chiplets 111 and 112 may be two chiplets within a chip such as an SOC. For example, chiplets 111 and 112 may be two processor chiplets within an SOC, and the embodiments of this disclosure do not limit the number of chiplets included within a chip such as an SOC. Chiplets 111 and 112 may be interconnected via an inter-chip interconnection protocol, which is a communication protocol for connecting different chiplets to realize high-speed data transmission and communication between chiplets. The inter-chip interconnection protocol may include a three-layer protocol consisting of a transport layer, a data link layer, and a physical layer.

[0023] The peripheral device 120 may be any of the external devices connected to the chiplet 111, such as network devices, accelerator devices, and storage devices. The chiplet 111 and the peripheral device 120 may be interconnected via a peripheral device protocol, which is a communication protocol for connecting chiplets and controlling external devices or peripheral devices, such as the CXL protocol.

[0024] The CXL protocol is a high-performance open interconnect protocol designed to connect computing, storage, and acceleration devices to support high-bandwidth, low-latency data transmission and resource sharing. Furthermore, peripheral device protocols are not limited to the CXL protocol; they may include the CCIX (Cache Coherent Interconnect for Accelerators) protocol, or other protocols that connect other processors (e.g., graphics processors) and acceleration devices to support high-performance computing and data transmission.

[0025] In order for a chiplet to support peripheral protocols and inter-chip interconnect protocols, the chiplet must implement protocol controllers that support the peripheral protocols and inter-chip interconnect protocols, respectively. For ease of understanding, Figure 1B illustrates another example in which a chiplet interconnects with peripherals and other chiplets, and as shown in Figures 1A and 1B, chiplet 111 implements a peripheral protocol controller 131 and an inter-chip interconnect protocol controller 132. Chiplet 111 may interconnect with peripheral 120 via peripheral protocols using the peripheral protocol controller 131, and chiplet 111 may interconnect with chiplet 112 via inter-chip interconnect protocols using the inter-chip interconnect protocol controller 132.

[0026] By implementing peripheral protocol controllers and inter-chip interconnection protocol controllers within a chiplet, the chiplet can select the appropriate protocol controller depending on the actual application scenario, thereby interconnecting with peripherals via peripheral protocols or with other chiplets via inter-chip interconnection protocols, and further addressing the needs of different application scenarios for the chiplet.

[0027] However, chiplets may not interconnect with peripherals and other chiplets at the same time; that is, a chiplet may interconnect with a peripheral or other chiplet at the same time, and in this case, the chiplet will use one of the protocol controllers, either the peripheral protocol controller or the inter-chip interconnection protocol controller, and the other unused protocol controller will need to be closed to reduce power consumption.

[0028] For example, in an application scenario where a chiplet interconnects with a peripheral device, the chiplet can choose to interconnect with the peripheral device via the peripheral protocol using a peripheral protocol controller, and to reduce power consumption, the chiplet can close any currently unused inter-chip interconnect protocol controllers. Furthermore, for example, in an application scenario where a chiplet interconnects with other chiplets, the chiplet can choose to use an inter-chip interconnect protocol controller to interconnect with other chiplets via the inter-chip interconnect protocol, and to reduce power consumption, the chiplet can close any currently unused peripheral protocol controllers.

[0029] As can be seen from the above, based on the mechanism that a chiplet may use one of the peripheral protocol and inter-chip interconnect protocol protocols at the same time, and the other protocol is not being used, if two types of protocol controllers, a peripheral protocol controller and an inter-chip interconnect protocol controller, are implemented simultaneously in a chiplet, the following problems may occur.

[0030] A chiplet may use either the peripheral protocol controller or the inter-chip interconnect protocol controller at the same time, requiring the other unused protocol controller to be closed. Therefore, if both the peripheral protocol controller and the inter-chip interconnect protocol controller are implemented simultaneously in a chiplet, it occupies a large amount of hardware resources in the chiplet, increasing its area and cost. Furthermore, an increase in the number of protocol controllers within a chiplet increases the complexity of the system bus design, increases the occupied hardware resources, and increases the difficulty and cost of designing the chiplet.

[0031] Furthermore, when peripheral device protocol controllers and inter-chip interconnection protocol controllers are implemented simultaneously in a chiplet, complex low-power design methods must be used for the protocol controllers that need to be closed in order to minimize the power consumption of those controllers. This further increases the complexity of the chiplet design.

[0032] Based on this, embodiments of the present disclosure provide an improved protocol controller design method that supports peripheral protocol and inter-chip interconnect protocol by designing a single protocol controller in a chiplet, thereby avoiding the problems associated with separately implementing a peripheral protocol controller and an interconnect protocol controller in a chiplet. For example, it avoids the occupation of many hardware resources when separately implementing a peripheral protocol controller and an interconnect protocol controller, saving hardware resources occupied by the protocol controller, reducing the chiplet area, lowering the chip cost, and easing the difficulty of chiplet design. Furthermore, by performing low-power control for protocols that need to be contained within a single protocol controller, the complexity of the control logic can be simplified, further reducing the complexity of chiplet design.

[0033] Based on the above concept, as an example of a selectable implementation, Figure 2A illustrates an example of the connection diagram of a protocol controller according to an embodiment of the present disclosure, and as shown in Figure 2A, the chiplet may include a protocol controller 200. The protocol controller 200 may include a first bus interface 210 and a second bus interface 220, the first bus interface 210 and the second bus interface 220 being connected to the system bus, that is, the first bus interface 210 being connected to the system bus and the second bus interface 220 being connected to the system bus.

[0034] The system bus may be a communication channel located within a chip (e.g., an SOC chip), used to connect different functional modules of the chip, and is a medium for data transmission and coordinated operation between functional modules. As a selectable implementation, the system bus may be an internal bus of the SOC chip or an on-chip bus.

[0035] In the embodiments of this disclosure, the first bus interface 210 and the second bus interface 220 are two sets of bus interfaces within a chiplet. The first bus interface 210 implements subprotocols of the first part of the Inter-Chip Interconnection Protocol and the Peripheral Protocol, thereby enabling support for interface-related functions of the Inter-Chip Interconnection Protocol and the interface-related functions of the first part of the Peripheral Protocol.

[0036] In the embodiments of this disclosure, the second bus interface 220 implements a subprotocol of the second part of the peripheral device protocol, thereby enabling support for the interface-related functions of the subprotocol of the second part of the peripheral device protocol.

[0037] In embodiments of the present disclosure, the first and second subprotocols of the peripheral device protocol are configured to be implemented by different bus interfaces; that is, the peripheral device protocol can be divided into the first and second subprotocols, which need to be configured on different bus interfaces, thereby allowing the first and second subprotocols of the peripheral device protocol to be implemented on different bus interfaces.

[0038] Based on this, since a chiplet may use only one of the peripheral protocol and the inter-chip interconnect protocol at the same time (i.e., when a chiplet uses the peripheral protocol, it does not use the inter-chip interconnect protocol, and when it uses the inter-chip interconnect protocol, it does not use the peripheral protocol), embodiments of the present disclosure can be configured when designing the protocol controller for a chiplet so that the first subprotocols of the inter-chip interconnect protocol and the peripheral protocol share a set of bus interfaces (i.e., a first bus interface) of the chiplet, thereby enabling multiplexing of the first bus interface by the first subprotocols of the inter-chip interconnect protocol and the peripheral protocol when the chiplet supports the first subprotocols of the inter-chip interconnect protocol and the peripheral protocol, and reducing the hardware resources occupied by the protocol controller.

[0039] Simultaneously, when the first bus interface implements the first part of the subprotocols of the inter-chip interconnection protocol and the peripheral device protocol, the chiplet's protocol controller can support the peripheral device protocol and the inter-chip interconnection protocol via two bus interfaces (i.e., the first bus interface and the second bus interface) by implementing the second part of the subprotocols of the peripheral device protocol in a separate bus interface (i.e., the second bus interface).

[0040] The protocol controller provided in the embodiments of this disclosure can be applied to a chiplet, and the protocol controller may include a first bus interface connected to a system bus and a second bus interface connected to a system bus. If the chiplet uses one of the protocols, the Inter-Chip Interconnection Protocol and the Peripheral Protocol, at the same time, and the first and second subprotocols of the Peripheral Protocol are implemented by different bus interfaces, then the protocol controller provided in the embodiments of this disclosure can implement the Inter-Chip Interconnection Protocol and the first subprotocol of the Peripheral Protocol on the first bus interface and the second subprotocol of the Peripheral Protocol on the second bus interface. This allows the Inter-Chip Interconnection Protocol and the first subprotocol of the Peripheral Protocol that the chiplet needs to support to share the first bus interface of the protocol controller, further reducing the hardware resources occupied by the protocol controller. Additionally, by implementing the second subprotocol, which needs to be configured separately from the first subprotocol, on the second bus interface of the protocol controller, the chiplet's protocol controller can support the Peripheral Protocol and the Inter-Chip Interconnection Protocol through two sets of interfaces: the first bus interface and the second bus interface.

[0041] As can be seen from the above, the embodiments of the present disclosure enable a single protocol controller in a chiplet to support peripheral protocols and inter-chip interconnect protocols, and the subprotocols of the first part of the inter-chip interconnect protocols and peripheral protocols can share a set of bus interfaces of the protocol controller (i.e., the first bus interface), improving the multiplexing of hardware resources. Furthermore, unlike methods of implementing peripheral protocol controllers and interconnect protocol controllers separately in a chiplet, the embodiments of the present disclosure can reduce the hardware resources occupied by the protocol controller, thereby saving hardware resources in the chiplet.

[0042] In one implementation example, taking the peripheral protocol as the CXL protocol, the first subprotocol of the peripheral protocol may include the internal memory and cache subprotocol of the CXL protocol, thereby realizing the internal memory and cache subprotocols of the CXL protocol and the inter-chip interconnection protocol on the first bus interface of the protocol controller, so that the internal memory and cache subprotocols of the CXL protocol share the first bus interface of the protocol controller together with the inter-chip interconnection protocol. The internal memory and cache subprotocols of the CXL protocol can be considered as subprotocols related to internal memory and cache within the CXL protocol, for example, the CXL.MEM (internal memory) subprotocol and CXL.CACHE (cache) subprotocol of the CXL protocol, where MEM is an abbreviation for MEMORY (internal memory).

[0043] In one implementation example, if the peripheral protocol is the CXL protocol, the second part of the peripheral protocol's subprotocol may include the input / output subprotocol of the CXL protocol, thereby enabling the implementation of the CXL protocol's input / output subprotocol on the protocol controller's second bus interface. The CXL protocol's input / output subprotocol is, for example, the CXL.IO (input / output) subprotocol of the CXL protocol.

[0044] The CXL protocol may also include the CXL.IO subprotocol, CXL.CACHE subprotocol, and CXL.MEM subprotocol. The CXL.IO subprotocol is one of the subprotocols within the CXL protocol, used to achieve high-performance input / output communication, and is the input / output subprotocol of the CXL protocol. The CXL.CACHE subprotocol is one of the subprotocols within the CXL protocol, used to support high-performance caching and sharing of data, and is the cache subprotocol of the CXL protocol. The CXL.MEM subprotocol is one of the subprotocols within the CXL protocol, used to support high-performance internal memory access and internal memory sharing, and is the internal memory subprotocol of the CXL protocol. The CXL.CACHE subprotocol and CXL.MEM subprotocol can be called the internal memory and cache subprotocols of the CXL protocol, as subprotocols within the CXL protocol that relate to internal memory and cache.

[0045] As an example of a selectable implementation, taking the peripheral protocol as the CXL protocol, Figure 2B illustrates another example of the connection of the protocol controller according to an embodiment of the present disclosure. As shown in Figures 2A and 2B, the first bus interface 210 can implement the CXL.CACHE subprotocol, the CXL.MEM subprotocol, and the inter-chip interconnection protocol, thereby enabling the chiplet to be connected to the system bus via the first bus interface to implement the internal memory and cache-related functions of the CXL protocol and the inter-chip interconnection protocol. The second bus interface can implement the CXL.IO subprotocol, thereby enabling the chiplet to be connected to the system bus via the second bus interface to implement the input and output-related functions of the CXL protocol.

[0046] In a further optional implementation, Figure 3 illustrates an example of how chiplets according to an embodiment of the present disclosure are interconnected, and as shown in Figures 2A and 3, the chiplets may further include a physical coding sublayer 310 connected to a protocol controller 200 and a physical layer interface 320 connected to the physical coding sublayer 310. Simultaneously, the protocol controller 200 may further include a third bus interface 230, which can provide connectivity to the physical coding sublayer 310.

[0047] Furthermore, the Physical Layer (PHY) interface 320 of the chiplet belongs to the physical layer of the chiplet and is used to handle physical layer connections for data transmission, such as transmitting data from the chiplet to a physical channel and receiving data from the physical channel and transmitting it within the chiplet. For example, the physical layer interface may be a high-speed PHY interface and is used to handle physical layer connections for high-speed data transmission.

[0048] The physical coding sublayer 310 may belong to a part of the chiplet's physical layer and is used to implement physical layer functions in the chiplet, such as data coding, adding and processing physical layer information.

[0049] As an optional implementation, the protocol controller provided in the embodiments of this disclosure may be connected to the system bus of a chip (e.g., an SOC chip) and the physical coding sublayer of a chiplet, for example, the protocol controller is connected between the system bus of the chip (e.g., an SOC chip) and the physical coding sublayer of a chiplet. The protocol controller is connected to the system bus via two sets of bus interfaces (i.e., a first bus interface and a second bus interface) to access the internal bus or on-chip bus of the chip (e.g., an SOC chip), and simultaneously connected to the physical coding sublayer of a chiplet via one set of bus interfaces (i.e., a third bus interface) to connect to the physical coding sublayer of the chiplet, and to other chiplets or peripherals via the physical layer interface of the chiplet. In other words, the chiplet is connected upward to the system bus of the chip (e.g., an SOC chip) via the bus interface of the protocol controller and downward to other chiplets or peripherals via the physical layer interface.

[0050] In selectable implementations, the protocol used by the system bus may also be called the system bus protocol, and the system bus protocol may be a standard system bus protocol, such as the AXI (Advanced eXtensible Interface) protocol, or a customized system bus protocol. In selectable implementations, the third bus interface of the protocol controller and the physical coding sublayer may be connected using a physical layer bus, and this physical layer bus may use a standard bus protocol such as the PIPE (PHY Interface for PCI Express) protocol, or a customized bus protocol. For example, if the peripheral protocol is the CXL protocol, the physical layer may use the PCIE (Peripheral Component Interconnect Express) bus interface standard, and the physical layer bus connecting the third bus interface of the protocol controller and the physical coding sublayer may be implemented based on the PIPE protocol, based on the CXL protocol and the PCIE protocol.

[0051] As a selectable implementation, a protocol may have multiple layers, such as a transport layer, a data link layer, and a physical layer. The physical layer of the protocol, as the lowest layer, is responsible for defining electrical characteristics, transmission medium, and connection interface, and is used to ensure correct device connection and data transmission. The data link layer is responsible for managing data transmission, such as data packetization, error detection, and correction. The transport layer is responsible for controlling data transmission and is used to ensure reliable data transmission. Based on this, Figure 4 illustrates an exemplary protocol controller according to an embodiment of the present disclosure, and as shown in Figures 3 and 4, the protocol controller 200 in the chiplet may include a bus interface module 410, a transport layer module 420, a data link layer module 430, and a physical layer module 440.

[0052] The bus interface module 410 can manage the connection between the protocol controller 200 and the bus interface connected to the system bus. Based on the fact that the protocol controller is equipped with a first bus interface and a second bus interface, each connected to the system bus, the bus interface module can manage the connection of the first bus interface and the second bus interface, respectively. As an optional implementation, Figure 5 illustrates an example of a bus interface module according to an embodiment of this disclosure, and as shown in Figure 5, the bus interface module 410 may include a first interface management module 411 and a second interface management module 412.

[0053] The first interface management module 411 is used for managing the connection between the first bus interface 210 and the system bus. That is, if the first bus interface 210 implements a subprotocol of the first part of the inter-chip interconnection protocol and the peripheral device protocol, the connection management between the first bus interface 210 and the system bus can be implemented by the first interface management module 411.

[0054] Furthermore, since the first bus interface 210 corresponds to the bus corresponding to the inter-chip interconnection protocol and the bus corresponding to the first part of the peripheral device protocol, the first interface management module 411 managing the connection between the first bus interface 210 and the system bus can be considered as the first interface management module 411 managing the connection between the bus corresponding to the inter-chip interconnection protocol and the bus corresponding to the first part of the peripheral device protocol and the system bus. In one implementation example, if the peripheral device protocol is the CXL protocol and the first part of the peripheral device protocol's subprotocols are the CXL.CACHE subprotocol and the CXL.MEM subprotocol, the first interface management module 411 can achieve connection management between the bus corresponding to the CXL.CACHE subprotocol and the CXL.MEM subprotocol and the system bus, and connection management between the bus corresponding to the inter-chip interconnection protocol and the system bus.

[0055] The second interface management module 412 is used to manage the connection between the second bus interface 220 and the system bus. That is, if the second bus interface 220 implements a subprotocol of the second part of the peripheral device protocol, the connection management between the second bus interface 220 and the system bus can be implemented by the second interface management module 412. Since the second bus interface 220 corresponds to the bus corresponding to the subprotocol of the second part of the peripheral device protocol, the second interface management module 412 managing the connection between the second bus interface 220 and the system bus can be considered as the second interface management module 412 managing the connection between the bus corresponding to the subprotocol of the second part of the peripheral device protocol and the system bus. In one implementation example, if the peripheral device protocol is the CXL protocol and the subprotocol of the second part of the peripheral device protocol is the CXL.IO subprotocol, the second interface management module 412 can implement the connection management between the bus corresponding to the CXL.IO subprotocol and the system bus.

[0056] In selectable implementations, the interface management module within the bus interface module can manage the connection and disconnection of the corresponding bus interface to the system bus by statistically tracking the internal status of the protocol controller and, based on the statistically tracked internal status of the protocol controller and the status of the corresponding bus interface on the system bus. In other words, the connection or disconnection of the first bus interface to the system bus, and the connection or disconnection of the second bus interface to the system bus, are managed by the corresponding interface management module based on the internal status of the protocol controller to the protocol and the status of the corresponding bus interface on the system bus.

[0057] As an optional implementation, the internal status of the protocol controller for a protocol is, for example, the processing status of the protocol for an internal module of the protocol controller, and for example, the processing status of protocol-related submodules within the transport layer module 420 and data link layer module 430 of the protocol controller.

[0058] In selectable implementations, the first interface management module can manage the connection and disconnection between the first bus interface and the system bus based on the internal status of the protocol controller's inter-chip interconnection protocol and the first part of the peripheral protocol's subprotocols, and the status of the first bus interface.

[0059] In one implementation example, taking the connection management of the first bus interface as an example, the first part of the subprotocols of the inter-chip interconnect protocol and the peripheral device protocol are implemented based on the first bus interface, and at this time, the processing status of the internal modules of the protocol controller for the first part of the subprotocols of the inter-chip interconnect protocol and the peripheral device protocol is both in an idle state (for example, the submodules in the transport layer module 420 and data link layer module 430 of the protocol controller that are related to the first part of the subprotocols of the inter-chip interconnect protocol and the peripheral device protocol are both in an idle state), and the inter-chip interconnect protocol and peripheral device If the corresponding first bus interface in the system bus of a subprotocol of the first part of the protocol is also in an idle state, the connection between the first bus interface and the system bus can be disconnected. If any of the internal modules of the protocol controller have data processing operations for the first part of the inter-chip interconnect protocol or the subprotocol of the first part of the peripheral protocol (for example, if any of the submodules in the transport layer module 420 and data link layer module 430 of the protocol controller that are related to the inter-chip interconnect protocol or the subprotocol of the first part of the peripheral protocol have data processing operations), the connection between the first bus interface and the system bus can be restored.

[0060] For example, if the peripheral device protocol is the CXL protocol, and the subprotocols of the first part of the peripheral device protocol are the CXL.CACHE subprotocol and the CXL.MEM subprotocol, then if the submodules in the transport layer module 420 and the data link layer module 430 related to the CXL.CACHE subprotocol, the CXL.MEM subprotocol, and the inter-chip interconnection protocol are all in an idle state, and statistically determined to be in an idle state, then the first interface management module can disconnect the connection between the first bus interface and the system bus. If statistically determined to be in an idle state for any of the submodules in the transport layer module 420 and the data link layer module 430 related to the CXL.CACHE subprotocol, the CXL.MEM subprotocol, and the inter-chip interconnection protocol, then the connection between the first bus interface and the system bus can be restored.

[0061] In selectable implementations, the second interface management module can manage the connection and disconnection between the second bus interface and the system bus based on the internal status of the second part of the protocol controller's peripheral protocol subprotocol and the status of the second bus interface.

[0062] In one implementation example, taking the connection management of the second bus interface as an example, if the second bus interface is used to implement a subprotocol of the second part of the peripheral protocol, and the processing status of the internal modules of the protocol controller for the subprotocol of the second part of the peripheral protocol is all in an idle state (for example, the submodules related to the subprotocol of the second part of the peripheral protocol in the transport layer module 420 and the data link layer module 430 of the protocol controller are all in an idle state), and the corresponding second bus interface on the system bus of the subprotocol of the second part of the peripheral protocol is also in an idle state, then the second interface management module can disconnect the connection between the second bus interface and the system bus. If there is a data processing operation for the subprotocol of the second part of the peripheral protocol in any of the internal modules of the protocol controller (for example, there is a data processing operation in any submodule related to the subprotocol of the second part of the peripheral protocol in the transport layer module 420 and the data link layer module 430 of the protocol controller), then the second interface management module can restore the connection between the second bus interface and the system bus.

[0063] Taking the CXL.IO subprotocol as an example, if the CXL.IO subprotocol is the subprotocol of the second part of the peripheral device protocol, the interface management module can disconnect the connection between the second bus interface and the system bus if it statistically determines that all submodules related to the CXL.IO subprotocol in the transport layer module 420 and the data link layer module 430 are in an idle state, and the corresponding second bus interface on the CXL.IO subprotocol system bus is also in an idle state. If there are data processing operations in any of the submodules related to the CXL.IO subprotocol in the transport layer module 420 and the data link layer module 430, the second interface management module can restore the connection between the second bus interface and the system bus.

[0064] Furthermore, the interface management module can manage the connection between the first bus interface and the system bus, and the connection between the second bus interface and the system bus, respectively, by performing hardware monitoring and statistics on the internal status of the protocol controller's protocol and the status of the corresponding bus interface on the system bus. The embodiments of this disclosure do not limit the hardware implementation method for the interface management module to monitor and statistics on the internal status of the protocol controller's protocol and the status of the corresponding bus interface on the system bus.

[0065] Returning to Figure 4, the transport layer module 420 is responsible for data transmission control of the protocol controller. Based on the requirement that the protocol controller supports the inter-chip interconnect protocol and the peripheral device protocol, and that a first bus interface is provided to implement the first part of the subprotocols of the inter-chip interconnect protocol and the peripheral device protocol, and a second bus interface is provided to implement the second part of the subprotocols of the peripheral device protocol, the transport layer module 420 can implement data transmission control of the inter-chip interconnect protocol and the first part of the subprotocols of the peripheral device protocol, and can also implement data transmission control of the second part of the subprotocols of the peripheral device protocol. In other words, the embodiments of this disclosure can implement the design of the transport layer of the transport layer module 420 for the transport layer of the inter-chip interconnect protocol and the first part of the subprotocols of the peripheral device protocol (e.g., CXL.CACHE subprotocol, CXL.MEM subprotocol), and for the transport layer of the second part of the subprotocols of the peripheral device protocol (e.g., CXL.IO subprotocol).

[0066] In selectable implementations, the transport layer module 420 may be connected to the system bus via a bus interface between the protocol controller and the system bus. That is, in selectable implementations where the transport layer module 420 is connected to the system bus and the data link layer module 430, and the transport layer interface of the transport layer module 420 is connected to the system bus via a bus interface between the protocol controller and the system bus, the transport layer interface of the transport layer module 420 is connected to the system bus via a bus interface between the protocol controller and the system bus, for example, the transport layer interface of the transport layer module 420 is connected to the system bus via a first bus interface and a second bus interface, respectively.

[0067] As an example of a selectable implementation, Figure 6A illustrates an exemplary transport layer module according to an embodiment of the present disclosure. As shown in Figure 6A, the transport layer module 420 is equipped with two transport layer submodules, which are divided into a first transport layer submodule 601 and a second transport layer submodule 602. The first transport layer submodule 601 implements data transmission control for the first part of the inter-chip interconnection protocol and the peripheral device protocol subprotocols, while the second transport layer submodule 602 implements data transmission control for the second part of the peripheral device protocol subprotocols. For example, the first transport layer submodule can implement data transmission control for the inter-chip interconnection protocol, the CXL.CACHE subprotocol and the CXL.MEM subprotocol, and the second transport layer submodule can implement data transmission control for the CXL.IO subprotocol.

[0068] In selectable implementations, to reduce the hardware resource occupation of the transport layer module, the transport layer module may have multiple submodules shared by two transport layer submodules (a first transport layer submodule and a second transport layer submodule), and these multiple submodules may be some of the submodules within the transport layer module, that is, two transport layer submodules (a first transport layer submodule and a second transport layer submodule) installed in the transport layer module 420 can share some of the submodules within the transport layer.

[0069] In an optional implementation, Figure 6B illustrates another exemplary diagram of a transport layer module according to an embodiment of the present disclosure, and as shown in Figure 6B, a plurality of submodules within the transport layer module 420 that are shared by the first transport layer submodule and the second transport layer submodule may be divided into at least a first transport layer submodule set and a second transport layer submodule set.

[0070] The first transport layer submodule set is used to process requests that need to be sent to the system bus from peripheral devices or other chiplets, and responses that need to be sent from the system bus to peripheral devices or other chiplets. The transport layer second submodule set is used to process requests that need to be sent from the system bus to peripheral devices or other chiplets, and responses that need to be sent from peripheral devices or other chiplets to the system bus.

[0071] In other words, the first transport layer submodule set has multiple submodules used to process requests that need to be sent from peripheral devices or other chiplets to the system bus, and responses that need to be sent from the system bus to peripheral devices or other chiplets, and may be shared by the first and second transport layer submodules. The second transport layer submodule set has multiple submodules used to process requests that need to be sent from the system bus to peripheral devices or other chiplets, and responses that need to be sent from peripheral devices or other chiplets to the system bus, and may be shared by the first and second transport layer submodules.

[0072] In a further optional implementation, as shown in Figure 6B, the submodules within the transport layer module 420 may include a transmit request queue 421, a receive response queue 422, a receive request queue 423, a transmit response queue 424, a transmit data cache 425, a receive data cache 426, a queue scheduling module 427, and a plurality of protocol parsing modules 428.

[0073] The transmit request queue 421 and the receive response queue 422 may be considered as selectable forms of the first transport layer submodule set, and the receive request queue 423 and the transmit response queue 424 may be considered as selectable forms of the second transport layer submodule set.

[0074] Furthermore, the multiple submodules within the transport layer module 420 that are shared by the first transport layer submodule and the second transport layer submodule may further include, in addition to the first transport layer submodule set (e.g., a transmit request queue 421 and a receive response queue 422) and the second transport layer submodule set (e.g., a receive request queue 423 and a transmit response queue 424), a transmit data cache 425, a receive data cache 426, and a queue scheduling module 427.

[0075] As an optional implementation, in this example implementation, the transmit request queue 421, receive response queue 422, receive request queue 423, transmit response queue 424, transmit data cache 425, receive data cache 426, and queue scheduling module 427 are multiple submodules within the transport layer module 420 that are shared by the first transport layer submodule and the second transport layer submodule. This allows the first transport layer submodule and the second transport layer submodule to share the above multiple submodules, enabling the sharing of hardware resources for the inter-chip interconnection protocol, the first part of the peripheral device protocol's subprotocols, and the second part of the subprotocols at the transport layer, thereby reducing the occupation of hardware resources.

[0076] The multiple protocol analysis modules 428 correspond to the number of protocols for which a protocol analysis module needs to be configured independently, with each protocol analysis module being used to analyze the requests and responses of the corresponding protocol. In one implementation example, the multiple protocol analysis modules may include a protocol analysis module for the inter-chip interconnect protocol, a protocol analysis module for the first part of the peripheral protocol's subprotocols, and a protocol analysis module for the second part of the peripheral protocol's subprotocols. The protocol analysis module for the inter-chip interconnect protocol is used to analyze the requests and responses of the inter-chip interconnect protocol, the protocol analysis module for the first part of the peripheral protocol's subprotocols is used to analyze the requests and responses of the first part of the subprotocols, and the protocol analysis module for the second part of the peripheral protocol's subprotocols is used to analyze the requests and responses of the second part of the subprotocols.

[0077] Taking the peripheral protocol as the CXL protocol as an example, the protocol analysis module corresponding to the first subprotocol of the peripheral protocol may include the protocol analysis module corresponding to the CXL.CACHE subprotocol and the protocol analysis module corresponding to the CXL.MEM subprotocol, and the protocol analysis module corresponding to the second subprotocol of the peripheral protocol may include the protocol analysis module corresponding to the CXL.IO subprotocol. In other words, the CXL.IO subprotocol, CXL.CACHE subprotocol, CXL.MEM subprotocol, and the inter-chip interconnection protocol each require the implementation of their own independent protocol analysis modules to analyze the requests and responses of their respective protocols.

[0078] In one implementation example, when a protocol controller is used as an inter-chip interconnect protocol controller, all requests transmitted by the protocol controller are inter-chip interconnect requests, and all responses transmitted by the protocol controller are inter-chip interconnect responses. In this case, the requests and responses can be analyzed using a protocol analysis module corresponding to the inter-chip interconnect protocol.

[0079] When a protocol controller is used as a CXL protocol controller, requests transmitted by the protocol controller may use the CXL.IO subprotocol, the CXL.CACHE subprotocol, or the CXL.MEM subprotocol, and responses transmitted by the protocol controller may use the CXL.IO subprotocol, the CXL.CACHE subprotocol, or the CXL.MEM subprotocol. In this case, it is necessary to select a protocol analysis module to analyze the requests and responses depending on the specific situation. For example, since data read / write requests and responses are mainly implemented by the CXL.CACHE subprotocol and the CXL.MEM subprotocol (i.e., the internal memory and cache subprotocols of the CXL protocol), data read / write requests and responses of the CXL protocol can be analyzed using the protocol analysis module corresponding to the CXL.CACHE subprotocol and the protocol analysis module corresponding to the CXL.MEM subprotocol. Requests and responses for reading and writing data related to the cache may be analyzed by a protocol analysis module corresponding to the CXL.CACHE subprotocol, and requests and responses for reading and writing data related to internal memory may be analyzed by a protocol analysis module corresponding to the CXL.MEM subprotocol. Furthermore, for example, since the configuration management of the input and output of the CXL protocol is mainly implemented by the CXL.IO subprotocol, requests and responses for the configuration management of the input and output of the CXL protocol can be analyzed by a protocol analysis module corresponding to the CXL.IO subprotocol.

[0080] As an optional implementation, data transmission control of the inter-chip interconnect protocol and the first part of the peripheral device protocol subprotocol is implemented based on the first transport layer submodule, and the protocol analysis module corresponding to the inter-chip interconnect protocol and the protocol analysis module corresponding to the first part of the peripheral device protocol subprotocol may be installed in the first transport layer submodule; and data transmission control of the second part of the peripheral device protocol subprotocol is implemented based on the second transport layer submodule, and the protocol analysis module corresponding to the second part of the peripheral device protocol subprotocol may be installed in the second transport layer submodule.

[0081] In selectable implementations, the transmit request queue, receive response queue, receive request queue, transmit response queue, transmit data cache, receive data cache, and queue scheduling module within the transport layer module may be set up as shared resources and shared by the first and second transport layer submodules. The embodiments of this disclosure do not limit the location of the shared submodules, which may be set up in either the first or second transport layer submodule, or in a shared resource area set up within the transport layer module.

[0082] The following describes the shared submodules within the transport layer module.

[0083] As shown in Figure 6B, the send request queue 421 is used to store at least the requests that a chiplet should send. The requests that a chiplet should send may be requests that the chiplet should send to the system bus, requests that come from peripheral devices or other chiplets connected to the chiplet and that need to be sent to the system bus, and requests that come from data read / write requests, interrupt requests, etc. For example, when a chiplet uses a peripheral device protocol (e.g., the CXL protocol), the requests that should be sent may come from peripheral devices connected to the chiplet (e.g., a CPU chiplet), and the chiplet needs to send the requests to the system bus. For example, when a chiplet uses an inter-chip interconnection protocol, the requests that should be sent may come from other chiplets (e.g., other CPU chiplets) connected to the chiplet (e.g., a CPU chiplet), and the chiplet needs to send the requests to the system bus.

[0084] In selectable implementations, as shown in Figures 3 and 4, requests to be transmitted from peripheral devices or other chiplets may be transmitted to the protocol controller via the chiplet's physical layer interface and physical coding sublayer, and within the protocol controller to the transport layer module via the physical layer module and data link layer module.

[0085] As can be seen from above, embodiments of the present disclosure can store requests to be sent from peripheral devices and other chiplets in a transmit request queue, that is, requests to be sent corresponding to peripheral device protocols (e.g., CXL protocol) and requests to be sent corresponding to inter-chip interconnect protocols can both be stored in the transmit request queue, that is, peripheral device protocols (e.g., CXL protocol) and inter-chip interconnect protocols can share the transmit request queue at the transport layer, thereby reducing the occupation of hardware resources involved when storing requests to be sent corresponding to peripheral devices (e.g., CXL protocol) and inter-chip interconnect protocols at the transport layer.

[0086] As an optional implementation, the data link layer module 430 can store requests to be sent in the request queue 421 when analyzing requests to be sent from other chiplets or peripheral devices, thereby saving the requests to be sent in the request queue 421.

[0087] The receive response queue 422 is used to store responses to be received that are marked in response to requests to be sent that have been sent in at least within the send request queue, where a sent request to be sent refers to a request that has been sent in the send request queue (the request needs to be sent to the system bus), and the sent request to be sent is dequeued and cleared from the send request queue. As an optional implementation, requests to be sent in the send request queue 421 can be sent to the system bus when the data transmission condition of sending data to the system bus is met, for example, when the bus interface used by the protocol corresponding to the request to be sent is in a status where it is connected to the system bus, and the system bus has the capability to receive the request (e.g., the system bus has space to receive the request), the data transmission condition of sending data to the system bus can be considered met, thereby allowing the transport layer module to dequeued and clear the requests to be sent in the send request queue 421 and send the dequeued requests to be sent to the bus system, and at the same time, the receive response queue 422 is marked with a response to be received for the requests to be sent to the system bus (i.e., sent requests to be sent).

[0088] In one implementation example, if the request to be sent corresponds to a peripheral protocol (e.g., the CXL protocol), when the data transmission condition of sending data to the system bus is met, the request to be sent corresponding to the peripheral protocol (e.g., the CXL protocol) can be dequeued from the request queue and sent to the system bus, and at the same time, the received response marked for the request to be sent corresponding to the peripheral protocol (e.g., the CXL protocol) can be stored in the received response queue. If the request to be sent corresponds to an inter-chip interconnect protocol, when the data transmission condition of sending data to the system bus is met, the request to be sent corresponding to the inter-chip interconnect protocol can be dequeued from the request queue and sent to the system bus, and at the same time, the received response marked for the request to be sent corresponding to the inter-chip interconnect protocol can be stored in the received response queue. In other words, both the responses to be received, marked for requests to be sent corresponding to peripheral device protocols (e.g., CXL protocol) transmitted to the system bus, and the responses to be received, marked for requests to be sent corresponding to inter-chip interconnect protocols transmitted to the system bus, can be stored in the receive response queue. This allows peripheral device protocols (e.g., CXL protocol) and inter-chip interconnect protocols to share the transport layer receive response queue, reducing the occupation of hardware resources.

[0089] Furthermore, when a request to be transmitted corresponding to the inter-chip interconnection protocol is transmitted to the system bus, it can be transmitted to a first bus interface connected to the system bus via the transport layer interface of the transport layer module, and then transmitted to the system bus via the first bus interface. When a request to be transmitted corresponding to the first part of the peripheral device protocol's subprotocols (for example, requests to be transmitted corresponding to the CXL.CACHE subprotocol and the CXL.MEM subprotocol) is transmitted to the system bus, it can be transmitted to a first bus interface connected to the system bus via the transport layer interface, and then transmitted to the system bus via the first bus interface. When a request to be transmitted corresponding to the second part of the peripheral device protocol's subprotocols (for example, requests to be transmitted corresponding to the CXL.IO subprotocol) is transmitted to the system bus, it can be transmitted to a second bus interface connected to the system bus via the transport layer interface, and then transmitted to the system bus via the second bus interface.

[0090] In a further optional implementation, when the transport layer module receives a response from the system bus (for ease of explanation, the response from the system bus may be called the first response), the transport layer module can compare the request to which the system bus's first response pertains with the request to be sent to which the response to be received stored in the receive response queue pertains. If the comparison results match, the system bus's first response can be stored in the receive response queue. If the comparison results do not match, the system bus's first response is discarded and an error is reported. If the comparison results match, the first response means that the system bus made a response to a request to be sent from a peripheral device or other chiplet, and therefore the first response and the data corresponding to the first response need to be fed back to the peripheral device or other chiplet. At this time, the transport layer module stores the first response in the receive response queue and, when the data transmission conditions are met (sending data to the data link layer), sends the first response and the data corresponding to the first response to the data link layer module and can further feed it back to the peripheral device or other chiplet.

[0091] As can be seen from the above, in further optional implementations, the receive response queue may also store the first response of the system bus, and the requests to which the stored first response of the system bus is targeted will match the requests to which the received response stored in the receive response queue is targeted.

[0092] In one implementation example, the response to be received may carry the identifier of the corresponding request to be sent, and the first response on the system bus may also carry the identifier of the target request. Therefore, embodiments of this disclosure can determine whether the request targeted by the first response on the system bus matches the request targeted by the response to be received by comparing whether the identifier carried in the response to be received matches the identifier carried in the first response on the system bus. In addition, embodiments of this disclosure can assign an independent identifier (e.g., an identification number) to each request in order to distinguish between different requests.

[0093] Furthermore, the request to which the first response of the system bus pertains may be a request to be sent corresponding to a peripheral protocol (e.g., the CXL protocol), or it may be a request to be sent corresponding to an inter-chip interconnect protocol. Responses corresponding to requests to be sent for different protocols can be transmitted to the transport layer module via the bus interface corresponding to the protocol. For example, if the first response of the system bus pertains to a request for an inter-chip interconnect protocol, the first response of the system bus pertains to the transport layer module via the system bus, the first bus interface of the protocol controller, and the transport layer interface. If the first response of the system bus pertains to a request for a subprotocol of the first part of the peripheral protocol (e.g., the CXL.CACHE subprotocol and the CXL.MEM subprotocol), the first response of the system bus pertains to the transport layer module via the system bus, the first bus interface of the protocol controller, and the transport layer interface. If the first response of the system bus pertains to a request for a subprotocol of the second part of the peripheral protocol (e.g., the CXL.IO subprotocol), the first response of the system bus pertains to the transport layer module via the system bus, the second bus interface of the protocol controller, and the transport layer interface.

[0094] In a further optional implementation, when the data transmission condition for sending data to the data link layer is met, the first response is dequeued and cleared from the receive response queue, and the first response and the data corresponding to the first response are sent to the data link layer module and further transmitted to other chiplets or peripherals. For example, when the data transmission condition for sending data to the data link layer is met, the first response and the data corresponding to the first response (the data corresponding to the first response can be stored in the receive data cache) in the receive response queue can be transmitted to the physical coding sublayer of the chiplet via the protocol controller's data link layer module and physical layer module, and further transmitted to the chiplet's physical layer interface and then to other chiplets or peripherals via the chiplet's physical layer interface.

[0095] As an optional implementation, satisfying the data transmission condition of sending data to the data link layer may, for example, mean that the data link layer module and physical layer module of the protocol controller are in a connected status and that the bandwidth between the data link layer module and the physical layer module supports the transmission of data that requires bandwidth (e.g., bandwidth supports the transmission of the first response and the data corresponding to the first response).

[0096] To facilitate understanding the process in which the transport layer module of the protocol controller sends a request to the system bus and receives a response from the system bus, Figure 6C illustrates an example of the interaction process between the protocol controller and the system bus according to an embodiment of the present disclosure as an optional implementation, and optional implementations of the interaction process described below should be referred to in the corresponding sections above. Referring to Figure 6C, the interaction process may include the following steps.

[0097] In step S610, the data link layer module stores the request to be sent in the request queue.

[0098] In selectable implementations, the data link layer module can analyze requests to be sent from peripheral devices or other chiplets and store those requests in the transport layer module's request queue.

[0099] In step S611, when the data transmission condition is met—that data should be sent to the system bus—the transport layer module dequeues the request to be sent from the transmission request queue and clears it, and then sends the request to be sent and the data corresponding to the request to be sent to the system bus.

[0100] In step S612, the transport layer module stores in the receive response queue the responses to be received that are marked in the transmit request queue to correspond to the requests to be transmitted.

[0101] When the data transmission condition is met, which is sending data to the system bus, the transport layer module can execute steps S611 and S612 synchronously.

[0102] In step S613, the system bus transmits the first response to the transport layer module.

[0103] Based on the protocol corresponding to the first response of the system bus, the first response of the system bus is transmitted to the transport layer interface via the bus interface corresponding to the protocol controller's protocol, thereby allowing access to the transport layer module.

[0104] In step S614, the transport layer module compares the request to which the first response of the system bus is to be addressed with the request to be sent, which is to which the response to be received is to be addressed.

[0105] In step S615, if the comparison results do not match, the transport layer module discards the first response from the system bus and reports an error.

[0106] In selectable implementations, the transport layer module can report error reporting information via interrupts and status registers, and can optionally transmit some error reporting information synchronously to peripherals or other chiplets via the data link layer.

[0107] In step S616, if the comparison results match, the transport layer module stores the first response from the system bus in the receive response queue.

[0108] In step S617, when the data transmission condition is met—that data is to be sent to the data link layer—the transport layer module dequeues and clears the first response from the receive response queue, and transmits the first response and the data corresponding to the first response to the data link layer module.

[0109] Step S617 is performed after step S616.

[0110] The requests and responses described above are involved in the analysis of the transport layer module. Based on the protocols used in the requests and responses, the transport layer module can be analyzed using the protocol analysis module corresponding to the protocol. For specific selectable implementation methods, please refer to the description above, and a detailed explanation is omitted here.

[0111] Returning to Figure 6B, the receive request queue 423 is used to store at least chiplet receive requests. A chiplet receive request may be a request received by the chiplet and transmitted by the system bus, or it may be a request from the system bus that needs to be sent to a peripheral device or other chiplet connected to the chiplet, or it may be request information used for data read / write requests, interrupt requests, etc. In other words, any receive request received by the chiplet and from the system bus that needs to be sent to a peripheral device or other chiplet can be stored in the receive request queue, meaning that peripheral protocols (e.g., the CXL protocol) and inter-chip interconnect protocols can share the transport layer receive request queue, thereby reducing the occupation of hardware resources.

[0112] In one implementation example, if a receive request transmitted by the system bus corresponds to a receive request corresponding to the inter-chip interconnection protocol, or to a subprotocol of the first part of the peripheral device protocol (e.g., a receive request corresponding to the CXL.CACHE subprotocol and the CXL.MEM subprotocol), the receive request transmitted by the system bus can be transmitted to the transport layer module via the first bus interface and the transport layer interface, and stored in the receive request queue. If a receive request transmitted by the system bus corresponds to a receive request of the second part of the peripheral device protocol (e.g., a receive request corresponding to the CXL.IO subprotocol), the receive request from the system bus can be transmitted to the transport layer module via the second bus interface and the transport layer interface, and stored in the receive request queue.

[0113] The transmit response queue 424 is used to store responses to be received that are marked in response to receive requests sent by chiplets, and receive requests sent by chiplets are dequeued and cleared from the receive request queue. In an optional implementation, when the data transmission condition of sending data to the data link layer is met, receive requests stored in the receive request queue 423 are dequeued and cleared, and the receive request queue and the data corresponding to the receive requests are sent to the data link layer module, and can reach the physical coding sublayer of the chiplet via the data link layer module and physical layer module, and further transmitted to peripheral devices or other chiplets via the physical layer interface of the chiplet, and at the same time, receive requests sent in the receive request queue can be marked as responses to be received, and responses to be received that are marked in response to the sent receive requests can be stored in the transmit response queue.

[0114] In one implementation example, if a receive request corresponds to a peripheral protocol (e.g., the CXL protocol), when the data transmission condition of sending data to the data link layer is met, the receive request corresponding to the peripheral protocol (e.g., the CXL protocol) can be dequeued and cleared from the receive request queue, and the receive request and the data corresponding to the receive request (the data corresponding to the receive request can be stored in the receive data cache) can be sent to the data link layer module. Simultaneously, the transmit response queue can store the response to be received, marked for the transmitted receive request corresponding to the peripheral protocol (e.g., the CXL protocol). If a receive request corresponds to an inter-chip interconnect protocol, when the data transmission condition of sending data to the data link layer is met, the receive request corresponding to the inter-chip interconnect protocol can be dequeued and cleared from the receive request queue, and the receive request and the data corresponding to the receive request can be sent to the data link layer module. Simultaneously, the transmit response queue can store the response to be received, marked for the transmitted receive request corresponding to the transmitted receive request corresponding to the inter-chip interconnect protocol. In other words, both the response to be received marked in response to a receive request corresponding to a transmitted peripheral protocol (e.g., the CXL protocol) and the response to be received marked in response to a receive request corresponding to a transmitted inter-chip interconnect protocol can be stored in the transmit response queue, thereby sharing the transmit response queue at the transport layer and reducing the occupation of hardware resources.

[0115] In selectable implementations, since the receive request and the data corresponding to the receive request are transmitted to the chiplet's physical layer (physical coding sublayer, physical layer interface) via the data link layer module and the physical layer module, satisfying the data transmission condition that a receive request corresponds to sending data to the data link layer may be considered as the data link layer module and the physical layer module being in a connected status and the bandwidth of the data link layer module and the physical layer module supporting the transmission of the receive request and the data corresponding to the receive request.

[0116] In further optional implementations, a peripheral device or other chiplet can feed back a response to the chiplet (for ease of explanation, the response fed back by the peripheral device or other chiplet may be called the second response), the second response can be parsed by the protocol controller's data link layer module, and when the data link layer module has parsed the second response fed back by the peripheral device or other chiplet, it transmits the second response to the transport layer module. This allows the transport layer module to compare the request for which the second response is relevant with the receive request for which the response to be received stored in the transmit response queue is relevant. If the comparison results match, the second response can be stored in the transmit response queue; otherwise, the second response is discarded and an error is reported. When the comparison results match, it means that the second response is a response made by the peripheral device or other chiplet to a receive request from the system bus, and therefore the second response and the data corresponding to the second response need to be fed back to the system bus. At this time, the transport layer module can feed back the second response and the data corresponding to the second response to the system bus when it has stored the second response in the transmit response queue and the data transmission conditions for sending data to the system bus are met.

[0117] As can be seen from the above, in further optional implementations, the transmit response queue may also be used to store second responses from peripherals or other chiplets, and the requests to which the stored second responses are targeted coincide with the receive requests to which the received responses stored in the transmit response queue are targeted.

[0118] In further optional implementations, when the data transmission condition for sending data to the system bus is met, the second response can be dequeued and cleared from the transmission response queue, thereby enabling the second response and the data corresponding to the second response to be sent to the system bus. In one example implementation, if the protocol corresponding to the second response is the inter-chip interconnect protocol, the second response and the data corresponding to the second response can be transmitted to the system bus via the transport layer interface and the first bus interface; if the protocol corresponding to the second response is a subprotocol of the first part of the peripheral protocol (e.g., CXL.CACHE subprotocol and CXL.MEM subprotocol), the second response and the data corresponding to the second response can be transmitted to the system bus via the transport layer interface and the first bus interface; and if the protocol corresponding to the second response is a subprotocol of the second part of the peripheral protocol (e.g., CXL.IO subprotocol), the second response and the data corresponding to the second response can be transmitted to the system bus via the transport layer interface and the second bus interface.

[0119] In selectable implementations, based on the requirement to transmit the second response and the data corresponding to the second response to the system bus via the transport layer interface, the data transmission condition that the second response corresponds to transmitting data to the system bus may be satisfied, for example, by having the bus interface and system bus corresponding to the protocol of the second response in a connected status, and the system bus having space to receive the response and data.

[0120] To facilitate understanding the process in which the system bus sends a request to the transport layer module of the protocol controller and the transport layer module feeds a response back to the system bus, Figure 6D illustrates an example of another interaction process between the protocol controller and the system bus according to an embodiment of the present disclosure as an optional implementation, and optional implementations of the interaction process described below should be referred to in the corresponding sections above. Referring to Figure 6D, the interaction process may include the following steps.

[0121] In step S620, the transport layer module stores the receive request from the system bus in the receive request queue.

[0122] Based on the protocol corresponding to the receive request, the receive request is transmitted to the transport layer interface via the bus interface corresponding to the protocol controller's protocol, thereby allowing it to enter the transport layer module.

[0123] In step S621, when the data transmission condition is met—that data must be sent to the data link layer—the receive request is dequeued and cleared from the receive request queue, and the receive request and the data corresponding to the receive request are sent to the data link layer module.

[0124] In step S622, the transport layer module stores in the transmit response queue the responses that are marked to be received in response to the receive requests that have been sent.

[0125] When the data transmission condition is met, which is to send data to the data link layer, the transport layer module can execute steps S621 and S622 synchronously.

[0126] In step S623, the data link layer module transmits a second response to the transport layer module.

[0127] The second response is a response from a peripheral device or other chiplet, transmitted by the peripheral device or other chiplet, and is transmitted to the transport layer module via the chiplet's protocol controller's data link layer module.

[0128] In step S624, the transport layer module compares the request for which the second response is to be received with the receive request for which the response to be received, stored in the transmit response queue, is to be received.

[0129] In selectable implementations, it is possible to compare whether the identifier carried in the second response matches the identifier carried in the response to be received, which is stored in the send response queue.

[0130] In step S625, if the comparison results do not match, the transport layer module discards the second response and reports an error.

[0131] In selectable implementations, the transport layer module can report error reporting information via interrupts and status registers, and can optionally transmit some error reporting information synchronously to peripherals or other chiplets via the data link layer.

[0132] In step S626, if the comparison results match, the transport layer module stores the second response in the transmit response queue.

[0133] In step S627, when the data transmission condition is met to send data to the system bus, the transport layer module dequeues and clears the second response from the transmission response queue, and transmits the second response and the data corresponding to the second response to the system bus.

[0134] Based on the protocol corresponding to the second response, the second response and the data corresponding to the second response can be transmitted to the system bus via the transport layer interface and the bus interface corresponding to the protocol controller protocol.

[0135] Returning to Figure 6B, the transmit data cache 425 is used to cache data corresponding to requests to be transmitted in the transmit request queue 421, and to cache data corresponding to the second response in the transmit response queue. In other words, when a request to be transmitted from a peripheral device or other chiplet is stored in the transmit request queue, and the data corresponding to the request to be transmitted is stored in the transmit data cache, it can be retrieved from the transmit data cache and transmitted when it is necessary to send the data corresponding to the request to be transmitted to the system bus. At the same time, when a second response (from the system bus) that needs to be fed back to a peripheral device or other chiplet is stored in the transmit response queue, and the data corresponding to the second response is stored in the transmit data cache, it can be retrieved from the transmit data cache and transmitted when it is necessary to feed the data corresponding to the second response back to a peripheral device or other chiplet.

[0136] The embodiments of this disclosure can store data corresponding to requests to be transmitted from peripheral devices or other chiplets, and data corresponding to second responses that need to be fed back to peripheral devices or other chiplets, in the transmit data cache. Therefore, the data corresponding to requests to be transmitted from peripheral devices or other chiplets, and data corresponding to second responses that need to be fed back to peripheral devices or other chiplets, can share the transmit data cache, and the protocol is not restricted (the peripheral device protocol or the inter-chip interconnection protocol is not restricted), and the occupation of hardware resources of the transmit data cache can be reduced.

[0137] The received data cache 426 is used to cache data corresponding to receive requests in the receive request queue and data corresponding to first responses in the receive response queue. In other words, when a receive request from the system bus is stored in the receive request queue and data corresponding to the receive request is stored in the received data cache, it can be retrieved from the received data cache and sent when it is necessary to send data corresponding to the receive request to a peripheral device or other chiplet. At the same time, when a first response (from a peripheral device or other chiplet) that needs to be fed back to the system bus is stored in the receive response queue and data corresponding to the first response is stored in the received data cache, it can be retrieved from the received data cache and sent when it is necessary to feed data corresponding to the first response back to the system bus.

[0138] The embodiments of this disclosure can store data corresponding to reception requests from the system bus and data corresponding to first responses that need to be fed back to the system bus in the received data cache. Therefore, the data corresponding to reception requests from the system bus and the data corresponding to first responses that need to be fed back to the system bus can share the received data cache, and the protocol is not restricted (peripheral device protocol or inter-chip interconnect protocol is not restricted), and the occupation of hardware resources of the received data cache can be reduced.

[0139] The queue scheduling module 427 is used to arbitrate scheduling the enqueue and dequeue processes of at least requests to be sent in the send request queue, first responses in the receive response queue, received requests in the receive request queue, and second responses in the send response queue. Enqueue processing refers to saving requests to a queue, and dequeue processing refers to retrieving requests from a queue. Arbitration scheduling by the queue scheduling module 427 is implemented based on at least one of the following mechanisms: request and response priority, protocol ordering requirements, letters of credit, etc. Embodiments of this disclosure do not limit the arbitration scheduling mechanism, and the arbitration scheduling mechanism can be configured according to the actual situation. For example, embodiments of this disclosure can configure the arbitration scheduling mechanism of the queue scheduling module 427 to be configurable. For example, the arbitration scheduling mechanism of the queue scheduling module is set and defined by a configuration register, thereby allowing the configuration register to change the priority of requests and responses defined by the arbitration scheduling, and further enabling configurable arbitration scheduling based on information such as the request address, priority, and request type. Embodiments of this disclosure enable the configurability of the arbitration scheduling mechanism by a configuration register and support the arbitration scheduling of requests and responses for peripheral device protocols (e.g., CXL protocol) and inter-chip interconnect protocols by sharing a queue scheduling module, thereby reducing the occupation of hardware resources.

[0140] The response format mentioned in the embodiments of this disclosure can correspond to the request format. For example, if the request to be sent is a read request, the corresponding first response may be a read response; if the request to be sent is a write request, the corresponding first response may be a write response, and the situation for the receive request and the second response is similar. The data corresponding to a read response may be understood as data that needs to be read, and the read response may carry status information related to the read response. The data corresponding to a write response may be understood as data that needs to be written, and the write response may carry the processing status of the write request related to the write response.

[0141] Embodiments of this disclosure enable the implementation of a transmit request queue, receive response queue, receive request queue, transmit response queue, transmit data cache, receive data cache, and queue scheduling module in the transport layer module of a protocol controller. Furthermore, two transport layer submodules (a first transport layer submodule and a second transport layer submodule) installed in the transport layer module can share the submodule to implement the processing of requests and responses related to peripheral device protocols (e.g., CXL protocol) between the system bus and peripheral devices, and the processing of requests and responses related to inter-chip interconnection protocols between the system bus and other chiplets. This reduces the occupation of hardware resources of the transport layer module of the protocol controller while allowing peripheral device protocols and inter-chip interconnection protocols to share the module.

[0142] As an optional implementation, Figure 7 illustrates an exemplary data link layer module according to an embodiment of the present disclosure, and as shown in Figures 4 and 7, the data link layer module 430 may include, from the perspective of the data transmission direction, a first subprotocol conversion module 711, a first subprotocol transmission data packetization module 712, an inter-chip interconnect transmission data packetization module 713, a first transmit retransmission cache module 714, a second subprotocol conversion module 715, a second subprotocol transmission data packetization module 716, and a second transmit retransmission cache module 717.

[0143] The data transmission direction of the data link layer module 430 may be such that the data link layer module 430 receives data transmitted by the transport layer module 420 and transmits data to the physical layer module 440. The data transmitted by the transport layer module 420 to the data link layer module 430 is from the system bus, and the data transmitted by the data link layer module 430 to the physical layer module 440 needs to be communicated to peripheral devices or other chiplets.

[0144] Viewed from the data reception direction of the data link layer 430, the data link layer module 430 may include a first subprotocol reception data depacketization module 721, a first subprotocol conversion module 722 in the reception direction, an inter-chip interconnect reception data depacketization module 723, a second subprotocol reception data depacketization module 724, and a second subprotocol conversion module 725 in the reception direction.

[0145] The data reception direction of the data link layer 430 may be the direction in which the data link layer 430 receives data transmitted by the physical layer module 440 and transmits the data to the transport layer module 420. The data transmitted by the physical layer module 440 to the data link layer 430 is from peripheral devices or other chiplets, and the data transmitted by the data link layer 430 to the transport layer module 420 needs to be transmitted to the system bus.

[0146] Furthermore, the protocol conversion modules involved in the data transmission and data reception directions of the data link layer module are primarily responsible for conversion between the system bus protocol (e.g., AXI protocol) and the peripheral device protocol (e.g., CXL protocol). They are involved in the conversion from the system bus protocol to the peripheral device protocol in the data transmission direction of the data link layer module, and from the peripheral device protocol to the system bus protocol in the data reception direction of the data link layer module. Note that protocol conversion is not required for inter-chip interconnection, so the data link layer module does not need to be equipped with a protocol conversion module for inter-chip interconnection.

[0147] In the selectable implementations, the subprotocols of the first part of the peripheral protocol (e.g., the CXL.CACHE subprotocol and the CXL.MEM subprotocol) and the subprotocol of the second part (e.g., the CXL.IO subprotocol) are required to implement protocol conversion modules in the data transmission and data reception directions of the data link layer, respectively. That is, the subprotocols of the first part are required to implement the transmission-direction subprotocol conversion module 711 of the first part in the data transmission direction, the subprotocols of the second part are required to implement the transmission-direction subprotocol conversion module 715 of the second part in the data transmission direction, the subprotocols of the first part are required to implement the reception-direction subprotocol conversion module 722 of the first part in the data reception direction, and the subprotocols of the second part are required to implement the reception-direction subprotocol conversion module 725 of the second part in the data reception direction.

[0148] In selectable implementations, the first part of the transmission subprotocol conversion module 711 is used to convert requests or responses and / or data in the data transmission direction of the data link layer module (corresponding to requests or responses and / or data transmitted by the transport layer module) from the system bus protocol (e.g., AXI protocol) to the first part of the peripheral protocol subprotocols (e.g., CXL.CACHE subprotocol and CXL.MEM subprotocol).

[0149] The second part of the transmission subprotocol conversion module 715 is used to convert requests or responses and / or data in the data transmission direction of the data link layer module (corresponding to requests or responses and / or data transmitted by the transport layer module) from the system bus protocol (e.g., AXI protocol) to the second part of the peripheral protocol subprotocol (e.g., CXL.IO subprotocol).

[0150] In selectable implementations, the first part subprotocol conversion module 722 in the receiving direction is coupled to the first part subprotocol received data depacketization module 721 and is used to perform conversion from the first part subprotocol of the peripheral protocol to the system bus protocol for data packets analyzed by at least the first part subprotocol received data depacketization module 721.

[0151] In selectable implementations, the receiving-direction second-part subprotocol conversion module 725 is coupled to the second-part subprotocol received data depacketization module 724 and is used to perform conversion from the second-part subprotocol of the peripheral protocol to the system bus protocol for data packets analyzed by at least the second-part subprotocol received data depacketization module 724.

[0152] The data packetization modules involved in the data transmission direction of the data link layer module described above are primarily responsible for packaging requests or responses and / or data (corresponding to requests or responses and / or data transmitted by the transport layer module) corresponding to the data transmission direction of the data link layer into data packets that match the corresponding protocol, based on the corresponding protocol. The first part of the inter-chip interconnect protocol and the peripheral device protocol (e.g., the CXL.CACHE subprotocol and the CXL.MEM subprotocol) and the second part of the subprotocol (e.g., the CXL.IO subprotocol) each need to implement a data packetization module in the data transmission direction of the data link layer. That is, the inter-chip interconnect protocol needs to implement the inter-chip interconnect data packetization module 713 in the data transmission direction, the first part of the subprotocol needs to implement the first part of the subprotocol data packetization module 712 in the data transmission direction, and the second part of the subprotocol needs to implement the second part of the subprotocol data packetization module 716 in the data transmission direction.

[0153] In selectable implementations, the inter-chip interconnect transmit data packetization module 713 may be used to package requests or responses and / or data transmitted by the transport layer module into data packets that match the inter-chip interconnect protocol, based on the inter-chip interconnect protocol.

[0154] In an optional implementation, the first subprotocol transmission data packetization module 712 is coupled to the transmission-direction first subprotocol conversion module 711, which can package the protocol requests or responses and / or data converted by the transmission-direction first subprotocol conversion module 711 into data packets that match the first subprotocol.

[0155] In an optional implementation, the second subprotocol transmission data packetization module 716 is coupled to the transmission-direction second subprotocol conversion module 715, which can package the protocol requests or responses and / or data converted by the transmission-direction second subprotocol conversion module 715 into data packets that match the second subprotocol.

[0156] For example, assuming that the length of the data packets of the CXL protocol is a predetermined length, the first subprotocol transmission data packetization module and the second subprotocol transmission data packetization module can sequentially concatenate the requests or responses and / or data of the protocol converted by the corresponding protocol conversion module into data packets of a predetermined length, thereby adding fields such as the data packet type to multiple requests or responses and concatenating them into a single data packet of a predetermined length. Of course, embodiments of this disclosure also support concatenating pure data and fields such as the data packet type into a single data packet of a predetermined length. In an example of selectable options, the predetermined length is, for example, 68 bytes.

[0157] In an optional implementation, the protocol controller may be equipped with a transmit-retransmit cache module that can cache data packets transmitted to a chiplet or peripheral device, which are data packets that have been packetized by a data link layer module. If a data packet is successfully received, it is removed from the transmit-retransmit cache module; if a data packet is not successfully received, it is retrieved from the transmit-retransmit cache module and retransmitted.

[0158] The transmit-retransmit cache module installed in the protocol controller may be, for example, a transmit-retransmit cache module involved in the data transmission direction of the data link layer module, and is used to cache data packets that have been packetized by the corresponding transmit data packetization module and to provide a data packet retransmission mechanism. For example, the transmit-retransmit cache module installed in the protocol controller may include a first transmit-retransmit cache module 714 and a second transmit-retransmit cache module 717.

[0159] The first transmit retransmit cache module 714 is connected in correspondence with the first subprotocol transmit data packetization module 712 and the inter-chip interconnect transmit data packetization module 713, and can cache data packets packetized by the first subprotocol transmit data packetization module 712 and the inter-chip interconnect transmit data packetization module 713. If the data packets packetized by the first subprotocol transmit data packetization module 712 are correctly received by a peripheral device, or if the data packets packetized by the inter-chip interconnect transmit data packetization module 713 are correctly received by another chiplet, the correctly received data packets can be deleted from the first transmit retransmit cache module 714. If the data packets are not correctly received, the incorrectly received data packets can be retrieved from the first transmit retransmit cache module 714 and retransmitted.

[0160] In response to this, the second transmission retransmission cache module 717 is connected in correspondence with the second part subprotocol transmission data packetization module 716, thereby enabling it to cache data packets packetized by the second part subprotocol transmission data packetization module 716. When data packets packetized by the second part subprotocol transmission data packetization module 716 are correctly received by a peripheral device, the correctly received data packets can be deleted from the second transmission retransmission cache module 717. If data packets are not correctly received, the incorrectly received data packets can be retrieved from the second transmission retransmission cache module 717 and retransmitted.

[0161] As an optional implementation, the receiving end of a data packet can perform a data packet check by examining a check field within the data packet. If the check is successful, the data packet is considered to have been received correctly, and at this time, the receiving end sends notification information to the transmitting end of the data packet to notify it that the data packet has been received correctly. If the transmitting end of the data packet has not received notification information that the data packet has been received correctly after a specified time, or has received notification information that the data packet was not received correctly, the data packet can be considered not to have been received correctly. Note that when sending data to a peripheral device via the protocol controller of a chiplet, the receiving end of the data packet may be the protocol controller of the peripheral device (e.g., the CXL protocol controller), and when sending data to another chiplet, the receiving end of the data packet may be the protocol controller of the other chiplet (the part of the protocol controller that supports inter-chip interconnection).

[0162] In an alternative implementation, the transmit-retransmit cache module may not be located in the data link layer module, but rather in the physical layer module 440 of the protocol controller. For example, an embodiment of the disclosure can determine the location of the transmit-retransmit cache module based on the version of the peripheral protocol. If the peripheral protocol version is version 1, the transmit-retransmit cache module may be located in the data link layer module. If the peripheral protocol version is version 2, the transmit-retransmit cache module may be located in the physical layer module, where version 2 is higher than version 1, for example, version 1 being CXL1.1 or CXL2.0, and version 2 being CXL3.0.

[0163] Returning to Figure 7, the receive data depackaging modules involved in the data reception direction of the data link layer module are primarily responsible for analyzing data packets transmitted by the physical layer module based on the corresponding protocol. The first part of the inter-chip interconnect protocol and the peripheral device protocol subprotocols (e.g., CXL.CACHE subprotocol and CXL.MEM subprotocol), and the second part of the subprotocol (e.g., CXL.IO subprotocol) each need to implement a receive data depackaging module in the data reception direction of the data link layer. Specifically, the inter-chip interconnect protocol needs to implement the inter-chip interconnect receive data depackaging module 723 in the data reception direction, the first part of the subprotocol needs to implement the first part of the subprotocol receive data depackaging module 721 in the data reception direction, and the second part of the subprotocol needs to implement the second part of the subprotocol receive data depackaging module 724 in the data reception direction.

[0164] In selectable implementations, the inter-chip interconnect receive data depacketization module 723 may be used to parse data packets from other chiplets transmitted by the physical layer module, based on the inter-chip interconnect protocol.

[0165] In an optional implementation, the first subprotocol receive data depacketing module 721 may be used to parse data packets from the peripheral device that are related to the first subprotocol, transmitted by the physical layer module, based on the first subprotocol of the peripheral device protocol.

[0166] In an optional implementation, the second part subprotocol receive data depacketing module 724 may be used to parse data packets from the peripheral device that are related to the second part subprotocol, transmitted by the physical layer module, based on the second part subprotocol of the peripheral device protocol.

[0167] As an optional implementation, Figure 8 illustrates an exemplary physical layer module according to an embodiment of the present disclosure, and as shown in Figures 4, 7, and 8, the physical layer module 440 may include a protocol arbitration module 811, a transmit / retransmit cache module 812, a physical layer coding module 813, and a physical layer decoding module 814.

[0168] The protocol arbitration module 811 may be used to arbitrate data packets for data packets packetized by the first part of the subprotocol transmission data packetization module in the data link layer module 430 and data packets packetized by the second part of the subprotocol transmission data packetization module, and to transmit the arbitrated data packets to the next module connected to the protocol arbitration module.

[0169] In selectable implementations, arbitration by the protocol arbitration module 811 may mean that when both the data packets packetized by the first subprotocol transmission data packetization module (corresponding to the data packets of the first subprotocol) and the data packets packetized by the second subprotocol transmission data packetization module (corresponding to the data packets of the second subprotocol) need to be transmitted using the physical layer bandwidth, the module arbitrates the data packets packetized by the first subprotocol transmission data packetization module (corresponding to the data packets of the first subprotocol) and the data packets packetized by the second subprotocol transmission data packetization module (corresponding to the data packets of the second subprotocol), and the data packet that wins the arbitration is entitled to be transmitted using the physical layer bandwidth. For example, when it is necessary to simultaneously transmit data packets of the CXL.IO subprotocol, CXL.CACHE subprotocol, and CXL.MEM subprotocol using the physical layer bandwidth, the CXL.IO subprotocol data packets, CXL.CACHE subprotocol data packets, and CXL.MEM subprotocol data packets can be arbitrated, and the data packet that wins the arbitration can be transmitted using the physical layer bandwidth.

[0170] As an optional implementation, the arbitration algorithm used by the protocol arbitration module 811 may be, for example, a round-robin algorithm, or other arbitration algorithms may be used, and the embodiments of this disclosure are not limited.

[0171] As an optional implementation, the transmit-retransmit cache module 812 is used to cache data packets and support the retransmission mechanism; a specific description can be found in the corresponding section above.

[0172] In selectable implementations, if the transmit-retransmit cache module is located in the data link layer module, the transmit-retransmit cache module may include the first transmit-retransmit cache module and the second transmit-retransmit cache module described above, and the related functions should be referred to in the description of the corresponding parts above.

[0173] Furthermore, if the transmit-retransmit cache module is installed in the data link layer module, the next module connected to the protocol arbitration module may be the physical layer coding module 813, and if the transmit-retransmit cache module is installed in the physical layer module, the next module connected to the protocol arbitration module may be the transmit-retransmit cache module.

[0174] In the available implementations, the physical layer coding module 813 is used to encode and transmit data packets, at least based on the physical layer protocol requirements of the chiplet.

[0175] In selectable implementations, the physical layer decoding module 814 is used to decode data received from the chiplet's physical layer, based at least on the chiplet's physical layer protocol requirements, to obtain data packets and transmit them to the data link layer module.

[0176] In selectable implementations, the physical layer coding module 813 and the physical layer decoding module 814 are coupled to the physical layer of the chiplet (e.g., the physical coding sublayer of the chiplet), thereby allowing the physical layer coding module 813 and the physical layer decoding module 814 to be connected to the physical coding sublayer of the chiplet via the third bus interface of the protocol controller.

[0177] In further optional implementations, based on the fact that the protocol controller's peripheral protocol and inter-chip interconnect protocol are connected to the chiplet's physical coding sublayer via a third bus interface, embodiments of the present disclosure can provide a mechanism for the protocol controller's peripheral protocol and inter-chip interconnect protocol to call the third bus interface in a time-division multiplexing manner to communicate data with the physical coding sublayer. For example, the time at which the protocol controller's peripheral protocol calls the third bus interface to communicate data with the physical coding sublayer and the time at which the protocol controller's inter-chip interconnect protocol calls the third bus interface can be determined in consultation with each other, thereby staggering the time at which the protocol controller's peripheral protocol calls the third bus interface and the time at which the inter-chip interconnect protocol calls the third bus interface, enabling the protocol controller's peripheral protocol and inter-chip interconnect protocol to time-division multiplex the third bus interface to communicate data with the physical coding sublayer.

[0178] In a further optional implementation, Figure 9 illustrates another exemplary diagram of a protocol controller according to an embodiment of the present disclosure, and as shown in Figures 4 and 9, the protocol controller may further include control registers 450 and a status and interrupt management module 460.

[0179] The control register 450 is used to implement a software-configurable register, which may include at least one of the following: a configuration register defined within a peripheral protocol (e.g., the CXL protocol), a customized configuration register for a peripheral protocol controller, and a configuration register for an inter-chip interconnect protocol controller, each of which may have an independent access address.

[0180] The status and interrupt management module 460 is used to implement software status registers and interrupt management, and the software status registers may include at least one of the following: status registers defined within a peripheral protocol (e.g., the CXL protocol), customized status registers of a peripheral protocol controller, and status registers of an inter-chip interconnect protocol controller.

[0181] In an optional implementation, the status and interrupt management module 460 can further implement interrupt management and interrupt reporting functions based on the interrupt configuration and interrupt status of the control register 450.

[0182] The configurable registers may be used to configure the behavior of the protocol controller. The status registers may be used to monitor the current status of the protocol controller and the data link, and may include whether or not a transmission error has occurred in the data, the current data transmission rate, and the current interrupt status.

[0183] The protocol controller provided in the embodiments of this disclosure can achieve interface multiplexing of the inter-chip interconnect protocol and the first part of the peripheral protocol subprotocols (e.g., CXL.CACHE subprotocol and CXL.MEM subprotocol) on a first bus interface connected to the system bus; in the transport layer module, in addition to the protocol analysis module, the remaining submodules of the transport layer module can all achieve multiplexing of the inter-chip interconnect protocol, the first part of the peripheral protocol subprotocol and the second part of the peripheral protocol subprotocol (e.g., CXL.IO subprotocol); in the data link layer module, the inter-chip interconnect protocol and the first part of the peripheral protocol subprotocol can share the transmit / retransmit cache module; and in the physical layer module, the inter-chip interconnect protocol, the first part of the peripheral protocol subprotocol and the second part of the peripheral protocol can share the transmit / retransmit cache module, the physical layer coding module and the physical layer decoding module. The protocol controller provided in the embodiments of this disclosure can support peripheral device protocols (e.g., CXL protocol) and inter-chip interconnection protocols. By achieving hardware resource redundancy, the protocol controller significantly reduces the occupation of hardware resources, while simultaneously reducing the resources required for chip integration and easing the complexity, thereby contributing to reduced chip costs and a shorter design cycle.

[0184] Based on the protocol controller provided in the embodiments of the present disclosure, the embodiments of the present disclosure further provide a protocol control method. As an optional implementation, Figure 10 illustrates an optional flowchart of a protocol control method according to an embodiment of the present disclosure, the method process may be applied to a protocol controller, and referring to Figure 10, the method process may include the following steps.

[0185] In step S01, the protocol controller determines the protocol currently in use.

[0186] In embodiments of this disclosure, the protocol currently used by the protocol controller may be a peripheral device protocol or an inter-chip interconnection protocol.

[0187] In step S02, if the protocol currently used by the protocol controller is a peripheral device protocol, the module separately configured for the inter-chip interconnection protocol within the protocol controller is closed.

[0188] If the protocol currently used by the protocol controller is a peripheral protocol (including subprotocols of the first and second parts of the peripheral protocol), the protocol controller is now used as a peripheral protocol controller, thereby closing off modules separately configured for inter-chip interconnect protocols within the protocol controller and reducing power consumption.

[0189] In selectable implementations, the step of closing a module separately configured for the inter-chip interconnection protocol within the protocol controller is: The steps may include closing at least one of the following modules: a software-configurable register related to the inter-chip interconnect in a control register; a software status register and interrupt management related to the inter-chip interconnect in a status and interrupt management module; a protocol analysis module corresponding to the inter-chip interconnect protocol in a transport layer module; an inter-chip interconnect transmit data packetization module in a data link layer module; and an inter-chip interconnect receive data depacketization module.

[0190] In step S03, if the protocol currently used by the protocol controller is the inter-chip interconnection protocol, the module separately configured for peripheral device protocols within the protocol controller is closed.

[0191] If the protocol currently used by the protocol controller is the inter-chip interconnect protocol, the protocol controller is now used as the inter-chip interconnect controller, which allows it to close modules that were previously configured for peripheral protocols within the protocol controller (for example, modules that were previously configured for the first part of the peripheral protocol's subprotocols and modules that were previously configured for the second part of the peripheral protocol's subprotocols), thereby reducing power consumption.

[0192] In selectable implementations, the step of closing a module separately configured for peripheral protocols within the protocol controller is: The steps may include closing at least one of the following modules: a software-configurable register related to the peripheral protocol (e.g., CXL protocol) in a control register; a software status register and interrupt management related module related to the peripheral protocol (e.g., CXL protocol) in a status and interrupt management module; a second bus interface corresponding to the subprotocol of the second part of the peripheral protocol; an analysis module corresponding to the peripheral protocol (e.g., CXL protocol) in a transport layer module (e.g., a protocol analysis module corresponding to the subprotocol of the first part in the transport layer module, and a protocol analysis module corresponding to the subprotocol of the second part); a protocol conversion module related to the peripheral protocol in a data link layer module (e.g., a subprotocol conversion module for the first part in the transmit direction, a subprotocol conversion module for the second part in the transmit direction, a subprotocol conversion module for the first part in the receive direction, and a subprotocol conversion module for the second part in the receive direction); a transmit data packetization module (e.g., a transmit data packetization module for the first subprotocol, and a transmit data packetization module for the second subprotocol); and a receive data depacketization module (e.g., a receive data depacketization module for the first subprotocol, and a receive data depacketization module for the second subprotocol).

[0193] According to the protocol control method provided in the embodiments of this disclosure, when the protocol controller uses a peripheral device protocol, the protocol controller closes a module separately configured for the inter-chip interconnect protocol within the protocol controller, thereby closing modules within the protocol controller that are not related to the currently used protocol, and thereby reducing the power consumption of the protocol controller.

[0194] The embodiments of the present disclosure further provide chiplets, which may include protocol controllers provided by the embodiments of the present disclosure.

[0195] In further optional implementations, the chiplet provided by the embodiments of this disclosure may further include a physical coding sublayer connected to a protocol controller and a physical layer interface connected to the physical coding sublayer.

[0196] Embodiments of the present disclosure further provide a system-on-a-chip, which may include a plurality of interconnected chiplets, the chiplets being chiplets according to embodiments of the present disclosure.

[0197] The embodiments of this disclosure further provide electronic devices such as terminal equipment or server equipment, which may include chiplets or system-on-chips provided by the embodiments of this disclosure.

[0198] The above describes the solutions of multiple embodiments provided by the embodiments of this disclosure. Each selectable form presented in the solutions of each embodiment can be combined or cross-referenced with each other without contradiction, thereby expanding the number of possible solutions of multiple embodiments, all of which may be considered solutions of embodiments disclosed in the embodiments of this disclosure.

[0199] While embodiments of this disclosure are disclosed as described above, this disclosure is not limited thereto. Any person skilled in the art can make any kind of changes and modifications without departing from the spirit and scope of this disclosure, and therefore the scope of protection of this disclosure should be limited to the scope defined by the claims.

Claims

1. A protocol controller applicable to a chiplet, A first bus interface connected to the system bus implements a subprotocol of the first part of the inter-chip interconnection protocol and peripheral device protocol, A second bus interface connected to a system bus that implements a subprotocol of the second part of the peripheral device protocol, the second bus interface being configured such that the subprotocol of the first part and the subprotocol of the second part are implemented by different bus interfaces, The chiplet is a protocol controller that uses one of the following protocols: an inter-chip interconnection protocol and a peripheral device protocol.

2. The protocol controller further includes a bus interface module, the bus interface module includes a first interface management module and a second interface management module. The first interface management module is used for managing the connection between the first bus interface and the system bus. The protocol controller according to claim 1, wherein the second interface management module is used for managing the connection between the second bus interface and the system bus.

3. The first interface management module is used for managing the connection between the first bus interface and the system bus. This includes managing the connection and disconnection between the first bus interface and the system bus based on the internal status of the protocol controller for the inter-chip interconnection protocol and the subprotocols of the first part, and the status of the first bus interface. The second interface management module is used for managing the connection between the second bus interface and the system bus. The protocol controller according to claim 2, comprising managing the connection and disconnection between the second bus interface and the system bus based on the internal status of the second part of the protocol controller to the subprotocol and the status of the second bus interface.

4. The first interface management module is used to manage the connection and disconnection between the first bus interface and the system bus based on the internal status of the protocol controller to the inter-chip interconnection protocol and the subprotocols of the first part, and the status of the first bus interface. If the processing status for the inter-chip interconnection protocol of the internal module of the protocol controller and the subprotocol of the first part are both in an idle state, and the first bus interface is also in an idle state, the connection between the first bus interface and the system bus is disconnected. If any internal module of the protocol controller has data processing operations for an inter-chip interconnection protocol or a subprotocol of the first part, this includes restoring the connection between the first bus interface and the system bus. The second interface management module is used to manage the connection and disconnection between the second bus interface and the system bus based on the internal status of the second part of the protocol controller for the subprotocol and the status of the second bus interface. If the processing status for the subprotocols of the second part of the internal module of the protocol controller is all in an idle state, and the second bus interface is also in an idle state, the connection between the second bus interface and the system bus is disconnected. The protocol controller according to claim 3, which includes restoring the connection between the second bus interface and the system bus if any internal module of the protocol controller has data processing operations for the subprotocol of the second part.

5. The protocol controller further includes a transport layer module, a data link layer module, and a physical layer module. The protocol controller according to claim 1, wherein the transport layer interface of the transport layer module is connected to the system bus via a first bus interface and a second bus interface, respectively, the transport layer module is connected to a data link layer module, the data link layer module is connected to the physical layer module, and the physical layer module is connected to the physical coding sublayer of the chiplet via a third bus interface of the protocol controller.

6. The transport layer module is equipped with a first transport layer submodule and a second transport layer submodule, the first transport layer submodule implements data transmission control of the inter-chip interconnection protocol and the first portion of the subprotocol, and the second transport layer submodule implements data transmission control of the second portion of the subprotocol. The protocol controller according to claim 5, wherein the transport layer module has a plurality of submodules shared by the first transport layer submodule and the second transport layer submodule, and the plurality of submodules are a subset of the submodules within the transport layer module.

7. The aforementioned multiple submodules are, A transport layer first submodule set for processing requests that need to be sent to the system bus from peripheral devices or other chiplets, and responses that need to be sent from the system bus to peripheral devices or other chiplets, The protocol controller according to claim 6, comprising at least a transport layer second submodule set for processing requests that need to be sent from the system bus to peripheral devices or other chiplets, and responses that need to be sent from peripheral devices or other chiplets to the system bus.

8. The transport layer first submodule set includes at least a transmit request queue and a receive response queue, The aforementioned transmission request queue is used to store at least requests from peripheral devices or other chiplets connected to the chiplet that need to be transmitted to the system bus, The receive response queue is used to store at least the receive response marked in the send request queue corresponding to the request to be sent, and to store the first response of the system bus, and the request to which the stored first response applies matches the request to which the receive response stored in the receive response queue applies. When the data transmission condition for sending data to the system bus is met, the request to be sent is dequeued and cleared from the send request queue, and the request to be sent and the data corresponding to the request to be sent are sent to the system bus. When the data transmission condition for sending data to the data link layer is met, the first response is dequeued and cleared from the receive response queue, and the first response and the data corresponding to the first response are sent to the data link layer module. The transport layer second submodule set includes at least a receive request queue and a transmit response queue, The aforementioned receive request queue is used to store at least receive requests for chiplets that need to be sent from the system bus to peripheral devices or other chiplets connected to the chiplet. The transmit response queue is used to store at least the response to be received that is marked in response to a transmitted receive request, and to store the second response of a peripheral device or other chiplet, and the request to which the stored second response is directed matches the receive request to which the response to be received stored in the transmit response queue is directed. The protocol controller according to claim 7, wherein when the data transmission condition of sending data to the data link layer is met, the receive request is dequeued and cleared from the receive request queue, and the receive request and the data corresponding to the receive request are sent to the data link layer module, and when the data transmission condition of sending data to the system bus is met, the second response is dequeued and cleared from the transmit response queue, and the second response and the data corresponding to the second response are sent to the system bus.

9. The aforementioned submodules further include a transmit data cache, a receive data cache, and a queue scheduling module. The transmitted data cache is used to cache at least the data corresponding to the requests to be transmitted in the transmitted request queue, and the data corresponding to the second response in the transmitted response queue. The received data cache is used to cache at least the data corresponding to the received requests in the received request queue and the data corresponding to the first response in the received response queue. The protocol controller according to claim 8, wherein the queue scheduling module is used to arbitrate scheduling of enqueue and dequeue processing of requests to be sent in a send request queue, first responses in a receive response queue, receive requests in a receive request queue, and second responses in a send response queue, and the arbitration scheduling mechanism of the queue scheduling module is set and defined by a configuration register.

10. The transport layer module is equipped with multiple protocol analysis modules, and the number of these multiple protocol analysis modules corresponds to the number of protocols for which a protocol analysis module needs to be configured independently. The plurality of protocol analysis modules include a protocol analysis module corresponding to an inter-chip interconnection protocol, a protocol analysis module corresponding to a subprotocol of the first part, and a protocol analysis module corresponding to a subprotocol of the second part. The protocol controller according to claim 6, wherein a protocol analysis module corresponding to the inter-chip interconnection protocol and a protocol analysis module corresponding to the subprotocol of the first part are installed in the first transport layer submodule, and a protocol analysis module corresponding to the subprotocol of the second part is installed in the second transport layer submodule.

11. The data link layer module includes a first subprotocol conversion module in the transmission direction, a first subprotocol transmission data packetization module, an inter-chip interconnect transmission data packetization module, a second subprotocol conversion module in the transmission direction, and a second subprotocol transmission data packetization module. The first part of the transmission direction subprotocol conversion module is used to perform conversion from the system bus protocol to the first part of the peripheral device protocol subprotocol for requests or responses and / or data transmitted by the transport layer module. The first subprotocol transmission data packetization module is used to package requests or responses and / or data of a protocol converted by the first subprotocol conversion module in the transmission direction into data packets that match the first subprotocol. The aforementioned inter-chip interconnect transmission data packetization module is used, at a minimum, to package requests or responses and / or data transmitted by the transport layer module into data packets that match the inter-chip interconnect protocol, based on the inter-chip interconnect protocol. The second part of the transmission direction subprotocol conversion module is used to perform conversion from the system bus protocol to the second part of the peripheral device protocol subprotocol for requests or responses and / or data transmitted by the transport layer module. The second part of the subprotocol transmission data packetization module is used to package the requests or responses and / or data of the protocol converted by the second part of the transmission subprotocol conversion module into data packets that match the second part of the subprotocol. The data link layer module further includes a first subprotocol receiving data depackaging module, a first subprotocol conversion module in the receiving direction, an inter-chip interconnect receiving data depackaging module, a second subprotocol receiving data depackaging module, and a second subprotocol conversion module in the receiving direction. The first subprotocol receiving data depacketing module is used to analyze data packets from a peripheral device that are transmitted by the physical layer module and relate to the first subprotocol, based at least on the first subprotocol of the peripheral device protocol. The first portion of the receiving subprotocol conversion module is used to perform conversion from the first portion of the peripheral device protocol to the system bus protocol for data packets analyzed by the first portion of the subprotocol receiving data depacketization module. The inter-chip interconnect receive data depacketing module is used, at a minimum, to analyze data packets from other chiplets transmitted by the physical layer module based on the inter-chip interconnect protocol. The second subprotocol receiving data depacketing module is used to analyze data packets from the peripheral device that are transmitted by the physical layer module and relate to the second subprotocol, based at least on the second subprotocol of the peripheral device protocol. The protocol controller according to claim 5, wherein the subprotocol conversion module of the second portion in the receiving direction is used to perform conversion from the subprotocol of the second portion of the peripheral device protocol to the system bus protocol for data packets analyzed by the subprotocol receiving data depacketization module of the second portion.

12. The physical layer module includes a protocol arbitration module, a physical layer coding module, and a physical layer decoding module. The protocol arbitration module is used to arbitrate data packets with respect to data packets packetized by the first part of the subprotocol transmission data packetization module within the data link layer module, and data packets packetized by the second part of the subprotocol transmission data packetization module, and to transmit the arbitrated data packets to the next module connected to the protocol arbitration module. The physical layer coding module is used to encode and transmit data packets based at least on the physical layer protocol requirements of the chiplet. The physical layer decoding module is used to decode data received from the physical layer of a chiplet, obtain a data packet, and transmit it to the data link layer module, based at least on the protocol requirements of the chiplet's physical layer. The protocol controller further includes a transmit-retransmit cache module, The transmit-retransmit cache module is used to cache data packets transmitted to a chiplet or peripheral device, which are data packets packetized by the data link layer module. If a data packet is received correctly, the correctly received data packet is removed from the transmit-retransmit cache module. If a data packet is not received correctly, the incorrectly received data packet is retrieved from the transmit-retransmit cache module and retransmitted. The transmit-retransmit cache module is installed in the data link layer module or the physical layer module. The protocol controller according to claim 11, wherein if the version of the peripheral device protocol is the first version, the transmit-retransmit cache module is installed in the data link layer module, and if the version of the peripheral device protocol is the second version, the transmit-retransmit cache module is installed in the physical layer module, and the second version is higher than the first version.

13. The transmit-retransmit cache module is installed in the data link layer module, and the transmit-retransmit cache module includes a first transmit-retransmit cache module and a second transmit-retransmit cache module. The first transmit-retransmit cache module is used to cache data packets packetized by at least the first portion of the subprotocol transmit-data packetization module and the inter-chip interconnect transmit-data packetization module. If the data packets packetized by the first portion of the subprotocol transmit-data packetization module are correctly received by a peripheral device, or if the data packets packetized by the inter-chip interconnect transmit-data packetization module are correctly received by another chiplet, the correctly received data packets are deleted from the first transmit-retransmit cache module. If the data packets are not correctly received, the incorrectly received data packets are retrieved from the first transmit-retransmit cache module and retransmitted. The protocol controller according to claim 12, wherein the second transmit-retransmit cache module is used to cache data packets packetized by the second part of the subprotocol transmit-data packetization module, and when the data packets packetized by the second part of the subprotocol transmit-data packetization module are correctly received by a peripheral device, the correctly received data packets are deleted from the second transmit-retransmit cache module, and when the data packets are not correctly received, the incorrectly received data packets are retrieved from the second transmit-retransmit cache module and retransmitted.

14. The protocol controller according to claim 12, wherein when the transmit-retransmit cache module is installed in the physical layer module, the next module connected to the protocol arbitration module is the transmit-retransmit cache module, and when the transmit-retransmit cache module is installed in the data link layer module, the next module connected to the protocol arbitration module is the physical layer encoding module.

15. The protocol controller further includes control registers and status and interrupt management modules. The control register is used to implement a software-configurable register, which includes at least one of the following: a configuration register defined in a peripheral protocol, a customized configuration register for a peripheral protocol controller, and a configuration register for an inter-chip interconnect protocol controller. The status and interrupt management module is used to implement software status registers and interrupt management, and the software status registers include at least one of the status registers defined in the peripheral protocol, customized status registers of the peripheral protocol controller, and status registers of the inter-chip interconnect protocol controller. The protocol controller according to claim 5, further used to implement interrupt management and interrupt reporting based on the interrupt configuration and interrupt status of the control registers, the status and interrupt management module is further used.

16. A protocol control method applicable to a protocol controller according to any one of claims 1 to 15, The step of determining the protocol currently being used by the protocol controller, If the protocol currently used by the protocol controller is a peripheral device protocol, the step is to close the module that has been separately configured for the inter-chip interconnection protocol within the protocol controller, A protocol control method that includes the step of closing a module separately configured for peripheral device protocols within a protocol controller if the protocol currently used by the protocol controller is an inter-chip interconnection protocol.

17. The step of closing a module separately configured for the inter-chip interconnection protocol within the protocol controller is: The protocol control method according to claim 16, comprising the step of closing at least one module among a software-configurable register related to inter-chip interconnection in a control register, a software status register and interrupt management related to inter-chip interconnection in a status and interrupt management module, a protocol analysis module corresponding to the inter-chip interconnection protocol in a transport layer module, an inter-chip interconnection transmit data packetization module and an inter-chip interconnection receive data depacketization module in a data link layer module.

18. The step of closing a module separately configured for peripheral device protocols within the protocol controller is: A protocol control method according to claim 17, comprising the step of closing at least one module among a software-configurable register related to the peripheral device protocol in a control register, a software status register and interrupt management related module related to the peripheral device protocol in a status and interrupt management module, a second bus interface corresponding to a subprotocol of the second part of the peripheral device protocol, a protocol analysis module corresponding to a subprotocol of the first part and a protocol analysis module corresponding to a subprotocol of the second part in a transport layer module, a first part subprotocol conversion module in the transmission direction, a first part subprotocol transmission data packetization module, a second part subprotocol conversion module in the transmission direction, a second part subprotocol transmission data packetization module, a first part subprotocol reception data depacketization module, a first part subprotocol conversion module in the reception direction, a second part subprotocol reception data depacketization module, and a second part subprotocol conversion module in the reception direction.

19. A chiplet comprising a protocol controller according to any one of claims 1 to 15.

20. The chiplet according to claim 19, further comprising a physical coding sublayer connected to a protocol controller and a physical layer interface connected to the physical coding sublayer.

21. A system-on-a-chip comprising a plurality of interconnected chiplets, wherein the chiplets include the chiplets described in claim 19.

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