Semiconductor structure and method for manufacturing the same

Abstract

To provide a semiconductor structure and a manufacturing method thereof.SOLUTION: A semiconductor structure includes: a substrate having a cell area and a terminal area, and having a first surface, a second surface positioned in the terminal area, and a third surface positioned in the cell area, facing the first surface, the second surface and the third surface being adjacent to each other, and positioned at different levels; a first trench structure positioned in the cell area, extending toward the first surface across the third surface, including a first semiconductor material layer and a first oxide layer partially projecting from the third surface, and extending toward a first direction that is parallel to the third surface; and a second trench structure positioned in the cell area, including a second semiconductor material layer and a second oxide layer partially projecting from the third surface, and extending in parallel to the first direction. A dope area is provided between the first trench structure and the second trench structure of the third surface, and the dope area extends in parallel to the third surface and toward a second direction that is vertical to the first direction.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a method for manufacturing the same, and more specifically, to a rectifier device of a trench-type metal-oxide semiconductor (MOS) structure and a method for manufacturing the same.

Background Art

[0002] Modern power circuits must have high-output, low-loss, and high-speed-switching rectifiers. For high-voltage applications that require a high breakdown voltage and a high operating temperature, a P-N junction gate rectifier with a high switching speed is always adopted. For low-voltage applications that require a high switching speed and a very low forward bias, a Schottky barrier rectifier is always adopted. A Schottky barrier rectifier is a plurality of carrier devices that operate a metal-oxide semiconductor (MOS) process, and only a very small reverse leakage current flowing through during the recovery process is allowed. Unfortunately, when operating at a high temperature, the Schottky barrier rectifier will receive a high reverse leakage current that is not desired to appear.

[0003] With a series of improvement measures currently adopted, the blocking ability of the Schottky rectifier has been improved. One of this type of improvement method is to utilize a junction barrier Schottky (JBS) rectifier, which combines a P / N junction gate with a sufficiently small Schottky barrier region and expands the space charge region from the P-N junction gate to eliminate the reduction of the Schottky barrier caused by mirror charges.

[0004] Another improvement method of this type is to utilize Schottky barrier diodes (SBDs), which have a relatively low forward voltage and are advantageous for reducing forward power loss. However, SBDs also have a relatively high reverse leakage current, leading to relatively high reverse power loss, which is a technical bottleneck in this type of device.

[0005] Therefore, existing rectifier devices require further improvement to achieve more ideal high power output and low loss, making them suitable for high-speed switching applications. [Overview of the project]

[0006] The embodiments of this disclosure relate to a semiconductor structure. The semiconductor structure is defined as a substrate having a cell area and a terminal area adjacent to the cell area as viewed from a top view, and having a first surface, a second surface facing the first surface and located within the terminal area, and a third surface facing the first surface and located within the cell area, wherein the second surface and the third surface are adjacent to each other and located at different levels, and a first trench structure located within the cell area and extending across the third surface toward the first surface, comprising at least a first semiconductor material layer protruding from the third surface and a first oxide layer surrounding the first semiconductor material, and the third surface and The invention includes a first trench structure extending in a parallel first direction, and a second trench structure located within a cell area and extending across a third surface to the first surface, comprising a second semiconductor material layer at least partially protruding from the third surface and a second oxide layer surrounding the second semiconductor material, and extending parallel to the first direction, wherein a first dope area is provided on the third surface of the substrate, and when viewed from an overhead angle, the first dope area is located between the first trench structure and the second trench structure, and the first dope area extends in a second direction parallel to the third surface and perpendicular to the first direction.

[0007] Embodiments of this disclosure relate to a method for manufacturing a semiconductor structure. The method involves forming a first trench, a second trench, and a third trench in a substrate, spaced apart and extending along a first direction and from a second surface toward a first surface opposite the second surface, wherein the substrate is defined to have a cell area and a termination area as viewed from a top view, the first and second trenches are located in the cell area, and the third trench is located in the termination area, and a first oxide layer is formed in the first trench and a second oxide layer is formed in the second trench. and a third oxide layer is formed in the third trench, and a first semiconductor material layer is formed in the first trench such that the first semiconductor material layer is surrounded by the first oxide layer and forms a first trench structure, a second semiconductor material layer is formed in the second trench such that the second semiconductor material layer is surrounded by the second oxide layer and forms a second trench structure, and a third semiconductor material is formed in the third trench such that the third semiconductor material layer is surrounded by the third oxide layer and forms a third trench structure The method includes forming a layer in a third trench, forming a shielding layer on a cell area, a first trench structure, and a second trench structure, and performing an etching process on the shielding layer to form a first opening and a second opening, wherein the first opening is extended along a first direction to at least partially expose a first semiconductor material layer, and the second opening is extended along a second direction perpendicular to the first direction to at least partially expose a second surface and a first trench structure, and after the first etching process, performing a second etching process on the second opening to form a third surface on the substrate and to at least partially cause the first trench structure and the second trench structure to protrude from the third surface of the cell area, and forming a first doped area on the third surface exposed near the second opening, wherein, when viewed from an overhead angle, the first doped area is located between the first trench structure and the second trench structure and extends toward the second direction.

[0008] The following detailed description, when combined with the attached drawings, will best provide an understanding of some embodiments of this disclosure. It should be noted that the various structures may not be drawn to scale. In fact, for clarity of explanation, the dimensions of the various structures can be arbitrarily enlarged or reduced. [Brief explanation of the drawing]

[0009] [Figure 1] This is a top view of a semiconductor structure based on a certain embodiment of the present invention. [Figure 2] This is a cross-sectional view along the line A-A' shown in Figure 1 of a semiconductor structure based on a certain embodiment of the present application. [Figure 3] This is a cross-sectional view along the B-B' tangent shown in Figure 1 of a semiconductor structure based on a certain embodiment of the present application. [Figure 4] This is a cross-sectional view along the C-C' tangent shown in Figure 1 of a semiconductor structure based on a certain embodiment of the present application. [Figure 5] This is one or more steps in a method for manufacturing a semiconductor structure based on certain embodiments of the present application. [Figure 6] This is one or more steps in a method for manufacturing a semiconductor structure based on certain embodiments of the present application. [Figure 7] This is one or more steps in a method for manufacturing a semiconductor structure based on certain embodiments of the present application. [Figure 8] This is one or more steps in a method for manufacturing a semiconductor structure based on certain embodiments of the present application. [Figure 9] This is one or more steps in a method for manufacturing a semiconductor structure based on certain embodiments of the present application. [Figure 10] This is one or more steps in a method for manufacturing a semiconductor structure based on certain embodiments of the present application. [Figure 11] This is one or more steps in a method for manufacturing a semiconductor structure based on certain embodiments of the present application. [Figure 12]This is one or more steps in a method for manufacturing a semiconductor structure based on certain embodiments of the present application. [Figure 13] This is one or more steps in a method for manufacturing a semiconductor structure based on certain embodiments of the present application. [Figure 14] This is one or more steps in a method for manufacturing a semiconductor structure based on certain embodiments of the present application. [Figure 15] This is one or more steps in a method for manufacturing a semiconductor structure based on certain embodiments of the present application. [Figure 16] This is one or more steps in a method for manufacturing a semiconductor structure based on certain embodiments of the present application. [Figure 17] This is one or more steps in a method for manufacturing a semiconductor structure based on certain embodiments of the present application. [Figure 18] This is one or more steps in a method for manufacturing a semiconductor structure based on certain embodiments of the present application. [Figure 19] This is one or more steps in a method for manufacturing a semiconductor structure based on certain embodiments of the present application. [Figure 20] This is one or more steps in a method for manufacturing a semiconductor structure based on certain embodiments of the present application. [Figure 21] This is one or more steps in a method for manufacturing a semiconductor structure based on certain embodiments of the present application. [Figure 22] This is one or more steps in a method for manufacturing a semiconductor structure based on certain embodiments of the present application. [Figure 23] This is one or more steps in a method for manufacturing a semiconductor structure based on certain embodiments of the present application. [Figure 24] This is one or more steps in a method for manufacturing a semiconductor structure based on certain embodiments of the present application. [Figure 25] This is one or more steps in a method for manufacturing a semiconductor structure based on certain embodiments of the present application.

Best Mode for Carrying Out the Invention

[0010] Identical or similar components are denoted with like reference numerals throughout the drawings and the detailed description. By incorporating the attached drawings into the following detailed description, certain embodiments of the present disclosure can be readily understood.

[0011] The following disclosure provides numerous different examples or exemplifications for implementing different features of the provided target. In the following, specific examples of components and arrangements will be described. Of course, these are merely examples and are not intended to be limiting. In the present disclosure, references to forming a first feature above or on a second feature can include embodiments where the first and second features are formed so as to be in direct contact, and further can include embodiments where another feature portion is formed between the first and second features so that the first and second features are not in direct contact. Also, the present disclosure can repeat the reference numerals and / or letters of the attached drawings in each embodiment. This kind of repetition is for simplification and clarification and does not itself indicate the relationship between each embodiment and / or arrangement being considered.

[0012] In the following, embodiments of the present disclosure will be examined in detail. However, what should be understood here is that the present disclosure provides numerous applicable concepts that can be embodied in various specific environments. The specific embodiments to be examined are merely exemplary and do not limit the scope of the present disclosure.

[0013] The present disclosure provides a semiconductor structure and a method for manufacturing the same. In the semiconductor structure of the present disclosure, the extending direction of the channel is perpendicular to the extending direction of the trench structure, and since the pitch of the channels can be adjusted according to the process capabilities, by increasing the channel density, the current density can be improved, the uniformity of the electric field can be improved, and the reverse leakage current can be reduced.

[0014] Figure 1 shows a top view of a semiconductor structure 10 based on a certain embodiment of the present application. Figure 2 shows a cross-sectional view of the semiconductor structure 10 based on a certain embodiment of the present application along tangent A-A'. Figure 3 shows a cross-sectional view of the semiconductor structure 10 based on a certain embodiment of the present application along tangent B-B'. Figure 4 shows a cross-sectional view of the semiconductor structure 10 based on a certain embodiment of the present application along tangent C-C'. Specifically, the semiconductor structure 10 is a trench-type MOS rectifier element structure having a vertical current conduction path. For example, current in the semiconductor structure 10 can be conducted vertically and pass through the semiconductor structure 10.

[0015] In a series of embodiments, the semiconductor structure 10 includes a substrate 11, a first trench structure 21, and a second trench structure 22.

[0016] In a series of embodiments, the substrate 11 includes a base material 111 and an epitaxial layer 112 located on the base material 111. In a series of embodiments, the base material 111 includes, for example, silicon, silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), gallium arsenide (GaAsP), or other semiconductor materials. In a series of embodiments, the epitaxial layer 112 includes, for example, silicon, silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), gallium arsenide (GaAsP), or other semiconductor materials. The base material 111 is an N-type or P-type semiconductor material. The epitaxial layer 112 is an N-type or P-type semiconductor material. In this series of embodiments, the substrate 111 and the epitaxial layer 112 have the same conductivity type; for example, both the substrate 111 and the epitaxial layer 112 are N-type.

[0017] The substrate 111 has the same conductivity type doping as the epitaxial layer 112. In the series of embodiments, the substrate 111 is part of a silicon substrate or silicon wafer. In the series of embodiments, the doping concentration of the substrate 111 is greater than the doping concentration of the epitaxial layer 112.

[0018] In a series of embodiments, the substrate 11 is defined to have a cell area A1 and a termination area A3 adjacent to the cell area, as viewed from a top view. The cell area A1 is used to house active or passive elements, and the termination area A3 is used to connect to the circuit termination. In a series of embodiments, the termination area A3 is adjacent to one side of the cell area A1. In a series of embodiments, the termination area A3 surrounds the cell area A1. In a series of embodiments, the substrate 11 has a first thickness T1 in the cell area A1 and a second thickness T3 in the termination area A3, where the second thickness T3 is greater than the first thickness.

[0019] In a series of embodiments, the substrate 11 may have a first surface 12A, a second surface 12B facing the first surface 12A and located within the terminal area A3, and a third surface 12C facing the first surface 12A and located within the cell area A1, wherein the second surface 12B and the third surface 12C are adjacent to each other and located at different levels. In a series of embodiments, the second surface 12B and the first surface 12A may be located on opposing sides of the substrate 11. In a series of embodiments, the first surface 12A, the second surface 12B, and the third surface 12C may be horizontal planes. For the sake of simplicity, the direction perpendicular to the first surface 12A, the second surface 12B, and the third surface 12C is defined as the vertical direction Z, and the plane formed by the first direction X and the second direction Y is perpendicular to the vertical direction Z. In a series of embodiments, the third surface 12C may be the active surface of the epitaxial layer 112. The bottom surface of the substrate 111 is a first surface 12A that is used in contact with a metal layer (not shown in the attached drawings, but formed on the first surface 12A so as to be in contact with the substrate 111, and can be a drain or cathode).

[0020] In a series of embodiments, the first trench structure 21 is located within the cell area A1 and extends across the third surface 12C toward the first surface 12A. The first trench structure 21 includes a first semiconductor material layer 212 that protrudes at least partially from the third surface 12C and a first oxide layer 211 surrounding the first semiconductor material layer 212. In a series of embodiments, the top surface of the first trench structure 21 and the second surface 12B are coplanar. Viewed from an overhead angle, the first trench structure 21 extends along the third surface 12C in a first direction X.

[0021] The first oxide layer 211 is used to electrically isolate the first semiconductor material layer 212 from the epitaxial layer 112. In other words, the first semiconductor material layer 212 is isolated from the epitaxial layer 112 via the first oxide layer 211 in the trench. In a series of embodiments, the sidewalls and bottomwalls of the first semiconductor material layer 212 are in contact with the first oxide layer 211. The thickness of the first oxide layer 211 can be adjusted, for example, by the dimensions of the first semiconductor material layer 212 or the operating voltage. For example, the thickness of the first oxide layer 211 is smaller than the width of the first semiconductor material layer 212 in the trench. In a series of embodiments, the first semiconductor material layer 212 comprises a polycrystalline silicon material.

[0022] In a series of embodiments, the second trench structure 22 is located within the cell area A1 and extends across the third surface 12C toward the first surface 12A. The second trench structure 22 includes a second semiconductor material layer 222 that protrudes at least partially from the third surface 12C and a second oxide layer 221 surrounding the second semiconductor material layer 222. In a series of embodiments, the top surface of the second trench structure 22 and the second surface 12B are coplanar. Viewed from an overhead angle, the second trench structure 22 extends along the third surface 12C in the first direction X. In a series of embodiments, the second trench structure 22 is located between the first trench structure 21 and the terminal area A3.

[0023] The second oxide layer 221 is used to electrically isolate the second semiconductor material layer 222 from the epitaxial layer 112. In other words, the second semiconductor material layer 222 is isolated from the epitaxial layer 112 via the second oxide layer 221 in the trench. In a series of embodiments, the second oxide layer 221 surrounds the second semiconductor material layer 222. In a series of embodiments, the side walls and bottom walls of the second semiconductor material layer 222 are in contact with the second oxide layer 221. The thickness of the second oxide layer 221 can be adjusted, for example, by the dimensions of the second semiconductor material layer 222 or the operating voltage. For example, the thickness of the second oxide layer 221 is smaller than the width of the second semiconductor material layer 222 in the trench. In a series of embodiments, the first oxide layer 211 and the second oxide layer 221 contain the same material. In a series of embodiments, the first semiconductor material layer 212 and the second semiconductor material layer 222 contain the same material. In the series of embodiments, the second semiconductor material layer 222 includes a polycrystalline silicon material. In the series of embodiments, the depth of the first trench structure 21 is basically the same as the depth of the second trench structure 22. In the series of embodiments, the width W1 of the first trench structure 21 is basically the same as the width W2 of the second trench structure 22.

[0024] In a series of embodiments, the semiconductor structure 10 further includes a third trench structure 23. The third trench structure 23 is located within the terminal area A3 and extends from the second surface 12B toward the first surface 12A. The third trench structure 23 is located on the outer edge of the semiconductor structure 10. The third trench structure 23 includes a third semiconductor material layer 232 and a third oxide layer 231 surrounding the third semiconductor material layer 232, and the third trench structure 23 extends toward the first direction X. In a series of embodiments, the top surface of the third trench structure 23 and the second surface 12B are coplanar. In a series of embodiments, the top surfaces of the first trench structure 21, the second trench structure 22, and the third trench structure 23 are coplanar. Viewed from an overhead angle, the third trench structure 23 extends toward the first direction X along the third surface 12C. In this series of embodiments, the second trench structure 22 is located between the first trench structure 21 and the third trench structure 23.

[0025] The third oxide layer 231 is used to electrically isolate the third semiconductor material layer 232 from the epitaxial layer 112. In other words, the third semiconductor material layer 232 is isolated from the epitaxial layer 112 via the third oxide layer 231 in the trench. In a series of embodiments, the third oxide layer 231 surrounds the third semiconductor material layer 232. In a series of embodiments, the side walls and bottom walls of the third semiconductor material layer 232 are in contact with the third oxide layer 231. The thickness of the third oxide layer 231 can be adjusted, for example, by the dimensions of the third semiconductor material layer 232 or the operating voltage. For example, the thickness of the third oxide layer 231 is smaller than the width of the third semiconductor material layer 232 in the trench. In a series of embodiments, the first oxide layer 211 and the third oxide layer 231 contain the same material. In a series of embodiments, the first semiconductor material layer 212 and the third semiconductor material layer 232 contain the same material. In the series of embodiments, the third semiconductor material layer 232 includes a polycrystalline silicon material. In the series of embodiments, the depth of the first trench structure 21 is basically the same as the depth of the third trench structure 23. In the series of embodiments, the width W1 of the first trench structure 21 is basically the same as the width W3 of the third trench structure 23.

[0026] In a series of embodiments, the semiconductor structure 10 further includes a plurality of trench structures located between the second trench structure 22 and the third trench structure 23, for example, a fourth trench structure 24, a fifth trench structure 25, and a sixth trench structure 26. In a series of embodiments, the distance between the third trench structure 23 and the cell area A1 is the greatest compared to the distance between the fourth trench structure 24, the fifth trench structure 25, and the sixth trench structure 26 and the cell area A1. In a series of embodiments, the third trench structure 23 is located on the outer edge of the semiconductor structure 10, and the fourth trench structure 24, the fifth trench structure 25, and the sixth trench structure 26 are located between the second trench structure 22 and the third trench structure 23. In a series of embodiments, the fourth trench structure 24, the fifth trench structure 25, and the sixth trench structure 26 are located in the terminal area A3, extend from the second surface 12B toward the first surface 12A, and extend parallel to the first direction X. In a series of embodiments, the structures of the fourth trench structure 24, the fifth trench structure 25, and the sixth trench structure 26 are basically identical to those of the third trench structure 23. In a series of embodiments, the top surfaces of the fourth trench structure 24, the fifth trench structure 25, and the sixth trench structure 26 are coplanar with the second surface 12B. In a series of embodiments, the top surfaces of the third trench structure 23, the fourth trench structure 24, the fifth trench structure 25, and the sixth trench structure 26 are coplanar. From an overhead view, the fourth trench structure 24, the fifth trench structure 25, and the sixth trench structure 26 each extend along the third surface 12C in the first direction X.

[0027] The first doped area 31 is located on the third surface 12C of the substrate 11. Viewed from an overhead angle, the first doped area 31 is located between the first trench structure 21 and the second trench structure 22, and extends along the third surface 12C in a second direction Y perpendicular to the first direction X. In a series of embodiments, the semiconductor structure 10 includes a plurality of doped areas located between the first trench structure 21 and the second trench structure 22. In a series of embodiments, the first doped area 31 is located above the epitaxial layer 112 and adjacent to the third surface 12C. The first doped area 31 has different conductivity types. In a series of embodiments, the first doped area 31 has a second type conductivity type. In a series of embodiments, the first doped area 31 has a P-type conductivity, and the epitaxial layer 112 has an N-type conductivity. In a series of examples, the doping concentration of the first dope area 31 is greater than the doping concentration of the epitaxial layer 112. In a series of examples, the first dope area 31 contains a P-type dopant, which may include, for example, boron, aluminum, gallium, indium, etc. In a series of examples, the P-type dopant contained in the first dope area 31 is boron.

[0028] In a series of embodiments, the second doped area 32 is located on the third surface 12C of the substrate 11. Viewed from an overhead angle, the second doped area 32 is located between the first trench structure 21 and the second trench structure 22 and adjacent to the first doped area 31. In a series of embodiments, the second doped area 32 is located at a distance from the first doped area 31. The distance D between the second doped area 32 and the first doped area 31 is adjustable according to the requirements and process capabilities, and the distance D1 is greater than 0. In a series of embodiments, the second doped area 32 extends in the same direction as the first doped area 31, for example, the second doped area 32 extends in the second direction Y. In a series of embodiments, the second doped area 32 is located above the epitaxial layer 112 and adjacent to the third surface 12C. The second doped area 32 has a different conductivity type than the epitaxial layer 112; for example, the second doped area 32 has a P-type and the epitaxial layer 112 has an N-type. The second doped area 32 has the same conductivity type as the first doped area 31; for example, both are P-type. In a series of embodiments, the doping concentration of the second doped area 32 is greater than the doping concentration of the epitaxial layer 112. In a series of embodiments, the doping concentration of the second doped area 32 is approximately the same as the doping concentration of the first doped area 31. In a series of embodiments, the second doped area 32 contains a P-type dopant, which can be, for example, boron, aluminum, gallium, indium, etc. In a series of embodiments, the P-type dopant contained in the second doped area 32 is boron.

[0029] The shielding layer 35 is located within the cell area A1 and on the second surface 12B. In a series of embodiments, the shielding layer 35 is separated from the termination area A3. In a series of embodiments, the shielding layer 35 covers a portion of the first trench structure 21 and a portion of the second trench structure 22. The upper surface of the shielding layer 35 is higher than the first doped area 31 and the second doped area 32. At least a portion of the first semiconductor material layer 212 and at least a portion of the second semiconductor material layer 222 are exposed from the shielding layer 35. At least a portion of the first oxide layer 211 and at least a portion of the second oxide layer 221 are exposed from the shielding layer 35.

[0030] Viewed from an overhead angle, the shielding layer 35 is located between the first doped area 31 and the second doped area 32. In a series of embodiments, the shielding layer 35 includes a first opening 41 and a second opening 42. The first opening 41 extends along a first direction X so as to expose at least a portion of the first semiconductor material layer 212, and the second opening 42 extends along a second direction Y perpendicular to the first direction X so as to expose at least a portion of the second surface 12B and the first trench structure 21. The first opening 41 and the second opening 42 intersect each other. The first doped area 31 is located within the second opening 42. In a series of embodiments, the shielding layer 35 further includes a third opening 43 that extends along a second direction Y perpendicular to the first direction X, exposing at least a portion of the second surface 12B and the first trench structure 21. The third opening 43 is installed parallel to the second opening 42 and intersects with the first opening 41. The second doped area 32 is located within the third opening 43. Viewed from an overhead angle, the first doped area 31 and the second doped area 32 are installed between the first trench structure 21 and the second trench structure 22, and are installed in a staggered pattern with respect to the shielding layer 35.

[0031] In a series of embodiments, the shielding layer 35 includes a fourth oxide layer 351 and a fourth semiconductor material layer 352 placed on the fourth oxide layer 351. The fourth oxide layer 351 is placed on the second surface 12B and covers at least a portion of the first trench structure 21 and at least a portion of the second trench structure 22. The fourth oxide layer 351 is in contact with the first oxide layer 211 and the second oxide layer 221. In a series of embodiments, the fourth oxide layer 351 is a gate oxide layer. In a series of embodiments, the thickness of the fourth oxide layer 351 is 50 Å to 150 Å. In a series of embodiments, the fourth semiconductor material layer 352 includes a polycrystalline silicon material.

[0032] In a series of embodiments, a third doped area 33 is further provided on the third surface 12C of the substrate 11. Viewed from an overhead angle, the third doped area 33 is located on the periphery of the cell area A1 and extends in the first direction X. In a series of embodiments, the third doped area 33 is located between the second trench structure 22 and the third trench structure 23. In a series of embodiments, the third doped area 33 is located between the second trench structure 22 and the terminal area A3. The second trench structure 22 is located between the first doped area 31 and the third doped area 33. In a series of embodiments, the third doped area 33 is located above the epitaxial layer 112 and adjacent to the third surface 12C. The third doped area 33 has a different conductivity type than the epitaxial layer 112; for example, the third doped area 33 has a P-type and the epitaxial layer 112 has an N-type. The third doped area 33, the second doped area 32, and the first doped area 31 have the same conductivity type; for example, they are all P-type. In the series of embodiments, the doping concentration of the third doped area 33 is greater than the doping concentration of the epitaxial layer 112. In the series of embodiments, the first doped area 31, the second doped area 32, and the third doped area 33 are high-concentration doped areas. In the series of embodiments, the first doped area 31, the second doped area 32, and the third doped area 33 are bulk doped areas. In the series of embodiments, the doping concentrations of the first doped area 31, the second doped area 32, and the third doped area 33 are approximately the same. In a series of embodiments, the third dope area 33 contains a P-type dopant, which can be, for example, boron, aluminum, gallium, indium, etc. In a series of embodiments, the P-type dopant contained in the third dope area 33 is boron. The width W5 of the third dope area 33 may be the same as or different from the width W4 of the first dope area 31. In a series of embodiments, the width W5 of the third dope area 33 is basically the same as the width W4 of the first dope area 31.

[0033] In a series of embodiments, the third doped area 33 is the first mesa surface between the cell area A1 and the terminal area A3. In a series of embodiments, the first mesa surface separates the second trench structure 22 of the cell area A1 from the third trench structure 23 of the terminal area A3. The width D2 of the first mesa surface is adjustable by the positions of the second trench structure 22 and the third trench structure 23. In a series of embodiments, the width D2 of the first mesa surface is adjustable by the positions of the second trench structure 22 and the fourth trench structure 24.

[0034] The semiconductor structure 10 further includes a conductive layer 38 such that the first trench structure 21 and the second trench structure 22 are electrically connected. The conductive layer 38 is positioned above the first doped area 31 and above the second doped area 32 and covers at least a portion of the shielding layer 35. The conductive layer 38 is further positioned in the first opening 41, the second opening 42 and the third opening 43 and is electrically connected to the first semiconductor material layer 212 and the second semiconductor material layer 222. In a series of embodiments, the conductive layer 38 extends along the sidewall of the shielding layer 35 and is in contact with and electrically connected to the first semiconductor material layer 212 and the second semiconductor material layer 222. In a series of embodiments, the conductive layer 38 is in contact with and electrically connected to a portion of the fourth trench structure 24, the fifth trench structure 25 and the sixth trench structure 26. In a series of embodiments, the conductive layer 38 may be, but is not limited to, a conductive material, such as a metal, including, for example, copper (Cu), gold (Au), silver (Ag), aluminum (Al), nickel (Ni), titanium (Ti), tungsten (W), tin (Sn), titanium nitride (TiN), aluminum-silicon alloy (AlSi), aluminum-silicon copper (AlSiCu) alloy, or other metals or alloys. In a series of embodiments, the portion of the conductive layer 38 surrounded by the shielding layer 35 becomes a conductive plug 383. In a series of embodiments, the conductive plug 383 has a columnar structure and has essentially the same width along the vertical direction Z. In a series of embodiments, the conductive plug 383 has a structure that is wider at the top and narrower at the bottom, and the width of the conductive plug 383 tends to decrease along the vertical direction Z as the conductive layer 38 approaches the first surface 12A.

[0035] In a series of embodiments, the conductive layer 38 includes a first conductive layer 381 which is placed on the shielding layer 35, extends along the sidewall of the shielding layer 35, and is in contact with the first semiconductor material layer 212 and the second semiconductor material layer 222. In a series of embodiments, the first conductive layer 381 is a seed layer. The conductive layer 38 includes a second conductive layer 382 which is placed on the first conductive layer 381, extends along the sidewall of the first conductive layer 381, and is in contact with the first semiconductor material layer 212 and the second semiconductor material layer 222.

[0036] In a series of embodiments, the conductive layer 38 is installed in the cell area A1 and the termination area A3. The conductive layer 38 is installed above the third dope area 33. The semiconductor structure 10 further includes a fifth oxide layer 37 installed between the third trench structure 23 and the conductive layer 38. The fifth oxide layer 37 is installed in the termination area A3 and is located on the second surface 12B. In a series of embodiments, the fifth oxide layer 37 is installed above the third trench structure 23, the fourth trench structure 24, the fifth trench structure 25, and the sixth trench structure 26. In a series of embodiments, the conductive layer 38 is installed above the first dope area 31, above the second dope area 32, and above the fifth oxide layer 37. In a series of embodiments, at least a portion of the fourth trench structure 24, the fifth trench structure 25, and the sixth trench structure 26 are exposed from the fifth oxide layer 37 and are electrically connected to the conductive layer 38 by contact. In a series of embodiments, the conductive layer 38 is electrically connected to the fourth trench structure 24, the fifth trench structure 25, and the sixth trench structure 26 across the fifth oxide layer 37. In a series of embodiments, the edge 371 of the fifth oxide layer 37 is exposed from the conductive layer 38.

[0037] In a series of embodiments, the third trench structure 23 is covered by a fifth oxide layer 37. In a series of embodiments, the fifth oxide layer 37 is located between the third trench structure 23 and the conductive layer 38, and electrically isolates the third trench structure 23 from the conductive layer 38. The third trench structure 23 is located on the periphery of the semiconductor structure 10 and is either floated or dummy so as to prevent the expansion of the depletion region when the semiconductor structure 10 is reverse biased.

[0038] In the case of a forward voltage, as indicated by the arrows in Figures 1 and 4, the current flows from the conductive layer 38 installed in the second opening 42 to the first doped area 31, from the first doped area 31 to the epitaxial layer 112, and from the third surface 12C towards the first surface 12A. In the case of a forward voltage, the current further flows from the conductive layer 38 installed in the third opening 43 to the second doped area 32, from the second doped area 32 to the epitaxial layer 112, and from the third surface 12C towards the first surface 12A. In a series of embodiments, the active surface of the semiconductor structure 10 is the third surface 12C. The current in the semiconductor structure 10 can flow in a direction perpendicular to the active surface of the semiconductor structure 10. In a series of embodiments, the current in the semiconductor structure 10 flows along the vertical direction Z.

[0039] In a series of embodiments, the first doped area 31 and the second doped area 32 each form a second mesa surface between the first trench structure 21 and the second trench structure 22. In a series of embodiments, the width of the second mesa surface is adjustable by the position of the first trench structure 21 and the second trench structure 22. The first trench structure 21 and the second trench structure 22 can reduce the electric field at the second mesa surface location, thereby reducing the reverse leakage current of the semiconductor structure 10. Furthermore, since the channel extension direction is perpendicular to the extension direction of the first trench structure 21 and the second trench structure 22, the channel position can be adjusted by process (for example, by further narrowing the channel) to further lower the forward voltage and increase the channel density, thereby increasing the current density.

[0040] Figures 5 to 25 show one or more steps in a method for manufacturing a semiconductor structure based on certain embodiments of the present application. At least some of these accompanying drawings have already been simplified to better illustrate aspects of the present disclosure.

[0041] Referring to Figures 5 and 6, the substrate 11 may include a base material 111 and an epitaxial layer 112 located on the base material 111. The manufacturing method includes epitaxial growth of the base material 111 to form the epitaxial layer 112. The base material 111 has a first surface 12A of the substrate 11, and the epitaxial layer 112 has a second surface 12B of the substrate 11, with the first surface 12A facing the second surface 12B. In a series of embodiments, ions are implanted simultaneously with epitaxial growth, and ions having N-type electrical properties are implanted to form an N-type epitaxial layer 112.

[0042] A patterned shielding layer 113 (hereinafter collectively referred to as the first shielding layer) shown in Figure 5 is formed on the epitaxial layer 112 to define the positions of the first trench 210, second trench 220, and third trench 230 shown in Figure 6. An etching process (e.g., a plasma dry etching process) is then performed on the epitaxial layer 112 via the first shielding layer 113 to form the first trench 210, second trench 220, and third trench 230. The etching process needle removes the epitaxial layer 112 from the second surface 12B and stops within the epitaxial layer 112. Depending on the positions defined by the first shielding layer 113, the first trench 210, second trench 220, and third trench 230 are formed spaced apart in the substrate 11 and extend along the first direction X and from the second surface 12B toward the first surface 12A facing the second surface. The first trench 210 and the second trench 220 are formed in the cell area A1 of the substrate 11, and the third trench 230 is formed in the end area A3 of the substrate 11.

[0043] In a series of embodiments, the first trench 210, the second trench 220, and the third trench 230 may have vertical side walls. The first trench 210, the second trench 220, and the third trench 230 may have arc-shaped bottom surfaces. Also, the first trench 210, the second trench 220, and the third trench 230 may be circular, elliptical, rectangular, or polygonal. In a series of embodiments, the first trench 210, the second trench 220, and the third trench 230 may have the same width. In a series of embodiments, the first trench 210, the second trench 220, and the third trench 230 may have the same depth. In a series of embodiments, the fourth trench 240, the fifth trench 250, and the sixth trench 260 may be formed spaced apart in the substrate 11 and extend along the first direction X and from the second surface 12B toward the first surface 12A facing the second surface. The fourth trench 240, the fifth trench 250, and the sixth trench 260 are located between the second trench 220 and the third trench 230.

[0044] Referring to Figure 7, the manufacturing method includes forming an in-trench oxide layer 219 in the first trench 210, the second trench 220, and the third trench 230. In a series of embodiments, the in-trench oxide layer 129 covers the second surface 12B. In a series of embodiments, the in-trench oxide layer 219 can be formed by thermal oxidation techniques or other deposition processes. In a series of embodiments, the in-trench oxide layer 219 can be deposited on the inner surfaces of the first trench 210, the second trench 220, and the third trench 230 (including opposing side walls and bottoms extending between side walls) in a shape-retaining or conformal manner. In a series of embodiments, the in-trench oxide layer 219 can be filled into the first trench 210, the second trench 220, and the third trench 230 by a deposition process such that the in-trench oxide layer 219 forms at least one groove in each of the first trench 210, the second trench 220, and the third trench 230. In a series of embodiments, the trench oxide layer 129 is such that the portion in the first trench 210 is the first oxide layer 211, the portion in the second trench 220 is the second oxide layer 221, and the portion in the third trench 230 is the third oxide layer 231. The first oxide layer 211, the second oxide layer 221, and the third oxide layer 231 are formed simultaneously.

[0045] Referring to Figure 8, the manufacturing method includes forming a first semiconductor material 215, a second semiconductor material 225, and a third semiconductor material 235 in a first trench 210, a second trench 220, and a third trench 230, respectively. In a series of embodiments, the first semiconductor material 215 is placed in the first trench 210 and on the top surface of the first oxide layer 211, the second semiconductor material 225 is placed in the second trench 220 and on the top surface of the second oxide layer 221, and the third semiconductor material 235 is placed in the third trench 230 and on the top surface of the third oxide layer 231.

[0046] The trench oxide layer 219 can surround the first semiconductor material 215, the second semiconductor material 225, and the third semiconductor material 235. In a series of embodiments, the first semiconductor material 215, the second semiconductor material 225, and the third semiconductor material 235 can be formed by physical vapor deposition (PVD), for example, sputtering or spray coating. In a series of embodiments, the first semiconductor material 215, the second semiconductor material 225, and the third semiconductor material 235 can be formed by electroplating or CVD. In a series of embodiments, the semiconductor material can be coated with the trench oxide layer 219, and then a dry etching process can be performed to remove the semiconductor material other than the first trench 210, the second trench 220, and the third trench 230 by a method such as etching, to form the first semiconductor material 215, the second semiconductor material 225, and the third semiconductor material 235. In a series of embodiments, the semiconductor material includes polycrystalline silicon.

[0047] Referring to Figure 9, the manufacturing method includes forming the first semiconductor material layer 212, the second semiconductor material layer 222, and the third semiconductor material layer 232 in the first trench 210, the second trench 220, and the third trench 230, respectively, such that the first semiconductor material layer 212 is surrounded by the first oxide layer 211 and forms the first trench structure 21, the second semiconductor material layer 222 is surrounded by the second oxide layer 221 and forms the second trench structure 22, and the third semiconductor material layer 232 is surrounded by the third oxide layer 231 and forms the third trench structure 23. In a series of embodiments, the top surfaces of the first semiconductor material layer 212, the second semiconductor material layer 222, and the third semiconductor material layer 232 are basically coplanar with the second surface 12B.

[0048] In a series of embodiments, the first semiconductor material 215, the second semiconductor material 225, and the third semiconductor material 235 are etched to form the first semiconductor material layer 212, the second semiconductor material layer 222, and the third semiconductor material layer 232, respectively. The etching process removes at least a portion of the first semiconductor material 215 in the first trench 210, at least a portion of the second semiconductor material 225 in the second trench 220, and at least a portion of the third semiconductor material 235 in the third trench 230. The first semiconductor material layer 212, the second semiconductor material layer 222, and the third semiconductor material layer 232 are formed by a dry etching process, with their positions defined by a second shielding layer (not shown). The dry etching process removes a portion of the first semiconductor material 215, the second semiconductor material 225, and the third semiconductor material 235 and stops at a predetermined depth of the first semiconductor material 215, the second semiconductor material 225, and the third semiconductor material 235.

[0049] For simplicity, the first semiconductor material layer 212 and the first oxide layer 211 are collectively referred to as the first trench structure 21, the second semiconductor material layer 222 and the second oxide layer 221 are collectively referred to as the second trench structure 22, and similarly, the third semiconductor material layer 232 and the third oxide layer 231 are collectively referred to as the third trench structure 23. The first trench structure 21, the second trench structure 22, and the third trench structure 23 are formed simultaneously. In a series of embodiments, the fourth trench structure 24, the fifth trench structure 25, and the sixth trench structure 26 are formed simultaneously with the first trench structure 21, the second trench structure 22, and the third trench structure 23.

[0050] In a series of embodiments, the oxide layer 370 is formed on the third trench structure 23 such that the oxide layer 370 covers the third trench structure 23. Referring to Figure 10, the manufacturing method includes forming the oxide layer 370 on the first trench structure 21, the second trench structure 22, and the third trench structure 23. In a series of embodiments, the oxide layer 370 is formed on the trench-internal oxide layer 219 and covers the first trench structure 21, the second trench structure 22, and the third trench structure 23. The oxide layer 370 is in contact with the first semiconductor material layer 212, the second semiconductor material layer 222, and the third semiconductor material layer 232. In a series of embodiments, the oxide layer 370 is further in contact with the semiconductor material layers of the fourth trench structure 24, the fifth trench structure 25, and the sixth trench structure 26.

[0051] The oxide layer 370 and the trench oxide layer 219 may be made of the same or different materials. In a series of embodiments, the oxide layer 370 may be formed by ALD, CVD or other deposition processes. In a series of embodiments, after forming the oxide layer 370, a polishing process, such as a CMP process, is performed to polish the top surface of the oxide layer 370 to a flat surface.

[0052] Referring to Figure 11, the manufacturing method includes removing a portion of the oxide layer 370 and a portion of the trench oxide layer 219 to expose the substrate 11 and the first trench structure 21 and second trench structure 22 located in the cell area A1. In a series of embodiments, the oxide layer 370 and the trench oxide layer 219 are locally removed by photolithography and etching processes. In a series of embodiments, at least a portion of the semiconductor material 112 of the fourth trench structure 24, the fifth trench structure 25, and the sixth trench structure 26 are exposed from the oxide layer 370. In a series of embodiments, after removing a portion of the oxide layer 370 and a portion of the trench oxide layer 219, the oxide layer 370 and the trench oxide layer 219 are located only in the termination area A3, and the oxide layer 370 covers the trench oxide layer 219 and the third trench structure 23, exposing the second surface 12B of the cell area. For simplicity, in the following explanation, the oxide layer 219 and oxide layer 370 located in the trench in terminal area A3 will be collectively referred to as the fifth oxide layer 37.

[0053] The manufacturing method includes forming a shielding layer 35 on the cell area A1, the first trench structure 21, and the second trench structure 22. Referring to Figure 12, the manufacturing method includes forming a fourth oxide layer 351 on the second surface 12B of the cell area and the fifth oxide layer 37, and forming a fourth semiconductor material layer 352 on the fourth oxide layer 351. The fourth oxide layer 351 and the fifth oxide layer 37 may be made of the same or different materials. In a series of embodiments, the thickness of the fourth oxide layer 351 is less than that of the fifth oxide layer 37. In a series of embodiments, the fourth oxide layer 351 is in contact with the sidewall of the fifth oxide layer 37, and the fourth semiconductor material layer 352 is in contact with the sidewall and top surface of the fifth oxide layer 37. In a series of embodiments, the fourth oxide layer 351 may be formed by thermal oxidation techniques or other deposition processes. In a series of embodiments, the fourth semiconductor material layer 352 can be formed by PVD, for example, sputtering or spray coating. In a series of embodiments, the fourth semiconductor material layer 352 can be formed by electroplating or CVD.

[0054] The manufacturing method includes performing an etching process on the shielding layer 35 to form a first opening 41, a second opening 42, and a third opening 43. Figure 13 is a top view of one step in a method for manufacturing a semiconductor structure 10 according to certain embodiments of the present application. Figure 14 shows a cross-sectional view along tangent A-A' of the step shown in Figure 13 in a method for manufacturing a semiconductor structure according to certain embodiments of the present application. Figure 15 shows a cross-sectional view along tangent B-B' of the step shown in Figure 12 in a method for manufacturing a semiconductor structure according to certain embodiments of the present application. Figure 16 shows a cross-sectional view along tangent C-C' of the step shown in Figure 13 in a method for manufacturing a semiconductor structure according to certain embodiments of the present application.

[0055] Referring to Figures 13 to 16, the manufacturing method includes performing a first etching process on the shielding layer 35 to extend the first opening 41 along a first direction X to expose at least a portion of the first semiconductor material layer 212, and forming the openings 421 and 431 to be spaced apart from each other and extending along a second direction Y perpendicular to the first direction to expose at least a portion of the second surface 12B and the first trench structure 21. The first etching process further includes removing a portion of the fourth oxide layer 351 and a portion of the fourth semiconductor material layer 352 so that the shielding layer 35 is located only on the cell area A1, the first trench structure 21 and the second trench structure 22, the second surface 12B between the second trench structure 22 and the termination area A3 is exposed, and the fifth oxide layer 37 is also exposed.

[0056] In a series of embodiments, a patterned shielding layer (hereinafter collectively referred to as the third shielding layer) is formed on the fourth semiconductor material layer 352 (not shown). The first opening 41 and openings 421 and 431 are positioned by the third shielding layer and can be formed by an etching process. The etching process removes the fourth oxide layer 351 and the fourth semiconductor material layer 352 and stops at the second surface 12B or the upper surface of the first trench structure 21 and the second trench structure 22. Depending on the position defined by the third shielding layer, the first opening 41 can cover at least a portion of the first semiconductor material layer 212, and the openings 421 and 431 can cover the first trench structure 21 and the second surface 12B partially adjacent to the first trench structure 21. In a series of embodiments, the first opening 41 extends downward to the top surface of the first semiconductor material layer 212. In a series of embodiments, the openings 421 and 431 extend downward to the top surface and second surface 12B of the first trench structure 21.

[0057] Referring to Figures 17 to 19, the manufacturing method includes, after a first etching process, performing a second etching process at openings 421 and 431 to form a third surface 12C on the substrate 11, and causing the first trench structure 21 and the second trench structure 22 to protrude at least partially from the third surface 12C of the cell area A1, and forming a second opening 42 and a third opening 43. Figure 17 is a top view of one step in a method for manufacturing a semiconductor structure according to certain embodiments of the present application. Figure 18 is a cross-sectional view along tangent A-A' of the step shown in Figure 17 in a method for manufacturing a semiconductor structure according to certain embodiments of the present application. Figure 19 is a cross-sectional view along tangent C-C' of the step shown in Figure 17 in a method for manufacturing a semiconductor structure according to certain embodiments of the present application.

[0058] The manufacturing method includes locally removing the epitaxial layer 112 using the shielding layer 35 as a shield. In a series of embodiments, an etching process is performed on the exposed epitaxial layer 112 using the shielding layer 35 and the fifth oxide layer 37 as shields. In a series of embodiments, a second etching process redefines the openings 421 and 431 as the second opening 42 and the third opening 43. In a series of embodiments, the sidewalls of the second opening 42 and the third opening 43 include the shielding layer 35 and a portion of the epitaxial layer 112. In a series of embodiments, the bottom of the openings 421 and 431 in Figure 12 is higher than or approximately equal to the horizontal height of the bottom of the second opening 42 and the third opening 43 in Figure 16. In a series of embodiments, the depth of the second opening 42 and the third opening 43 is greater than the depth of the openings 421 and 431.

[0059] After the second etching process, the substrate 11 has a first thickness T1 in the cell area A1 and a second thickness T3 in the terminal area A3, where the second thickness T3 is greater than the first thickness. In the series of embodiments, the horizontal height of the fifth oxide layer 37 is greater than the horizontal height of the shielding layer 35, and the horizontal height of the shielding layer 35 is greater than the horizontal height of the third surface 12C.

[0060] Referring to Figures 20-22, the manufacturing method includes forming a first doped area 31 on the third surface 12C exposed at the second opening 42, and forming a second doped area 32 on the third surface 12C exposed at the third opening 43. Viewed from an overhead angle, the first doped area 31 and the second doped area 32 are located between the first trench structure 21 and the second trench structure 22, respectively, and extend toward the second direction Y. The manufacturing method further includes forming a third doped area 33 between the cell area A1 and the termination area A3, with the first doped area 31 and the third doped area 33 being separated. Viewed from an overhead angle, the second trench structure 22 is located between the first doped area 31 and the third doped area 33. Figure 19 is a top view of one step in a method for manufacturing a semiconductor structure according to certain embodiments of the present application. Figure 20 shows a cross-sectional view along tangent A-A' of the step shown in Figure 18 in a method for manufacturing a semiconductor structure according to certain embodiments of the present invention. Figure 21 shows a cross-sectional view along tangent B-B' of the step shown in Figure 19 in a method for manufacturing a semiconductor structure according to certain embodiments of the present invention.

[0061] The first doped area 31, the second doped area 32, and the third doped area 33 can be formed by performing a diffusion or ion implantation process from the third surface 12C. After the first doped area 31, the second doped area 32, and the third doped area 33 are formed, the first trench structure 21 and the second trench structure 22 protrude at least partially from the first doped area 31, the second doped area 32, and the third doped area 33.

[0062] The depths of the first doped area 31, the second doped area 32, and the third doped area 33 are less than the depths of the first trench structure 21 and the second trench structure 22. In other words, the bottoms of the first doped area 31, the second doped area 32, and the third doped area 33 are higher than the bottoms of the first trench structure 21 and the second trench structure 22. In a series of embodiments, the coverage area of ​​the first doped area 31, the second doped area 32, and the third doped area 33 is defined as being within cell area A1 and the epitaxial layer 112 in parts other than the shielding layer 35 and the first trench structure 21 and the second trench structure 22. In a series of embodiments, an annealing process is performed after the ion implantation process to diffuse the doping ions. In a series of embodiments, the doping ions are, for example, boron ions, aluminum ions, gallium ions, indium ions, etc. In this series of embodiments, boron ions are injected into the first doping area 31, the second doping area 32, and the third doping area 33.

[0063] In a series of embodiments, a patterned shielding layer (hereinafter collectively referred to as the third shielding layer) is formed on the shielding layer 35 and the fifth oxide layer 37 to define the positions of the first doped area 31, the second doped area 32, and the third doped area 33, and the conductivity type and depth of the first doped area 31, the second doped area 32, and the third doped area 33 are defined by adjusting the implanted ions, energy, and dose in the diffusion or ion implantation process. Ions are implanted into the third surface 12C along the vertical Z direction. In a series of embodiments, the third shielding layer is formed after performing a photolithography process using a photomask having a corresponding pattern. In a series of embodiments, the first doped area 31, the second doped area 32, and the third doped area 33 are each formed by performing an annealing process after performing an ion implantation process on the third surface 12C each time to diffuse the doping ions.

[0064] Referring to Figures 23 to 25, the manufacturing method includes forming a conductive layer 38 on a first semiconductor material layer 212, a second semiconductor material layer 222, and a third semiconductor material layer 232. The conductive layer 38 can be formed by electroplating or CVD. The material of the conductive layer 38 may include copper (Cu), gold (Au), silver (Ag), aluminum (Al), nickel (Ni), titanium (Ti), tungsten (W), tin (Sn), titanium nitride (TiN), aluminum-silicon (AlSi) alloy, aluminum-silicon copper (AlSiCu) alloy, or other metals or alloys. The first trench structure 21 and the second trench structure 22 are electrically connected to the conductive layer 38. In a series of embodiments, the manufacturing method includes further removing a portion of the conductive layer 38 at the edge of the termination area A3 to expose the edge 371 of the fifth oxide layer 37 from the conductive layer 38.

[0065] The manufacturing method includes forming a first conductive layer 381 on a shielding layer 35, a third surface 12C, and a fifth oxide layer 37. The first conductive layer 381 extends along the sidewall of the shielding layer 35 and is in contact with the first semiconductor material layer 212 and the second semiconductor material layer 222. In a series of examples, the first conductive layer 381 contains titanium (Ti).

[0066] The manufacturing method includes forming a second conductive layer 382 on the first conductive layer 381, extending it along the sidewall of the first conductive layer 381, and bringing it into contact with the first semiconductor material layer 212 and the second semiconductor material layer 222. In a series of examples, the second conductive layer 382 contains titanium nitride (TiN).

[0067] The semiconductor structure 10 formed by the above steps can be basically identical to the semiconductor structure 10 shown in Figures 1 to 4. The semiconductor structure 10 has a first doped area 31 and a second doped area 32 located between the first trench structure 21 and the second trench structure 22, and the first doped area 31 and the second doped area 32 are spaced apart from each other and extend in a second direction Y) parallel to the third surface 12C and perpendicular to the first direction X, thereby achieving the effect of increasing channel density.

[0068] Based on the structure and process of the Disclosure described above, the same or similar semiconductor structures can be achieved under the same purpose and concept by adjusting or changing the order of the steps in the process.

[0069] In this specification, for convenience, spatial relative terms such as “below,” “underside,” “bottom,” “up,” “top,” “left,” and “right” may be used to describe the relationship between one component or feature and one or more other components or features, as shown in the accompanying drawings. Except for the directions depicted in the accompanying drawings, the spatial relative terms are intended to also cover different directions during use or operation of the device. The device may be oriented in other ways (e.g., rotated 90 degrees or positioned in other directions), and the spatial relative terms used herein may be interpreted in a corresponding manner. It should be understood here that when a component is referred to as “connected” or “joined” to another component, it may be directly connected to or joined to the other component, or an intermediate component may exist.

[0070] As used herein, the terms “approximately,” “basically,” “basically,” and “about” are used to describe or interpret small changes. When used in conjunction with an event or situation, the terms can specifically point to instances where the event or situation has occurred precisely and instances where it will occur in the near future. When used in relation to a given value or range, as herein, the term “about” means that the whole is within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. In this specification, a range can be expressed as extending from one endpoint to another or intervening between the endpoints. Unless otherwise specified, all ranges disclosed herein encompass the endpoints. The term “basically coplanar” can indicate that the difference in the positions where two surfaces are located along the same plane is within a few microns (μm), for example, within 10 μm, 5 μm, 1 μm, or 0.5 μm. Where a numerical value or characteristic is referred to as "fundamentally" identical, the term can be used to indicate that the value is within ±10%, ±5%, ±1%, or ±0.5% of the mean of the aforementioned value. The foregoing outlines the features of several embodiments and the details of this disclosure. The embodiments described herein can be readily used as a basis for designing or modifying other processes and structures to accomplish the same or similar purposes and / or to realize the same or similar advantages of the embodiments presented herein. Such equivalent structures do not deviate from the spirit and scope of this disclosure, and any modifications, substitutions, and changes can be made in any way that does not deviate from the spirit and scope of this disclosure. [Explanation of Symbols]

[0071] 10 Semiconductor Structures 11 circuit boards 12A 1st surface 12B 2nd surface 12C 3rd surface 21. First Trench Structure 22. Second Trench Structure 23 Third Trench Structure 24. Fourth Trench Structure 25. Trench Structure No. 5 26. Trench Structure No. 6 31. First Dope Area 32. Second Dope Area 33. Third Dope Area 35 Shielding layer 37. Fifth Oxide Layer 38 Conductive layer 41. First opening 42. Second opening 43 Third opening 111 Base material 112 Semiconductor materials, epitaxial layers 113 Shielding layer, first shielding layer 129 Oxidized layer inside the trench 210 Trench 1 211 First Oxide Layer 212 First Semiconductor Material Layer 215 Semiconductor Materials 219 Oxidized layer inside the trench 220 Second Trench 221 Second Oxide Layer 222 Second Semiconductor Material Layer 225 Semiconductor Materials (Part 2) 230 Trench No. 3 231 Third Oxide Layer 232 Third Semiconductor Material Layer 235 Third Semiconductor Materials 240 Trench No. 4 250 Trench No. 5 260 Trench No. 6 351 Fourth Oxide Layer 352 Fourth Semiconductor Material Layer 370 Oxide layer 371 En 381 First conductive layer 382 Second conductive layer 383 Conductive plug 421 Aperture 431 Aperture A-A' tangent A1 Cell Area A3 Termination Area B-B' tangent C-C' tangent D distance D1 Distance MOS Trench Type PGaAs T1 First thickness T3 Second thickness X 1st direction Y Second direction Z vertical direction

Claims

1. A substrate defined as having a cell area and a terminal area adjacent to the cell area when viewed from above, wherein the substrate has a first surface, a second surface facing the first surface and located within the terminal area, and a third surface facing the first surface and located within the cell area, wherein the second surface and the third surface are adjacent to each other and located at different levels, A first trench structure located within the cell area and extending across the third surface toward the first surface, comprising a first oxide layer surrounding a first semiconductor material layer that at least partially protrudes from the third surface, and extending in a first direction parallel to the third surface, A second trench structure located within the cell area and extending across the third surface toward the first surface, comprising a second oxide layer surrounding a second semiconductor material layer that at least partially protrudes from the third surface, and extending parallel to the first direction, is included. A first doped area is provided on the third surface of the substrate, and, viewed from an overhead perspective, the first doped area is located between the first trench structure and the second trench structure, and the first doped area extends in a second direction parallel to the third surface and perpendicular to the first direction. Furthermore, the shielding layer located within the cell area and on the second surface includes a fourth oxide layer and a fourth semiconductor material layer placed on the fourth oxide layer. A semiconductor structure characterized by the following.

2. The semiconductor structure according to claim 1, wherein a second doping area is further provided on the third surface of the substrate, and when viewed from an overhead perspective, the second doping area is located between the first trench structure and the second trench structure, in close proximity to the first doping area, and the second doping area extends in the second direction.

3. The semiconductor structure according to claim 2, wherein, when viewed from an overhead angle, the shielding layer is located between the first doped area and the second doped area.

4. The semiconductor structure according to claim 3, wherein the fourth oxide layer is installed on the second surface and covers at least a portion of the first trench structure and at least a portion of the second trench structure.

5. Furthermore, The semiconductor structure according to claim 3, comprising a conductive layer installed above the first dope area and above the second dope area, and covering at least a portion of the shielding layer.

6. The semiconductor structure according to claim 5, wherein the conductive layer, the first semiconductor material layer, and the second semiconductor material layer are electrically connected.

7. The semiconductor structure according to claim 5, wherein the conductive layer extends along the side wall of the shielding layer and is in contact with the first semiconductor material layer.

8. Furthermore, The semiconductor structure according to claim 1, comprising a third trench structure located within the terminal area and extending from the second surface toward the first surface, wherein the third trench structure comprises a third semiconductor material layer and a third oxide layer surrounding the third semiconductor material layer, and the third trench structure extends parallel to the first direction.

9. The semiconductor structure according to claim 8, wherein the width of the first trench structure is the same as the width of the third trench structure.

10. The semiconductor structure according to claim 8, wherein the depth of the first trench structure is the same as the depth of the third trench structure.

11. The semiconductor structure according to claim 8, wherein the third trench structure is located at the periphery of the semiconductor structure.

12. Furthermore, A fourth trench structure is located within the terminal area, between the cell area and the third trench structure, extending from the second surface toward the first surface and parallel to the first direction, A fifth oxide layer is installed above the third trench structure and above the fourth trench structure, The present invention includes a conductive layer positioned above the first dope area, above the second dope area, and above the fifth oxide layer, The semiconductor structure according to claim 11, wherein the conductive layer is electrically connected to the fourth trench structure across the fifth oxide layer, and the fifth oxide layer electrically isolates the third semiconductor material layer from the conductive layer.

13. The semiconductor structure according to claim 1, wherein the substrate has a first thickness in the cell area and a second thickness in the termination area, the second thickness being greater than the first thickness.

14. The semiconductor structure according to claim 1, wherein a third doped area is further provided on the third surface of the substrate, and when viewed from an overhead perspective, the third doped area is located on the periphery of the cell area and extends toward the first direction.

15. The semiconductor structure according to claim 1, wherein the first trench structure is electrically connected to the second trench structure.

16. The semiconductor structure according to claim 8, wherein the top surfaces of the first trench structure, the second trench structure, and the third trench structure are coplanar.

17. The semiconductor structure according to claim 1, wherein the top surfaces of the first trench structure and the second trench structure and the second surface are coplanar.

18. The method involves forming a first trench, a second trench, and a third trench in a substrate, spaced apart and extending along a first direction from a second surface toward a first surface opposite the second surface, wherein the substrate is defined to have a cell area and a terminal area when viewed from above, the first trench and the second trench are located in the cell area, and the third trench is located in the terminal area. A first oxide layer is formed in the first trench, a second oxide layer is formed in the second trench, and a third oxide layer is formed in the third trench. The first semiconductor material layer is formed in the first trench such that the first semiconductor material layer is surrounded by the first oxide layer and forms a first trench structure; the second semiconductor material layer is formed in the second trench such that the second semiconductor material layer is surrounded by the second oxide layer and forms a second trench structure; and the third semiconductor material layer is formed in the third trench such that the third semiconductor material layer is surrounded by the third oxide layer and forms a third trench structure. A shielding layer is formed on the cell area, the first trench structure, and the second trench structure. A first etching process is performed on a shielding layer to form a first opening and a second opening, wherein the first opening is extended along a first direction to at least partially expose the first semiconductor material layer, and the second opening is extended along a second direction perpendicular to the first direction to at least partially expose the second surface and the first trench structure. After the first etching process, a second etching process is performed on the second opening to form a third surface on the substrate, and the first trench structure and the second trench structure are made to protrude at least partially from the third surface of the cell area. The first doped area is formed on the third surface exposed near the second opening, wherein, when viewed from an overhead perspective, the first doped area is located between the first trench structure and the second trench structure and extends in the second direction. A method for manufacturing a semiconductor structure, characterized by including [the specified element].

19. Forming the first semiconductor material layer, the second semiconductor material layer, and the third semiconductor material layer further involves, The first semiconductor material is placed in the first trench such that the top surface of the first semiconductor material and the top surface of the first oxide layer are coplanar; the second semiconductor material is placed in the second trench such that the top surface of the second semiconductor material and the top surface of the second oxide layer are coplanar; and the third semiconductor material is placed in the third trench such that the top surface of the third semiconductor material and the top surface of the third oxide layer are coplanar. The third etching process includes performing the process to remove at least partially the first semiconductor material in the first trench, at least partially the second semiconductor material in the second trench, and at least partially the third semiconductor material in the third trench, The manufacturing method according to claim 18, wherein the top surface of the first semiconductor material layer, the top surface of the second semiconductor material layer, and the top surface of the third semiconductor material layer formed after the third etching process are coplanar with the second surface of the substrate.

20. The manufacturing method according to claim 18, wherein, after the second etching process, the substrate has a first thickness in the cell area and a second thickness in the terminal area, the second thickness being greater than the first thickness.

21. Furthermore, This includes forming a second doped area between the cell area and the terminal area, The manufacturing method according to claim 18, wherein the first doping area and the second doping area are separated, and when viewed from an overhead perspective, the second trench structure is located between the first doping area and the second doping area.

22. The manufacturing method according to claim 18, wherein the first oxide layer, the second oxide layer, and the third oxide layer are formed simultaneously.

23. Furthermore, The conductive layer is formed on the first semiconductor material layer, the second semiconductor material layer, and the third semiconductor material layer, The manufacturing method according to claim 21, wherein the first trench structure and the second trench structure are electrically connected to the conductive layer.

24. The manufacturing method according to claim 18, wherein forming the first doped area includes implanting ions into the exposed third surface near the second opening.

Images