Wiring board

Abstract

To improve quality of a wiring board.SOLUTION: A wiring boar 1 of the embodiment has a first interlayer insulating layer 2, a first conductor layer 3 formed on the first interlayer insulating layer 2 and including a conductor pad 3a, a second conductor layer 4 formed on the opposite side of the first conductor layer 3 through the first interlayer insulating layer 2, and a solder resist layer 7 formed on the first interlayer insulating layer 2. The solder resist layer 7 has apertures 7a to expose the surface 3f1 and side surface 3f2 on the opposite side of the first interlayer insulating layer 2 in the conductor pad 3a. The wiring board 1 of the embodiment is further provided with a conductor pattern 5 formed between the first conductor layer 3 and the second conductor layer 4 so as to overlap the outer edge of the conductor pad 3a.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a wiring board.

Background Art

[0002] Patent Document 1 discloses a multilayer wiring board having a pad portion formed on an insulating layer and joined to a semiconductor element. A solder resist is provided on the insulating layer, and the pad portion is arranged so as to be separated from the solder resist in the opening of the solder resist.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a conductor pad formed on an insulating layer and the insulating layer thereunder, such as the pad portion disclosed in Patent Document 1, stress may occur due to a difference in the coefficient of thermal expansion between the conductor pad and the insulating layer, an external force applied from an external component connected to the conductor pad, or the like. Therefore, it is considered that defects such as cracks due to this stress are likely to occur in the conductor pad and the insulating layer in its vicinity.

Means for Solving the Problems

[0005] The wiring board according to the present invention comprises a first interlayer insulating layer, a first conductor layer formed on the first interlayer insulating layer and including a conductor pad, a second conductor layer formed on the opposite side of the first conductor layer via the first interlayer insulating layer, and a solder resist layer formed on the first interlayer insulating layer. The solder resist layer has an opening that exposes the surface and side of the conductor pad opposite to the first interlayer insulating layer, and the wiring board further comprises a conductor pattern formed between the first conductor layer and the second conductor layer so as to overlap with the outer edge of the conductor pad.

[0006] According to embodiments of the present invention, it is possible to provide a high-quality wiring board in which defects such as cracks in the insulating layer around the conductor pads provided on the wiring board are less likely to occur. [Brief explanation of the drawing]

[0007] [Figure 1] A cross-sectional view showing an example of a wiring board according to one embodiment of the present invention. [Figure 2] Enlarged view of part II in Figure 1. [Figure 3] View from direction A in Figure 1. [Figure 4] A cross-sectional view showing an example of the state during the manufacturing process of a wiring board according to one embodiment of the present invention. [Figure 5] A cross-sectional view showing an example of the state during the manufacturing process of a wiring board according to one embodiment of the present invention. [Figure 6] A cross-sectional view showing an example of the state during the manufacturing process of a wiring board according to one embodiment of the present invention. [Figure 7] A cross-sectional view showing an example of the state during the manufacturing process of a wiring board according to one embodiment of the present invention. [Figure 8] A cross-sectional view showing an example of the state during the manufacturing process of a wiring board according to one embodiment of the present invention. [Figure 9] A cross-sectional view showing an example of the state during the manufacturing process of a wiring board according to one embodiment of the present invention. [Figure 10] A cross-sectional view showing an example of the state during the manufacturing process of a wiring board according to one embodiment of the present invention. [Figure 11] A cross-sectional view showing an example of the state during the manufacturing process of a wiring board according to one embodiment of the present invention. [Modes for carrying out the invention]

[0008] A wiring board according to an embodiment of the present invention will be described with reference to the drawings. Figure 1 is a cross-sectional view showing an example of a wiring board according to one embodiment of the present invention. Figure 2 is an enlarged view of part II in Figure 1. Figure 3 is a view taken from direction A in Figure 1. For convenience, the solder resist layer 7 is not shown in Figure 3.

[0009] In this specification, the side of the wiring board 1 that is further away from the core insulating layer 20 in the thickness direction described later will be referred to as the "upper side," "outer side," "upper," or simply "upper," while the side that is closer to the core insulating layer 20 will be referred to as the "lower side," "inner side," "downward," or simply "down." Furthermore, in each conductor layer and each interlayer insulating layer, the surface facing away from the core insulating layer 20 will be referred to as the "upper surface," and the surface facing the core insulating layer 20 will be referred to as the "lower surface." In addition, the thickness direction of the wiring board 1 will be referred to as the "thickness direction Z" or simply the "Z direction."

[0010] As shown in Figure 1, the wiring board 1 has two surfaces extending in a direction perpendicular to the thickness direction Z of the wiring board 1: a first surface 11 and a second surface 12 which is the surface opposite to the first surface 11.

[0011] First, the general configuration of the wiring board 1 will be described. In the example shown in Figure 1, the wiring board 1 includes an insulating layer 20 (hereinafter also referred to as the core insulating layer 20) located in the center of the wiring board 1 in the thickness direction Z, and conductor layers and insulating layers alternately laminated on each of the two sides of the core insulating layer 20 (two opposing main surfaces of the core insulating layer 20 in the thickness direction Z (first main surface 20a and second main surface 20b)). On the first main surface 20a of the core insulating layer 20, three conductor layers 31 and two insulating layers 21 (hereinafter also referred to as interlayer insulating layers 21) are alternately laminated, and an insulating layer 23 (hereinafter also referred to as the interlayer insulating layer 23) is further laminated on top of them, and the conductor layer 33 is formed on the interlayer insulating layer 23. A solder resist layer 70 is formed on the interlayer insulating layer 23. Furthermore, the number of conductor layers and insulating layers laminated on the first main surface 20a of the core insulating layer 20 is not limited to the number of layers described above, but can be any number of layers.

[0012] On the other hand, on the second main surface 20b of the core insulating layer 20, which is the surface opposite to the first main surface 20a, two conductor layers 32 and a second conductor layer 4 are alternately laminated with two insulating layers 22 (hereinafter also referred to as interlayer insulating layers 22). An insulating layer (first interlayer insulating layer) 2 is further laminated on top of these, and a conductor layer (first conductor layer) 3 is formed on the first interlayer insulating layer 2. A solder resist layer 7 is formed on the first interlayer insulating layer 2. Note that the number of conductor layers and insulating layers laminated on the second main surface 20b of the core insulating layer 20 is not limited to the number of layers described above, and any number of layers is possible.

[0013] The core insulating layer 20 has through-hole conductors 20c formed therein that connect the conductor layer 31 and the conductor layer 32. The core insulating layer 20, the conductor layer 31 on the first main surface 20a, and the conductor layer 32 on the second main surface 20b constitute the core substrate of the wiring board 1. The first interlayer insulating layer 2 and the interlayer insulating layers 21 to 23 each have via conductors 6 (hereinafter also referred to as via 6) formed therein that connect the conductor layers sandwiching the first interlayer insulating layer 2 and the interlayer insulating layers 21 to 23, respectively.

[0014] The core insulating layer 20, the first interlayer insulating layer 2, and the interlayer insulating layers 21 to 23 are each formed using an insulating resin such as, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), or a phenolic resin. Note that the core insulating layer 20, the first interlayer insulating layer 2, and the interlayer insulating layers 21 to 23 may contain a reinforcing material (core material) such as glass fiber, aramid fiber, or aramid non-woven fabric and / or an inorganic filler such as silica.

[0015] In this embodiment, the first conductor layer 3, the second conductor layer 4, and the conductor layers 31 to 33, the via 6, the through-hole conductor 20c, and the conductor pattern 5 described later are formed using an arbitrary metal such as copper or nickel, and are constituted by, for example, a metal foil such as a copper foil and / or a metal film formed by plating or sputtering. The first conductor layer 3, the second conductor layer 4, and the conductor layers 31 to 33, the via 6, the through-hole conductor 20c, and the conductor pattern 5 are shown as a single-layer structure in FIG. 1, but may have a multilayer structure having two or more metal layers. For example, the conductor layer 31 and the conductor layer 32 formed on the first main surface 20a and the second main surface 20b sides of the core insulating layer 20, respectively, may have a three-layer structure including a metal foil, an electroless plating film, and an electrolytic plating film. Further, the first conductor layer 3, the second conductor layer 4, the conductor layers 31 to 33, the via 6, the through-hole conductor 20c, and the conductor pattern 5 may have a two-layer structure or a three-layer structure including, for example, an electroless plating film and an electrolytic plating film (see FIG. 2).

[0016] In this embodiment, the first interlayer insulating layer 2, the conductor layer 3, and the solder resist layer 7 are formed on the second surface 12 side of the wiring board 1, and form the surface layer portion on the second surface 12 side of the wiring board 1. The second surface 12 is constituted by the exposed surfaces orthogonal to the Z direction in the first interlayer insulating layer 2, the conductor layer 3, and the solder resist layer 7, respectively.

[0017] Also, in the wiring board 1, the interlayer insulating layer 23, the conductor layer 33, and the solder resist layer 70 are formed on the first surface 11 side of the wiring board 1, and form the surface layer portion on the first surface 11 side of the wiring board 1. The first surface 11 is composed of the exposed surfaces orthogonal to the Z direction in the interlayer insulating layer 23, the conductor layer 33, and the solder resist layer 70, respectively.

[0018] Next, the wiring board 1 according to the present embodiment will be described in more detail. As shown in FIGS. 1 and 2, the wiring board 1 according to the present embodiment includes a first conductor layer 3, a first interlayer insulating layer 2, a second conductor layer 4, and a conductor pattern 5. Also, in the present embodiment, the wiring board 1 further includes a via (via conductor) 6. Also, in the present embodiment, the wiring board 1 includes a solder resist layer 7.

[0019] The first conductor layer 3 is formed on the first interlayer insulating layer 2 and includes conductor pads 3a. In the present embodiment, the first conductor layer 3 includes a plurality of conductor pads 3a. Therefore, in the present embodiment, the wiring board 1 includes a plurality of conductor pads 3a on the second surface 12. The first conductor layer 3 is patterned so as to have conductor pads 3a of a predetermined shape and size. In the wiring board 1 shown in FIGS. 1 and 3, the first conductor layer 3 is patterned so as to have a plurality of conductor pads 3a. In the example shown in FIG. 3, the conductor pad 3a has a substantially circular planar shape. The "planar shape" is the shape of an object such as the conductor pad 3a in a plan view, and the "plan view" means viewing the object with a line of sight parallel to the Z direction. Note that the shape of the conductor pad 3a is not limited to being substantially circular, and may be formed, for example, in a substantially rectangular shape.

[0020] In the wiring board 1 shown in Figure 1, the second surface 12 may be a component mounting surface on which electronic components such as semiconductor integrated circuit devices are mounted, similar to the first surface 11 described later. The second surface 12 may also be a connection surface connected to an external element S1, such as a motherboard of any electrical device, when the wiring board 1 itself is mounted on an external element S1. That is, the wiring board 1 may constitute part of the package of a component E1, such as a semiconductor integrated circuit, mounted on the first surface 11. In that case, the wiring board 1 may be mounted on the external element S1 together with the component E1, with the second surface 12 facing the external element S1, as shown in Figure 1.

[0021] If the second surface 12 is the connection surface with the external element S1, the second surface 12 may have a connection portion with the external element S1. In the example wiring board 1 shown in Figure 1, the conductor pad 3a is connected to the external element S1. Therefore, the conductor pad 3a in the example shown in Figure 1 is a connection pad that is connected to the external element S1 on the wiring board 1.

[0022] In the example shown in Figure 1, the conductor pad 3a is not directly connected to any other conductor pads and / or wiring patterns included in the first conductor layer 3. That is, the conductor pad 3a in the example shown in Figure 1 is a so-called independent pad. Also, in the example shown in Figure 1, the conductor pad 3a is connected to a via conductor 6 that connects the conductor layers (first conductor layer 3 and second conductor layer 4) that sandwich the first interlayer insulating layer 2. Therefore, the conductor pad 3a in the example shown in Figure 1 is also a so-called via pad.

[0023] The conductor pad 3a can be electrically and mechanically connected to the electrode S11 of the external element S1 by a bonding material such as solder. The external element S1 may be a motherboard constituting any electrical device, as described above, or any electronic component having a package size larger than the wiring board 1. The conductor pad 3a can be connected to any board, electrical component, or mechanical component, etc., but is not limited to these.

[0024] In the example shown in Figure 2, the conductor pad 3a is composed of a conductive film that constitutes the first conductor layer 3. Specifically, the conductor pad 3a comprises an electroless plating film 111 formed in a predetermined pattern on the first interlayer insulating layer 2, and an electrolytic plating film 112 formed on the electroless plating film 111. In the example shown in Figure 2, the conductor pad 3a further comprises a metal film 113 formed to cover the exposed portions of the electroless plating film 111 and the electrolytic plating film 112, but the metal film 113 is not required.

[0025] In this embodiment, on the first surface 11 side (see Figure 1) of the wiring board 1, the conductor layer 33 is formed on the interlayer insulating layer 23 and includes a plurality of component mounting pads 33a. Each conductor layer 31, 32, and 33 is patterned to have conductor pads and / or wiring patterns of a predetermined shape and size. Each component mounting pad 33a is a conductor pad on which a component E1 to be mounted on the wiring board 1 is placed when the wiring board 1 is used. That is, the first surface 11 is the component mounting surface of the wiring board 1. The electrodes E2 of the component E1 are electrically and mechanically connected to the component mounting pads 33a via a bonding material (not shown), such as solder.

[0026] Examples of component E1 include, but are not limited to, electronic components such as active components like semiconductor integrated circuit devices and transistors, and passive components like electrical resistors. Component E1 may also be, for example, a wiring material including fine wiring formed on a semiconductor substrate.

[0027] The first interlayer insulating layer 2 is a layer on which the first conductor layer 3 is formed on its outside (upper side). In this embodiment, the outermost (uppermost) interlayer insulating layer (first interlayer insulating layer 2) among the one or more interlayer insulating layers located on the second surface 12 side of the wiring board 1 has a two-layer structure. The first interlayer insulating layer 2 includes a second insulating layer 202 laminated on the interlayer insulating layer 22 below the first interlayer insulating layer 2, and a first insulating layer 201 on top of the second insulating layer 202. That is, the second insulating layer 202 is located on the second conductor layer 4 side in the thickness direction Z of the wiring board 1. The first insulating layer 201 is located on the first conductor layer 3 side in the thickness direction Z of the wiring board 1. The conductor pattern 5 is formed on the second insulating layer 202 and covered by the first insulating layer 201. That is, the first insulating layer 201 is provided so as to cover the conductor pattern 5 formed on the second insulating layer 202. The first insulating layer 201 and the second insulating layer 202 may be made of the same resin material or may be made of different resin materials.

[0028] Furthermore, in this embodiment, the outermost (uppermost) interlayer insulating layer 23 located on the first surface 11 side of the wiring board 1 has a two-layer structure. The two-layer structure includes a second insulating layer 232 laminated on an interlayer insulating layer 21 below the interlayer insulating layer 23, and a first insulating layer 231 on top of the second insulating layer 232. In the example shown in Figure 1, no conductor pattern is formed on the interlayer insulating layer 23. However, a conductor pattern may be formed on the interlayer insulating layer 23. For example, a conductor pattern may be formed on the second insulating layer 232.

[0029] The second conductor layer 4 is formed on the opposite side from the first conductor layer 3 via the first interlayer insulating layer 2. In the example shown in Figures 1 and 2, the second conductor layer 4 is formed on the interlayer insulating layer 22 below the first interlayer insulating layer 2. The second conductor layer 4 is formed on the interlayer insulating layer 22 as a continuous pattern with vias 6 formed in the interlayer insulating layer 22 below the first interlayer insulating layer 2. The second conductor layer 4 is electrically connected to the first conductor layer 3 via vias 6 formed in the first interlayer insulating layer 2.

[0030] The via 6, which is integrally formed with the first conductor layer 3, connects the first conductor layer 3 and the second conductor layer 4. In this embodiment, the via 6 is formed in a through-hole that penetrates the first interlayer insulating layer 2. In this embodiment, the via 6 is formed in a frustum shape such that its diameter gradually decreases from the outside to the inside in the thickness direction Z of the wiring board 1. However, the shape of the via 6 is not limited to this, and for example, it may be formed in a columnar shape with a substantially constant width in the thickness direction Z of the wiring board 1. The same applies to via 6 formed in other interlayer insulating layers.

[0031] In this embodiment, via 6 is formed inside the ring in the conductor pattern 5. That is, in this embodiment, in the thickness direction Z of the wiring board 1, the diameter (outer diameter) of via 6 is smaller than the inner diameter of the substantially annular conductor pattern 5.

[0032] The conductor pattern 5 is formed between the first conductor layer 3 and the second conductor layer 4 so as to overlap with the outer edge of the conductor pad 3a. The conductor pattern 5 functions to prevent cracks from expanding within the first interlayer insulating layer 2 if they occur in the first interlayer insulating layer 2 around the conductor pad 3a due to stress in the first interlayer insulating layer 2. The stress generated in the first interlayer insulating layer 2 is caused by, for example, the difference in thermal expansion coefficients between the first interlayer insulating layer 2 and the conductor pad 3a formed on the first interlayer insulating layer 2, or by external forces applied from external components connected to the conductor pad 3a (for example, external elements S1 such as the motherboard of an electrical device).

[0033] In other words, the conductor pattern 5 functions as a stopper to prevent crack expansion in the event that a crack occurs in the first interlayer insulating layer 2 located around the conductor pad 3a. For example, even if a crack occurs in the first interlayer insulating layer 2 due to the aforementioned stress, extending inward in the thickness direction Z of the wiring board 1 (towards the core insulating layer 20), the wiring board 1 can prevent the crack from expanding by providing the conductor pattern 5.

[0034] In other words, the stress described above is likely to be concentrated in the boundary portion of the first interlayer insulating layer 2 between the region in contact with the conductor pad 3a and the region not in contact with the conductor pad 3a, that is, at the location in the first interlayer insulating layer 2 that is in contact with the outer edge of the conductor pad 3a. The first interlayer insulating layer 2 may not be able to withstand the concentrated stress, and cracks may occur from the portion in contact with the outer edge of the conductor pad 3a. However, in this embodiment, the conductor pattern 5 is formed between the first conductor layer 3 and the second conductor layer 4 so as to overlap with the outer edge of the conductor pad 3a, so that if a crack occurs in the first interlayer insulating layer 2, it is possible to prevent the crack from expanding.

[0035] The configuration of the conductor pattern 5 will now be explained in more detail. The conductor pattern 5 is formed between the first conductor layer 3 and the second conductor layer 4 in the thickness direction Z of the wiring board 1, so as to overlap with the outer edge of the conductor pad 3a in the thickness direction Z of the wiring board 1. In the examples shown in Figures 1 to 3, the conductor pattern 5 is formed with a predetermined gap between it and the first conductor layer 3 in the thickness direction Z of the wiring board 1. That is, the conductor pattern 5 is formed with a predetermined gap between it and the conductor pad 3a in the thickness direction Z of the wiring board 1. The predetermined gap is, for example, the distance required for insulation between the conductor pattern 5 and the first conductor layer 3.

[0036] In the examples shown in Figures 1 to 3, the conductor pattern 5 is formed in a substantially annular shape. However, the shape and size of the conductor pattern 5 are not particularly limited, as long as it is formed between the first conductor layer 3 and the second conductor layer 4 so as to overlap with the outer edge of the conductor pad 3a. It is sufficient that, when viewed from a direction along the thickness direction Z of the wiring board 1 (for example, direction A), the outer edge of the conductor pad 3a is located between the inner and outer circumferences of the conductor pattern 5. For example, the conductor pattern 5 may be shaped such that, when viewed from a direction along the thickness direction Z of the wiring board 1, the center of the ring in the width direction of the ring (the center between the inner and outer edges of the ring) follows the outer edge of the conductor pad 3a. For example, if the conductor pad 3a is substantially circular, the conductor pattern 5 may be substantially annular (see Figure 3), or it may be an annular shape with a polygonal outer and / or inner circumference. Furthermore, the conductor pattern 5 may be formed to be continuous along the entire circumferential direction of the ring, or it may be formed discontinuously (intermittently) in a part of the circumferential direction of the ring.

[0037] Furthermore, in the examples shown in Figures 1 to 3, the conductor pattern 5 is formed at a predetermined distance from the second conductor layer 4 in the thickness direction Z of the wiring board 1. The predetermined distance is, for example, the distance required for insulation between the conductor pattern 5 and the second conductor layer 4. That is, in this embodiment, the conductor pattern 5 is formed so as not to be electrically connected to other conductors (first conductor layer 3, second conductor layer 4, and via 6). However, the conductor pattern 5 may be formed so as to be electrically connected to other conductors (for example, a part of either or both of the first conductor layer 3 and the second conductor layer 4) if no particular electrical problems arise. Furthermore, in the example shown in Figure 3, the first conductor layer 3 includes a plurality of conductor pads 3a. A conductor pattern 5 is provided for each conductor pad 3a. The conductor patterns 5 provided for each conductor pad 3a are independent of each other. That is, in this embodiment, a plurality of conductor patterns 5, each overlapping the outer edge of each conductor pad 3a, are formed without being connected to each other.

[0038] The solder resist layer 7 is formed on the first interlayer insulating layer 2. By being formed on the first interlayer insulating layer 2, the solder resist layer 7 has the function of protecting the first interlayer insulating layer 2. The solder resist layer 7 is formed using, for example, epoxy resin or polyimide resin. As shown in Figures 1 to 3, the solder resist layer 7 has openings 7a that expose the conductor pads 3a. More specifically, as shown in Figure 2, the solder resist layer 7 has openings 7a that expose the surface (front) 3f1 and side 3f2 of the conductor pad 3a opposite to the first interlayer insulating layer 2. In the example shown in Figure 2, the solder resist layer 7 is spaced apart from the peripheral edge (outer edge) of each conductor pad 3a so as not to cover the peripheral edge. As a result, the openings 7a expose the surface 3f1 and side 3f2 of each conductor pad 3a opposite to the first interlayer insulating layer 2. Therefore, the wiring board 1 and the external element S1 can be firmly connected over a large area.

[0039] Similarly, the solder resist layer 70 (see Figure 1) has an opening 70a that exposes the component mounting pads 33a. More specifically, the solder resist layer 70 has an opening 70a that exposes only the surface of the component mounting pad 33a opposite to the interlayer insulating layer 23 (the front surface). In the example shown in Figure 1, the solder resist layer 70 is provided so as to cover the peripheral edge of each component mounting pad 33a. As a result, the opening 70a exposes only a portion of the surface of each component mounting pad 33a opposite to the interlayer insulating layer 23.

[0040] Next, the manufacturing method of the wiring board 1 according to this embodiment will be described with reference to Figures 1 to 11. Figures 4 to 11 are cross-sectional views showing an example of the state during the manufacturing process of the wiring board of one embodiment of the present invention.

[0041] The wiring board 1 shown in Figures 1 to 3 can be manufactured by a general wiring board manufacturing method. For example, a double-sided copper-clad laminate including a core insulating layer 20 (see Figure 1) is prepared. Then, a conductor layer 31 including a predetermined wiring pattern is formed on the first main surface 20a of the core insulating layer 20 by a subtractive method or the like, and a conductor layer 32 including a predetermined wiring pattern is formed on the second main surface 20b of the core insulating layer 20. At the same time, through-hole conductors 20c are formed by filling through holes provided in the core insulating layer 20 with conductors, and the core substrate of the wiring board 1 is prepared.

[0042] An interlayer insulating layer 21 is laminated on the first main surface 20a side of the core insulating layer 20, and a conductor layer 31 is formed on the interlayer insulating layer 21. Similarly, an interlayer insulating layer 22 is laminated on the second main surface 20b side of the core insulating layer 20, and a conductor layer 32 is formed on the interlayer insulating layer 22. The lamination of each interlayer insulating layer and the formation of the conductor layer are then repeated on both sides of the core substrate. The interlayer insulating layer 21 and the conductor layer 31 on it, the interlayer insulating layer 22 and the conductor layer 32 on it, and the conductor layer 4 are each formed, for example, by a general build-up substrate manufacturing method. For example, each interlayer insulating layer is formed by thermocompression bonding a film-like epoxy resin onto the core substrate or onto each of the previously formed interlayer insulating layers and each of the conductor layers. In addition, each conductor layer is formed using any method for forming a conductor pattern, such as a semi-additive method or a fully additive method, which includes the formation of a plating resist and pattern plating. In the formation of each conductor layer using a conductor pattern formation method such as the semi-additive method, vias 6 can be formed within each interlayer insulating layer.

[0043] The outermost insulating layers (interlayer insulating layer 23 and first interlayer insulating layer 2) are formed on the first main surface 20a side and the second main surface 20b side of the core insulating layer 20, respectively. In this embodiment, a conductor pattern 5 is formed during the formation of the first interlayer insulating layer 2. The conductor pattern 5 is formed between the first conductor layer 3 and the second conductor layer 4 so as to overlap with the outer edge of the conductor pad 3a, which is formed in a later step than the formation of the conductor pattern 5.

[0044] In the example shown in Figure 1, no conductor pattern is formed on the interlayer insulating layer 23, but a conductor pattern may be formed on the interlayer insulating layer 23. When a conductor pattern is formed on the interlayer insulating layer 23, the conductor pattern is formed between the conductor layer 31 and the conductor layer 33 so as to overlap with the outer edge of the component mounting pad 33a, which is formed in a later step than the formation of the conductor pattern.

[0045] More specifically, as shown in Figure 4, the outermost interlayer insulating layer 22 is formed on the wiring board 1, vias 6 are formed within the interlayer insulating layer 22, and a second conductor layer 4 is formed on the interlayer insulating layer 22.

[0046] In the example shown in Figure 4, an electroless plating film 111, which serves as a seed metal film, is formed on the interlayer insulating layer 22 containing through holes for via formation and on the inner surface of the through holes by electroless plating or the like. Then, an electroplating film 112 is filled into the through holes for via formation. The electroplating film 112 is formed on the electroless plating film 111 on the interlayer insulating layer 22. The electroplating film 112 on the interlayer insulating layer 22 and the electroplating film 112 in the through holes for via formation are formed integrally. Vias 6 are formed by the electroless plating film 111 and the electroplating film 112 in the through holes for via formation. The second conductor layer 4 is formed by the electroless plating film 111 and the electroplating film 112 on the interlayer insulating layer 22.

[0047] Subsequently, as shown in Figure 5, a second insulating layer 202, which is a part of the first interlayer insulating layer 2, is formed on the interlayer insulating layer 22 and the second conductor layer 4. Then, as shown in Figure 6, a conductor pattern 5 is formed on the second insulating layer 202. The conductor pattern 5 is formed on the second insulating layer 202 so as to overlap with the outer edge of the conductor pad 3a (see Figures 9 to 11) which is formed in a later step than the formation of the conductor pattern 5. In this embodiment, the conductor pattern 5 is formed in a substantially annular shape. Furthermore, the conductor pattern 5 is formed in a region such that vias 6 (vias connecting the first conductor layer 3 and the second conductor layer 4, see Figures 9 to 11) which are formed in a later step than the formation of the conductor pattern 5 are formed inside the annular shape of the conductor pattern 5.

[0048] In detail, the conductor pattern 5 is formed using any method for forming a conductor pattern, such as a semi-additive method, which uses a plating resist (not shown) having an appropriate opening pattern that includes the conductor pattern 5. Specifically, an electroless plating film 111, which will serve as a seed metal film, is formed over the entire surface of the second insulating layer 202 by electroless plating or the like. Subsequently, a plating resist having the opening pattern is formed on the electroless plating film 111. Then, an electrolytic plating film 112 is formed on the areas of the electroless plating film 111 where the plating resist has not been formed by electrolytic plating. After that, the plating resist is removed. Then, the electroless plating film 111 exposed by the removal of the plating resist is removed by etching. The conductor pattern 5 is formed by the electroless plating film 111 and the electrolytic plating film 112 remaining on the second insulating layer 202.

[0049] Subsequently, as shown in Figure 7, the first insulating layer 201 is formed on the second insulating layer 202 and the conductor pattern 5. The first interlayer insulating layer 2 is formed by the first insulating layer 201 and the second insulating layer 202. The first insulating layer 201 and the second insulating layer 202 may be made of the same resin material or of different resin materials.

[0050] Subsequently, as shown in Figure 8, through-holes 203 are formed in the first interlayer insulating layer 2 by irradiation with laser light or the like. The through-holes 203 are formed so as to expose the second conductor layer 4. Then, as shown in Figure 9, a first conductor layer 3 is further formed on the first interlayer insulating layer 2. The first conductor layer 3 is formed using any method for forming a conductor pattern, such as a semi-additive method using a plating resist 8 having an appropriate opening pattern that includes a conductor pad 3a. An electroless plating film 111 is formed on the inner surface of the through-holes 203 by electroless plating or the like. An electrolytic plating film 112 is filled inside the through-holes 203. An electrolytic plating film 112 is formed on the electroless plating film 111 on the interlayer insulating layer 22. The electroless plating film 111 and the electrolytic plating film 112 inside the through-holes 203 constitute a via 6. On the first interlayer insulating layer 2, the electroless plating film 111 and the electrolytic plating film 112 are formed such that their outer edges overlap the conductor pattern 5 when viewed from a direction along the thickness direction Z of the wiring substrate 1.

[0051] Similarly, an outermost conductive layer 33 is formed on the outermost interlayer insulating layer 23 (see Figure 1). The outermost conductive layer 33 is formed using any conductive pattern formation method, such as a semi-additive method using a plating resist (not shown) having an appropriate opening pattern that includes component mounting pads 33a.

[0052] Subsequently, as shown in Figure 10, the plating resist 8 is removed. Then, the electroless plating film 111 exposed by the removal of the plating resist 8 is removed by etching. After that, as shown in Figure 11, a solder resist layer 7 is formed on the first interlayer insulating layer 2. An opening 7a is provided in the solder resist layer 7. The solder resist layer 7 is formed, for example, by coating, spraying, or laminating a photosensitive epoxy resin or polyimide resin in a film form. Then, the opening 7a is formed, for example, by exposure and development, or by laser processing. The opening 7a is formed to expose the entire surface of the exposed electroless plating film 111 and electrolytic plating film 112 in Figure 10, that is, the surface (front) 112f1 and side surface 112f2 of the first conductor layer 3 opposite to the first interlayer insulating layer 2.

[0053] Similarly, a solder resist layer 70 (see Figure 1) is formed on the outermost interlayer insulating layer 23. An opening 70a is provided in the solder resist layer 70. The solder resist layer 70 can be formed in the same manner as the solder resist layer 7.

[0054] Subsequently, as shown in Figure 2, a metal film 113 is formed on the exposed surfaces of the electroplated film 112 and the electroless plating film 111. The metal film 113 is formed, for example, by electroless plating. This forms the first conductor layer 3, which includes the conductor pad 3a. Through these steps, the wiring board 1, which includes the conductor pattern 5 illustrated in Figure 2, is completed.

[0055] The wiring board of this embodiment is not limited to the structures illustrated in each drawing or the structures and materials illustrated herein. The wiring board of this embodiment may have any laminated structure. Furthermore, the wiring board of this embodiment may be a coreless board that does not include a core board. The wiring board of this embodiment may include any number of conductor layers and insulating layers. For example, the first conductor layer 3 may include different conductor patterns in addition to the conductor pad 3a. [Explanation of Symbols]

[0056] 1 Wiring board 2. First interlayer insulating layer 3. First Conductor Layer 3a Conductor pad 3f1 The side of the conductor pad opposite to the first interlayer insulating layer. 3f2 side 4. Second Conductor Layer 5 Conductor Patterns 6 via conductors (vias) 7 Solder Resist Layer 7a aperture 231 First insulating layer 232 Second insulating layer Z-axis wiring board thickness direction

Claims

1. The first interlayer insulating layer, A first conductor layer formed on the first interlayer insulating layer, including a conductor pad, A second conductor layer formed on the opposite side from the first conductor layer via the first interlayer insulating layer, A wiring substrate comprising a solder resist layer formed on the first interlayer insulating layer, The solder resist layer has an opening that exposes the surface and side of the conductor pad opposite to the first interlayer insulating layer. The wiring board further includes a conductor pattern formed between the first conductor layer and the second conductor layer so as to overlap with the outer edge of the conductor pad. The first conductor layer includes a plurality of conductor pads, The conductor pattern is provided for each of the conductor pads, The conductor patterns provided for each conductor pad are independent of each other.

2. A wiring board according to claim 1, The device further comprises vias connecting the first conductor layer and the second conductor layer.

3. A wiring board according to claim 2, The aforementioned conductor pattern is formed in a substantially annular shape, The via is formed inside the ring in the conductor pattern.

4. A wiring board according to claim 1, The first interlayer insulating layer is A second insulating layer located on the second conductor layer side in the thickness direction of the wiring board, The wiring board includes a first insulating layer located on the first conductor layer side in the thickness direction, The conductor pattern is formed on the second insulating layer and covered by the first insulating layer.

5. A first interlayer insulating layer, A first conductor layer formed on the first interlayer insulating layer, including a conductor pad, A second conductor layer formed on the opposite side from the first conductor layer via the first interlayer insulating layer, A wiring substrate comprising a solder resist layer formed on the first interlayer insulating layer, The solder resist layer has an opening that exposes the surface and side of the conductor pad opposite to the first interlayer insulating layer. The wiring board further includes a conductor pattern formed between the first conductor layer and the second conductor layer so as to overlap with the outer edge of the conductor pad. The first interlayer insulating layer is A second insulating layer located on the second conductor layer side in the thickness direction of the wiring board, The wiring board includes a first insulating layer located on the first conductor layer side in the thickness direction, The conductor pattern is formed on the second insulating layer and covered by the first insulating layer. The first insulating layer and the second insulating layer are made of the same resin material.

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