Erasable programmable single-layer polycarbonate non-volatile memory cell

Abstract

To provide an erasable programmable single-poly non-volatile memory cell.SOLUTION: A memory cell includes multiple doped regions formed by different manufacturing procedures. The memory cell includes a select transistor and a floating gate transistor. The channel length of the floating gate transistor is shorter than the channel length of the select transistor. A doping process in a manufacturing method is changed, such that the multiple doped regions have different parameters and characteristics, and the channel resistance of the floating gate transistor is larger than the channel resistance of the select transistor.SELECTED DRAWING: Figure 2H

Description

Technical Field

[0001] The present invention relates to non-volatile memories, particularly to erasable programmable single-poly non-volatile memory cells.

Background Art

[0002] As is well known, a memory cell of a non-volatile memory includes a storage unit. For example, the storage unit is a floating-gate transistor. The storage state of the memory cell is determined according to the number of charges accumulated in the floating gate of the floating-gate transistor.

[0003] To be compatible with a standard CMOS manufacturing process, a memory cell of a conventional non-volatile memory includes a single-poly floating-gate transistor. The floating-gate transistor and related electronic components are collaboratively formed as a single-poly non-volatile memory cell.

[0004] For example, an erasable programmable single-poly non-volatile memory is disclosed in Patent Document 1. FIG. 1A is a schematic top view showing a conventional single-poly non-volatile memory cell. FIG. 1B is a schematic cross-sectional view showing a conventional single-poly non-volatile memory cell, which is a view cut along line a1-a1. FIG. 1C is a schematic cross-sectional view showing a conventional single-poly non-volatile memory cell, which is a view cut along line b1-b1. FIG. 1D is a schematic equivalent circuit diagram of a conventional single-poly non-volatile memory cell.

[0005] As shown in Figures 1A to 1D, three p-type doped regions 131, 132, and 133 are formed in the N-well region NW. Furthermore, a selection gate 134 and a floating gate 136, formed of a polysilicon layer, are located in the region between the p-type doped regions 131, 132, and 133. An n-type doped region 138 is formed in the P-well region PW. The floating gate 136 extends outward from the separation structure 139 and is located lateral to the n-type doped region 138. For example, the separation structure 139 is a shallow trench separation (STI) structure.

[0006] Conventional single-layer polycarbonate non-volatile memory cells consist of a selection transistor MS, a floating gate transistor MF, and an n-type transistor Mn. The selection transistor MS and floating gate transistor MF are p-type transistors and are formed in the N-well region NW. The n-type transistor Mn is formed in the P-well region PW.

[0007] The p-type doped region 131, the p-type doped region 132, the selection gate 134, and the N-well region NW work together to form a selection transistor MS. The p-type doped region 132, the p-type doped region 133, the floating gate 136, and the N-well region NW work together to form a floating gate transistor MF. The floating gate 136 and the assist gate region 135 work together to form an n-type transistor Mn. Furthermore, the erase gate region 135 includes a P-well region PW and an n-type doped region 138.

[0008] Refer to Figure 1D. The selection gate voltage VSG is applied to the selection gate 134 of the selection transistor MS. The source line voltage VSL is applied to the first drain / source terminal of the selection transistor MS. The N-well voltage VNW is applied to the body terminal of the selection transistor MS. The first drain / source terminal of the floating gate transistor MF is connected to the second drain / source terminal of the selection transistor MS. The bit line voltage VBL is applied to the second drain / source terminal of the floating gate transistor MF. The N-well voltage VNW is applied to the body terminal of the floating gate transistor MF.

[0009] Furthermore, the two drain / source terminals of the n-type transistor Mn can be considered to be connected to the n-type doped region 138. The P-well voltage VPW is applied to the body terminal of the n-type transistor Mn. The gate terminal of the n-type transistor Mn is connected to the floating gate 136. The disappearance line voltage VEL is applied to the two drain / source terminals of the n-type transistor Mn. In other words, the n-type transistor Mn is equivalent to a metal oxide semiconductor capacitor, which will also be referred to as a MOS capacitor below.

[0010] Conventional memory cells consist of two transistors, MS and MF, and one capacitor, and are sometimes called 2T1C cells.

[0011] By providing appropriate bias voltages as the selection gate voltage VSG, source line voltage VSL, bit line voltage VBL, erase line voltage VEL, N-well voltage VNW, and P-well voltage VPW, it is possible to selectively perform program, erase, or read operations on the memory cell.

[0012] Generally, in the doping process of the memory cell manufacturing process described above, all p-type doped regions 131, 132, and 133 are formed using the same manufacturing procedure, and therefore the p-type doped regions 131, 132, and 133 have the same parameters and characteristics.

[0013] Similarly, all p-type doped regions of other memory cells disclosed in Patent Document 1 are also formed using the same manufacturing procedure. [Prior art documents] [Patent Documents]

[0014] [Patent Document 1] U.S. Patent No. 8941167 [Overview of the project] [Problems that the invention aims to solve]

[0015] Many of the objectives, features, and advantages of the present invention will become apparent upon reading the following detailed description of embodiments of the invention in conjunction with the accompanying drawings. However, the drawings used herein are for illustrative purposes only and should not be considered limiting. [Means for solving the problem]

[0016] One embodiment of the present invention provides an eraseable programmable single-layer polynonvolatile memory cell. The eraseable programmable single-layer polynonvolatile memory cell includes an isolation structure, a first well region, a second well region, a first gate structure, and a second gate structure. The isolation structure is formed on a semiconductor substrate. The surface of the semiconductor substrate is divided into a first region and a second region by the isolation structure. The first well region is formed on the surface of the semiconductor substrate corresponding to the first region. The second well region is formed on the surface of the semiconductor substrate corresponding to the second region. The first gate structure and the second gate structure are formed on the surface of the semiconductor substrate corresponding to the first region. The region of the semiconductor substrate surface corresponding to the first region is divided by the first gate structure and the second gate structure into a first merged doped region, a second merged doped region, and a third merged doped region. The memory cell further comprises a fourth merged doped region. The fourth merged doped region is formed on the surface of the semiconductor substrate corresponding to the second region and is located lateral to the side of the second gate structure. The first merged doped region is located lateral to the first side of the first gate structure. The second merge-doped region is located between the second side of the first gate structure and the first side of the second gate structure. The third merge-doped region is located lateral to the second side of the second gate structure. The second gate structure extends outward through the surface of the isolation structure into the second region. Part of the second region is covered by the second gate structure. The first merge-doped region, the first gate structure, and the second merge-doped region work together to form a selection transistor. The second merge-doped region, the second gate structure, and the third merge-doped region work together to form a floating-gate transistor. The second gate structure and the fourth merge-doped region work together to form a first MOS capacitor. The channel resistance of the floating-gate transistor is greater than the channel resistance of the selection transistor. [Brief explanation of the drawing]

[0017] [Figure 1A] (Prior Art) This is a schematic top view showing a conventional single-layer poly non-volatile memory cell. [Figure 1B](Prior Art) It is a schematic cross-sectional view showing a conventional single-layer poly non-volatile memory cell, and is a view cut along the line a1-a1. [Figure 1C] (Prior Art) It is a schematic cross-sectional view showing a conventional single-layer poly non-volatile memory cell, and is a view cut along the line b1-b1. [Figure 1D] (Prior Art) It is a schematic equivalent circuit diagram of a conventional single-layer poly non-volatile memory cell. [Figure 2A] It is a diagram schematically showing the steps of a method for manufacturing a single-layer poly non-volatile memory cell according to the first embodiment of the present invention. [Figure 2B] It is a diagram schematically showing the steps of a method for manufacturing a single-layer poly non-volatile memory cell according to the first embodiment of the present invention. [Figure 2C] It is a diagram schematically showing the steps of a method for manufacturing a single-layer poly non-volatile memory cell according to the first embodiment of the present invention. [Figure 2D] It is a diagram schematically showing the steps of a method for manufacturing a single-layer poly non-volatile memory cell according to the first embodiment of the present invention. [Figure 2E] It is a diagram schematically showing the steps of a method for manufacturing a single-layer poly non-volatile memory cell according to the first embodiment of the present invention. [Figure 2F] It is a diagram schematically showing the steps of a method for manufacturing a single-layer poly non-volatile memory cell according to the first embodiment of the present invention. [Figure 2G] It is a diagram schematically showing the steps of a method for manufacturing a single-layer poly non-volatile memory cell according to the first embodiment of the present invention. [Figure 2H] It is a diagram schematically showing the steps of a method for manufacturing a single-layer poly non-volatile memory cell according to the first embodiment of the present invention. [Figure 2I] It is a schematic equivalent circuit diagram of a single-layer poly non-volatile memory cell according to the first embodiment of the present invention. [Figure 2J] It is a bias voltage table showing the bias voltages for performing a program operation, an erase operation, and a read operation on the memory cell according to the first embodiment of the present invention. [Figure 2K]This figure shows the program operation in a memory cell according to the first embodiment of the present invention. [Figure 2L] This figure shows the erasure operation in a memory cell according to the first embodiment of the present invention. [Figure 2M] This figure shows the read operation in a memory cell according to the first embodiment of the present invention. [Figure 3A] This figure schematically shows a first modified example of the doping process in the manufacturing method of the first embodiment. [Figure 3B] This figure schematically shows a first modified example of the doping process in the manufacturing method of the first embodiment. [Figure 3C] This figure schematically shows a first modified example of the doping process in the manufacturing method of the first embodiment. [Figure 4A] This figure schematically shows a second modified example of the doping process in the manufacturing method of the first embodiment. [Figure 4B] This figure schematically shows a second modified example of the doping process in the manufacturing method of the first embodiment. [Figure 4C] This figure schematically shows a second modified example of the doping process in the manufacturing method of the first embodiment. [Figure 5A] This figure schematically shows a third modified example of the doping process in the manufacturing method of the first embodiment. [Figure 5B] This figure schematically shows a third modified example of the doping process in the manufacturing method of the first embodiment. [Figure 5C] This figure schematically shows a third modified example of the doping process in the manufacturing method of the first embodiment. [Figure 6] This figure schematically shows a fourth modified example of the doping process in the manufacturing method of the first embodiment. [Figure 7A] This figure schematically shows the steps of a method for manufacturing a single-layer polynonvolatile memory cell according to a second embodiment of the present invention. [Figure 7B] This figure schematically shows the steps of a method for manufacturing a single-layer polynonvolatile memory cell according to a second embodiment of the present invention. [Figure 7C]This figure schematically shows the steps of a method for manufacturing a single-layer polynonvolatile memory cell according to a second embodiment of the present invention. [Figure 7D] This figure schematically shows the steps of a method for manufacturing a single-layer polynonvolatile memory cell according to a second embodiment of the present invention. [Figure 7E] This figure schematically shows the steps of a method for manufacturing a single-layer polynonvolatile memory cell according to a second embodiment of the present invention. [Figure 7F] This figure schematically shows the steps of a method for manufacturing a single-layer polynonvolatile memory cell according to a second embodiment of the present invention. [Figure 7G] This figure schematically shows the steps of a method for manufacturing a single-layer polynonvolatile memory cell according to a second embodiment of the present invention. [Figure 7H] This is a schematic equivalent circuit diagram of a single-layer poly-nonvolatile memory cell according to a second embodiment of the present invention. [Modes for carrying out the invention]

[0018] This invention provides a single-layer polynonvolatile memory cell. In the memory cell, multiple doped regions are formed by different manufacturing procedures. That is, the doping process in the manufacturing method of the memory cell is modified. As a result, the multiple doped regions have different parameters and characteristics, and the channel resistance of the floating gate transistor is greater than the channel resistance of the selected transistor. The inventive concept of this invention is described in more detail below.

[0019] Figures 2A to 2H schematically show the steps for manufacturing a single-layer polynonvolatile memory cell according to the first embodiment of the present invention. Figure 2I is a schematic equivalent circuit diagram of a single-layer polynonvolatile memory cell according to the first embodiment of the present invention. Hereinafter, the single-layer polynonvolatile memory cell will be referred to as a memory cell.

[0020] As shown in Figure 2A, a separation structure formation process is performed. A separation structure 202 is formed on the semiconductor substrate Sub. Regions A and B are defined by the separation structure 202. The semiconductor substrate Sub is covered with the separation structure 202. The surfaces of the semiconductor substrate Sub corresponding to regions A and B are exposed. Next, a well region formation process is performed. A first well region (e.g., a P-well region) is formed on the surface of the semiconductor substrate Sub corresponding to region A. Furthermore, a second well region is formed on the surface of the semiconductor substrate Sub corresponding to region B. For example, the second well region is a low-concentration doped P-well region (LPW), a P-well region (PW), or an N-well region (NW).

[0021] Next, a gate structure formation process is performed. As shown in Figure 2B, four gate oxide layers 223, 225, 227, and 229 are formed on the surface of the semiconductor substrate Sub. Gate structure 223 includes a gate dielectric layer 203 and a polysilicon gate layer 213. Gate structure 225 includes a gate dielectric layer 205 and a polysilicon gate layer 215. Gate structure 227 includes a gate dielectric layer 207 and a polysilicon gate layer 217. Gate structure 229 includes a gate dielectric layer 209 and a polysilicon gate layer 219. The gate dielectric layer 203 is placed between the polysilicon gate layer 213 and the semiconductor substrate Sub. The gate dielectric layer 205 is placed between the polysilicon gate layer 215 and the semiconductor substrate Sub. The gate dielectric layer 207 is placed between the polysilicon gate layer 217 and the semiconductor substrate Sub, and the gate dielectric layer 209 is placed between the polysilicon gate layer 219 and the semiconductor substrate Sub.

[0022] Two gate structures 223 and 225 are formed on the surface of region A. Furthermore, region A is divided into three sub-regions by the two gate structures 223 and 225. Gate structure 225 is L-shaped. The extended portion of gate structure 225 extends outward through the surface of isolation structure 202 to a region on the surface of region B. Two gate structures 227 and 229 cover only isolation structure 202. Furthermore, the two gate structures 227 and 229 are positioned laterally to the two mutually opposite sides of gate structure 225, respectively. The polysilicon gate layer 215 of gate structure 225 functions as the floating gate of the floating gate transistor. The polysilicon gate layer 213 of gate structure 223 functions as the selection gate of the selection transistor. In one embodiment, the channel length LF of the floating gate transistor is shorter than the channel length LS of the selection transistor. That is, LF <LSである。

[0023] As is well known, the channel resistance of a transistor is related to the channel length and channel width. The wider the channel width, the lower the channel resistance. The narrower the channel width, the higher the channel resistance. The shorter the channel length, the lower the channel resistance. The longer the channel length, the higher the channel resistance. In other words, if the n-doped regions in the structure of Figure 2B are formed by the same manufacturing process, the channel resistance of the floating gate transistor will be lower than that of the selected transistor.

[0024] In one embodiment, the doping process for doping the n-type doped region is specifically designed to change the concentration distribution of the n-type doped region. In particular, the channel resistance of the floating gate transistor is changed, and therefore the channel resistance of the floating gate transistor becomes greater than that of the selected transistor. The doping process will be described in more detail below with reference to a cross-sectional view along the cd line of the structure shown in Figure 2B.

[0025] Refer to Figure 2C. First, the gate structure 225 in region A and the regions on both sides of it are covered by the mask 240, shown by the dotted line. The gate structure 223 and the regions on both sides of it are exposed. Furthermore, region B is exposed. That is, only a portion of the surface between the gate structure 223 and the gate structure 225 is covered by the mask 240, and the rest of the surface between the gate structure 223 and the gate structure 225 is not covered by the mask 240. Next, the first low-concentration doped-drain process (LDD process) is performed. As a result, n-type low-concentration doped-drain regions (n-LDD regions) 241, 242, and 243 are formed on the surface of the semiconductor substrate Sub that is not covered by the mask 240. n-LDD regions 241 and 242 are formed beneath the surface of region A and are located on both sides of the gate structure 223, respectively. n-LDD region 243 is formed beneath the surface of region B and is located next to the gate structure 225.

[0026] Refer to Figure 2D. After mask 240 is removed, the gate structures 223 (and their side regions) in regions A and B are covered with mask 250, indicated by the dotted line. In other words, the regions previously covered by mask 240 are exposed. Next, a second LDD process is performed. As a result, n-type low-concentration doped drain regions (n-LDD regions) 251 and 252 are formed on the surface of the semiconductor substrate Sub that is not covered by mask 250. The n-LDD regions 251 and 252 are formed beneath the surface of region A and are located on both sides of the gate structure 225, respectively.

[0027] For example, masks 240 and 250 are photoresists. In one embodiment, the dopant concentrations in n-LDD regions 251 and 252 are smaller than the dopant concentrations in n-LDD regions 241, 242, and 243.

[0028] Please refer to Figure 2E. After the mask 250 is removed, a spacer 248 is formed on the side wall of gate structure 223, and a spacer 258 is formed on the side wall of gate structure 225. Furthermore, spacers (not shown) are formed on the side walls of gate structures 227 and 229.

[0029] Please refer to Figure 2F. Next, an n-type ion implantation process is performed on the surface of the semiconductor substrate Sub using the two gate structures 223 and 225 and the two spacers 248 and 258 as masks. As a result, three n-type ion implantation regions 261, 262, and 263, indicated by the shaded lines, are formed in three sub-regions of region A that are not covered by the two gate structures 223 and 225 and the two spacers 248 and 258, and an n-type ion implantation region 264, also indicated by the shaded lines, is formed in region B that is not covered by the gate structure 225 and the spacer 258. In particular, the n-type ion implantation regions 261, 262, 263, and 264 have the highest dope concentrations, and their dopant concentrations are higher than those of the n-LDD regions 241, 242, 243, and 251.

[0030] Refer to Figure 2F. Next, the n-LDD region 241 and the n-type ion implantation region 261 work together to form a merged n-doped region 271. The merged n-doped region 271 is formed on the surface of the semiconductor substrate Sub and is located next to the first side of the gate structure 223. The n-LDD region 242, the n-LDD region 251, and the n-type ion implantation region 262 work together to form a merged n-doped region 272. The merged n-doped region 272 is formed on the surface of the semiconductor substrate Sub and is located between the second side of the gate structure 223 and the first side of the gate structure 225. The n-LDD region 252 and the n-type ion implantation region 263 work together to form a merged n-doped region 273. The merged n-doped region 273 is formed on the surface of the semiconductor substrate Sub, while the n-LDD region 243 and the n-type ion implantation region 264 are formed on the surface of the semiconductor substrate Sub and are located next to the second side of the gate structure 225. The n-type LDD region 243 and the n-type ion implantation region 264 work together to form a merged n-doped region 274. The merged n-doped region 274 is formed on the surface of the semiconductor substrate Sub and is located next to the extension of the gate structure 225. A bird's-eye view of the structure shown in Figure 2F is shown in Figure 2G.

[0031] In region A, the gate structure 223 and the merged n-doped regions 271 and 272 on either side work together to form a selection transistor. Furthermore, the gate structure 225 and the two merged n-doped regions 272 and 273 on either side work together to form a floating gate transistor. In this embodiment, the floating gate transistor and the selection transistor are n-type transistors and are configured within the P-well region PW. That is, the body terminals of the floating gate transistor and the body terminals of the selection transistor are connected to the P-well region PW.

[0032] In region B, the n-type doped region 274 is the erase gate region. The gate structure 225 is extended outward and positioned next to the erase gate region. As a result, the erase gate region and the gate structure 225 cooperate to form an n-type transistor. Furthermore, the n-type transistor is connected as a MOS capacitor.

[0033] Refer to Figure 2H. Next, a metal layer 280 is formed on the polysilicon gate layer 215. The metal layer 280 is electrically connected to the two polysilicon gate layers 217 and 219. Once the process of forming the metal conductors is complete, a memory cell of the first embodiment is manufactured. That is, the n-type doped region 271 is connected to the source line SL, the n-type doped region 273 is connected to the bit line BL, the n-type doped region 274 is connected to the erase line EL, the polysilicon gate layer 213 is connected to the selection gate line SG, and the metal layer 280 is connected to the assist gate line AG.

[0034] In the memory cell according to this embodiment, gate structures 227 and 229 are arranged on the surface of the isolation structure 202. Furthermore, a metal layer 280 is arranged on the polysilicon gate structure 225. As a result, the polysilicon gate layer 215 and the polysilicon gate layer 217 work together to form a first poly / polyplate capacitor, and the polysilicon gate layer 215 and the polysilicon gate layer 219 work together to form a second poly / polyplate capacitor. Furthermore, the polysilicon gate layer 215 and the metal layer 280 work together to form a metal / polyplate capacitor.

[0035] As shown in Figure 2I, the memory cell according to the first embodiment comprises a selection transistor MS, a floating gate transistor MF, a MOS capacitor CMOS, a first poly / polyplate capacitor CP1, a metal / polyplate capacitor CP2, and a second poly / polyplate capacitor CP3. The first poly / polyplate capacitor CP1, the metal / polyplate capacitor CP2, and the second poly / polyplate capacitor CP3 are connected in parallel with each other. The three capacitors connected in parallel, CP1, CP2, and CP3, are equivalent to a plate capacitor CP. It should be noted that the capacitor CP of the memory cell is not limited to the three capacitors connected in parallel, CP1, CP2, and CP3. For example, at least one capacitor is feasible.

[0036] The gate terminal of the selection transistor MS is connected to the selection gate line SG. The first drain / source terminal of the selection transistor MS is connected to the source line SL. The first drain / source terminal of the floating gate transistor MF is connected to the second drain / source terminal of the selection transistor MS. The second drain / source terminal of the floating gate transistor MF is connected to the bit line BL.

[0037] The first terminal of the MOS capacitor CMOS is connected to the floating gate 215. The second terminal of the MOS capacitor CMOS is connected to the erase line EL. The first terminal of the first poly / poly plate capacitor CP1 is connected to the floating gate 215. The second terminal of the first poly / poly plate capacitor CP1 is connected to the assist gate line AG. The first terminal of the metal / poly plate capacitor CP2 is connected to the floating gate 215. The second terminal of the metal / poly plate capacitor CP2 is connected to the assist gate line AG. The first terminal of the second poly / poly plate capacitor CP3 is connected to the floating gate 215. The second terminal of the second poly / poly plate capacitor CP3 is connected to the assist gate line AG. In other words, the first terminal of the plate capacitor CP is connected to the floating gate 215, and the second terminal of the plate capacitor CP is connected to the assist gate line AG.

[0038] The memory cell according to the first embodiment includes two transistors MS and MF and two capacitors CP and CMOS, and is therefore sometimes referred to as a 2T2C cell.

[0039] Figure 2J is a bias voltage table showing the bias voltages for performing program, erase, and read operations on a memory cell according to the first embodiment of the present invention. Figure 2K is a diagram showing the program operation in the memory cell according to the first embodiment of the present invention. Figure 2L is a diagram showing the erase operation in the memory cell according to the first embodiment of the present invention. Figure 2M is a diagram showing the read operation in the memory cell according to the first embodiment of the present invention.

[0040] When a program operation (PGM), erase operation (ERS), and read operation (Read) are performed, a ground voltage (0V) is applied to the P-well area PW and the source line SL. Also, the assist gate line voltage VAG is higher than the erase voltage VEE, the erase voltage VEE is higher than the program voltage VPP, the program voltage VPP is higher than the read voltage VR, and the read voltage VR is higher than the ground voltage (0V). For example, the assist gate line voltage VAG is 15V, the erase voltage VEE is 12V, the program voltage VPP is 9V, and the read voltage VR is 5V.

[0041] Please refer to Figure 2K. When the program operation is executed, the program voltage VPP is applied to the bit line BL, the program voltage VPP is applied to the selection gate line SG, the voltage between the ground voltage (0V) and the erase voltage VEE is applied to the erase line EL, and the voltage between the ground voltage (0V) and the assist gate line voltage VAG is applied to the assist gate line AG.

[0042] While the program operation is being executed, the selection transistor MS is turned on, and a program current IP is generated between the bit line BL and the source line SL. When the hot carriers (e.g., electrons) of the program current IP flow through the channel region corresponding to the floating gate 215, a channel hot electron (CHE) effect occurs. Due to the CHE effect, electrons are injected into the floating gate 215.

[0043] As mentioned above, the channel resistance of the floating-gate transistor MF is greater than that of the selection transistor MS. After the program voltage VPP is supplied to the bit line BL, the voltage between the first and second drain / source terminals of the floating-gate transistor MF becomes greater than the voltage between the first and second drain / source terminals of the selection transistor MS. As a result, when the programmed operation is performed, electrons are injected into the floating gate 215 more efficiently.

[0044] Refer to Figure 2L. When the erase operation (ERS) is performed, the ground voltage (0V) is applied to the bit line BL, the ground voltage (0V) is applied to the source line SL, the ground voltage (0V) is applied to the select gate line SG, the erase voltage VEE is applied to the erase line EL, and a voltage between the negative assist gate line voltage -VAG and the ground voltage (0V) is applied to the assist gate line AG.

[0045] When the erase operation is performed, the selection transistor MS is turned off. Under these conditions, the Fowler-Nordheim tunneling effect (FN) occurs between the two terminals of the MOS transistor CMOS. As a result, electrons are ejected from the floating gate 215 to the erase line EL. The voltage applied to the assist gate line AG helps to increase the rate at which electrons are ejected from the floating gate 215. As a result, the erasure efficiency is improved.

[0046] Refer to Figure 2M. When a read operation is performed, the read voltage VR is applied to the bit line BL, the ground voltage (0V) is applied to the source line SL, the read voltage VR is applied to the select gate line SG, the ground voltage (0V) is applied to the erase line EL, and a voltage between a negative assist gate line voltage -VAG and a positive assist gate line voltage VAG is applied to the assist gate line AG. The magnitude of the read current IR is adjusted according to the voltage applied to the assist gate line AG.

[0047] When a read operation is performed, the selection transistor MS turns on, and a read current IR is generated between the bit line BL and the source line SL. The memory state of the memory cell can be determined according to the magnitude of the read current IR. For example, if electrons are accumulated in the floating gate 215, the magnitude of the read current IR is very small (e.g., almost zero). Therefore, the memory cell is determined to be in the first memory state. On the other hand, if no electrons are accumulated in the floating gate 215, the magnitude of the read current IR is very large. Under these circumstances, the memory cell is determined to be in the second memory state.

[0048] As described above, the present invention provides two LDD processes to generate LDD regions with different dopant concentrations. As a result, the floating gate transistor MF with a short channel length has a high channel resistance. Refer again to Figure 2F. In the merged n-doped region 272, the dopant concentration is lower in the n-LDD region 251 closer to the first side of the gate structure 225 of the floating gate transistor MF. In the merged n-doped region 273, the dopant concentration is lower in the n-LDD region 252 closer to the second side of the gate structure 225 of the floating gate transistor MF. In the merged n-doped region 271, the dopant concentration is higher in the n-LDD region 241 closer to the first side of the gate structure 223 of the selected transistor MS. In the merged n-doped region 272, the dopant concentration is higher in the n-LDD region 242 closer to the first side of the gate structure 223 of the selected transistor MS. The difference in dopant concentration near the channel can affect the channel resistance of the floating gate transistor MF and the channel resistance of the selection transistor MS; therefore, the channel resistance of the floating gate transistor MF is greater than that of the selection transistor MS.

[0049] The doping process in the first embodiment is modifiable. Several modifications of the doping process are described below. By using these modifications, the channel resistance of the floating gate transistor MF with a short channel length can be increased.

[0050] Figures 3A, 3B, and 3C schematically show a first modified example of the doping process in the manufacturing method of the first embodiment, and the procedure of the doping process in this modified example follows the structure shown in Figure 2B.

[0051] Refer to Figure 3A. First, the gate structure 225, gate structure 223, and the regions on both sides of gate structure 225 in region A are covered with a mask 340, indicated by a dotted line. Furthermore, only the side region of gate structure 223 (e.g., the right side region) is exposed. Next, a first low-concentration doped-drain process (LDD process) is performed. As a result, n-type low-concentration doped-drain regions (n-LDD regions) 341 and 343 are formed on the surface of the semiconductor substrate Sub that is not covered by the mask 340. n-LDD region 341 is formed beneath the surface of region A and is located next to the side (e.g., the right side) of gate structure 223. n-LDD region 343 is formed beneath the surface of region B and is located next to gate structure 225.

[0052] Refer to Figure 3B. After mask 340 is removed, the side (e.g., the right side) of the gate structure 223 in regions A and B is covered with mask 350, indicated by the dotted line. In other words, the region previously covered by mask 340 is exposed. Next, a second LDD process is performed. As a result, n-type low-concentration doped drain regions (n-LDD regions) 351 and 352 are formed on the surface of the semiconductor substrate Sub that is not covered by mask 350. The n-LDD regions 351 and 352 are formed beneath the surface of region A and are located on both sides of the gate structure 225, respectively.

[0053] For example, masks 340 and 350 are photoresists. In one embodiment, the dopant concentrations in n-LDD regions 351 and 352 are smaller than the dopant concentrations in n-LDD regions 341 and 243.

[0054] Refer to Figure 3C. After forming spacers 248 and 258, the n-type ion implantation process is performed on the surface of the semiconductor substrate Sub using the two gate structures 223 and 225 and the two spacers 248 and 258 as masks. As a result, three n-type ion implantation regions 261, 262, and 263, indicated by the shaded lines, are formed in three sub-regions of region A that are not covered by the two gate structures 223 and 225 and the two spacers 248 and 258, and an n-type ion implantation region 264, also indicated by the shaded lines, is formed in region B that is not covered by the gate structure 225 and spacer 258.

[0055] Please refer to Figure 3C again. Next, the n-LDD region 341 and the n-type ion implantation region 261 work together to form a merged n-doped region 271. The merged n-doped region 271 is formed on the surface of the semiconductor substrate Sub and is located next to the first side of the gate structure 223. The n-LDD region 351 and the n-type ion implantation region 262 work together to form a merged n-doped region 272. The merged n-doped region 272 is formed on the surface of the semiconductor substrate Sub and is located between the second side of the gate structure 223 and the first side of the gate structure 225. The n-LDD region 352 and the n-type ion implantation region 263 work together to form a merged n-doped region 273. The merged n-doped region 273 is formed on the surface of the semiconductor substrate Sub and is located next to the second side of the gate structure 225. The n-LDD region 343 and the n-type ion implantation region 264 work together to form a merged n-doped region 274. The merged n-doped region 274 is formed on the surface of the semiconductor substrate Sub and is located lateral to the extension of the gate structure 225.

[0056] Please compare the structure in Figure 2F with the structure in Figure 3C. The dopant concentration in the n-LDD region 242 on the left side of the gate structure 223 of the memory cell in Figure 2F is higher than the dopant concentration in the n-LDD region 351 on the left side of the gate structure 223 of the memory cell in Figure 3C. The dopant concentrations in the other n-LDD regions are the same.

[0057] Please refer to Figure 3C again. In the merged n-doped region 272, the dopant concentration is lower in the n-LDD region 351 closer to the first side of the gate structure 225 of the floating gate transistor MF. In the merged n-doped region 273, the dopant concentration is lower in the n-LDD region 352 closer to the second side of the gate structure 225 of the floating gate transistor MF. In the merged n-doped region 271, the dopant concentration is higher in the n-LDD region 341 closer to the first side of the gate structure 223 of the selection transistor MS. In the merged n-doped region 272, the dopant concentration is lower in the n-LDD region 351 closer to the first side of the gate structure 223 of the selection transistor MS. The difference in dopant concentration near the channel can affect the channel resistance of the floating gate transistor MF and the selection transistor MS, so the channel resistance of the floating gate transistor MF will be greater than the channel resistance of the selection transistor MS.

[0058] Subsequent steps for manufacturing the memory cell can be seen in Figures 2G and 2H, and the equivalent circuit is the same as in Figure 2I.

[0059] Figures 4A, 4B, and 4C schematically show a second modified example of the doping process in the manufacturing method of the first embodiment. The procedure of the doping process in this modified example follows the structure shown in Figure 2B.

[0060] Refer to Figure 4A. First, the gate structure 225 and the side of region A where the gate structure 225 is located (e.g., the left side) are covered with the mask 440 shown by the dotted line. The gate structure 223 and the regions on both sides of it are exposed. Furthermore, region B is exposed. Next, a first low-concentration doped-drain process (LDD process) is performed. As a result, n-type low-concentration doped-drain regions (n-LDD regions) 441, 442, and 443 are formed on the surface of the semiconductor substrate Sub that is not covered by the mask 440. n-LDD region 441 is formed beneath the surface of region A and is located next to one side of the gate structure 223 (e.g., the right side). n-LDD region 442 is formed beneath the surface of region A and is located next to the other side of the gate structure 223 (e.g., the left side). n-LDD region 443 is formed beneath the surface of region B and is located next to the gate structure 225.

[0061] Refer to Figure 4B. After mask 440 is removed, the gate structures 223 (and their side regions) in regions A and B are covered with mask 450, indicated by the dotted line. In other words, the regions previously covered by mask 440 are exposed. Next, a second LDD process is performed. As a result, an n-type low-concentration doped drain region (n-LDD region) 452 is formed on the surface of the semiconductor substrate Sub that is not covered by mask 450. The n-LDD region 452 is formed beneath the surface of region A and is located lateral to the side (e.g., left side) of the gate structure 225. For example, masks 440 and 450 are photoresists. In one embodiment, the dopant concentration of the n-LDD region 452 is lower than the dopant concentrations of the n-LDD regions 441, 442, and 443.

[0062] Refer to Figure 4C. After forming spacers 248 and 258, the two gate structures 223 and 225 and the two spacers 248 and 258 are used as masks to perform an n-type ion implantation process on the surface of the semiconductor substrate Sub. As a result, three n-type ion implantation regions 261, 262, and 263, indicated by the shaded lines, are formed in three sub-regions of region A that are not covered by the two gate structures 223 and 225 and the two spacers 248 and 258, and an n-type ion implantation region 264, also indicated by the shaded lines, is formed in region B that is not covered by the gate structure 225 and spacer 258.

[0063] Please refer to Figure 4C again. Next, the n-LDD region 441 and the n-type ion implantation region 261 work together to form a merged n-doped region 271. The merged n-doped region 271 is formed on the surface of the semiconductor substrate Sub and is located next to the first side of the gate structure 223. The n-LDD region 442 and the n-type ion implantation region 262 work together to form a merged n-doped region 272. The integrated n-doped region 272 is formed on the surface of the semiconductor substrate Sub and is located between the second side of the gate structure 223 and the first side of the gate structure 225. The n-LDD region 452 and the n-type ion implantation region 263 work together to form a merged n-doped region 273. The merged n-doped region 273 is formed on the surface of the semiconductor substrate Sub and is located next to the second side of the gate structure 225. The n-LDD region 443 and the n-type ion implantation region 264 work together to form a merged n-doped region 274. The merged n-doped region 274 is formed on the surface of the semiconductor substrate Sub and is located next to the extension of the gate structure 225.

[0064] Please compare the structure in Figure 2F with the structure in Figure 4C. The dopant concentration in the n-LDD region 251 to the right of the gate structure 225 in the memory cell in Figure 2F is lower than the dopant concentration in the n-LDD region 442 to the right of the gate structure 225 in the memory cell in Figure 4C. The dopant concentrations in the other n-LDD regions are the same.

[0065] Please refer to Figure 4C again. In the merged n-doped region 272, the dopant concentration is higher in the n-LDD region 442 closer to the first side of the gate structure 225 of the floating gate transistor MF. In the merged n-doped region 273, the dopant concentration is lower in the n-LDD region 452 closer to the second side of the gate structure 225 of the floating gate transistor MF. In the merged n-doped region 271, the dopant concentration is higher in the n-LDD region 441 closer to the first side of the gate structure 223 of the selection transistor MS. In the merged n-doped region 272, the dopant concentration is higher in the n-LDD region 442 closer to the first side of the gate structure 223 of the selection transistor MS. The difference in dopant concentration near the channel can affect the channel resistance of the floating gate transistor MF and the selection transistor MS, so the channel resistance of the floating gate transistor MF will be greater than the channel resistance of the selection transistor MS.

[0066] Subsequent steps for manufacturing the memory cell can be seen in Figures 2G and 2H, and the equivalent circuit is the same as in Figure 2I.

[0067] From the above explanation, by adjusting the dopant concentration of the n-LDD regions in the merged n-doped regions 271, 272, and 273, the channel resistance of the floating gate transistor MF becomes greater than the channel resistance of the selected transistor MS. The merged n-doped region 271 includes a first n-LDD region located next to the first side of the gate structure 223. The merged n-doped region 272 includes a second n-LDD region and a third n-LDD region. The second n-LDD region is located next to the second side of the gate structure 223. The third n-LDD region is located next to the first side of the gate structure 225. The merged n-doped region 273 includes a fourth n-LDD region located next to the second side of the gate structure 225.

[0068] In the example in Figure 2F, the dopant concentration in the 4th n-LDD region 252 is the same as that in the 3rd n-LDD region 251, the dopant concentration in the 2nd n-LDD region 242 is the same as that in the 1st n-LDD region 241, and the dopant concentration in the 4th n-LDD region 252 is lower than that in the 1st n-LDD region 241.

[0069] In the example shown in Figure 3C, the dopant concentration in the 4th n-LDD region 352 is the same as that of the 3rd n-LDD region 351, the dopant concentration in the 3rd n-LDD region 351 is the same as that of the 2nd n-LDD region 351, and the dopant concentration in the 4th n-LDD region 352 is lower than that of the 1st n-LDD region 341.

[0070] In the example in Figure 4C, the dopant concentration in the third n-LDD region 442 is the same as that of the second n-LDD region 442, the dopant concentration in the second n-LDD region 442 is the same as that of the first n-LDD region 441, and the dopant concentration in the fourth n-LDD region 452 is lower than that of the first n-LDD region 441.

[0071] In the embodiments described above, n-LDD regions 243, 343, 443, and 543 of region B are all formed in the first LDD process, and their dopant concentrations are relatively high. It should be noted that various modifications and changes can be made while maintaining the teachings of the present invention. For example, in another embodiment, the n-LDD regions of region B are created using two LDD processes, resulting in lower dopant concentrations. In several other embodiments, the order of the two LDD processes is changed. For example, the dopant concentration of the first LDD process is low, and the dopant concentration of the second LDD process is high.

[0072] Of course, the doping process may be further modified to achieve the concentration distributions shown in Figures 2F, 3C, or 4C. Figures 5A, 5B, and 5C schematically show a third modification of the doping process in the manufacturing method of the first embodiment. The procedure of the doping process in this modification follows the structure shown in Figure 2B.

[0073] Refer to Figure 5A. First, a first low-concentration doped-drain process (LDD process) is performed using gate structures 223 and 225 as masks. As a result, n-type low-concentration doped-drain regions (n-LDD regions) 541, 542, and 543 are formed on the surface of the semiconductor substrate Sub that is not covered by the masks. n-LDD region 541 is formed beneath the surface of the semiconductor substrate Sub and is located next to the first side of gate structure 223. n-LDD region 542 is formed beneath the surface of the semiconductor substrate Sub and is located between the second side of gate structure 223 and the first side of gate structure 225. n-LDD region 544 is formed beneath the surface of the semiconductor substrate Sub and is located next to the second side of gate structure 225. n-LDD region 543 is formed beneath the surface of region B and is located next to gate structure 225.

[0074] Refer to Figure 5B. After forming spacers 248 and 258, an n-type ion implantation process is performed on the surface of the semiconductor substrate Sub using the two gate structures 223 and 225 and the two spacers 248 and 258 as masks. As a result, three n-type ion implantation regions 261, 262, and 263, shown by the diagonal lines, are formed in three sub-regions of region A that are not covered by the two gate structures 223 and 225 and the two spacers 248 and 258, and an n-type ion implantation region 264, shown by the diagonal lines, is formed in region B that is not covered by the gate structure 225 and spacer 258.

[0075] In this embodiment, the dopant concentrations in n-LDD regions 541, 542, and 544 are the same. As mentioned above, it is preferable that the channel resistance of the floating gate transistor MF is greater than the channel resistance of the selection transistor MS. See Figure 5C. To achieve this objective, the surface of the semiconductor substrate Sub is covered with a mask 560, exposing only the gate structure 225 of region A and the regions on both sides thereof. Next, an anti-punch-through (APT) injection process is performed. As a result, two anti-punch-through (APT) regions 561 and 562 are formed. APT region 561 is in contact with n-LDD region 542. APT region 562 is in contact with n-LDD region 544. For example, the APT process is a halo injection process or a pocket injection process. Since APT regions 561 and 562 are in contact with n-LDD regions 542 and 544, respectively, high resistance and a high electric field are generated in n-LDD regions 542 and 544. As a result, the channel resistance of the floating gate transistor MF becomes greater than the channel resistance of the selection transistor MS.

[0076] After removing mask 560, the subsequent steps for manufacturing the memory cell can be seen in Figures 2G and 2H, and the equivalent circuit is the same as in Figure 2I.

[0077] In the doping process shown in Figures 5A, 5B, and 5C, the APT regions 561 and 562 are located next to the n-LDD regions 542 and 544, respectively. It should be noted that various modifications and changes can be made while maintaining the teachings of the present invention. For example, in one modification, a single APT region is in contact with the n-LDD region 544 adjacent to the second side of the gate structure 225. In another modification, a single APT region is in contact with the n-LDD region 542 adjacent to the first side of the gate structure 225. In yet another modification, three APT regions are formed. Two of the three APT regions are in contact with the n-LDD regions 542 and 544 adjacent to the two sides of the gate structure 225, respectively, and one of the three APT regions is in contact with the n-LDD region 541 adjacent to the first side of the gate structure 223. However, there are no APT regions in contact with the n-LDD region 542 adjacent to the second side of the gate structure 223. As a result, the channel resistance of the floating gate transistor MF becomes greater than the channel resistance of the selection transistor MS.

[0078] Furthermore, it should be noted that while the conductivity of the aforementioned APT region can be either n-type or p-type, p-type is preferred due to its superior performance.

[0079] In other embodiments, a p-type channel injection process is performed in the region below the gate structure 225. As a result, the channel resistance of the floating gate transistor MF increases. Figure 6 schematically shows a fourth modification of the doping process in the manufacturing method of the first embodiment. The procedure of the doping process in this modification follows the structure of Figure 2F.

[0080] By applying a p-type channel injection process to the structure in Figure 2F, a p-type channel-doped region 602 is formed. The p-type channel-doped region 602 is formed on the surface of the semiconductor substrate Sub and is located beneath the gate structure 225. Since the p-type channel-doped region 602 and the merged n-doped regions 272 and 273 have different dopant types, the channel resistance of the floating gate transistor MF can be increased. Similarly, the p-type channel injection process can be applied to the structures in Figures 3C, 4C, 5B, or 5C. As a result, the p-type channel-doped region 602 is formed on the surface of the semiconductor substrate Sub and is located beneath the gate structure 225.

[0081] Figures 7A to 7G schematically show the steps of the manufacturing method for a single-layer polynonvolatile memory cell according to the second embodiment of the present invention. Figure 7H is a schematic equivalent circuit diagram of the single-layer polynonvolatile memory cell according to the second embodiment of the present invention.

[0082] As shown in Figure 7A, a separation structure formation process is performed. First, a separation structure 702 is formed on the p-type substrate Sub. The separation structure 702 defines region A and region B. Region B is a rectangular region. Region A consists of two rectangular sub-regions A1 and A2. Next, a well region formation process is performed. A first well region (e.g., a P-well region) is formed on the surface of the semiconductor substrate Sub corresponding to region A. Furthermore, a second well region is formed on the surface of the semiconductor substrate Sub corresponding to region B. For example, the second well region is a low-concentration doped P-well region LPW, a P-well region PW, or an N-well region NW. In subsequent steps, a floating gate transistor, a selection transistor, and an assist gate region are formed in region A, and an erase gate region is formed in region B.

[0083] Next, a gate structure formation process is performed. As shown in Figure 7B, two gate oxide films 703 and 705 are formed. Then, two polysilicon gate layers 713 and 715 are formed on the two gate oxide films 703 and 705, respectively. As a result, two gate structures 723 and 725 are formed. The two gate structures 723 and 725 are formed on the surface of region A. Furthermore, region A is divided into three sub-regions by the two gate structures 723 and 725. The gate structures 723 and 725 are formed on the surface corresponding to region A1. The first sub-region is located to the left of gate structure 723. The second sub-region 723 is located between the right side of gate structure 723 and the left side of gate structure 725. The third sub-region is located to the right of gate structure 725 (including region A2). In other words, the third sub-region is an L-shaped sub-region.

[0084] Furthermore, two extension segments extend outward from the gate structure 725 through the surface of the isolation structure 702. The first extension segment of the gate structure 725 extends outward toward region B. Furthermore, a portion of region B is covered by the first extension segment of the gate structure 725. The second extension segment of the gate structure 725 extends outward toward sub-region A2. Furthermore, a portion of sub-region A2 is covered by the second extension segment of the gate structure 725. In this embodiment, the polysilicon gate layer 715 of the gate structure 725 functions as a floating gate. The polysilicon gate layer 713 of the gate structure 723 functions as a selection gate. In one embodiment, the channel length LF of the floating gate transistor is shorter than the channel length LS of the selection transistor. That is, LF <LSである。

[0085] The doping process will be explained in more detail below, with reference to the cross-sectional view along the ef line of the structure shown in Figure 7B.

[0086] Refer to Figure 7C. First, the gate structure 725 in region A and the regions on both sides of it are covered by the mask 740, shown by the dotted line. The gate structure 723 and the regions on both sides of it are exposed. Furthermore, region B is exposed. That is, only a portion of the surface between the gate structure 723 and the gate structure 725 is covered by the mask 740, and the rest of the surface between the gate structure 723 and the gate structure 725 is not covered by the mask 740. Next, the first low-concentration doped-drain process (LDD process) is performed. As a result, n-type low-concentration doped-drain regions (n-LDD regions) 741, 742, and 743 are formed on the surface of the semiconductor substrate Sub that is not covered by the mask 740. n-LDD regions 741 and 742 are formed beneath the surface of region A and are located laterally on both sides of the gate structure 723, respectively. n-LDD region 743 is formed beneath the surface of region B and is located laterally on the gate structure 725.

[0087] Refer to Figure 7D. After mask 740 is removed, the gate structures 723 (and their side regions) in regions A and B are covered with mask 750, indicated by the dotted line. In other words, the regions previously covered by mask 740 are exposed. Next, a second LDD process is performed. As a result, n-type low-concentration doped drain regions (n-LDD regions) 751 and 752 are formed on the surface of the semiconductor substrate Sub that is not covered by mask 750. The n-LDD regions 751 and 752 are formed beneath the surface of region A and are located laterally on both sides of the gate structure 725, respectively.

[0088] For example, masks 740 and 750 are photoresists. In one embodiment, the dopant concentrations in n-LDD regions 751 and 752 are smaller than the dopant concentrations in n-LDD regions 741, 742, and 743.

[0089] Refer to Figure 7E. After removing the mask 750, spacers 748 are formed on the sidewall of gate structure 723 and spacers 758 are formed on the sidewall of gate structure 725. After forming spacers 748 and 758, the two gate structures 723 and 725 and the two spacers 748 and 758 are used as masks to perform an n-type ion implantation process on the surface of semiconductor substrate Sub. As a result, three n-type ion implantation regions 761, 762 and 763, indicated by the diagonal lines, are formed in three sub-regions of region A that are not covered by the two gate structures 723 and 725 and the two spacers 748 and 758, and an n-type ion implantation region 764, indicated by the diagonal lines, is formed in region B that is not covered by gate structure 725 and spacer 758. In particular, n-type ion implantation regions 761, 762, 763, and 764 have the highest doping concentrations, and their dopant concentrations are higher than those of the n-LDD regions 741, 742, 743, 751, and 752.

[0090] Refer to Figure 7E. Next, the n-LDD region 741 and the n-type ion implantation region 761 work together to form a merged n-doped region 771. The merged n-doped region 771 is formed on the surface of the semiconductor substrate Sub and is located next to the first side of the gate structure 723. The n-LDD region 742, the n-LDD region 751, and the n-type ion implantation region 762 work together to form a merged n-doped region 772. The merged n-doped region 772 is formed on the surface of the semiconductor substrate Sub and is located between the second side of the gate structure 723 and the first side of the gate structure 775. The n-LDD region 752 and the n-type ion implantation region 763 work together to form a merged n-doped region 773. The merged n-doped region 773 is formed on the surface of the semiconductor substrate Sub and is located next to the second side of the gate structure 775. The n-type LDD region 743 and the n-type ion implantation region 764 work together to form a merged n-type doped region 774. The merged n-type doped region 774 is formed on the surface of the semiconductor substrate Sub and is located next to the extension of the gate structure 725. A bird's-eye view of the structure shown in Figure 7E is shown in Figure 7F.

[0091] In region A, the gate structure 723 and the merged n-doped regions 771 and 772 on either side work together to form a selection transistor. Furthermore, the gate structure 725 and the two merged n-doped regions 772 and 773 on either side work together to form a floating gate transistor. In this embodiment, the floating gate transistor and the selection transistor are n-type transistors and are configured within the P-well region PW. That is, the body terminals of the floating gate transistor and the body terminals of the selection transistor are connected to the P-well region PW.

[0092] The n-doped region 773 is the drain / source terminal of the floating transistor. Furthermore, the n-doped region 773 can function as an assist gate region. That is, the second extension segment of the gate structure 725 extends outward into the region lateral to the assist gate region. As a result, the assist gate region and the gate structure 725 work together to form an n-type transistor. Furthermore, the n-type transistor is connected as a MOS capacitor.

[0093] In region B, the n-type doped region 774 is the erase gate region. The first extension segment of the gate structure 725 extends outward to the region adjacent to the erase gate region. As a result, the erase gate region and the gate structure 725 work together to form an n-type transistor. Furthermore, the n-type transistor is connected as another MOS capacitor.

[0094] Please refer to Figure 7G. Once the process of forming the metal conductor wires is complete, the memory cell according to this embodiment is manufactured. Specifically, the n-type doped region 771 is connected to the source line SL, the n-type doped region 773 is connected to the bit line BL, the n-type doped region 775 is connected to the erase line EL, and the polysilicon gate layer 713 is connected to the selection gate line SG.

[0095] As shown in Figure 7H, the equivalent circuit of the memory cell according to this embodiment includes a selection transistor MS, a floating gate transistor MF, a first MOS capacitor CEG, and a second MOS capacitor CAG.

[0096] The gate terminal of the selection transistor MS is connected to the selection gate line SG. The first drain / source terminal of the selection transistor MS is connected to the source line SL. The first drain / source terminal of the floating gate transistor MF is connected to the second drain / source terminal of the selection transistor MS. The second drain / source terminal of the floating gate transistor MF is connected to the bit line BL. The first terminal of the first MOS capacitor CEG is connected to the floating gate 715 of the floating gate transistor MF. The second terminal of the first MOS capacitor CEG is connected to the erase line EL. The first terminal of the second MOS capacitor CAG is connected to the floating gate 715 of the floating gate transistor MF. The second terminal of the second MOS capacitor CAG is connected to the bit line BL.

[0097] The memory cell according to the second embodiment is composed of two transistors MS and MF and two capacitors CEG and CAG, and is therefore sometimes called a 2T2C cell.

[0098] By applying an appropriate bias voltage to the memory cell according to the second embodiment, program operation (PGM), erase operation (ERS), or read operation (Read) can be performed. In this embodiment, the memory cell does not have an assist gate line AG. Therefore, in the bias voltage table shown in Figure 2J, the bias voltage corresponding to the assist gate line AG is ignored. The operation of the memory cell according to the second embodiment is the same as that of the first embodiment, so it will not be described again here.

[0099] Please refer to Figure 7E again. In the merged n-doped region 772, the dopant concentration is lower in the n-LDD region 751, which is closer to the first side of the gate structure 725 of the floating gate transistor MF. In the merged n-doped region 773, the dopant concentration is lower in the n-LDD region 752, which is closer to the second side of the gate structure 725 of the floating gate transistor MF. In the merged n-doped region 771, the dopant concentration is higher in the n-LDD region 741, which is closer to the first side of the gate structure 723 of the selection transistor MS. In the merged n-doped region 772, the dopant concentration is higher in the n-LDD region 742, which is closer to the first side of the gate structure 723 of the selection transistor MS. The difference in dopant concentration near the channel affects the channel resistance of the floating gate transistor MF and the channel resistance of the selection transistor MS, so the channel resistance of the floating gate transistor MF is greater than the channel resistance of the selection transistor MS.

[0100] The doping process in the second embodiment can be modified by referring to a modified example of the first embodiment. Specifically, the first modified example in Figures 3A, 3B, and 3C, the second modified example in Figures 4A, 4B, and 4C, the third modified example in Figures 5A, 5B, and 5C, or the fourth modified example in Figure 6 can be applied to the memory cell according to the second embodiment. By using these modified examples, the channel resistance of the floating gate transistor MF becomes greater than the channel resistance of the selection transistor MS.

[0101] In the embodiments described above, the floating gate transistor MF and the selection transistor MS of the memory cell are n-type transistors. That is, the LDD region is an n-type LDD region, and the ion implantation region is an n-type ion implantation region. It should be noted that various modifications and changes are possible while maintaining the teachings of the present invention. For example, in another embodiment, the floating gate transistor MF and the selection transistor MS of the memory cell are p-type transistors. That is, the LDD region is a p-type LDD region, and the ion implantation region is a p-type ion implantation region. Furthermore, the p-type LDD region and the p-type ion implantation region are formed within the N-well region. Similarly, the MOS transistors CMOS, CEG, and CAG are p-type transistors.

[0102] From the above description, the present invention provides an eraseable programmable single-layer polynonvolatile memory cell. In the embodiments described above, the memory cell is a 2T2C cell. Of course, the inventive concept of the present invention can also be applied to a 2T1C cell. For example, in the example of Figure 2I, a memory cell without plate capacitors CP1, CP2, and CP3 can be considered a 2T1C cell. Similarly, in the example of Figure 7H, a memory cell without MOS capacitor CAG can be considered a 2T1C cell.

[0103] While the present invention has described embodiments that are currently considered most practical and preferred, it should be understood that the present invention is not limited to the disclosed embodiments. On the contrary, it is intended to include various modifications and similar configurations that fall within the spirit and scope of the appended claims, and the claims should be interpreted most broadly to encompass all such modifications and similar configurations.

Claims

1. A separation structure formed on a semiconductor substrate, the separation structure dividing the surface of the semiconductor substrate into a first region and a second region, A first well region formed on the surface of the semiconductor substrate corresponding to the first region, A second well region formed on the surface of the semiconductor substrate corresponding to the second region, A first gate structure and a second gate structure formed on the surface of the semiconductor substrate corresponding to the first region, wherein the first gate structure and the second gate structure divide the region on the surface of the semiconductor substrate corresponding to the first region into a first merge-doped region, a second merge-doped region, and a third merge-doped region, A fourth merge-doped region is formed on the surface of the semiconductor substrate corresponding to the second region and is located lateral to the side of the second gate structure, It has, The first merge-doped region is located next to the first side of the first gate structure, the second merge-doped region is located between the second side of the first gate structure and the first side of the second gate structure, and the third merge-doped region is located next to the second side of the second gate structure. The second gate structure extends outward through the surface of the separation structure toward the second region, and a portion of the second region is covered by the second gate structure. The first merge-doped region, the first gate structure, and the second merge-doped region are formed together as a selection transistor; the second merge-doped region, the second gate structure, and the third merge-doped region are formed together as a floating-gate transistor; the second gate structure and the fourth merge-doped region are formed together as a first MOS capacitor; the channel resistance of the floating-gate transistor is greater than the channel resistance of the selection transistor. The second gate structure includes an extension portion that extends through the surface of the separation structure toward the third merge-doped region, and the extension portion of the second gate structure and the third merge-doped region work together to form a second MOS capacitor, the first gate structure is connected to the selection gate line, the first merge-doped region is connected to the source line, the third merge-doped region is connected to the bit line, and the fourth merge-doped region is connected to the erase line. Erasable program single-layer poly non-volatile memory cell.

2. The first merge-doped region includes a first ion implantation region and a first low-concentration doped drain region; the second merge-doped region includes a second ion implantation region, a second low-concentration doped drain region and a third low-concentration doped drain region; the third merge-doped region includes a third ion implantation region and a fourth low-concentration doped drain region; the first low-concentration doped drain region is located lateral to the first side of the first gate structure; the second low-concentration doped drain region is located lateral to the second side of the first gate structure; the third low-concentration doped drain region is located lateral to the first side of the second gate structure; and the fourth low-concentration doped drain region is located lateral to the second side of the first gate structure. The eraseable programmable single-layer polynonvolatile memory cell according to claim 1.

3. The dopant concentration in the first low-concentration doped drain region is the same as the dopant concentration in the second low-concentration doped drain region, the dopant concentration in the third low-concentration doped drain region is the same as the dopant concentration in the fourth low-concentration doped drain region, and the dopant concentration in the fourth low-concentration doped drain region is lower than the dopant concentration in the first low-concentration doped drain region. The eraseable programmable single-layer polynonvolatile memory cell according to claim 2.

4. The dopant concentrations in the fourth low-concentration doped drain region, the third low-concentration doped drain region, and the second low-concentration doped drain region are the same, and the dopant concentration in the fourth low-concentration doped drain region is lower than the dopant concentration in the first low-concentration doped drain region. The eraseable programmable single-layer polynonvolatile memory cell according to claim 2.

5. The dopant concentrations in the first low-concentration doped drain region, the second low-concentration doped drain region, and the third low-concentration doped drain region are the same, and the dopant concentration in the fourth low-concentration doped drain region is lower than the dopant concentration in the first low-concentration doped drain region. The eraseable programmable single-layer polynonvolatile memory cell according to claim 2.

6. The system further comprises a first anti-punch-through injection region, the first anti-punch-through injection region being in contact with the fourth low-concentration doped drain region. The eraseable programmable single-layer polynonvolatile memory cell according to claim 2.

7. The system further comprises a first anti-punch-through injection region, the first anti-punch-through injection region being in contact with the third low-concentration doped drain region. The eraseable programmable single-layer polynonvolatile memory cell according to claim 2.

8. The device further comprises a first anti-punch-through injection region and a second anti-punch-through injection region, wherein the first anti-punch-through injection region is in contact with the fourth low-concentration doped drain region, and the second anti-punch-through injection region is in contact with the third low-concentration doped drain region. The eraseable programmable single-layer polynonvolatile memory cell according to claim 2.

9. The invention further comprises a first anti-punch-through injection region, a second anti-punch-through injection region, and a third anti-punch-through injection region, wherein the first anti-punch-through injection region is in contact with the fourth low-concentration doped drain region, the second anti-punch-through injection region is in contact with the third low-concentration doped drain region, and the third anti-punch-through injection region is in contact with the second low-concentration doped drain region. The eraseable programmable single-layer polynonvolatile memory cell according to claim 2.

10. The invention further comprises a first anti-punch-through injection region, a second anti-punch-through injection region, and a third anti-punch-through injection region, wherein the first anti-punch-through injection region is in contact with the fourth low-concentration doped drain region, the second anti-punch-through injection region is in contact with the third low-concentration doped drain region, and the third anti-punch-through injection region is in contact with the first low-concentration doped drain region. The eraseable programmable single-layer polynonvolatile memory cell according to claim 2.

11. The system further comprises a channel-doped region, the channel-doped region being formed on the surface of the semiconductor substrate and positioned beneath the second gate structure, and the channel-doped region and the second merge-doped region having different dopant types. The eraseable programmable single-layer polynonvolatile memory cell according to claim 2.

12. The present invention further comprises a third gate structure, the third gate structure being formed on the separation structure and positioned lateral to the first side of the second gate structure, and the third gate structure and the second gate structure working together to form a first poly / polyplate capacitor. The eraseable programmable single-layer polynonvolatile memory cell according to claim 1.

13. The present invention further comprises a fourth gate structure, the fourth gate structure being formed on the separation structure and positioned lateral to the second side of the second gate structure, the fourth gate structure and the second gate structure working together to form a second poly / polyplate capacitor, and the second poly / polyplate capacitor and the first poly / polyplate capacitor being connected in parallel with each other. The eraseable programmable single-layer polynonvolatile memory cell according to claim 12.

14. The structure further comprises a metal layer, the metal layer being formed on the second gate structure, the metal layer and the second gate structure working together to form a metal / polyplate capacitor, and the metal / polyplate capacitor and the first poly / polyplate capacitor being connected in parallel to each other. The eraseable programmable single-layer polynonvolatile memory cell according to claim 12.

15. The third gate structure is connected to the assist gate line. The eraseable programmable single-layer polynonvolatile memory cell according to claim 12.

16. When the program operation is executed, a ground voltage is applied to the source line, a program voltage is applied to the selection gate line, the program voltage is applied to the bit line, a first voltage in the range between the ground voltage and the erase voltage is applied to the erase line, a second voltage in the range between the ground voltage and the assist gate voltage is applied to the assist gate line, the assist gate voltage is higher than the erase voltage, the erase voltage is higher than the program voltage, and the program voltage is higher than the ground voltage. The eraseable programmable single-layer polynonvolatile memory cell according to claim 15.

17. When the erase operation is performed, the source line is subjected to a ground voltage, the selection gate line is subjected to the ground voltage, the bit line is subjected to the ground voltage, the erase line is subjected to an erase voltage, the assist gate line is subjected to a voltage in the range between a negative assist gate voltage and the ground voltage, the assist gate voltage is higher than the erase voltage, and the erase voltage is higher than the ground voltage. The eraseable programmable single-layer polynonvolatile memory cell according to claim 15.

18. When a read operation is performed, the source line is subjected to a ground voltage, the selection gate line is subjected to a read voltage, the bit line is subjected to the read voltage, the erase line is subjected to the ground voltage, the assist gate line is subjected to a voltage in the range between a negative assist gate voltage and a positive assist gate voltage, the assist gate voltage is higher than the read voltage, and the read voltage is higher than the ground voltage. The eraseable programmable single-layer polynonvolatile memory cell according to claim 15.

19. The channel length of the floating gate transistor is shorter than the channel length of the selection transistor. The eraseable programmable single-layer polynonvolatile memory cell according to claim 1.

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