Power converter

Abstract

To provide a power converter to achieve high-speed drive while loss is suppressed when a switching element is driven in an MHz band.SOLUTION: A power converter 10 includes a semiconductor switch M1 whose resonance frequency determined based on gate capacitances Cgd and Cgs and parasitic inductance Lg existing in a gate loop is configured to be 100 MHz or less. A gate drive part 12 outputs gate voltage obtained by superimposing voltage of an odd-order frequency of three or more of a fundamental frequency on voltage of the fundamental frequency. The gate drive part 12 adjusts the odd-order frequency so as to be different from the resonance frequency of the gate loop of the semiconductor switch M1, and shifts a phase of the voltage of the odd-order frequency from the phase of the voltage of the fundamental frequency by a predetermined amount, superimposes the voltage amplified by class E amplifiers 22 and 25 thereon and outputs it to the semiconductor switch M1.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] This invention relates to a power converter. [Background technology]

[0002] MHz-band high-frequency power supplies are widely used in applications such as induction heating, plasma processes, and contactless power supply, and there is a high demand for high efficiency and high output in these applications. To meet these needs, MHz-band high-frequency power supplies can be made more efficient and powerful by using high-voltage and high-current capacity SiC elements in a resonant inverter and driving the SiC elements at high speed.

[0003] High-voltage and high-current SiC-MOSFETs have input capacitance characteristics of several nF or more. Furthermore, their packages often have a reactance component of around 10-20 nH that leaks around the gate. When a typical square wave voltage is applied to the gate for high-speed driving of a SiC-MOSFET, resonance may occur due to the reactance component leaking around the gate and the gate input capacitance. In this case, peaking exceeding the gate breakdown voltage occurs in the gate voltage waveform, raising concerns about reduced reliability of the device.

[0004] Patent Document 1 proposes a method to suppress ringing caused by LC resonance due to parasitic capacitance of the switching element by reducing the rate of change of the drive signal immediately after the start and immediately before the completion of the ON operation transition time using an ON speed reduction unit. However, the drive signal generation circuit described in Patent Document 1 employs a hard-switching bush-pull circuit, which results in large losses when driving the switching element in the MHz band.

[0005] On the other hand, Non-Patent Document 1 shows that a steep off-waveform can be obtained by superimposing a sinusoidal gate voltage and its third harmonic onto the SW element of a Class E amplifier. However, there is no specific description of the means for generating the sinusoidal wave or the phase difference between the fundamental wave and the harmonics. Furthermore, although it is thought that a steep off-waveform can be obtained by applying the phase difference shown in the diagram, the peak value of the wave decreases in the latter half of the conduction period, raising concerns about increased conduction loss.

[0006] Furthermore, while peaking can be prevented in principle by changing the gate voltage to a sinusoidal shape, a steep gate voltage off characteristic cannot be obtained, making high-speed driving impossible and increasing switching losses. In addition, the gate voltage also decreases during the conduction period, raising concerns about increased conduction losses. Here, high-speed driving refers to shortening the transition time from on to off and off to on.

[0007] Non-patent document 2 describes a gate driving method in which a sine wave with an amplitude greater than the gate voltage amplitude allowed by the SiC-MOSFET is generated using a Class E amplifier, and then the voltage is clamped by a diode to reduce it to a gate voltage amplitude below the gate voltage amplitude allowed by the SiC. However, this method has the problem of generating losses in the clamping diode. [Prior art documents] [Patent Documents]

[0008] [Patent Document 1] International Publication No. 2013 / 065150 (Japanese Patent Application No. 2013-541543) [Non-patent literature]

[0009] [Non-Patent Document 1] Shuto et al., Peaking of the Gate Drive Signal of a Class E Amplifier by the Third Harmonic, 2010 Joint Conference of Electrical Engineering Societies, Kyushu Branch [Non-Patent Document 2] Son et al., 3. A Study on a High-Speed ​​SiC-MOSFET Drive Circuit Based on a Class E Amplifier, IEICE Technical Report: IEICE Technical Report 116(133), 43-49, 2016-07-14. [Overview of the project] [Problems that the invention aims to solve]

[0010] The object of the present invention is to provide a power converter that enables high-speed driving while suppressing losses when driving switching elements in the MHz band. [Means for solving the problem]

[0011] According to the invention described in claim 1, the main power conversion unit is configured such that the resonant frequency, determined based on the gate capacitance and the inductance present in the gate loop, is 100 MHz or less. Parasitic components due to the gate capacitance and inductance exist in the gate. The device includes a switching element, which is driven by a fundamental frequency of 1 MHz or higher to produce a power output. The gate drive unit outputs a gate voltage obtained by superimposing a voltage of the fundamental frequency with a voltage of an odd-order frequency of three or more than the fundamental frequency. The odd-order frequencies are set to be different from the resonant frequencies of the gate loop of the switching element in the main power conversion unit. The gate drive unit, The system comprises a first Class E amplifier that amplifies the fundamental frequency voltage in Class E, and a second Class E amplifier that amplifies the odd-order frequency voltage in Class E. The first and second Class E amplifiers are configured to operate using a common DC power supply voltage. The gate drive unit is: The phase of the odd-order frequency voltage is shifted by a predetermined amount from the phase of the fundamental frequency voltage so that the phase of the fundamental frequency and the odd-order frequency sinusoidal voltage are matched at the gate position of the switching element. First Class E amplifier and second Class E amplifier The amplified voltage is superimposed and output to the switching element. The multiplexing circuit combines the outputs of the first Class E amplifier and the second Class E amplifier. The first matching circuit is located at the output of the first Class E amplifier and makes the reactance component of the impedance seen from the multiplexing circuit towards the gate terminal side of the switching element of the main power conversion section zero or capacitive. The second matching circuit is located at the output of the second Class E amplifier and makes the reactance component of the impedance seen from the multiplexing circuit towards the gate terminal side of the switching element of the main power conversion section zero or capacitive. Furthermore, the input impedances of the first and second matching circuits are set to satisfy the condition that the DC power supply voltage, which is commonly input to the first and second Class E amplifiers, provides a desired voltage amplitude to the gate of the semiconductor switch, based on the circuit configuration and parasitic components of the first and second matching circuits. In addition, the load resistances of the first and second Class E amplifiers are set to a value equal to the input impedance as seen from the input side of the first and second matching circuits, respectively, and are set to the condition that the imaginary part of the input impedance of the first and second matching circuits is zero.

[0012] According to the invention described in claim 1, The phase of the fundamental frequency and the odd-order frequency sinusoidal voltages is matched at the gate position of the switching element. By applying a gate voltage to a switching element with the phase of the odd-order frequency voltage shifted by a predetermined amount compared to the phase of the fundamental frequency voltage, the inductance and gate capacitance of the gate loop affect the phase of the fundamental frequency voltage and the odd-order frequency voltage at the gate position of the switching element. This allows for a steeper adjustment of the gate voltage by adjusting the odd-order frequency voltage. As a result, high-speed operation is possible while suppressing losses in the switching element. [Brief explanation of the drawing]

[0013] [Figure 1] Electrical configuration block diagram of the power converter in the first embodiment [Figure 2] Electrical configuration block diagram of the gate drive unit [Figure 3]Examples of electrical configurations for phase adjustment circuits and BPF (bandpass filters) [Figure 4] Electrical configuration examples of amplifiers, matching circuits, multiplexing circuits, and their peripheral circuits. [Figure 5] Diagram explaining the technical significance [Figure 6] Drain current-gate voltage characteristic diagram of a switching element [Figure 7] Electrical configuration example of amplifier, matching circuit, multiplexing circuit, and peripheral circuit in the second embodiment [Modes for carrying out the invention]

[0014] Several embodiments of the power converter 10 will be described below with reference to the drawings. Components identical across multiple embodiments will be denoted by the same reference numerals, and in some embodiments described later, their descriptions may be omitted.

[0015] (First Embodiment) The first embodiment will be described with reference to Figures 1 to 6. As shown in Figure 1, the power converter 10 includes a main power conversion unit 11 that mainly converts power using a SiC power card 13, and a gate drive unit 12 that drives the gate terminals of the SiC power card 13, and a DC voltage V DC Input power and convert it to load R L This is a high-frequency power supply that outputs power.

[0016] The main power conversion unit 11 is equipped with a SiC power card 13. The SiC power card 13 incorporates a SiC power semiconductor switch M1 (hereinafter referred to as semiconductor switch M1) with a body diode. The semiconductor switch M1 is a switching element made of, for example, a SiC-MOSFET. The SiC power card 13 employs a structure in which heat sinks are soldered to both sides of the semiconductor package of the semiconductor switch M1, allowing the heat generated when the semiconductor switch M1 operates to be efficiently dissipated to the cooler, thus achieving both high power and miniaturization. The semiconductor switch M1 of the SiC power card 13 has a gate capacitance C as a parasitic capacitance between its gate terminal and the drain / source terminals.gd , C gs is generated.

[0017] Also, a gate terminal is provided on the SiC power card 13. Between the gate terminal of the SiC power card 13 and the gate of the semiconductor switch M1 in the package of the SiC power card 13, there is parasitic inductance L due to a lead frame or bonding wire g , gate parasitic resistance R g exists. The SiC power card 13 is a power semiconductor module configured such that the resonance frequency f0 determined based on the gate capacitance C gd , C gs and the parasitic inductance L g is about several tens of MHz or less with 100 MHz or less.

[0018] For example, when a rectangular voltage of a fundamental frequency (for example, 6.78 MHz) is applied to the gate terminal of the SiC power card 13, a large resonance voltage peak occurs in the gate loop, and an excessive voltage stress is applied to the gate of the semiconductor switch M1. Therefore, in this embodiment, the configuration of the gate drive unit 12 is used to apply the voltage of the fundamental frequency and the odd-order frequencies (for example, third and fifth frequencies) that become harmonics. The gate drive unit 12 drives the SiC power card 13 with a fundamental frequency of 1 MHz or more to output power to the load R L .

[0019] Hereinafter, a circuit configuration example of the main power conversion unit 11 will be described with reference to FIG. 1. The DC voltage source 100 is applied to the node N1 through the choke coil Lc. Between the node N1 and the ground node Ng, the drain-source terminals of the semiconductor switch M1 are connected. A capacitor Cp is configured between the node N1 and the ground node Ng. Therefore, the capacitor Cp is connected in parallel between the drain-source terminals of the semiconductor switch M1.

[0020] Between the node N1 and the output terminal T1 to the load R L , an inductor Ls and a capacitor Cs are connected in series. The load R LThis is connected between the output terminal T1 and the ground node Ng. The main power conversion unit 11 is configured in this way.

[0021] On the other hand, the gate drive unit 12 includes a plurality of AC voltage sources 14a to 14c and a multiplexing circuit 15. The plurality of AC voltage sources 14a to 14c are illustrated as voltage sources that output an AC voltage of the fundamental frequency and AC voltages of odd-order frequencies of three or more than this fundamental frequency. The multiplexing circuit 15 combines the output voltages of these plurality of AC voltage sources 14a to 14c and applies them to the SiC power card 13 as a gate voltage Vg.

[0022] Figure 2 illustrates the configuration of the gate drive unit 12. The gate drive unit 12, together with the square wave oscillator 20, includes Class E amplifiers 22 and 25 as amplifiers that amplify the voltages of the fundamental frequency and odd-order frequencies, and outputs a desired gate voltage Vg by processing the output voltage of the square wave oscillator 20.

[0023] The gate drive unit 12 performs a third-harmonic superimposed gate drive by superimposing a fundamental frequency sinusoidal voltage and a third-frequency sinusoidal voltage, and outputs the gate-source voltage vgs of the semiconductor switch M1 to be between -5V and 20V. In this way, high-speed switching can be achieved without causing the gate loop to resonate, that is, without applying excessive voltage stress to the gate terminal of the SiC power card 13.

[0024] The square wave oscillator 20 generates and outputs a square wave pulse voltage with a predetermined fundamental frequency (e.g., 6.78 MHz). At this time, for example, the third frequency included in the square wave pulse and the resonant frequency f0 of the gate loop of the SiC power card 13 are different from each other. setting It will be done.

[0025] The gate drive unit 12 includes multiple gate voltage generation units 16 and 17 to output voltages of the fundamental frequency and third frequency. The gate voltage generation unit 16 is provided to output an AC voltage of the fundamental frequency and is configured by connecting a phase adjustment circuit 21, a Class E amplifier 22, and a matching circuit 23 in cascaded order, and outputs the generated AC voltage of the fundamental frequency to the multiplexing circuit 15. The gate voltage generation unit 16 generates a sinusoidal voltage of the fundamental frequency using the Class E amplifier 22.

[0026] The phase adjustment circuit 21 is provided to create a phase difference between the output voltages of the gate voltage generation units 16 and 17. It advances the fundamental frequency voltage generated by the gate voltage generation unit 16 relative to the third frequency generated by the gate voltage generation unit 17 and outputs it to the Class E amplifier 22. The Class E amplifier 22 is a Class E amplifier that amplifies the fundamental frequency voltage and outputs it to the multiplexing circuit 15 through the matching circuit 23. The matching circuit 23 is a circuit that impedance matches the output impedance of the Class E amplifier 22 with the input impedance of the SiC power card 13.

[0027] On the other hand, the gate voltage generation unit 17 is provided to output an odd-order frequency AC voltage and is configured by connecting the BPF 24, the Class E amplifier 25, and the matching circuit 26 in cascade, and outputs the generated odd-order frequency AC voltage to the multiplexing circuit 15. The gate voltage generation unit 17 uses the Class E amplifier 25 to generate a third-order frequency sinusoidal voltage.

[0028] BPF24 is a bandpass filter that passes the third frequency of the fundamental frequency included in the square wave from the square wave oscillator 20 (e.g., 6.78 MHz), while attenuating the fundamental frequency and signals of the fifth order and above of this fundamental frequency. The Class E amplifier 25 is a Class E amplifier that amplifies the voltage at the third frequency of the fundamental frequency and outputs it to the multiplexer 15 through the matching circuit 26. The matching circuit 26 is a circuit that matches the output impedance of the Class E amplifier 25 with the input impedance of the SiC power card 13. These phase adjustment circuits 21, Class E amplifiers 22, matching circuits 23, BPFs 24, Class E amplifiers 25, and matching circuits 26 represent configurations equivalent to the aforementioned multiple AC voltage sources 14a to 14c. The multiplexing circuit 15 combines the output voltages of multiple Class E amplifiers 22 and 25 (equivalent to multiple amplifiers) that amplify the fundamental frequency and odd-order frequency voltages, and applies the gate voltage Vg to the SiC power card 13.

[0029] This gate drive unit 12 connects multiple gate voltage generation units 16 and 17 in parallel, and the gate voltage generation unit 16 is equipped with a phase adjustment circuit 21. As a result, it can output voltage to the multiplexing circuit 15 with the phase of odd-order frequency voltages delayed compared to the phase of the fundamental frequency voltage. The multiplexing circuit 15 then combines and superimposes the odd-order frequency voltages with the phase of odd-order frequency voltages delayed compared to the phase of the fundamental frequency voltage and outputs the gate voltage Vg to the SiC power card 13. Consequently, the gate drive unit 12 can superimpose and output a third-order signal voltage as an odd-order frequency on the fundamental frequency signal voltage.

[0030] Next, the specific circuit configuration will be explained with reference to Figures 3 and 4. Figure 3 shows an example of the circuit configuration of the phase adjustment circuit 21 and the BPF 24, and Figure 4 shows an example of the circuit configuration of the Class E amplifiers 22 and 25, the matching circuits 23 and 26, and the subsequent stage.

[0031] As illustrated in Figure 3, the phase adjustment circuit 21 is composed of an integrator 31, a resistor voltage divider circuit 32 formed by connecting resistors Ra and Rb in series, a D flip-flop 33, and other peripheral circuits 34. The integrator 31 receives a square wave output by the square wave oscillator 20 as input, and slows down the voltage waveform by lagging the voltage phase according to a predetermined time constant, and a DC blocking capacitor C b1 This is used to input the clock terminal CLK of the D flip-flop 33.

[0032] The D flip-flop 33 is configured by pulling up its D terminal to the power supply Vcc. The D flip-flop 33 is also configured by connecting a resistor voltage divider circuit 32 to the clock terminal CLK, which divides the power supply Vcc. Furthermore, peripheral circuits 34 are connected to the / Q and / CLR terminals of the D flip-flop 33. Peripheral circuits 34 are configured by combining resistors Rx1 and Rx2, diode Da, and capacitor Cx, etc., as shown in the diagram.

[0033] The D flip-flop 33 outputs a square wave voltage from its Q terminal in synchronization with the input voltage of the clock terminal CLK. The integrator 31 blunts the square wave voltage output by the square wave oscillator 20, and this shaped voltage is input to the clock terminal CLK. Furthermore, the D flip-flop 33 can adjust the rising edge timing of its Q terminal to either the leading or lagging side by adjusting the bias of its input voltage CLK using the resistor voltage divider circuit 32. As a result, the phase adjustment circuit 21 can output the phase-adjusted result based on the integration result from the integrator 31.

[0034] Furthermore, the output of the square wave oscillator 20 is connected to the buffer gate 35 and capacitor C. b2 and resistor R y It is input to BPF24 through a series circuit. BPF24 is connected to capacitor C j1 ~C j5 , inductor L j1 ~L j4 , and resistor R j3 This is an LCR filter circuit formed by combining the components as shown in the diagram. In this embodiment, the third frequency of the fundamental frequency is passed through, while the first and fifth and higher frequencies are attenuated. The phase adjustment circuit 21 is provided to adjust the phase of the fundamental wave, so that the relationship between the phase of the voltage at the fundamental frequency and the phase of the voltage at odd-numbered frequencies can be changed.

[0035] Furthermore, a DC blocking capacitor C is placed after the BPF24. b1 A bias circuit B1 is provided via [a certain route]. The bias circuit B1 has a bias voltage V b The variable resistor R bThe divided voltage is then passed through the MOS transistor M of the Class E amplifier 25. p2 Apply to the gate (see below).

[0036] As shown in Figure 4, Class E amplifiers 22 and 25 use a common DC power supply voltage V d It operates using the following. The Class E amplifier 22 uses a choke coil L c1 MOS transistor M p1 , Capacitor C p1 , inductor L for resonance s1 , and capacitor C s1 It is provided in the illustrated form.

[0037] DC power supply voltage V d This is a choke coil L c1 Through node N 11 It is applied to node N. 11 and Grand Node N g Between them is a MOS transistor M p1 The drain and source are connected. Node N 11 and Grand Node N g Capacitor C is between them. p1 It is composed of.

[0038] Therefore, capacitor C p1 is a MOS transistor M p1 It is connected in parallel between the drain and source of node N. 11 And the input node N of the matching circuit 23 12 Between them is an inductor L s1 and capacitor C s1 The two are connected in series. Element C that constitutes the Class E amplifier 22 p1 , L s1 , C s1 The component values ​​are designed to match the fundamental frequency.

[0039] Matching circuit 23 is located at node N 12 and Grand Node N g Capacitor C connected between m1 and node N 12 and the input node N of the multiplexing circuit 1513 Capacitor C connected between ms The matching circuit 23 is configured between the output of the Class E amplifier 22 and the input of the multiplexing circuit 15, and has the characteristic of making the reactance component of the impedance viewed from the output side of the Class E amplifier 22 to the gate terminal side of the SiC power card 13 zero or capacitive. This enables Class E operation or pseudo-Class E operation of the Class E amplifier 22.

[0040] On the other hand, the Class E amplifier 25 has a choke coil L c2 MOS transistor M p2 , Capacitor C p2 , inductor L for resonance s2 , and capacitor C s2 It is constructed by connecting the components in the illustrated configuration, and its circuit configuration is identical to that of the Class E amplifier 22.

[0041] DC power supply voltage V d This is a choke coil L c2 Through node N 21 It is applied to node N. 21 and Grand Node N g Between them is a MOS transistor M p2 The drain and source are connected. Node N 21 and Grand Node N g Capacitor C is between them. p2 It is composed of.

[0042] Therefore, capacitor C p2 is a MOS transistor M p2 It is connected in parallel between the drain and source of node N. 21 and the input node N of the matching circuit 26 22 Between them is an inductor L s2 and capacitor C s2 The two are connected in series. Element C constitutes the Class E amplifier 25. p2 , L s2 , C s2 Each element value is designed to match the third frequency of the fundamental frequency.

[0043] Matching circuit 26 is located at node N 22 and Grand Node N g Capacitor C connected between m2 and node N 22 and the input node N of the multiplexing circuit 15 23 The circuit includes an inductor Lm connected between the two components. The matching circuit 26 is located at the output of the Class E amplifier 25 and has the characteristic of making the reactance component of the impedance viewed from the output side of the Class E amplifier 22 to the gate terminal side of the SiC power card 13 zero or capacitive. This enables Class E operation or pseudo-Class E operation of the Class E amplifier 25.

[0044] The multiplexing circuit 15 includes, in the illustrated configuration, a parallel resonant circuit 15a consisting of an inductor L1 and a capacitor C1, and a parallel resonant circuit 15b consisting of an inductor L2 and a capacitor C2. The parallel resonant circuit 15a has node N 13 and node N o It is connected between and and the parallel resonant circuit 15b is at node N 23 and node N o A capacitor C3 is connected in series between them.

[0045] The multiplexing circuit 15 is designed so that the impedance of the Class E amplifier 25 at odd-order frequencies can be considered as open-circuited at the output of the Class E amplifier 22, with the element values ​​of the parallel resonant circuits 15a and 15b being designed so that the impedance of the Class E amplifier 22 at the fundamental frequency can be considered as open-circuited at the output of the Class E amplifier 25.

[0046] In other words, the parallel resonant circuit 15a is designed to pass the fundamental frequency but block odd-order frequencies, while the parallel resonant circuit 15b is designed to pass odd-order frequencies (third-order frequencies in this configuration) but block the fundamental frequency.

[0047] For example, the parallel resonance circuit 15a on the side of the class-E amplifier 22 is set with element values so as to satisfy the resonance condition at the third harmonic frequency which is the operating frequency of the class-E amplifier 25, and the parallel resonance circuit 15b on the side of the class-E amplifier 25 is set with element values so as to satisfy the resonance condition at the fundamental frequency which is the operating frequency of the class-E amplifier 22. Thereby, the class-E amplifiers 22 and 25 can operate without mutual interference, and the multiplexing circuit 15 can synthesize the outputs of the fundamental frequency and odd harmonic frequencies of each of the class-E amplifiers 22 and 25.

[0048] Also, a bias circuit B2 is configured at the subsequent stage of the multiplexing circuit 15. The bias circuit B2 applies a divided voltage obtained by dividing the bias voltage V b by the variable resistor R b to the gate terminal of the SiC power card 13. Further, the capacitors C3 and C4 are connected between the output of the multiplexing circuit 15 and the gate terminal of the SiC power card 13. The capacitors C3 and C4 are capacitors that block the bias voltage of the bias circuit B2 to the multiplexing circuit 15 and the class-E amplifiers 22 and 25 sides.

[0049] Next, a method for setting each element value will be described. The design of the element values of the class-E amplifiers 22 and 25 and the matching circuits 23 and 26 is performed in consideration of the parasitic components of the SiC power card 13 such that the fundamental wave amplitude: 13.26 V and the third harmonic amplitude: 4.42 V corresponding to the voltage swing width of the voltage between the gate and source of the semiconductor switch M1, i.e., 25 V, are applied to the gate of the semiconductor switch M1.

[0050] When the real part of the impedance seen from the gate terminal of the SiC power card 13 on the side of the matching circuits 23 and 26 is defined as the load resistance value, it is desirable to set the load Q value depending on the load resistance value to 3 or less for the class-E amplifiers 22 and 25. The load Q value can be arbitrarily determined by the designer based on the semiconductor design of the SiC power card 13. The characteristics of the class-E amplifiers 22 and 25 are determined by the inductors L s1 , L s2 and the capacitors C s1 , C s2It is uniquely determined by the load resistance value and load Q value on the output side when operating the resonant circuit according to

[0051] Also, the internal parasitic capacitance of the SiC power card 13 varies according to the drain voltage applied to the semiconductor switch M1. Therefore, the input impedance seen from the gate terminal side of the SiC power card 13 also varies due to the change in the drain voltage of the semiconductor switch M1. This means that the load impedance of the class-E amplifiers 22 and 25 varies. Therefore, by setting the load Q value depending on the load resistance value to 3 or less, the influence of the load impedance change on the operation of the class-E amplifiers 22 and 25 is reduced. That is, by setting the load Q value to 3 or less, it is possible to ensure the operation stability of the class-E amplifiers 22 and 25 against the characteristic variations of the parasitic capacitance of the SiC power card 13 and the drain voltage dependency.

[0052] Also, the resonance frequency f0 of the gate loop and the third harmonic frequency are offset by at least f0 / (2 × load Q value of the gate loop) or more, and the inductance L g , the gate parasitic resistance R g and the gate capacitance C gd , C gs are preferably set such that the relationship is established. By setting it in this way, it is possible to ensure the overall operation stability without causing a resonance phenomenon due to the parasitic components of the gate loop.

[0053] <Element value setting method> The class-E amplifiers 22 and 25 can be determined to have a predetermined relationship between the DC power supply voltage Vd and the amplitude of the output voltage Vo under the class-E operation conditions using mathematical formulas and the like. Also, the gate voltage Vg of the semiconductor switch M1 of the SiC power card 13 is affected by the element values of the matching circuits 23 and 26 and the parasitic components of the SiC power card 13 in relation to the output voltage Vo of the class-E amplifiers 22 and 25. Based on the circuit configurations of the matching circuits 23 and 26 and the parasitic components of the SiC power card 13, any DC power supply voltage V of the class-E amplifiers 22 and 25 dFrom this, the input impedances of matching circuits 23 and 26 required to provide the desired voltage amplitude to the gate of semiconductor switch M1 can be determined.

[0054] The load resistance Ro of the Class E amplifiers 22 and 25 is equal to the input impedance of the matching circuits 23 and 26 as seen from the input side. By using the condition that the imaginary part of the input impedance of the matching circuits 23 and 26 is zero, the input impedance of the matching circuits 23 and 26 and the load resistance Ro can be determined. The inductors L that make up the matching circuits 23 and 26 are then determined according to this load resistance Ro. m , Capacitor C m1 , C ms , C m2 Each element value, and the inductor L that constitutes the Class E amplifiers 22 and 25. s1 , L s2 , Capacitor C s1 , C s2 , C p1 , C p2 The values ​​of each element can be set.

[0055] By setting the element values ​​in this way, the common DC power supply voltage V d Even when using this to operate the Class E amplifiers 22 and 25, it becomes possible to adjust their combined output so that it stays within the gate breakdown voltage of the semiconductor switch M1.

[0056] Next, we will explain the technical significance and effects of the above configuration. Between the gate terminal of the SiC power card 13 and the gate of the semiconductor switch M1 within the package of the SiC power card 13, there is a parasitic inductance L due to the lead frame and bonding wires. g It exists.

[0057] Parasitic inductance L g When this effect occurs, the gate voltage of semiconductor switch M1 leads the phase of the voltage at the gate terminal of SiC power card 13. In particular, at odd multiples frequencies higher than the fundamental frequency, the reactance due to the parasitic inductor Ls becomes large, and the waveform of the voltage applied to the gate of semiconductor switch M1 is distorted.

[0058] Therefore, in this configuration, the phase of the odd-order frequency sinusoidal voltage is delayed compared to the phase of the fundamental frequency sinusoidal voltage, and the voltage is superimposed by the multiplexing circuit 15 and applied to the gate terminal of the SiC power card 13. As shown in Figure 5, the voltage applied to the gate terminal of the SiC power card 13 can be applied to the gate of the semiconductor switch M1 with the phase of the fundamental frequency sinusoidal voltage and the phase of the third-order frequency sinusoidal voltage roughly in agreement by delaying the phase of the third-order frequency sinusoidal voltage with respect to the fundamental frequency.

[0059] As shown in Figure 6, the gate voltage-drain current characteristics of the semiconductor switch M1 allow for larger currents to flow and smaller losses as the gate voltage increases. By using Class E amplifiers 22 and 25 in the preceding stage, the gate applied voltage can be increased in the latter half of the ON period. Therefore, the current flowing through the semiconductor switch M1 during the ON period can be increased in the latter half of the ON period, as shown in Figure 5.

[0060] According to this embodiment, by applying a third-order frequency sinusoidal voltage to the gate terminal of the SiC power card 13 with a phase delay compared to the fundamental frequency sinusoidal voltage, the phases of the fundamental frequency and odd-order frequency sinusoidal voltages can be roughly matched at the gate position of the semiconductor switch M1. This prevents unwanted peaking and allows for a steep rise in the gate voltage, enabling the application of a high gate voltage, especially in the latter half of the ON period. While the rise of the gate voltage has been described here, the fall can also be made similarly steep.

[0061] According to the configuration of this embodiment, losses in the semiconductor switch M1 built into the SiC power card 13 can be reduced, the power conversion efficiency of the main power conversion unit 11 can be improved, and the output voltage can be increased. Excessive voltage is no longer applied to the gate of the semiconductor switch M1, and the lifespan of the semiconductor switch M1 can be extended.

[0062] The package of this type of existing semiconductor switch M1 has a parasitic inductance L gAlthough the package is relatively large, it can be used in MHz band high-frequency power supplies, and in particular, MHz drive can be achieved by power modules for hybrid vehicle (HV) inverters. Furthermore, overall efficiency at low output can be improved. In addition, heat dissipation of the gate drive unit 12 can be simplified. Moreover, heat dissipation can be simplified even if the semiconductor switch M1 is a large-capacity element with a large total gate charge.

[0063] (Second Embodiment) The second embodiment will be described with reference to Figure 7. In the first embodiment, the problem of the output voltage fluctuating when the load impedance of the Class E amplifiers 22 and 25 changes was addressed by setting the load Q value, which depends on the load resistance value observed from the matching circuits 23 and 26 to the input of the gate terminal of the SiC power card 13, to 3 or less. In the second embodiment, instead of or in addition to this, the output of the Class E amplifiers 22 and 25 of the first embodiment is made to have constant voltage source characteristics. In this embodiment, it is desirable to take the following measures to address the problem that the output voltage tends to fluctuate when the load impedance of the Class E amplifiers 22 and 25 changes.

[0064] As shown in Figure 7, it is preferable to add gyrators 40 and 41 as immittance conversion circuits at the outputs of the Class E amplifiers 22 and 25, respectively. Gyrator 40 is a capacitor C h11 , inductor L h1 , Capacitor C h12 It is configured in a π-type configuration, and the gyrator 41 is a capacitor C h21 , inductor L h2 , Capacitor C h22 It is configured in a π-type configuration. The values ​​of each element constituting the gyrators 40 and 41 are set to match the fundamental frequency and third frequency, respectively, and their circuit constants are different from each other.

[0065] By adding gyrators 40 and 41, the output of gyrator 40 will operate as a constant voltage source. Therefore, even if the input impedance seen at the gate terminal of the SiC power card 13 fluctuates, the output voltage of gyrator 40 can be stably maintained.

[0066] Note that capacitor C on the output side of gyrators 40 and 41 h12 , C h22 And capacitor C on the input side of matching circuits 23 and 26. m1 , C m2 It may be configured by sharing resources.

[0067] (Other embodiments) The present invention is not limited to the embodiments described above, and can be implemented in various modified forms and is applicable to various embodiments without departing from its essence. For example, the following modifications or extensions are possible.

[0068] In the preceding explanation, for the sake of simplicity, we described a configuration where odd-order frequencies were set to the third order, but this is not the only possible configuration. It may also be applied to a configuration in which a gate voltage Vg with a fifth-order or higher odd-order superimposed is output to the SiC power card 13. For example, by superimposing a fifth-order odd-order frequency voltage, the phase of the fundamental frequency voltage and the phase of the odd-order frequency voltage will be aligned, in which case a steeper adjustment can be achieved, and the drop in gate voltage during the ON period can be reduced.

[0069] The preceding Class E amplifiers 22 and 25 are configured to operate in Class E, but are not limited to Class E operation. In particular, amplifier 25, which amplifies odd-order frequency sinusoidal voltages, may be composed of Class A, B, AB, or C amplifiers.

[0070] Although the present invention has been described in accordance with the embodiments described above, it is understood that the present invention is not limited to such embodiments or structures. The present invention also encompasses various modifications and variations within the equivalence range. In addition, various combinations and forms, as well as other combinations and forms that include one, more, or fewer elements, fall within the scope and conceptual range of the present invention. [Explanation of Symbols]

[0071] In the drawing, 10 is the power converter (high-frequency power supply), 11 is the main power conversion unit, 12 is the gate drive unit, C gd , C gsis the gate capacitance, Lg is the parasitic inductance, 22 and 25 are Class E amplifiers (amplifiers), and 40 and 41 are immittance conversion circuits.

Claims

1. A main power conversion unit (11) is provided with a switching element (M1) whose resonant frequency (f0), determined based on the gate capacitance (Cgd, Cgs) and the inductance (Lg) present in the gate loop, is configured to be 100 MHz or less, and which has parasitic components due to the gate capacitance and the inductance in its gate, and which outputs power when the switching element is driven at a fundamental frequency of 1 MHz or higher, The system includes a gate drive unit (12) that outputs a gate voltage to the switching element obtained by superimposing a voltage of the fundamental frequency with a voltage of an odd-order frequency of three or more than the fundamental frequency, The odd-order frequencies are set to be different from the resonant frequencies of the gate loops of the switching elements in the main power conversion unit. The gate drive unit comprises a first Class E amplifier (22) that amplifies the fundamental frequency voltage in Class E, and a second Class E amplifier (25) that amplifies the odd-order frequency voltage in Class E, and the first Class E amplifier and the second Class E amplifier are configured to operate using a common DC power supply voltage (Vd). The voltages amplified by the first Class E amplifier and the second Class E amplifier are superimposed and output to the switching element, such that the phases of the fundamental frequency and the odd-order frequency sinusoidal voltages are aligned at the gate position of the switching element, by shifting the phase of the odd-order frequency voltages by a predetermined amount compared to the phase of the fundamental frequency voltage. A combining circuit (15) that combines the outputs of the first Class E amplifier and the second Class E amplifier, A first matching circuit (23) located at the output of the first Class E amplifier, which makes the reactance component of the impedance viewed from the multiplexing circuit towards the gate terminal side of the switching element of the main power conversion section zero or capacitive, The second Class E amplifier is located at the output and includes a second matching circuit (26) that makes the reactance component of the impedance viewed from the multiplexing circuit towards the gate terminal side of the switching element of the main power conversion section zero or capacitive, The input impedances of the first matching circuit and the second matching circuit are set to satisfy the condition that a desired voltage amplitude is applied to the gate of the switching element from the DC power supply voltage (Vd) that is commonly input to the first and second Class E amplifiers (22, 25), based on the circuit configuration of the first matching circuit and the second matching circuit and the parasitic components. The load resistances (Ro) of the first Class E amplifier and the second Class E amplifier are set to a value equal to the input impedance as seen from the input side of the first matching circuit and the second matching circuit, respectively, and the power converter is set to a condition that makes the imaginary part of the input impedance of the first matching circuit and the second matching circuit zero.

2. The power converter according to claim 1, wherein the gate drive unit superimposes the voltages amplified by the first Class E amplifier and the second Class E amplifier on the switching element, with the phase of the odd-order frequency voltage being slower than the phase of the fundamental frequency voltage, and outputs the result to the switching element.

3. The power converter according to claim 1 or 2, wherein the gate drive unit outputs a sinusoidal voltage of the third order as the odd-order frequency by superimposing it on the sinusoidal voltage of the fundamental frequency.

4. The power converter according to claim 1 or 2, wherein the relationship between the inductance and the gate capacitance is set such that the resonant frequency and the odd-order frequency are shifted by at least f0 / (2 × Q value of the gate loop).

5. The power converter according to any one of claims 1 to 4, wherein the multiplexing circuit combines the outputs of the first Class E amplifier and the second Class E amplifier using a parallel resonant circuit (15a, 15b) such that the impedance at odd-order frequencies viewed from the output of the first Class E amplifier to the output side of the second Class E amplifier can be considered to be open-circuited, and the impedance at the fundamental frequency viewed from the output of the second Class E amplifier to the output side of the first Class E amplifier can be considered to be open-circuited.

6. The power converter according to claim 1, wherein the load Q value observed from the gate input of the switching element through the multiplexing circuit is set to 3 or less.

7. The power converter according to claim 1, further comprising immittance conversion circuits (40, 41) positioned between the outputs of each of the first and second Class E amplifiers and the multiplexing circuit, wherein the output voltages of the first and second Class E amplifiers are generated as a constant voltage source by the immittance conversion circuits.

8. The power converter according to any one of claims 1 to 7, wherein the switching element is composed of a SiC power semiconductor switch (M1) and is configured as a SiC power card (13).

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