Memory system

Abstract

To provide a memory system capable of improving read latency.SOLUTION: A memory system includes a memory controller configured to write data in a first mode and a second mode to blocks of a first area and a second area of a non-volatile memory, respectively. The first mode is a write mode for writing data with a first number of bits per memory cell. The second model is a write mode for writing data with a second number of bits larger than the first number of bits per memory cell. The memory controller is further configured to write the data received from the host to a first block in the first area in the first mode, and execute copy processing to copy system data and user data of the data written in the first block, to a second block in the first area in the first mode and to a third block of the second area in the second mode, respectively.SELECTED DRAWING: Figure 8

Description

Technical Field

[0001] Embodiments of the present invention relate to a memory system.

Background Art

[0002] In recent years, memory systems equipped with non-volatile memories have become widely popular. As one such memory system, a solid-state drive (SSD) equipped with a NAND-type flash memory and a Universal Flash Storage (UFS) device are known. There is a demand to improve the read latency for such memory systems.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] One embodiment provides a memory system capable of improving read latency.

Means for Solving the Problems

[0005] The memory system of the embodiment comprises a non-volatile memory having a first region and a second region, each containing a plurality of blocks, and a memory controller electrically connected to the non-volatile memory and configured to write data to each block of the first region in a first mode and to write data to each block of the second region in a second mode, wherein the first mode is a write mode for writing data with a first number of bits per memory cell, and the second mode is a write mode for writing data with a second number of bits greater than the first number of bits per memory cell, and the memory controller writes data received from the host to the first block of the first region in the first mode, copies system data from the data written to the first block to the second block of the first region in the first mode, and copies user data to the third block of the second region in the second mode, and performs a copy process. [Brief explanation of the drawing]

[0006] [Figure 1] A block diagram showing an example configuration of a memory system according to the first embodiment. [Figure 2] A diagram showing the memory arrangement of a non-volatile memory according to the first embodiment. [Figure 3] A flowchart showing an example of a write process by the memory controller according to the first embodiment. [Figure 4] A diagram illustrating the contents of the L2P table according to the first embodiment. [Figure 5] A diagram illustrating the contents of the L2P table according to the first embodiment. [Figure 6] A diagram illustrating the contents of the L2P table according to the first embodiment. [Figure 7] A diagram illustrating the contents of the L2P table according to the first embodiment. [Figure 8] A flowchart showing an example of garbage collection processing by the memory controller according to the first embodiment. [Figure 9]A diagram illustrating the operation of garbage collection according to the first embodiment. [Figure 10] A diagram illustrating the writing format in the second embodiment. [Figure 11] A diagram showing the command format for write commands in the UFS standard. [Figure 12] A flowchart showing an example of a write process by the memory controller according to the second embodiment. [Figure 13] A flowchart showing an example of garbage collection processing by a memory controller according to the second embodiment. [Figure 14] A figure showing an example of an L2P table according to a modified example of the second embodiment. [Figure 15] A figure showing an example of an L2P table according to a modified example of the second embodiment. [Figure 16] A figure showing an example of an L2P table according to a modified example of the second embodiment. [Figure 17] A figure showing an example of an L2P table according to a modified example of the second embodiment. [Figure 18] A flowchart showing an example of garbage collection processing by a memory controller according to the third embodiment. [Figure 19] A diagram showing an example of an L2P table according to the third embodiment. [Figure 20] A flowchart showing an example of garbage collection processing by a memory controller according to the fourth embodiment. [Figure 21] A diagram showing an example of an L2P table according to the fourth embodiment. [Figure 22] A flowchart showing an example of garbage collection processing by a memory controller according to the fifth embodiment. [Figure 23] A figure showing an example of an L2P table according to the fifth embodiment. [Figure 24] A flowchart showing an example of garbage collection processing by a memory controller according to the sixth embodiment. [Figure 25]A diagram showing an example of the L2P table according to the sixth embodiment. [Figure 26] A flowchart showing an example of garbage collection processing by the memory controller according to the seventh embodiment. [Figure 27] A diagram for explaining data movement in the seventh embodiment. [Figure 28] A flowchart showing an example of data movement processing by the memory controller according to the seventh embodiment. [Figure 29] A diagram for explaining data movement processing in the seventh embodiment. **Embodiments for Carrying Out the Invention**

[0007] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0008] (First Embodiment) In this embodiment, data to be subject to high-speed reading is determined, and for the data to be subject to high-speed reading, even when garbage collection is executed, it is stored in an area in the memory cell array where high-speed reading is possible. This embodiment thereby improves the read latency.

[0009] (Configuration of Memory System) FIG. 1 is a block diagram showing a configuration example of a memory system according to the first embodiment. The memory system 1 of this embodiment includes a memory controller 3 and a nonvolatile memory 2. Note that the nonvolatile memory 2 may include a plurality of memory chips. The memory system 1 can be connected to a host device 4. The host device 4 is, for example, an electronic device such as a personal computer or a mobile terminal. The host device 4 has a central processing unit (CPU) 4a, a ROM (not shown), and a DRAM 4b.

[0010] The memory system 1 may be implemented on a motherboard on which the host device 4 is mounted. The memory system 1 may consist of multiple semiconductor chips. Examples of the memory system 1 include a UFS (Universal Flash Storage) device in which the memory controller 3 and non-volatile memory 2 are configured as a single package, a memory card such as an SD card, an SSD (Solid-State-Drive), or an eMMC (embedded-Multi-Media-Card).

[0011] Non-volatile memory 2 is, for example, a NAND flash memory. Non-volatile memory 2 has a memory cell array comprising multiple memory cell transistors. Each memory cell transistor constitutes an electrically rewritable memory cell. Non-volatile memory 2 includes multiple bit lines BL, multiple word lines WL, and source lines CELSRC, etc., to control the voltage applied to the memory cell transistors. Non-volatile memory 2 comprises multiple blocks. Each block functions as the smallest unit of data erasure operation. Each block contains multiple pages. Each page functions as a unit of data write operation and data read operation. Note that each word line WL may also function as a unit of data write operation and data read operation.

[0012] Each memory cell in non-volatile memory 2 can be written to n bits of data (where n is an integer greater than or equal to 1). The memory cell may be an SLC (Single Level Cell) capable of storing 1 bit of data. The memory cell may be an MLC (Multi Level Cell) capable of storing 2 bits of data. The memory cell may be a TLC (Triple Level Cell) capable of storing 3 bits of data. The memory cell may be a QLC (Quad Level Cell) capable of storing 4 bits of data.

[0013] The memory controller 3 may consist of a system LSI (Large-Scale Integrated Circuit) or a SoC (System-on-a-Chip). The functions of each part of the memory controller 3 may be realized by dedicated hardware, a processor that executes programs, or a combination thereof.

[0014] The memory controller 3 includes a host interface circuit (hereinafter referred to as host I / F) 10, a processor 11, RAM 12, buffer memory 13, a memory interface circuit (hereinafter referred to as memory I / F) 14, and an error checking and correction (ECC) circuit (hereinafter referred to as ECC circuit) 15. The host I / F 10, processor 11, RAM 12, buffer memory 13, memory I / F 14, and ECC circuit 15 are connected to each other by an internal bus 16.

[0015] The processor 11 is composed of a central processing unit (CPU), etc. The processor 11 comprehensively controls each part of the memory system 1 by executing a program (firmware) stored in a ROM (not shown). When the processor 11 receives a request from the host device 4 via the host I / F 10, it performs various controls by executing processing according to that request. For example, the processor 11 instructs the memory I / F 14 to write data to the non-volatile memory 2 according to a request from the host device 4. The processor 11 also instructs the memory I / F 14 to read data from the non-volatile memory 2 according to a request from the host device 4.

[0016] When processor 11 receives a data write request from host device 4, it determines the storage area (memory region) on non-volatile memory 2 for the data received from host device 4. In other words, processor 11 manages the destination of data writes. Processor 11 manages the relationship between host addresses and memory addresses using a Logical to Physical (L2P) table 12. The host address is the logical address of the data received from host device 4. An example of a logical address is a logical block address. Hereinafter, the host address will be referred to as host address LBA. The memory address is the physical address that indicates the storage area on non-volatile memory 2 where the data is stored. Hereinafter, the memory address will be referred to as memory address PBA. L2P table 12a stores data that associates the host address LBA, used when host device 4 accesses memory system 1, with the memory address PBA of non-volatile memory 2. L2P table 12a is stored, for example, in RAM 12.

[0017] Data can only be written to one page of non-volatile memory 2 once per erase / write cycle. Therefore, the processor 11 writes updated data corresponding to a host address LBA to a different storage location in non-volatile memory 2, rather than to the storage location in non-volatile memory 2 where the previous data corresponding to that host address LBA is stored. The processor 11 then invalidates the previous data by updating the L2P table 12a to associate this host address LBA with this different storage location. Data referenced from the L2P table 12a (i.e., data associated with a host address LBA) is called valid data. Data not associated with any host address LBA is called invalid data. Valid data is data that may be read later by the host device 4. Invalid data is data that can no longer be read by the host device 4. Blocks that store only invalid data are called free blocks.

[0018] When processor 11 receives a data write request from host device 4, it determines the memory address PBA corresponding to the request. Then, processor 11 instructs memory I / F 14 to write the data to the memory area at the determined memory address PBA. Memory controller 3 updates L2P table 12a to associate the host address LBA and memory address PBA related to the request. At any time, processor 11 devolves L2P table 12a from RAM 12 to non-volatile memory 2.

[0019] When processor 11 receives a data read request from host device 4, it refers to L2P table 12a for the host address LBA specified in the request and identifies memory address PBA. Then, processor 11 instructs memory I / F 14 to read data from the storage area at memory address PBA. In other words, when processor 11 receives a request from host device 4, it identifies the memory address PBA corresponding to the host address LBA involved in the request and reads the data.

[0020] RAM12 temporarily stores not only the L2P table 12a but also various other data.

[0021] The ECC circuit 15 encodes the data to be written to the non-volatile memory 2. The ECC circuit 15 decodes the data read from the non-volatile memory 2.

[0022] The buffer memory 13 temporarily stores data received from the host device 4. The buffer memory 13 also temporarily stores data read from the non-volatile memory 2. The buffer memory 13 is a general-purpose memory, such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory).

[0023] The host I / F 10 performs processing in accordance with the interface standard with the host device 4. The host I / F 10 outputs requests and data received from the host device 4 to the internal bus 16. The host I / F 10 also transmits data read from the non-volatile memory 2 and responses from the processor 11 to the host device 4.

[0024] The memory interface 14 performs processing related to writing data to the non-volatile memory 2 and reading data from the non-volatile memory 2, under the control of the processor 11.

[0025] Figure 2 shows the memory layout of non-volatile memory 2. In the example in Figure 2, non-volatile memory 2 includes an SLC area and a QLC area. The shaded area in Figure 2 indicates the area where valid data is stored.

[0026] The SLC area is a storage area where each memory cell is used as SLC. The MLC area is a storage area where each memory cell is used as MLC. The TLC area is a storage area where each memory cell is used as TLC. The QLC area is a storage area where each memory cell is used as QLC. The memory system 1 has a recording mode in which 1 bit of data is written to each memory cell in the SLC area (SLC mode), a recording mode in which 2 bits of data are written to each memory cell in the MLC area (MLC mode), a recording mode in which 3 bits of data are written to each memory cell in the TLC area (TLC mode), and a recording mode in which 4 bits of data are written to each memory cell in the QLC area (QLC mode). These modes are specified by the memory controller 3. The time it takes to write data to the SLC area is shorter than the time it takes to write data to the MLC area, TLC area, or QLC area. Also, the time it takes to read data stored in the SLC area is shorter than the time it takes to read data stored in the MLC area, TLC area, or QLC area. In other words, reading data from the SLC region is faster than reading data from a region where each memory cell is configured to store multiple bits of data (hereinafter also referred to as the multi-level region). In the following explanation, the QLC region will be used as an example of the multi-level region, but the multi-level region may also be the MLC region or the TLC region.

[0027] The memory controller 3 may use a certain storage area of ​​the non-volatile memory 2 as a dedicated area for either the SLC area or the QLC area; that is, the memory controller 3 may use one storage area as the SLC area and another area as the QLC area throughout the entire lifetime of the memory system 1. Alternatively, the memory controller 3 may use a certain storage area of ​​the non-volatile memory 2 as a shared area for either the SLC area or the QLC area; that is, the memory controller 3 may use one storage area as the SLC area or the QLC area. Based on the host address LBA related to the request from the host device 4, the memory controller 3 writes data to the SLC area or the QLC area, or reads data from the SLC area or the QLC area.

[0028] As mentioned above, the write and read speeds for each memory cell in the SLC area are faster than those for each memory cell in the QLC area. The UFS 3.0 standard defines high-speed write commands. Writing with high-speed write commands is expected to be faster than writing with normal write commands. Furthermore, data written to non-volatile memory 2 with high-speed write commands is expected to be read faster than data written with normal write commands. Therefore, when high-speed writing is specified, the memory controller 3 may write in SLC mode, and when normal writing is specified, it may write in QLC mode.

[0029] For example, data written to a memory system 1 implemented in a mobile device such as a smartphone can be broadly divided into system data, which forms the core of the system, such as the OS (operating system) and kernel (hereinafter referred to as system data), and user data, such as photos, videos, and applications, which are saved by the end user (hereinafter referred to as user data). System data is system information for smartphones, etc., and tends to be read frequently after being written. In contrast, user data is read only when in use, so it tends to be read relatively less frequently. Therefore, it is desirable that system data be written to the SLC area using SLC mode and read from the SLC area at high speed.

[0030] However, in memory system 1, garbage collection is performed to increase the number of free blocks. Garbage collection is performed, for example, when the number of free blocks falls below a predetermined number. In garbage collection, all valid data in multiple blocks (original blocks) containing a mixture of valid and invalid data is moved to erased blocks. The original blocks from which all valid data has been moved are managed as free blocks. After the data erasure operation, the free blocks become available for reuse as new write destination blocks. This garbage collection may cause system data written to the SLC area using high-speed write commands to be moved to the QLC area.

[0031] Furthermore, the memory controller 3 cannot distinguish between system data and user data. Therefore, it is not guaranteed that the memory controller 3 can reliably write system data to the non-volatile memory 2 in SLC mode. In other words, there is a risk that even system data may be written to the QLC area.

[0032] Some memory systems always write data to non-volatile memory in SLC mode when a write request is made from a host device, and then move the data from the SLC area to the QLC area. Even in this case, system data written to the SLC area is moved to the QLC area, making it impossible to read the system data at high speed.

[0033] (countermeasure) Therefore, this embodiment determines the data to be read at high speed, i.e., system data, and always stores data determined to be system data in the SLC area. PCs and smartphones use file systems for data management. In file systems, the host address LBA assigned to the OS and kernel is often known. For example, small host address LBAs are often assigned to system data such as the OS and kernel. This embodiment utilizes the fact that the host address LBA of system data may be known and determines whether the data to be written is system data based on the host address LBA. For example, if it is known that system data is written to logical address space 0 to 10 GB, this embodiment treats the data within that host address LBA as system data. This embodiment writes system data to the SLC area and also controls its movement to the SLC area during garbage collection. To enable this control, the memory controller 3 of this embodiment controls the updating of the L2P table 12a.

[0034] (Writing and garbage collection) Figure 3 is a flowchart showing an example of a write operation by the processor 11 of the memory controller 3.

[0035] When the memory controller 3 receives a write request from the host device 4, it executes the write process shown in Figure 3. That is, in step S1, the processor 11 is in a waiting state for a write request (write command) from the host device 4 (S1).

[0036] When processor 11 receives a write request (YES in S1), it determines whether the host address LBA of the data to be written is an address specified as a logical address for system data, or an address commonly used as a logical address for system data (hereinafter referred to as a system data address) (S2). If the host address LBA specified by the host device 4 is a system data address (YES in S2), processor 11 determines that the data is system data and writes the data to the SLC area (S4).

[0037] If the processor 11 determines that the host address LBA specified by the host device 4 is not a system data address (NO in S2), it determines that the data is user data and writes the data to the area corresponding to the command from the host device 4. That is, if the data is requested to be written with a high-speed write command, the processor 11 writes the data to the SLC area, and if the data is requested to be written with a normal write command, it writes the data to the QLC area (S3).

[0038] The processor 11 updates the L2P table 12a to associate the host address LBA involved in the write request with the memory address PBA where the data was written in step S3 or step S4.

[0039] Figures 4 through 7 are diagrams illustrating the contents of the L2P table.

[0040] Figure 4 shows the state before data writing is performed. The L2P table 12a contains information on the host address (LBA), memory address (PBA), and enable / disable flag. The host address LBA indicates the logical address specified by the host device 4. The memory address PBA indicates the physical address of the storage area in the non-volatile memory 2. The enable / disable flag indicates whether the data held at that address is valid or invalid data. During garbage collection, the processor 11 of the memory controller 3 targets data with the enable / disable flag set to move during garbage collection.

[0041] Figure 5 shows the state of the L2P table 12a when data with host addresses LBA0-3 (system data addresses) is written to non-volatile memory 2. The processor 11 writes data with host address LBA as the system data address to the SLC area, regardless of whether the write request is a high-speed write command or a normal write command. Hereafter, the logical address where host address LBA is x will be denoted as LBAx. Also, the memory address PBA corresponding to page PageW of block BlkY will be denoted as BlkY,PageW. The example in Figure 5 shows that the data for LBA0 is written to Blk0,Page0, the data for LBA1 is written to Blk0,Page1, the data for LBA2 is written to Blk0,Page2, and the data for LBA3 is written to Blk0,Page3. The enable / disable flags for these memory addresses PBA are set to "1", indicating enable.

[0042] Here, for example, let's assume that the data in LBA3 is overwritten by the host device 4. Figure 6 shows an example of the L2P table 12a in this case. In this case, the data in LBA3 that the host device 4 instructs to write is written to the free area Blk0,Page4. Note that Blk0,Page4 is the memory address PBA of the SLC area. In this case, the enable / disable flag for Blk0,Page3 will be "0" indicating disabled, and the enable / disable flag for Blk0,Page4 will be "1" indicating enabled.

[0043] Next, let's assume that, for example, Blk0 in the SLC area is subject to garbage collection. In this case as well, data with a small host address LBA, that is, data with a system data address, is system data. Therefore, the processor 11 moves this data to the SLC area during garbage collection.

[0044] Figure 8 is a flowchart showing an example of garbage collection processing by processor 11. When processor 11 determines that garbage collection (GC) is necessary (YES in S6), it refers to L2P table 12a (S7) to determine whether the data to be garbage collected is data with a system data address (S8).

[0045] If processor 11 determines that the data subject to garbage collection is data at a system data address (YES in S8), it determines that the data is system data and moves the data to the SLC area (S9). If processor 11 determines that the data subject to garbage collection is not data at a system data address (NO in S8), it determines that the data is user data and moves the data to the QLC area (S10).

[0046] The processor 11 updates the L2P table 12a to associate the host address LBA of the data subject to garbage collection with the memory address PBA in step S9 or step S10 where the data was written (S30).

[0047] Figure 7 shows an example of the L2P table 12a after garbage collection targeting Blk0 has finished from the state shown in Figure 6. The processor 11 writes the data from Blk0, Page 0, 1, 2, and 4 to the storage area of ​​other memory addresses PBA in the SLC area (Blk1, Page 0~3 in Figure 7) through garbage collection. Note that Blk1, Page 0~3 are the memory addresses PBA in the SLC area. In this case, the enable / disable flag for Blk0 becomes "0" indicating disabled, and the enable / disable flag for Blk1, Page 0~3 becomes "1" indicating enabled. Although omitted in Figure 7, valid data is also moved to block Blk1 from other blocks besides block Blk0 through garbage collection.

[0048] Since system data is always stored in the SLC area, high-speed reading is possible.

[0049] Figure 9 is a diagram illustrating the operation of garbage collection. System data is written to the SLC area regardless of whether the write request is made using a high-speed write command or a normal write command. During garbage collection, the processor 11 moves the system data to the SLC area. On the other hand, user data may also be written to the SLC area in response to a high-speed write command. In this case, the host address LBA of the user data is not the address for system data, so during garbage collection, the processor 11 moves the user data to the QLC area. User data other than system data is moved to the QLC area by garbage collection, making it possible to make effective use of the memory area.

[0050] In this embodiment, the host address LBA determines whether the data to be written is system data or user data. In this embodiment, system data is written to the SLC area and is also moved to the SLC area during garbage collection. As a result, system data can be stored in the SLC area, enabling high-speed reading and achieving low read latency.

[0051] (Second embodiment) Figure 10 is a diagram illustrating the write format in the second embodiment. The hardware configuration of this embodiment is the same as in the first embodiment. In the first embodiment, it was determined whether the data to be written was system data or not based on the address range of the host address LBA. In contrast, in this embodiment, the host device 4 adds information to the write command to determine whether it is system data or user data. For example, in the UFS standard, a reserved area is allocated in the write command. The host device 4 sends a write command that includes information indicating that it is system data in this reserved area.

[0052] Figure 11 shows an example of the command format for a write command in the UFS standard. Figure 11 shows the data assigned to bits 7-0 of each of Byte 0-9 in the write command. Byte 0 is assigned the OPERATION CODE. Byte 1 is assigned WRPROTECT, DPO, FUA, Reserved, FUA_NV, and Obsolete. Byte 2-5 are assigned the host address LBA (LOGICAL BLOCK ADDRESS). Byte 7-8 are assigned the data length (TRANSFER LENGTH). Byte 9 is assigned the control code (CONTROL).

[0053] Byte6 is allocated a reserved area and a group number. For example, the host device 4 adds data identification information to the reserved area, indicating whether it is system data or user data. Alternatively, the host device 4 may add data identification information to the group number.

[0054] When processor 11 receives a write command, it reads, for example, data identification information located in the reserved area to determine whether the data instructed to be written by the write command is system data or user data. If processor 11 determines that the data instructed to be written by the write command is system data, it writes the system data to the SLC area. Furthermore, processor 11 adds an identification flag indicating that the written data is system data to the written data (the data body) and writes it to the non-volatile memory 2. For example, processor 11 writes the identification flag to a column address adjacent to the data body.

[0055] Figure 10 shows the writing format in this case. As shown in Figure 10, the processor 11 writes the data body with an identification flag added to it. For example, the processor 11 may set the identification flag to "1" for system data and to "0" for user data.

[0056] Next, the operation of the embodiment configured in this way will be described with reference to Figures 12 and 13. Figure 12 is a flowchart illustrating the operation during writing, and Figure 13 is a flowchart illustrating the operation during garbage collection.

[0057] When the memory controller 3 receives a write request (write command) from the host device 4, it executes the data writing process shown in Figure 12. That is, when the processor 11 receives a write request from the host device 4 (YES in S1), it reads the data identification information contained in the write command (S11) and determines whether the data to be written by the write command is system data or not (S12).

[0058] If the processor 11 determines that the data written from the host device 4 is system data (YES in S12), it writes the data to the SLC area (S13). If the processor 11 determines that the data from the host device 4 is not system data (NO in S12), it writes the data to the area corresponding to the command from the host device 4. That is, if the data is requested to be written using a high-speed write command, the processor 11 writes the data to the SLC area, and if the data is requested to be written using a normal write command, it writes the data to the QLC area (S14).

[0059] In this embodiment, during the writing process in steps S13 and S14, the processor 11 adds an identification flag to the data body indicating whether or not it is system data.

[0060] Next, the SLC area is to be subject to garbage collection. As shown in Figure 13, when the processor 11 determines that garbage collection (GC) is necessary (YES in S15), it reads the data to be garbage collected (S16) and determines whether the data is system data or not based on the attached identification flag (S17).

[0061] If the data subject to garbage collection is system data (YES in S18), the processor 11 moves the data to the SLC area (S19). If the processor 11 determines that the data subject to garbage collection is not system data (NO in S18), it moves the data to the QLC area (S20).

[0062] Thus, in this embodiment as well, system data can always be stored in the SLC area, enabling high-speed reading and achieving low read latency.

[0063] (modified version) Figures 14 to 17 show examples of the contents of the L2P table in modified examples. Figure 10 illustrates an example in which an identification flag based on data identification information included in the write command from the host device 4 is added to the data body and written to the non-volatile memory 2. In contrast, Figures 14 to 17 show examples in which data identification information is recorded in the L2P table 12a.

[0064] The processor 11 of the memory controller 3 writes the data identification information contained in the write command from the host device 4 to the L2P table 12a. Figure 14 shows the state before data writing is performed. The L2P table 12a includes data identification information in addition to the host address (LBA), memory address (PBA), and enable / disable flag information.

[0065] Figure 15 shows the state of L2P table 12a when data with host addresses LBA0-3 is written to non-volatile memory 2. In L2P table 12a, "System" indicates system data and "User" indicates user data. The data identification information in L2P table 12a is obtained by the processor 11 by extracting the data identification information included in the write command from the host device 4. Data with LBA0-2 is system data, and data with LBA3 is user data. The processor 11 writes data that has been identified as system data by the data identification information to the SLC area, regardless of whether the write request is a high-speed write command or a normal write command. In the example in Figure 15, the data for LBA0 is written to Blk0,Page0, the data for LBA1 is written to Blk0,Page1, and the data for LBA2 is written to Blk0,Page2. Blk0 is included in the SLC area. Furthermore, it is shown that the user data for LBA3 is written to Blk0,Page3 in the SLC area in response to a write request with a high-speed write command. Furthermore, the enable / disable flag for these memory address PBAs is set to "1," indicating that they are enabled.

[0066] Here, for example, let's assume that the system data of LBA2 is overwritten by the host device 4. Figure 16 shows an example of the L2P table 12a in this case. In this case, the data of LBA2 that the host device 4 instructs to write is written to the free area Blk0,Page4. Note that Blk0,Page4 is the memory address PBA of the SLC area. In this case, the enable / disable flag of Blk0,Page2 will be "0" indicating disabled, and the enable / disable flag of Blk0,Page4 will be "1" indicating enabled.

[0067] Next, let's assume that, for example, Blk0 in the SLC area is subject to garbage collection. System data written to the SLC area is moved to the SLC area during garbage collection. If system data is stored in a block subject to garbage collection, the processor 11 moves that data to the SLC area. Also, if user data is stored in a block subject to garbage collection, the processor 11 moves that data to the QLC area.

[0068] Figure 17 shows an example of the L2P table 12a in this case. The processor 11 writes the data from Blk0,Page0,1,4 to the memory area at other memory addresses PBA in the SLC area (Blk1,Page0~2 in Figure 17) through garbage collection. Note that Blk1,Page0~2 are the memory addresses PBA in the SLC area. In this case, the enable / disable flag for Blk0 becomes "0" indicating disabled, and the enable / disable flag for Blk1,Page0~2 becomes "1" indicating enabled. The processor 11 also moves the user data that was written to Blk0,Page3 to Blk11,Page0 in the QLC area.

[0069] Thus, in this modified example as well, system data can be stored in the SLC area, enabling high-speed retrieval. Furthermore, user data is moved to the QLC area through garbage collection, allowing for efficient use of memory space.

[0070] (Third embodiment) Figure 18 is a flowchart showing an example of garbage collection processing by the processor 11 according to the third embodiment. The hardware configuration of this embodiment is the same as that of the first embodiment. The first and second embodiments were examples where prior information about the host address LBA of the system data was available or data identification information indicating system data was input. In this embodiment, the memory controller 3 determines whether the data to be written is system data or user data without this prior information or data identification information.

[0071] Generally, system data is characterized by fewer write accesses and more read accesses. Therefore, the processor 11 of the memory controller 3 counts the number of data reads for each host address LBA and stores the count results in a management table. When garbage collection is required, the processor 11 refers to the management table and determines that data with a read count above a predetermined threshold is system data and moves it to the SLC area, while data with a read count below a predetermined threshold is determined to be user data and moves it to the QLC area.

[0072] For example, L2P table 12a may be used as a management table to register the read count information. Although the memory address PBA in L2P table 12a is updated by garbage collection, other information, including the read count, is retained.

[0073] Next, the operation of the embodiment will be described with reference to Figures 18 and 19. Figure 19 is a diagram showing an example of an L2P table 12a that includes read count information. Figure 19 shows an example where data written with LBA0 specified has been read 100 times, data written with LBA1 specified has been read 1 time, data written with LBA2 specified has been read 10 times, and data written with LBA3 specified has been read 100 times. Note that the judgment result in Figure 19 shows the judgment result between system data and user data when the threshold is 100, but the L2P table 12a does not necessarily have to include the judgment result.

[0074] In this embodiment, the processor 11 counts the number of times each piece of data has been read for each host address LBA. That is, when the processor 11 receives a read request from the host device 4, it increments the read count in the L2P table 12a for the host address LBA specified by the read request. The number of reads for the data that has been read increases. As a result, as shown in Figure 19, the number of reads for the data in LBA0 and LBA3 is assumed to be 100 or more, which is the threshold.

[0075] In this state, Blk0 is assumed to be subject to garbage collection. As shown in Figure 18, the processor 11 determines whether garbage collection is necessary (S21). If the processor 11 determines that garbage collection is necessary (YES in S21), it obtains the number of reads recorded for the host address LBA that is subject to garbage collection (S22). The processor 11 determines whether the obtained number of reads is greater than or equal to a threshold (S23). The processor 11 determines that data with a read count greater than or equal to the threshold is system data (YES in S23) and moves the data to the SLC area (S24). The processor 11 also determines that data with a read count less than the threshold is user data (NO in S23) and moves the data to the QLC area (S25).

[0076] As a result, in the example shown in Figure 19, the data from LBA0 and LBA3 is moved to the SLC area as system data, and the data from LBA1 and LBA2 is moved to the QLC area as user data. In this way, the system data can be read from the SLC area at high speed.

[0077] Thus, the same effects as those of the above embodiments can be obtained in this embodiment as well. In this embodiment, while system data may be written to the QLC area, data that is frequently read is reliably moved to the SLC area and read at high speed.

[0078] (Fourth embodiment) Figure 20 is a flowchart showing an example of garbage collection processing by the processor 11 according to the fourth embodiment. In Figure 20, the same reference numerals are used for the same steps as in Figure 18, and their descriptions are omitted. The hardware configuration of this embodiment is the same as that of the first embodiment. In the third embodiment, system data with many read accesses was determined by managing the number of reads. In this embodiment, system data is determined by the elapsed time from the last read time to the present.

[0079] The processor 11 of the memory controller 3 manages the access time for each read access to the data, and calculates the difference between the current time and the last read access time (elapsed time since the last read) for each host address LBA, and stores it in a management table. When the processor 11 determines that garbage collection is necessary, it refers to the management table and determines that data whose elapsed time since the last read is within a predetermined threshold is system data. The processor 11 controls the movement of data determined to be system data to the SLC area. The processor 11 determines that data whose elapsed time since the last read exceeds a predetermined threshold is user data. The processor 11 controls the movement of data determined to be user data to the QLC area.

[0080] For example, L2P table 12a may be used as a management table to register information on the elapsed time since the last read. Although the memory address PBA in L2P table 12a is updated by garbage collection, other information, including the elapsed time since the last read, is retained.

[0081] Next, the operation of the embodiment will be described with reference to Figures 20 and 21. Figure 21 is a diagram showing an example of an L2P table 12a that includes information on the elapsed time since the last read. Figure 21 shows an example where data written with LBA0 specified has an elapsed time of 1 hour since the last read, data written with LBA1 specified has an elapsed time of 10 minutes since the last read, data written with LBA2 specified has an elapsed time of 2 days since the last read, and data written with LBA3 specified has an elapsed time of 1 month since the last read. Note that the judgment result in Figure 21 shows the judgment result between system data and user data when the threshold is 1 hour, but the L2P table 12a does not necessarily have to include the judgment result.

[0082] In this embodiment, the processor 11 manages the last read access time for each data for each host address LBA. That is, when the processor 11 receives a read request from the host device 4, it manages the last read access time for the host address LBA of the L2P table 12a specified by the read request. The elapsed time since the last read of system data for which read requests occur relatively frequently is relatively short. In the example in Figure 21, the elapsed time since the last read of the data in LBA0 and LBA1 is below the threshold, while the elapsed time since the last read of the data in LBA2 and LBA3 exceeds the threshold.

[0083] In this state, Blk0 is assumed to be subject to garbage collection. As shown in Figure 20, when the processor 11 determines that garbage collection is necessary (YES in S21), it obtains the elapsed time since the last read recorded for the host address LBA that is subject to garbage collection (S31). The processor 11 determines whether the obtained elapsed time since the last read is below a threshold (S32). The processor 11 determines that data whose elapsed time since the last read is below the threshold is system data (YES in S32) and moves the data to the SLC area (S24). The processor 11 also determines that data whose elapsed time since the last read exceeds the threshold is user data (NO in S32) and moves the data to the QLC area (S25).

[0084] As a result, in the example shown in Figure 21, the data in LBA0 and LBA1 is moved to the SLC area as system data, and the data in LBA2 and LBA3 is moved to the QLC area as user data. In this way, the system data can be read from the SLC area at high speed.

[0085] Thus, the same effects as those of the third embodiment can be obtained in this embodiment as well.

[0086] (Fifth embodiment) Figure 22 is a flowchart showing an example of garbage collection processing by the processor 11 according to the fifth embodiment. In Figure 22, the same reference numerals are used for the same steps as in Figure 18, and their descriptions are omitted. The hardware configuration of this embodiment is the same as that of the first embodiment. In the third embodiment, system data with many read accesses was determined by managing the number of read accesses. In this embodiment, the determination of whether or not something is system data is made more accurately by determining not only read accesses but also write accesses.

[0087] For example, in the case of user data that is written and read frequently, such as game save data, it is possible that a determination based on the number of reads may be misidentified as system data. Therefore, this embodiment uses information on the number of reads and writes to determine whether the data is system data or user data.

[0088] The processor 11 of the memory controller 3 counts the number of data reads for each host address LBA and stores the count results in a management table. The processor 11 also counts the number of data writes for each host address LBA and stores the count results in a management table. The write count is incremented each time data is written when the same host address LBA is specified, that is, each time the data is overwritten.

[0089] When the processor 11 determines that garbage collection is necessary, it refers to the management table and determines that data with a read count of more than or equal to a predetermined first threshold and a write count of less than a predetermined second threshold is system data and controls it to move to the SLC area. The processor 11 determines that data with a read count of less than a predetermined first threshold or a write count of more than or equal to a predetermined second threshold is user data and controls it to move to the QLC area.

[0090] Furthermore, an L2P table 12a may be used as a management table to register information on the write and read count results. Garbage collection updates the memory address PBA in the L2P table 12a, but other information, including the write and read count results, is retained.

[0091] Next, the operation of the embodiment will be described with reference to Figures 22 and 23. Figure 23 is a diagram showing an example of an L2P table 12a that includes read count and write count information. Figure 23 shows an example where data written with LBA0 specified has a write count of 1 and a read count of 100, data written with LBA1 specified has a write count of 1 and a read count of 1, data written with LBA2 specified has a write count of 100 and a read count of 10, and data written with LBA3 specified has a write count of 100 and a read count of 100. Note that the judgment result in Figure 23 shows the judgment result between system data and user data when the second threshold for the write count is 10 and the first threshold for the read count is 100, but the L2P table 12a does not have to include the judgment result.

[0092] In this embodiment, the processor 11 counts the number of writes and reads for each data for each host address LBA. That is, when the processor 11 receives a write request from the host device 4, it increments the write count in the L2P table 12a for the host address LBA specified by the write request. Also, when the processor 11 receives a read request from the host device 4, it increments the read count in the L2P table 12a for the host address LBA specified by the read request. The write count for overwritten data and the read count for read data increase. As a result, as shown in Figure 23, the number of write operations (1) for LBA0 is less than the second threshold (10) and the number of read operations (100) is equal to or greater than the first threshold (100); the number of write operations (1) for LBA1 is less than the second threshold (10) and the number of read operations (1) is equal to or less than the first threshold (100); the number of write operations (100) for LBA2 is equal to or greater than the second threshold (10) and the number of read operations (10) is equal to or greater than the first threshold (10); and the number of write operations (100) for LBA3 is equal to or greater than the second threshold (10) and the number of read operations (100) is equal to or greater than the first threshold (100).

[0093] In this state, Blk0 is assumed to be subject to garbage collection. As shown in Figure 22, when the processor 11 determines that garbage collection is necessary (YES in S21), it obtains the write count and read count recorded for the host address LBA that is subject to garbage collection (S33). The processor 11 determines whether the obtained write count is less than the second threshold and the read count is greater than or equal to the first threshold, that is, whether the data is system data or not (S34). The processor 11 determines that data with a write count less than the second threshold and a read count greater than or equal to the first threshold is system data (YES in S34) and moves the data to the SLC area (S24). Alternatively, the processor 11 determines that data with a write count greater than or equal to the second threshold or a read count less than the first threshold is user data (NO in S34) and moves the data to the QLC area (S25).

[0094] As a result, in the example shown in Figure 23, the data in LBA0 is moved to the SLC area as system data, and the data in LBA1-3 is moved to the QLC area as user data. In this way, the system data can be read from the SLC area at high speed.

[0095] Thus, the same effects as those of the above embodiments can be obtained in this embodiment as well. In addition, in this embodiment, more information is used to determine the system data than in the third embodiment, and it is believed that highly accurate determination is possible.

[0096] (Sixth embodiment) Figure 24 is a flowchart showing an example of garbage collection processing by the processor 11 according to the sixth embodiment. In Figure 24, the same reference numerals are used for the same steps as in Figure 18, and their descriptions are omitted. The hardware configuration of this embodiment is the same as that of the first embodiment. In the fourth embodiment, system data that frequently receives read access is determined by the elapsed time since the last read. In this embodiment, it is determined whether data is system data or user data based on the elapsed time since the last read and the elapsed time from the last write to the present.

[0097] The processor 11 of the memory controller 3 manages the read access time for each host address LBA, calculates the elapsed time since the last read, and stores it in a management table. The processor 11 also manages the write access time for each host address LBA, calculates the difference from the current time, i.e., the difference between the current time and the last write access time (elapsed time since the last write), and stores it in a management table.

[0098] When processor 11 determines that garbage collection is necessary, it refers to the management table and determines that data whose elapsed time since the last read is within a predetermined third threshold and whose elapsed time since the last write is greater than or equal to a predetermined fourth threshold is system data. Processor 11 controls the movement of data determined to be system data to the SLC area. Processor 11 also determines that data whose elapsed time since the last read exceeds a predetermined third threshold or whose elapsed time since the last write is less than a predetermined fourth threshold is user data. Processor 11 controls the movement of data determined to be user data to the QLC area.

[0099] Furthermore, an L2P table 12a may be used as a management table to register information on the elapsed time since the last write and the elapsed time since the last read. Although the memory address PBA in the L2P table 12a is overwritten by garbage collection, other information, including the elapsed time since the last write and the elapsed time since the last read, is retained.

[0100] Next, the operation of the embodiment will be described with reference to Figures 24 and 25. Figure 25 is a diagram showing an example of an L2P table 12a that includes information on the elapsed time since the last read and the elapsed time since the last write. Figure 25 shows an example where data written with LBA0 specified has an elapsed time of 1 month since the last write and an elapsed time of 1 hour since the last read; data written with LBA1 specified has an elapsed time of 1 hour since the last write and an elapsed time of 10 minutes since the last read; data written with LBA2 specified has an elapsed time of 1 month since the last write and an elapsed time of 2 days since the last read; and data written with LBA3 specified has an elapsed time of 1 month since the last write and an elapsed time of 1 month since the last read. Note that the judgment result in Figure 25 shows the judgment result between system data and user data when the fourth threshold for the elapsed time since the last write is 1 month and the third threshold for the elapsed time since the last read is 1 hour, but the L2P table 12a does not have to include the judgment result.

[0101] In this embodiment, the processor 11 manages the last write access time and last read access time for each data for each host address LBA. That is, when the processor 11 receives a write request from the host device 4, it manages the last write access time for the host address LBA specified by the write request. Also, when the processor 11 receives a read request from the host device 4, it manages the last read access time for the host address LBA specified by the read request. The elapsed time since the last read of system data that is read relatively frequently is relatively short. On the other hand, the elapsed time since the last write of system data that is written (overwritten) infrequently is relatively long. In the example in Figure 25, for the data specified in LBA0, the elapsed time since the last write (1 month) is 1 month or more and the elapsed time since the last read (1 hour) is 1 hour or less. For the data specified in LBA1 to LBA3, the elapsed time since the last write is less than the 4th threshold (1 month) or the elapsed time since the last read is greater than the 3rd threshold (1 hour).

[0102] In this state, Blk0 is assumed to be subject to garbage collection. As shown in Figure 24, when the processor 11 determines that garbage collection is necessary (YES in S21), it obtains the elapsed time since the last write and the elapsed time since the last read recorded for the host address LBA that is subject to garbage collection (S35). The processor 11 determines whether the obtained elapsed time since the last write is greater than or equal to the fourth threshold and the elapsed time since the last read is less than or equal to the third threshold, that is, whether or not it is system data (S36). The processor 11 determines that data with an elapsed time since the last write greater than or equal to the fourth threshold and an elapsed time since the last read less than or equal to the third threshold is system data (YES in S36) and moves the data to the SLC area (S24). The processor 11 also determines that data with an elapsed time since the last write less than the fourth threshold or an elapsed time since the last read greater than the third threshold is user data (NO in S36) and moves the data to the QLC area (S25).

[0103] As a result, in the example shown in Figure 25, the data in LBA0 is moved to the SLC area as system data, and the data in LBA1-3 is moved to the QLC area as user data. In this way, the system data can be read from the SLC area at high speed.

[0104] Thus, the same effects as those of the above embodiments can be obtained in this embodiment as well. Furthermore, in this embodiment, more information is used to determine the system data than in the fourth embodiment, and it is believed that highly accurate determination is possible.

[0105] In the third to sixth embodiments described above, the memory controller 3 determines whether the data is system data or user data, and at the time of garbage collection, it may make a determination that differs from the actual data type. However, even in this case, by retaining and updating information other than the memory address PBA before and after garbage collection, it is believed that a determination result that matches the actual data type can ultimately be obtained.

[0106] (Seventh Embodiment) This embodiment improves read disturb resistance. The hardware configuration of this embodiment is the same as that of the first embodiment.

[0107] When a data read operation is performed in a memory system, the number of error bits in the block containing the word line WL from which the data read operation was performed tends to increase. Generally, an error bit threshold is maintained within the memory system, and when a data read operation is performed, the number of error bits is compared with the threshold. If the number of error bits exceeds the threshold, a refresh process is performed in which the data targeted by the data read operation is copied to another block. A characteristic of NAND flash memory is that the ease with which error bits increase depends greatly on the data storage method. For example, the more bits a single memory cell stores, the easier it is for error bits to increase. In other words, the more bits a single memory cell stores, the weaker the read disturb tolerance tends to be. On the other hand, as mentioned above, the more bits a single memory cell stores, the slower the write speed to NAND flash memory tends to be.

[0108] In typical memory systems, the storage method is selected according to the application. Data that is frequently written (updated) or of high importance is often written to the SLC area in SLC mode, while data that is not frequently written (updated) or of low importance is often written to the QLC area in QLC mode.

[0109] However, if read access occurs frequently to multi-level memory areas such as QLC areas, the number of refresh operations may increase due to the low read disturb tolerance of multi-level memory areas. This increase in refresh operations can potentially degrade the access performance of the memory system.

[0110] Therefore, this embodiment records the number of reads for each host address LBA, compares the difference between the number of reads and the average number of reads with a threshold, and controls the system to save the data to the SLC mode area based on the comparison result. This improves read disturb resistance.

[0111] The processor 11 of the memory controller 3 counts the number of data reads for each host address LBA and stores the count results in a management table. Then, at a predetermined timing, or when garbage collection is required, the processor 11 refers to the management table to obtain the number of reads and calculates the difference between the number of reads and the average number of reads. For example, the processor 11 obtains the average number of reads for the entire non-volatile memory 2. The processor 11 may also obtain the average number of reads for a block BLK, for example. If the difference is greater than a predetermined threshold, the processor 11 moves the data to the SLC area to improve read disturb resistance.

[0112] Furthermore, an L2P table 12a may be used as a management table to register information on the read count results. In this case, the contents of L2P table 12a are the same as those of the third embodiment described with reference to Figure 19. Note that while the memory address PBA in L2P table 12a is updated by garbage collection, other information, including the read count, is retained.

[0113] Next, the operation of the embodiment will be described with reference to Figures 26 to 29. Figure 26 is a flowchart showing an example of garbage collection processing by the processor 11 according to the seventh embodiment. In Figure 26, the same reference numerals are used for the same steps as in Figure 18, and their explanation is omitted. Figure 27 is a diagram for illustrating the movement of data in the multi-level region and the SLC region. Figure 27 shows the QLC region on the left and the SLC region on the right. The example on the left of Figure 27 shows blocks BlkM, BlkM+1, and BlkM+2 in the QLC region. Each block has pages Page0 to PageL. The example on the right of Figure 27 shows blocks BlkN, BlkN+1, and BlkN+2 in the SLC region. Each block has pages Page0 to PageK, where K is smaller than L.

[0114] The processor 11 counts the number of times each piece of data is read for each host address LBA. That is, when the processor 11 receives a read request from the host device 4, it increments the read count in the L2P table 12a for the host address LBA specified by the read request. For each host address LBA that has been written, the processor 11 calculates the difference between the read count and the average read count. The read count of data increases with each read operation, and the difference from the average read count becomes larger for data that is read frequently. As a result, as shown in Figure 27, for data stored in the pages (shaded areas) of blocks BlkM, BlkM+1, and BlkM+2 in the QLC area, the difference between the read count and the average read count is considered to be greater than or equal to a threshold.

[0115] In this state, it is assumed that the timing for the move process has arrived. For example, the move process may be performed simultaneously with garbage collection. As shown in Figure 26, the processor 11 determines the timing for the move process (S21). If the processor 11 determines, for example, that garbage collection is necessary (YES in S21), it obtains the read count from the L2P table 12a (S22). The processor 11 calculates the difference between the read count and the average read count (S41), and determines for each host address LBA whether the calculated difference is greater than or equal to a threshold (S42). For data where the calculated difference is greater than or equal to a threshold (YES in S42), the processor 11 moves it to the SLC area as shown by the arrow in Figure 27 (S24). For data where the calculated difference is less than a threshold (NO in S42), the processor 11 moves it to the QLC area (S25).

[0116] Thereafter, similarly, when a move operation is performed, data whose read count is determined to be more than a threshold higher than the average read count is moved to the SLC area. As a result, for subsequent reads, data whose read count is determined to be more than a threshold higher than the average read count is stored in the SLC area, which has high read disturb resistance, thereby suppressing the increase in error bits.

[0117] Furthermore, as the number of reads for each data increases, the amount of data moved to the SLC area increases, and the available space in the SLC area runs out. Therefore, if the available space in the SLC area falls below a predetermined threshold, for example, the processor 11 may perform a move process in which data with a relatively high number of reads is moved to the SLC area, and data with a relatively low number of reads is moved to the QLC area.

[0118] Figure 28 is a flowchart illustrating this movement process. Figure 29 is a diagram illustrating this movement process. Figure 29 shows blocks BlkN~BlkN+2 and BlkO~BlkO+2 in the SLC region.

[0119] Now, because the available space in the SLC area has fallen below a threshold, a move operation will be performed on blocks BlkN to BlkN+2. As shown in Figure 28, the processor 11 determines whether or not it is time to perform the move operation (S51). When it is time to perform the move operation (YES in S51), the processor 11 obtains the read count for the data stored in BlkN to BlkN+2 by referring to the L2P table 12a. The processor 11 moves (copies) a predetermined number of data with the highest read count to the SLC area (S54), and moves (copies) the remaining data to the QLC area (S55).

[0120] Alternatively, the difference between the number of reads and the average number of reads may be used to determine which data should be moved.

[0121] The example in Figure 29 shows that some of the data stored in BlkN~BlkN+2 is moved to block BlkO. The processor 11 moves the data stored in BlkN~BlkN+2 that is not moved to block BlkO to the QLC area. This makes it possible to increase the free space in the SLC area.

[0122] In this embodiment, data with a relatively large number of reads can be stored in an SLC area with excellent read disturb resistance, thereby suppressing the increase in error bits.

[0123] In the seventh embodiment, an example was shown in which the difference between the number of reads and the average number of reads was determined based on the host address LBA. However, the difference between the number of reads and the average number of reads may be determined based on the memory address PBA, and the move process may be performed. Also, although it was explained that the read count information in the management table is retained even when garbage collection is performed, the read count information may be reset after each garbage collection.

[0124] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0125] 1...Memory system, 2...Non-volatile memory, 3...Memory controller, 4...Host device, 11...Processor, 12...RAM, 12a...L2P table, 13...Buffer memory.

Claims

1. A non-volatile memory having a first region and a second region, each containing multiple blocks, A memory controller is electrically connected to the non-volatile memory and configured to write data to each block of the first region in a first mode and to write data to each block of the second region in a second mode. It is equipped with, The first mode is a write mode for writing data with a first number of bits per memory cell. The second mode is a writing mode for writing data with a second number of bits greater than the first number of bits per memory cell. The aforementioned memory controller The data received from the host is written to the first block of the first area in the first mode. A copy process is performed in which, of the data written to the first block, system data is copied to the second block of the first area using the first mode, and user data is copied to the third block of the second area using the second mode. Memory system.

2. The memory controller determines whether the data received from the host is system data or user data based on the range of the first logical addresses of the data received from the host, and then executes the copy process. The memory system according to claim 1.

3. The memory controller determines whether the data received from the host is system data or user data based on the identification information attached to the write command received from the host, and then executes the copy process. The memory system according to claim 1.

4. The aforementioned memory controller Identification information indicating whether the data received from the host is system data or user data is written to a column address in the first block that is contiguous to the column address where the data received from the host is written. The system obtains the identification information from the first block, determines whether the data received from the host is system data or user data based on the obtained identification information, and then executes the copy process. The memory system according to claim 1.

5. The memory controller determines the access status to the first logical address of the data received from the host, and based on the determination result, determines whether the data received from the host is system data or user data, and then executes the copy process. The memory system according to claim 1.

6. The memory controller determines that the data received from the host is system data if the number of reads to the first logical address is equal to or greater than a first threshold. The memory system according to claim 5.

7. The memory controller determines that the data received from the host is system data if the elapsed time since the last read to the first logical address is less than or equal to the second threshold. The memory system according to claim 5.

8. The memory controller determines that the data received from the host is system data if the number of reads to the first logical address is equal to or greater than the third threshold, and the number of writes to the first logical address is less than the fourth threshold. The memory system according to claim 5.

9. The memory controller determines that the data received from the host is system data if the elapsed time since the last write to the first logical address is greater than or equal to the fifth threshold, and the elapsed time since the last read to the first logical address is less than the sixth threshold. The memory system according to claim 5.

10. The memory controller determines that the data received from the host is system data if the difference between the number of reads to the first logical address and the average number of read accesses to the non-volatile memory is greater than or equal to a seventh threshold. The memory system according to claim 5.

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