Memory system

Abstract

To shorten the time period of data transfer.SOLUTION: A memory system in an embodiment comprises a nonvolatile memory that includes a plurality of memory packages, a plurality of memory dies provided in respective ones of the plurality of memory packages, and a plurality of planes provided in respective ones of the plurality of memory dies and respectively storing data and a memory controller that reads data from the nonvolatile memory based on round-robin processing. The memory controller, when selecting a plane to execute data transfer in the next cycle from among the plurality of planes, selects a plane belonging to a memory package different from a memory package to which the plane under data transfer belongs by the round-robin processing.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The embodiments relate to a memory system.

Background Art

[0002] NAND type flash memories capable of storing data non-volatiley are known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] Shorten the data transfer period.

Means for Solving the Problems

[0005] The memory system of the embodiments is The non-volatile memory includes at least a first memory device and a second memory device, and a controller electrically connected to the non-volatile memory, communicating with a host, and configured to control the order of transfers of a plurality of data items such that when two or more data items are ready to be transferred from the first memory device and at least one data item is ready to be transferred from the second memory device, the two or more data items are transferred discontinuously from the first memory device.

Brief Description of the Drawings

[0006] [Figure 1] A diagram showing the configuration of the information processing system of the embodiments. [Figure 2] A diagram showing the configuration of the non-volatile memory of the memory system of the first embodiment. [Figure 3] A diagram showing the configuration of the memory controller of the memory system of the first embodiment. [Figure 4] A diagram showing the functional configuration of the memory system of the first embodiment. [Figure 5]A flowchart illustrating the operation of the memory system according to the first embodiment. [Figure 6] A diagram illustrating the effects of the memory system of the first embodiment. [Figure 7] A diagram showing the functional configuration of the memory system in the second embodiment. [Figure 8] A flowchart illustrating the operation of the memory system in the second embodiment. [Modes for carrying out the invention]

[0007] The memory system of the embodiment will be described with reference to Figures 1 to 8.

[0008] The following description of this embodiment will be given in detail with reference to the drawings. In the following description, elements having the same function and configuration will be denoted by the same reference numeral. Furthermore, in each of the following embodiments, if components (for example, circuits, wiring, various voltages and signals, etc.) that are denoted with reference numerals / letters at the end for differentiation do not need to be distinguished from one another, the reference numerals / letters at the end will be omitted.

[0009] (Embodiment) (1) First Embodiment (a) Configuration (a-1) Configuration of Information Processing System 1 Figure 1 is a block diagram showing an example of the configuration of the information processing system 1 of this embodiment.

[0010] Information processing system 1 includes a host device HD and a memory system MS.

[0011] A host device (HD) is an electronic device such as a personal computer, a mobile device, or a server.

[0012] The memory system MS is a semiconductor storage device such as a memory card or an SSD (solid state drive). The memory system MS includes a non-volatile memory 10 and a memory controller 20.

[0013] The non-volatile memory 10 is a memory device that stores data non-volatilely. In the present embodiment, the non-volatile memory 10 is, for example, a NAND type flash memory. However, the non-volatile memory 10 may be a NOR type flash memory, MRAM (Magneto-resistive Random Access Memory), PRAM (Phase change Random Access Memory), ReRAM (Resistive Random Access Memory), or FeRAM (Ferroelectric Random Access Memory). The non-volatile memory 10 includes a plurality of memory packages 100. Each of the plurality of memory packages 100 includes a plurality of memory dies (memory chips) 110. Each of the plurality of memory dies 110 includes a plurality of planes PLN. In the present embodiment, storing (writing) data in the non-volatile memory 10 is also referred to as "non-volatilization".

[0014] The memory controller 20 is a control device that controls the non-volatile memory 10. The memory controller 20 is, for example, a semiconductor integrated circuit configured as a SoC (System On a Chip). The memory controller 20 controls the non-volatile memory 10 based on an instruction (request) received from the host device HD, and executes data read operations, write operations, and erase operations. The memory controller 20 may manage a plurality of non-volatile memories 10 collectively. The memory controller 20 is connected to the host device HD via the bus B1. The non-volatile memory 10 is connected to the memory controller 20 via the bus B2. Note that the host device HD and the memory controller 20 may be connected via a network.

[0015] (a-2) Hardware configuration of the memory system MS (a-2-1) Hardware configuration of the non-volatile memory 10 FIG. 2 is a block diagram showing an example of the hardware configuration of the non-volatile memory 10 of the present embodiment.

[0016] In a certain memory package 100 of the non-volatile memory 10, each memory die 110 includes, for example, a plurality of planes PLN and a control circuit 130.

[0017] Each of the plurality of planes PLN is a circuit that can operate independently of and in parallel (simultaneously) with each other. The set of the plurality of planes PLN is also called a memory core circuit 120.

[0018] The control circuit 130 is a set of a plurality of circuits that control the operations of the plurality of planes PLN.

[0019] Each plane PLN includes a memory cell array 121, a row decoder module 122, and a sense amplifier module 123.

[0020] The memory cell array 121 is a storage circuit that includes a set of a plurality of memory cells MC. The plurality of memory cells MC may be arranged two-dimensionally or three-dimensionally.

[0021] The row decoder module 122 is a decoder that decodes a row address. The row decoder module 122 selects a row (one block BLK) of the memory cell array 121 based on the decoding result. The row decoder module 122 transfers voltages to a plurality of wirings (word lines WL and bit lines BL) provided in the selected block BLK, respectively.

[0022] The sense amplifier module 123 is a sense circuit that senses data read from the selected block BLK based on the voltage of the bit line BL during a read operation. The sense amplifier module 123 transmits the read data to the memory controller 20 via the control circuit 130 during a read operation. The sense amplifier module 123 can apply a voltage corresponding to the data to be written to the memory cell MC to each bit line BL during a write operation.

[0023] The memory cell array 121 includes multiple blocks BLK (BLK0 to BLKn-1), where n is a natural number. A block BLK is used, for example, as a data erase unit. Each block BLK contains multiple pages. A page is a unit of data read, and a page is also a unit of data write. A page corresponds, for example, to data stored by multiple memory cells MC connected to a single word line WL. Multiple memory cells MC connected to a single word line WL can store data for multiple pages, depending on the number of bits of data each memory cell MC stores.

[0024] A block BLK includes multiple memory cells MC, multiple bit lines BL, and multiple word lines WL. Each memory cell MC stores at least one bit of data nonvolatilously. Each memory cell MC is associated with one bit line BL and one word line WL. Each memory cell MC is identified based on an address that identifies the word line WL and an address that identifies the bit line BL.

[0025] The control circuit 130 includes a memory interface (memory I / F) 131, a sequencer 132, and a driver module 133.

[0026] The memory interface 131 is a hardware interface connected to the memory controller 20 via bus B2. The memory interface 131 communicates with the non-volatile memory 10 and the memory controller 20 according to the interface standard. The interface standard supported by the memory interface 131 is, for example, the NAND interface standard. For example, the memory interface 131 sends the row address to each row decoder module 122. During a read operation, the memory interface 131 receives the read data from each of the sense amplifier modules 123. During a write operation, the memory interface 131 sends data to a certain sense amplifier module 123.

[0027] The sequencer 132 is a control circuit that controls the overall operation of the memory die 110. Based on commands received via the memory interface 131, the sequencer 132 controls the driver module 133, multiple row decoder modules 122, and multiple sense amplifier modules 123, etc., to perform read operations, write operations, erase operations, etc.

[0028] The driver module 133 is a circuit that generates voltages used for read, write, and erase operations. The driver module 133 is connected to each of the row decoder modules 122 via multiple signal lines. Based on the address received via the memory interface 131, the driver module 133 can change the voltage applied to each of the multiple signal lines corresponding to multiple word lines WL and multiple bit lines BL.

[0029] In the memory space of the non-volatile memory 10, the identification number (address value) of the memory package 100 corresponds to the upper-level address hierarchy in the memory space. The identification number (address) of the plane PLN corresponds to the lower-level address hierarchy in the memory space. The identification number (address) of the memory die 110 corresponds to the middle-level address hierarchy between the hierarchy of the memory package 100 and the hierarchy of the plane PLN in the memory space.

[0030] (a-2-2) Hardware configuration of the memory controller 20 Figure 3 is a block diagram showing an example of the hardware configuration of the memory controller 20 in this embodiment.

[0031] The memory controller 20 of this embodiment includes a host interface (host I / F) 21, a memory interface (memory I / F) 22, a CPU (Central Processing Unit) 23, an ECC (Error Correction Code) circuit 24, a ROM (Read Only Memory) 25, a RAM (Random Access Memory) 26, and a buffer memory 27.

[0032] The host interface 21 is a hardware interface connected to the host device HD via bus B1. The host interface 21 communicates with the host device HD and the memory controller 20 according to the interface standard. The interface standards supported by the host interface 21 are SATA (Serial Advanced Technology Attachment) and PCIe. TM Examples include PCI Express.

[0033] The memory interface 22 is a hardware interface connected to the non-volatile memory 10 via bus B2. The memory interface 22 communicates with the non-volatile memory 10 and the memory controller 20 according to the interface standard. The interface standard supported by the memory interface 22 is, for example, the NAND interface standard.

[0034] The CPU 23 is a processor. The CPU 23 controls the overall operation of the memory controller 20. The CPU 23 instructs the non-volatile memory 10 to write data via the memory interface 22 in accordance with write requests received via the host interface 21. The CPU 23 also instructs the non-volatile memory 10 to read data via the memory interface 22 in accordance with read requests received via the host interface 21.

[0035] The ECC circuit 24 is a circuit that performs ECC processing. ECC processing includes data encoding and decoding. The ECC circuit 24 encodes the data to be written to the non-volatile memory 10. The ECC circuit 24 decodes the data read from the non-volatile memory 10.

[0036] ROM25 is a non-volatile memory. ROM25 is, for example, an EEPROM. TMIt is an electrically erasable, programmable, read-only memory. ROM25 stores programs such as firmware. For example, the operation of the memory controller 20, which will be described later, is realized by the CPU 23 executing the firmware in ROM25.

[0037] RAM26 is volatile memory. RAM26 can be, for example, DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory). RAM26 is used as a working area for the CPU23. RAM26 stores management tables such as lookup tables (LUTs) that associate logical addresses with physical addresses. Management tables are a type of system data for the memory system MS. LUTs may also be called “address translation tables” or “logical address / physical address translation tables”.

[0038] The buffer memory 27 is volatile memory. The buffer memory 27 is such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory). The buffer memory 27 temporarily stores data received via the host I / F 21 or data received via the memory I / F 22. The buffer memory 27 may be externally connected to the memory controller 20.

[0039] (a-2-3) Functional configuration of the non-volatile memory 10 and memory controller 20 Figure 4 is a block diagram showing an example of the functional configuration of the non-volatile memory 10 and memory controller 20 in the memory system MS of this embodiment.

[0040] As described above, the non-volatile memory 10 includes multiple memory packages 100. Each of the multiple memory packages 100 is connected to the memory controller 20 via channels Ch(Ch0, Ch1, ...). A certain number (for example, two) of memory packages 100 are connected to one channel Ch. The set of multiple channels Ch constitutes bus B2.

[0041] Each memory package 100 includes multiple memory dies 110 and a NAND control unit 190. One memory package, for example, includes two memory dies 110. However, the number of memory dies 110 included in a memory package 100 may be three or more.

[0042] Each memory die 110 contains multiple plane PLNs. One memory die 110 contains, for example, two plane PLNs. However, the number of plane PLNs in a memory die 110 may be three or more. Each plane PLN independently executes an operation sequence according to a command.

[0043] The NAND control unit 190 is a functional block representing a collection of control circuits 130 for multiple memory dies 110. The NAND control unit 190 controls various operations of multiple plane PLNs of the memory package 100. In read operations, the NAND control unit 190 sends data read from the plane PLN to the memory controller 20. In write operations, the NAND control unit 190 sends data to be written to the non-volatile memory 10 to the plane PLN.

[0044] The memory controller 20 includes a command generation unit 210 and a plurality of channel control units 220.

[0045] The command generation unit 210 is a functional block that generates commands.

[0046] Each of the channel control units 220 is a functional block that controls one of several channels Ch.

[0047] The channel control unit 220 includes a read issuance unit 221, a read period end detection unit 222, and a data transfer control unit 223.

[0048] The read issuing unit 221 issues a read command to each of the multiple memory packages 100 belonging to channel Ch, based on the command.

[0049] The read period end detection unit 222 detects a plane PLN whose read period has ended from among multiple plane PLNs. The read period is the period from when the read operation of a plane PLN is started until it is completed. A plane PLN whose read period has ended is a plane PLN that is capable of data transfer during a read operation, or a plane PLN that is waiting for a data transfer instruction. For example, based on various functions, the read period end detection unit 222 can monitor the operating status of the memory package 100, the operating status of the memory die 110, and the operating status of the plane PLNs via the NAND control unit 190. Based on the monitoring results, the read period end detection unit 222 detects a plane (a plane capable of data transfer) PLN whose read period has ended. For example, the read period end detection unit 222 notifies the hierarchical state storage unit 30, described later, of the plane PLN whose read period has ended.

[0050] The data transfer control unit (also called the data output control unit) 223 controls the order of data transfer (data output) of data read from each memory package 100's plane PLN by round-robin processing. When the data transfer control unit 223 selects a plane PLN to perform data transfer in the next cycle from among multiple plane PLNs capable of data transfer, it preferentially selects a plane PLN belonging to a different memory package 100 (or memory die 110) than the one to which the plane PLN currently undergoing data transfer belongs, by round-robin processing. The data transfer control unit 223 is configured, for example, by software, hardware, or a combination of software and hardware.

[0051] The data transfer control unit 223 includes a hierarchical state storage unit 30 and a hierarchical round-robin scheduler 40.

[0052] The hierarchical state storage unit 30 stores various information regarding data transfer at each level, including a level containing multiple memory packages 100, a level containing multiple memory dies 110, and a level containing multiple plane PLNs. For example, based on a notification from the read period end detection unit 222, the hierarchical state storage unit 30 stores the read period end status of each memory package 100 (whether data transfer is possible or not, waiting for data transfer), the read period end status of each memory die 110, and the read period end status of the plane PLN. Here, the read operation end status indicates whether the data read from the plane can be transferred to the memory controller 20, depending on whether the read period has ended or not. The hierarchical state storage unit 30 can also send the stored information to the channel control unit 220 and / or the hierarchical round-robin scheduler 40.

[0053] The hierarchical round-robin scheduler (also called the round-robin control unit) 40 controls the execution timing of various processes for round-robin processing, the execution period of various operations, and various settings. For example, the hierarchical round-robin scheduler 40 hierarchically searches for data-transferable memory packages 100, data-transferable memory dies 110, and data-transferable planes PLN based on the information from the hierarchical state storage unit 30. The hierarchical round-robin scheduler 40 detects data-transferable planes PLN based on the search results from the round-robin processing. The hierarchical round-robin scheduler 40 selects a plane PLN on which to perform data transfer based on the detection results. The hierarchical round-robin scheduler 40 controls data transfer from the selected plane PLN.

[0054] The hierarchical state storage unit 30 includes a register area 300 and a logical operation unit 390.

[0055] Register area 300 stores information.

[0056] The logical operation unit 390 performs logical operations (for example, OR operations) on the values ​​of registers 322 and 332. The logical operation unit 390 may be provided outside the hierarchical state storage unit 30 as a component of the data transfer control unit 223.

[0057] The register area 300 includes the channel correspondence section 310.

[0058] The channel support unit 310 is provided for corresponding channels Ch between the non-volatile memory 10 and the memory controller 20. The channel support unit 310 stores information regarding the data transferable state of multiple memory packages 100 in the corresponding channel Ch during round-robin processing.

[0059] The channel support unit 310 includes a register 311, a plurality of registers 312, and a plurality of memory package support units 320.

[0060] Register 311 stores information (for example, the identification number or address value of the memory package 100) indicating which of the multiple memory packages 100 in the hierarchy of the corresponding channel Ch is the memory package 100 to be monitored in the round-robin process.

[0061] Each of the multiple registers 312 stores information indicating whether the corresponding memory package 100 has finished its read period (i.e., whether data transfer is possible) in the hierarchy of the memory package 100.

[0062] For example, if a memory package 100 is in a state where data transfer is impossible (i.e., the memory dies 110 of the memory package 100 do not contain any plane PLNs whose read period has ended), the register 312 corresponding to that memory package 100 stores a first value (N). The first value is, for example, one bit of data. One bit of data means either "0" data or "1" data.

[0063] Furthermore, for example, if a memory package 100 is in a state where data transfer is possible (i.e., at least one memory die 110 of the memory package 100 contains a plane PLN whose read period has ended), the register 312 corresponding to that memory package 100 stores a second value (Y) that is different from the first value. The second value is, for example, a 1-bit data. A 1-bit data can mean either "0" data or "1" data.

[0064] Furthermore, for example, the value of register 312 relating to a certain memory package 100 is determined based on the result of a logical operation on the values ​​of multiple registers 322 relating to a memory die 110 belonging to that memory package 100. The logical operation performed on the values ​​of the multiple registers 322 is, for example, a logical OR operation.

[0065] Each of the multiple memory package support units 320 corresponds to one of the multiple memory packages 100 belonging to channel Ch. Each of the multiple memory package support units 320 stores information regarding the data transfer-ready state of the multiple memory dies 110 of the corresponding memory package 100 during round-robin processing.

[0066] Each memory package corresponding section 320 includes register 321 and a plurality of registers 322.

[0067] Register 321 stores information (for example, the identification number or address value of the memory die 110) indicating which of the multiple memory dies 110 in the hierarchy of the memory dies 110 of the corresponding memory package 100 is the memory die 110 to be monitored in the round-robin process.

[0068] Each of the multiple registers 322 stores information indicating whether the corresponding memory die 110 has finished its read period in the hierarchy of the memory die 110.

[0069] For example, if a memory die 110 is in a state where data transfer is impossible (i.e., it does not contain a plane PLN whose read period has ended), the register 322 corresponding to that memory die 110 stores a third value (N). This third value is, for example, one bit of data.

[0070] Furthermore, for example, if a memory die 110 is in a state where data transfer is possible (i.e., it is in a state that includes a plane PLN whose read period has ended), the register 322 corresponding to that memory die 110 stores a fourth value (Y) that is different from the third value. The fourth value is, for example, 1 bit of data.

[0071] Furthermore, for example, the value of register 322 relating to a certain memory die 110 is determined based on the result of a logical operation on the values ​​of multiple registers 332 relating to a plane PLN belonging to that memory die 110. The logical operation performed on the values ​​of the multiple registers 332 is, for example, a logical OR operation.

[0072] Each memory package support section 320 includes multiple memory die support sections 330.

[0073] Each of the multiple memory die support units 330 corresponds to one of the multiple memory dies 110 belonging to the memory package 100. Each of the multiple memory die support units 330 stores information regarding the data transferable state of the multiple planes PLN of the corresponding memory die 110 in round-robin processing.

[0074] Each memory die corresponding section 330 includes a register 331 and a plurality of registers 332.

[0075] Register 331 stores information (for example, the identification number or address value of the plane PLN) indicating which of the multiple plane PLNs in the plane PLN hierarchy of the corresponding memory die 110 is the plane PLN to be monitored in the round-robin process.

[0076] Each of the multiple registers 332 stores information indicating whether the corresponding plane PLN in the plane PLN hierarchy has reached the end of its read period.

[0077] For example, if a certain plane PLN is in a state where data transfer is impossible (i.e., the read period has not yet ended), the register 332 corresponding to that plane PLN stores a fifth value (N). This fifth value is, for example, one bit of data.

[0078] Furthermore, for example, if a certain plane PLN is in a state where data transfer is possible (i.e., the read period has ended), the register 332 corresponding to that plane PLN stores a sixth value (Y) that is different from the fifth value. The sixth value is, for example, 1 bit of data.

[0079] Furthermore, for example, when the read period (tR) of a certain plane PLN ends, the value of register 332 corresponding to that plane PLN changes from the 5th value to the 6th value. When register 332 has the 6th value, the plane PLN corresponding to register 332 indicates that it is waiting for data transfer (a state in which data transfer is possible). When data transfer of a data-transferable plane PLN is completed, the value of register 332 corresponding to that plane PLN changes from the 6th value to the 5th value.

[0080] (b) Operation Figure 5 is a flowchart showing the operation of the memory system MS in the first embodiment.

[0081] The memory controller 20 performs round-robin processing for multiple data transfers from the non-volatile memory 10.

[0082] The data transfer control unit 223 of the memory controller 20 monitors the memory space of the corresponding memory packages 100 hierarchically using a hierarchical round-robin scheduler 40, based on information (data) from the hierarchical state storage unit 30, to determine the read period completion status (whether data transfer is possible or not) of multiple memory packages 100, the read period completion status of multiple memory dies 110, and the read period completion status of multiple plane PLNs.

[0083] Here, one channel Ch (for example, channel Ch <0> The round-robin processing and data transfer of the channel control unit 220 and memory package 100 related to ) will be described.

[0084] At the start of a data transfer or during a data transfer from a certain plane PLN, the hierarchical round-robin scheduler 40 determines the memory package 100 corresponding to the identification number stored in register 311 (S1). If no identification number is stored in register 311, the hierarchical round-robin scheduler 40 determines the channel Ch <0> The system determines which memory package 100 to target has a certain identification number (i). i is a non-negative integer. For example, if data transfer is currently in progress for a certain memory package 100, the system targets a different memory package 100 than the one currently performing the data transfer. If no identification number is stored in register 311, the hierarchical round-robin scheduler 40 stores the identification number of the target memory package 100 in register 311.

[0085] The hierarchical round-robin scheduler 40 determines whether the target memory package 100 is in a state where data transfer is possible (S2). Information on whether the target memory package 100 is in a state where data transfer is possible is stored in the corresponding register 312.

[0086] If the target memory package 100 is not in a state where data transfer is possible (S2 NO), the hierarchical round-robin scheduler 40 increments (adds 1) or decrements (subtracts 1) the value of register 311 (S3). In this way, the hierarchical round-robin scheduler 40 changes the value of register 311. After that, the hierarchical round-robin scheduler 40 performs the process in S1.

[0087] If the target memory package 100 is in a state where data transfer is possible (S2 YES), the hierarchical round-robin scheduler 40 determines which of the multiple memory dies 110 belonging to the target memory package 100 corresponds to the identification number stored in register 321 (S4). If no identification number is stored in register 321, the hierarchical round-robin scheduler 40 determines which memory die 110 has a certain identification number (j-th), where j is a non-negative integer. If no identification number is stored in register 321, the hierarchical round-robin scheduler 40 stores the identification number of the target memory die 110 in register 321.

[0088] The hierarchical round-robin scheduler 40 determines whether the target memory die 110 is in a state where data transfer is possible (S5). Information on whether the target memory die 110 is in a state where data transfer is possible is stored in the corresponding register 322.

[0089] If the target memory die 110 is not in a state where data transfer is possible (S5 NO), the hierarchical round-robin scheduler 40 increments or decrements the value of register 321 (S6). In this way, the hierarchical round-robin scheduler 40 changes the value of register 321. After that, the hierarchical round-robin scheduler 40 performs the process in S4.

[0090] If the target memory die 110 is in a state where data transfer is possible (S5 YES), the hierarchical round-robin scheduler 40 selects the target memory die 110 and then increments or decrements the value of register 321 (S7). In this way, the hierarchical round-robin scheduler 40 changes the value of register 321. This prevents the memory die 110 with the same identification number from being selected consecutively, even when multiple read operations are performed in succession.

[0091] The hierarchical round-robin scheduler 40 determines which of the multiple plane PLNs belonging to the selected memory die 110 corresponds to the plane PLN corresponding to the identification information stored in register 331 (S8). If no identification information is stored in register 331, the hierarchical round-robin scheduler 40 determines which plane PLN corresponds to a certain identification number (the kth). k is a non-negative integer. If no identification information is stored in register 331, the hierarchical round-robin scheduler 40 stores the identification number of the target plane PLN in register 331.

[0092] The hierarchical round-robin scheduler 40 determines whether the target plane PLN is in a state where data transfer is possible (S9). Information on whether the target plane PLN is in a state where data transfer is possible is stored in the corresponding register 332.

[0093] If the target plane PLN is not in a state where data transfer is possible (S9 NO), the hierarchical round-robin scheduler 40 increments or decrements the value of register 331 (S10). In this way, the hierarchical round-robin scheduler 40 changes the value of register 331. After that, the hierarchical round-robin scheduler 40 performs the process in S8.

[0094] If the target plane PLN is in a state where data transfer is possible (S9 YES), the hierarchical round-robin scheduler 40 determines the target plane PLN to be the plane PLN for data transfer (S11). The hierarchical round-robin scheduler 40 may change the value of register 331 after determining the plane PLN for data transfer. This prevents the selection of plane PLNs with the same identification number consecutively, even when multiple read operations are performed in succession.

[0095] The hierarchical round-robin scheduler 40 instructs the data transfer control unit 223 to transfer data to the plane PLN that is the target of the determined data transfer (S12).

[0096] When a data transfer is instructed, the data transfer control unit 223 causes the non-volatile memory 10 to output the data of the target plane PLN to the memory controller 20 (S13). The data is output to the memory controller 20 via the NAND control unit 190 and channel Ch. After the data transfer of the target plane PLN is completed, information indicating that data transfer is impossible is stored in the register 332 corresponding to the target plane PLN.

[0097] After the data transfer of the target plane PLN is completed, the hierarchical round-robin scheduler 40 checks whether the data transfer corresponding to all read commands has been completed (S14).

[0098] If data transfer for all read commands is not complete (S13 NO), the hierarchical round-robin scheduler 40 increments or decrements the value of register 311 (S15). Then, the hierarchical round-robin scheduler 40 performs the process in S1.

[0099] If data transfer for all read commands is complete (S13 YES), the memory controller 20 terminates the series of processes shown in Figure 5 (termination).

[0100] Figure 6 is a schematic diagram illustrating the data transfer process in the memory system MS of this embodiment, which uses round-robin processing to control the order of data transfer. In Figure 6, an example is shown in which two memory packages 100 perform data transfer in parallel. In Figure 6, "(1), (2), (3), ..., (15), (16)" indicate the order in which the read periods end.

[0101] By controlling the order of data transfer through round-robin processing, data (multiple data items) is output to channel Ch (bus B2) from each of the multiple memory packages 100.

[0102] In this embodiment, when the preceding data transfer of a plane PLN of a certain memory package 100 is completed, a plane PLN of a different memory package 100 from the one performing the preceding data transfer is selected from among one or more plane PLNs capable of data transfer.

[0103] Therefore, in this embodiment, data transfer of the plane PLN after the read period tR has ended is performed alternately from the two memory packages 100, regardless of the order in which the data read period tR ends within each memory package 100. When two consecutive data transfers are performed in different memory packages 100, no data output wait time tWHR2 occurs.

[0104] As a result, the memory system MS of this embodiment can suppress the occurrence of waiting time tWHR2 between data transfers.

[0105] Therefore, the memory system MS of this embodiment can shorten the time required to complete multiple data transfers.

[0106] When multiple memory dies 110 of a single memory package 100 transfer data in parallel based on a data transfer order set by round-robin processing, a plane PLN of a memory die 110 different from the memory die 110 performing the preceding data transfer is selected as the target for the next data transfer. After the completion of the preceding data transfer on a certain memory die 110, the data transfer of the other memory die 110 is performed by the selected plane PLN.

[0107] (c) Effects The memory system MS of the first embodiment searches for the memory package 100, memory die 110, and plane PLN that are the targets for data transfer following the data transfer in the previous cycle, for each memory package 100 and memory die 110, using a round-robin process. This ensures that the memory system MS of the first embodiment will select a plane PLN capable of performing data transfer within a certain number of cycles. Therefore, the memory system MS of the first embodiment can guarantee an upper limit on the data transfer latency.

[0108] (d) Summary When data transfer units are hierarchically searched for in the order of memory package 100, memory die 110, and plane PLN by round-robin processing, multiple memory packages 100 and / or memory dies 110 having different identification numbers tend to be selected sequentially (alternatingly) as targets for data transfer. Therefore, consecutive data transfers from memory packages 100 and / or memory dies 110 having the same identification number can be relatively avoided. As a result, the occurrence of waiting time between multiple data transfers is suppressed in the memory system MS of the first embodiment. Therefore, the memory system MS of the first embodiment can shorten the time for data transfer. The memory system MS of the first embodiment can make data transfer more efficient. The memory system MS of the first embodiment can improve the performance of the memory system.

[0109] (2) Second embodiment (a) Configuration Figure 7 is a schematic diagram showing the configuration of the memory system MS according to the second embodiment.

[0110] In the second embodiment, an index (identification number) Idx is assigned to each of the smallest units of data output. For example, each of the multiple planes PLN contained in the non-volatile memory 10 is a smallest unit of data output.

[0111] In the example shown in Figure 7, in the non-volatile memory 10, one Channel Ch contains two memory packages 100. One memory package 100 contains two memory dies 110. One memory die 110 contains two planes PLN.

[0112] In this case, the index Idx is assigned to each of the multiple plane PLNs, which are data transfer units, as follows:

[0113] The index Idx of "0" is assigned to the plane PLN of "0" belonging to the memory package 100 and the memory die 110 with the identification number "0".

[0114] The index Idx of "1" is assigned to the plane PLN of "0" which belongs to the memory package 100 with identification number "1" and the memory die 110 with identification number "0".

[0115] The index Idx of "2" is assigned to the plane PLN of "0" that belongs to the memory package 100 with identification number "0" and the memory die 110 with identification number "1".

[0116] The index Idx of "3" is assigned to the plane PLN of "0" that belongs to the memory package 100 and the memory die 110 with identification number "1".

[0117] The index Idx of "4" is assigned to the plane PLN of "1" which belongs to the memory package 100 and the memory die 110 with identification number "0".

[0118] The index Idx of "5" is assigned to the plane PLN of "1" that belongs to the memory package 100 with identification number "1" and the memory die 110 with identification number "0".

[0119] The index Idx of "6" is assigned to the plane PLN of "1" which belongs to the memory package 100 with identification number "0" and the memory die 110 with identification number "1".

[0120] The index Idx of "7" is assigned to the plane PLN of "1" that belongs to the memory package 100 and the memory die 110 with identification number "1".

[0121] Each of the two adjacent index Idx is associated with a memory package 100 with a different identification number.

[0122] For example, an array of multiple index Idx is set based on a numerical value where the number of the plane PLN is the most significant digit, the number of the memory package 100 is the least significant digit, and the number of the memory die 110 is the digit between the number of the plane PLN and the number of the memory package 100.

[0123] Thus, depending on the number of planes PLN within a single memory package 100, eight index Idx are set up for round-robin processing of data transfer.

[0124] In this embodiment, the data transfer control unit 223 includes a one-dimensional state storage unit 50 and a one-dimensional round-robin scheduler 60.

[0125] The one-dimensional state storage unit 50 includes a register area 500. The register area 500 includes multiple registers 501 and 502. Register 501 stores the value (m) of the index Idx to be monitored. m is a non-negative integer.

[0126] Each of the multiple registers 502 stores a value indicating whether the plane PLN corresponding to the index Idx is capable of transferring data. The values ​​of register 502 are controlled, for example, by the read period end detection unit 222.

[0127] Register 502 stores a seventh value (N) if the read period for the corresponding index Idx plane PLN has not yet ended (i.e., data transfer is not possible). The seventh value is a single bit of data ("0" data or "1" data).

[0128] Register 502 stores an eighth value (Y) that is different from the seventh value if the read period of the corresponding index Idx plane PLN has ended (data transfer is possible or pending). The eighth value is a 1-bit data ("0" data or "1" data).

[0129] The one-dimensional round-robin scheduler (round-robin control unit) 60 sets the value of the monitored index Idx to register 501.

[0130] The one-dimensional round-robin scheduler 60 monitors whether the plane PLN corresponding to the monitored index Idx is capable of data transfer, based on the values ​​of multiple registers 502.

[0131] For example, a one-dimensional round-robin scheduler 60 can control data transfer from each plane of the non-volatile memory 10.

[0132] (b) Operation Figure 8 is a flowchart showing the operation of the memory system MS according to the second embodiment.

[0133] At the start of a data transfer or during a data transfer from a certain plane PLN, the one-dimensional round-robin scheduler 60 determines the plane PLN with index Idx corresponding to the identification number stored in register 501 (S21).

[0134] The one-dimensional round-robin scheduler 60 determines whether the target plane PLN is capable of data transfer (S22).

[0135] If the target plane PLN is not capable of data transfer (S22 NO), the one-dimensional round-robin scheduler 60 changes the value of register 501 by incrementing or decrementing it (S23). Then, the one-dimensional round-robin scheduler 60 performs the process in S21.

[0136] If the target plane PLN is capable of data transfer (S22 YES), the one-dimensional round-robin scheduler 60 determines the target plane PLN to be the plane PLN for data transfer (S24).

[0137] The one-dimensional round-robin scheduler 60 instructs the data transfer control unit 223 to transfer data from the determined plane PLN (S25).

[0138] When data transfer is instructed, the data transfer control unit 223 causes the non-volatile memory 10 to output the data of the plane PLN to be transferred to the memory controller 20 (S26).

[0139] After the data transfer of the target plane PLN is completed, the one-dimensional round-robin scheduler 60 checks whether the data transfer for all read commands has been completed (S27).

[0140] If data transfer for all read commands is not complete (S27 NO), the one-dimensional round-robin scheduler 60 changes the value of register 501 (S28). Then, the one-dimensional round-robin scheduler 60 performs the process in S21.

[0141] If data transfer for all read commands is complete (S27 YES), the memory controller 20 terminates the series of processes shown in Figure 8 (termination).

[0142] (c) Summary In the memory system MS of the second embodiment, data transfers from the non-volatile memory 10 are managed in units of planes PLN, each assigned a different index Idx. This allows the memory system MS of the second embodiment to relatively easily control the order of multiple data transfers from the non-volatile memory 10.

[0143] In the memory system MS of the second embodiment, the multiple planes PLN are explored in a cycle corresponding to the number of index Idx. Therefore, in the second embodiment, each of the multiple planes PLN can be reliably selected as the target for data transfer. Thus, the memory system MS of the second embodiment can guarantee an upper limit on the data transfer latency.

[0144] In the second embodiment, the memory system MS can reduce the number of registers 501 that store the identification numbers of the monitored items by making the search hierarchy one-dimensional through round-robin processing. As a result, in the second embodiment, the size of the register area 500 of the state storage unit 50 can be reduced.

[0145] The memory system MS of the second embodiment can achieve substantially the same effects as the first embodiment. The memory system MS of the second embodiment can reduce the time for data transfer. The memory system MS of the second embodiment can improve the performance of the memory system.

[0146] (3) Others The embodiments are illustrative and the scope of the invention is not limited thereto. [Explanation of Symbols]

[0147] 1… Information processing system HD…Host device MS...Memory System 100...Memory package 110...Memory Dial PLN...Plain 222...Read period end detection unit 223...Data Transfer Control Unit 30... Hierarchical state memory unit 311, 312, 321, 322, 331, 332… registers 40…Hierarchical Round Robin Scheduler 50...One-dimensional state memory unit 501, 502… registers 60...One-dimensional round-robin scheduler

Claims

1. A non-volatile memory comprising at least a first memory device and a second memory device, A controller is electrically connected to the non-volatile memory, communicates with a host, and is configured to control the transfer order of a plurality of data items so that the two or more data items are transferred discontinuously from the first memory device when two or more data items are ready to be transferred from the first memory device and at least one data item is ready to be transferred from the second memory device. A memory system equipped with the following features.

2. Each of the first and second memory devices is a memory package, a memory die, or a plane of a memory die. The memory system according to claim 1.

3. The controller is configured to control the order of the transfer of the plurality of data items by instructing the non-volatile memory to transfer the plurality of data items in an order different from the order in which the plurality of data items are ready to be transferred within the non-volatile memory. The memory system according to claim 1.

4. The two or more data items ready to be transferred in the first memory device include at least a first data item and a second data item, The at least one data item that is ready to be transferred in the second memory device includes at least a third data item, The aforementioned controller, It is determined that the first and second data items are ready to be transferred from the first memory device, and that the third data item is ready to be transferred from the second memory device. The non-volatile memory is instructed to transfer the first data item from the first memory device, Before instructing the non-volatile memory to transfer the second data item from the first memory device, instruct the non-volatile memory to transfer the third data item from the second memory device, The non-volatile memory is instructed to transfer the second data item from the first memory device. The memory system according to claim 1, further configured as follows.

5. The first memory device includes a third memory device and a fourth memory device, The second memory device includes a fifth memory device. The first data item is transferred from the third memory device to the first memory device. The third data item is transferred from the fifth memory device to the second memory device. The second data item is transferred from the fourth memory device to the first memory device. The memory system according to claim 4.

6. Each of the first and second memory devices is a memory package, and each of the third, fourth, and fifth memory devices is a memory die. Or, Each of the first and second memory devices is a memory die, and each of the third, fourth, and fifth memory devices is a plane of the memory die. The memory system according to claim 5.

7. The controller is Even if the preparation for transferring the third data item from the second memory device is complete before the preparation for transferring the third data item from the second memory device is complete, the non-volatile memory is instructed to transfer the third data item from the second memory device before instructing the non-volatile memory to transfer the second data item from the first memory device. The memory system according to claim 4, configured as described above.

8. further comprising a first register, The aforementioned controller, The identifier of one of the first and second memory devices is stored in the first register. If any one of the two or more data items is transferred from the first memory device, the identifier of the second memory device is stored in the first register. The memory system according to claim 1, further configured as follows.

9. The memory system according to claim 8, wherein the controller is configured to determine which of the first and second memory devices is the target of data transfer, based at least on the information stored in the first register.

10. further comprising a second register, The aforementioned controller, When any one of the two or more data items is ready to be transferred from the first memory device, the identifier of the first memory device is stored in the second register. Based on the information stored in the second register, the memory device to be transferred is determined. The memory system according to claim 9, further configured as follows.

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