Semiconductor equipment

Abstract

To provide a semiconductor device that suppresses electrical oscillation generated by a gate capacitor with a simple additional circuit.SOLUTION: It has a first power module 7a having a first reference potential terminal 9a and a first control signal input terminal 8a, a second power module 7b connected in parallel to the first power module 7a and having a second reference potential terminal 9b and a second control signal input terminal 8b, a first capacitor 16a connected between the first control signal input terminal 8a and the first reference potential terminal 9a, and a first filter 17a connected in series with the first capacitor 16a in the path between the control terminals from the first control signal input terminal 8a to the second control signal input terminal 8b via the first capacitor 16a, and the first filter 17a has a frequency characteristic where the impedance increases as the frequency increases.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] This application relates to a semiconductor device.

Background Art

[0002] In recent years, semiconductor devices incorporated in power conversion devices for electric power trains of hybrid vehicles or electric vehicles are composed of power modules incorporating switching elements such as IGBTs (Insulated Gate Bipolar Transistors) or MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). When processing large amounts of power, multiple switching elements or power modules are connected in parallel and simultaneously switched to increase the power capacity that can be processed.

[0003] A switching element is operated by a drive circuit connected to a control signal input terminal (for example, the gate terminal of a MOSFET). The switching speed of such a switching element, that is, the current change speed di / dt and the voltage change speed dv / dt, are determined by the gate resistance of the drive circuit and the parasitic capacitance of the switching element (for example, Cgs and Cgd of a MOSFET). In addition to the elements that determine these switching speeds, a gate capacitor may be used to adjust dv / dt. Generally, a gate capacitor is connected to the control signal input terminal of a switching element and is used for purposes such as reducing switching losses or suppressing steep voltage changes by adjusting dv / dt.

[0004] However, since gate capacitors are generally mounted on the control board along with the drive circuit, a loop circuit is formed by, for example, the parasitic capacitance between the gate and source terminals of a MOSFET, the gate capacitor, the wiring on the control board, and the wiring of the power module terminals, and LC resonance or LC oscillation occurs in this loop circuit. Also, when multiple modules are connected in parallel, the impedance between the gates of the modules decreases due to passing through the gate capacitor, causing resonance or oscillation between the modules. When such electrical vibrations occur, there is a risk that control of the power converter may be lost due to malfunction of the switching element, failure of the switching element due to exceeding its withstand voltage, or failure of components on the control board.

[0005] As a technique for suppressing electrical vibrations in semiconductor devices equipped with gate capacitors, it has been proposed to provide a switch that connects or disconnects the gate capacitor and the gate of a switching element, thereby disconnecting the gate capacitor and the gate of the switching element when the gate capacitor is not needed (see, for example, Patent Document 1). [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2022-41081 [Overview of the project] [Problems that the invention aims to solve]

[0007] In the semiconductor device described in Patent Document 1, a circuit is provided to control a switch that connects and disconnects the gate capacitor and the gate of the switching element. The switch is operated by determining the desired timing to control the connection and disconnection of the gate capacitor and the gate of the switching element. If the circuit that determines the desired timing or the circuit that controls the switch malfunctions due to noise or component variations, for example, if the device is connected at the timing when disconnection is desired, electrical oscillations may occur. If the device is disconnected at the timing when connection is desired, the effect of the gate capacitor is not obtained, the switching speed of the switching element deviates from the design value, and excessive surges may occur, potentially causing the switching element to fail due to voltage breakdown. Thus, the need to control the operating timing of the connection and disconnection switches increases the difficulty of the design. Furthermore, there was a problem that large-scale additional circuits were required, such as a switch that connects and disconnects the gate capacitor and the gate of the switching element, and a control circuit that determines the timing of connecting and disconnecting the gate capacitor and operates the switch.

[0008] This invention was made to solve the above-mentioned problems and aims to provide a semiconductor device that suppresses electrical vibrations caused by the presence of a gate capacitor with a simple additional circuit. [Means for solving the problem]

[0009] The semiconductor device disclosed herein includes: a drive circuit that outputs a switching control signal from a gate voltage output terminal; a first power module containing a first semiconductor switching element and equipped with a first reference potential terminal and a first control signal input terminal into which a switching control signal is input; a second power module connected in parallel to the first power module and containing a second semiconductor switching element and equipped with a second reference potential terminal and a second control signal input terminal into which a switching control signal is input; a first resistor connected between the gate voltage output terminal and the first control signal input terminal; a second resistor connected between the gate voltage output terminal and the second control signal input terminal; a first capacitor connected between the first control signal input terminal and the first reference potential terminal; a second capacitor connected between the second control signal input terminal and the second reference potential terminal; and a first filter connected in series with the first capacitor in the control terminal path from the first control signal input terminal to the second control signal input terminal via the first and second capacitors. The device further includes a third resistor connected in series with the first capacitor in a first loop path from the first control signal input terminal through the first capacitor to the first reference potential terminal, and a fourth resistor connected in series with the second capacitor in a second loop path from the second control signal input terminal through the second capacitor to the second reference potential terminal. The first filter has a frequency characteristic in which the impedance increases as the frequency increases. The resistance of the third resistor is smaller than that of the first resistor, and the resistance of the fourth resistor is smaller than that of the second resistor. It is characterized by the following: [Effects of the Invention]

[0010] The semiconductor device disclosed herein includes a drive circuit that outputs a switching control signal from a gate voltage output terminal; a first power module that contains a first semiconductor switching element and has a first reference potential terminal and a first control signal input terminal into which a switching control signal is input; a second power module connected in parallel to the first power module and containing a second semiconductor switching element and has a second reference potential terminal and a second control signal input terminal into which a switching control signal is input; a first resistor connected between the gate voltage output terminal and the first control signal input terminal; a second resistor connected between the gate voltage output terminal and the second control signal input terminal; a first capacitor connected between the first control signal input terminal and the first reference potential terminal; a second capacitor connected between the second control signal input terminal and the second reference potential terminal; and a first filter connected in series with the first capacitor in the control terminal path from the first control signal input terminal to the second control signal input terminal via the first and second capacitors. The first filter has a frequency characteristic in which the impedance increases as the frequency increases, so that electrical oscillations caused by the presence of a gate capacitor can be suppressed with a simple additional circuit. [Brief explanation of the drawing]

[0011] [Figure 1] This is a schematic diagram of the power conversion device in Embodiment 1. [Figure 2] This is a circuit diagram of a semiconductor device according to Embodiment 1. [Figure 3] This is a circuit diagram of a semiconductor device as an example. [Figure 4] This figure shows the frequency characteristics of the impedance between the gate node and source node in the comparative semiconductor device. [Figure 5] This figure shows the frequency characteristics of the impedance between the gate node and the source node in the semiconductor device of Embodiment 1. [Figure 6] This is a circuit diagram of a semiconductor device according to Embodiment 2. [Figure 7]It is a diagram showing the time change of the gate-source current of the power module. [Figure 8] It is a diagram showing the time change of the gate-source voltage of the power module. [Figure 9] It is a diagram showing an example of the arrangement of the semiconductor device according to Embodiment 2 on the substrate. [Figure 10] It is a circuit diagram of a modification of the semiconductor device according to Embodiment 2. [Figure 11] It is a circuit diagram of the semiconductor device according to Embodiment 3.

Embodiments for Carrying Out the Invention

[0012] Hereinafter, a semiconductor device according to an embodiment for carrying out the present application will be described in detail with reference to the drawings. In each figure, the same reference numerals indicate the same or corresponding parts.

[0013] Embodiment 1. FIG. 1 is a schematic diagram of a power conversion device in Embodiment 1. The power conversion device in Embodiment 1 is an inverter circuit 1 that converts DC power into AC power. A DC power supply 2 is connected to the input section, and a motor 3, which is a load, is connected to the output of the inverter circuit 1. Here, when this power conversion device is applied to an electric vehicle or a hybrid vehicle, the DC power supply 2 is a power storage device, typically a battery composed of a secondary battery such as a nickel-hydrogen battery or a lithium-ion battery, and its voltage is about 200V to 1000V. The inverter circuit 1 is a three-phase inverter including a smoothing capacitor 4 for removing voltage ripple or noise at the input stage and semiconductor devices 5a, 5b, 5c, 5d, 5e, 5f each having a semiconductor switching element. It converts the power of the DC power supply 2 and outputs AC power from the power output nodes 6a, 6b, 6c to the motor 3 that drives the drive wheels of the electric vehicle or the hybrid vehicle.

[0014] FIG. 2 is a circuit diagram of the semiconductor device 5a according to Embodiment 1. Since the three phases constituting the power conversion device in Embodiment 1 have the same configuration, and the high-side arm and the low-side arm of each phase have the same configuration, the semiconductor device 5a of the low-side arm will be described.

[0015] The semiconductor device 5a includes a first power module 7a containing a first semiconductor switching element 11a and a second power module 7b containing a second semiconductor switching element 11b. The first power module 7a and the second power module 7b are connected in parallel. The first power module 7a includes a first control signal input terminal 8a which is a gate terminal to which a switching control signal is input, a first reference potential terminal 9a which is a source terminal, and a drain terminal 10a connected to the power output node 6a. The second power module 7b includes a second control signal input terminal 8b which is a gate terminal to which a switching control signal is input, a second reference potential terminal 9b which is a source terminal, and a drain terminal 10b connected to the power output node 6a. The first power module 7a and the second power module 7b operate simultaneously as a pair to output AC power to the same power output node 6a.

[0016] The first power module 7a and the second power module 7b are, for example, sealed with a molded resin, but may also be sealed with a gel or the like. Also, a 2-in-1 form power module in which the low-side arm and the high-side arm are sealed with a molded resin in the same package may be used by connecting two of them in parallel. Further, in the power conversion device in Embodiment 1, in order to output a large power, two power modules are connected in parallel for each phase. However, the number of power modules connected in parallel may be changed according to the target output power.

[0017] The first semiconductor switching element 11a and the second semiconductor switching element 11b are semiconductor switching elements for power control, such as MOSFETs or IGBTs. The first semiconductor switching element 11a and the second semiconductor switching element 11b are not limited to these, and other semiconductor switching elements such as bipolar transistors may also be used. In Figure 2, the first semiconductor switching element 11a and the second semiconductor switching element 11b are configured to use MOSFETs and the parasitic diode of the MOSFET as a freewheeling diode, but when using switching elements that do not have parasitic diodes, such as IGBTs, a configuration in which freewheeling diodes are connected in parallel may also be used.

[0018] The first semiconductor switching element 11a and the second semiconductor switching element 11b are formed on a semiconductor substrate made of a material such as silicon, silicon carbide, or gallium nitride, and the first semiconductor switching element 11a and the second semiconductor switching element 11b may be made of a wide-bandgap semiconductor with a bandgap wider than that of silicon. A MOSFET formed of silicon carbide, which is a wide-bandgap semiconductor, has high transconductance, which reduces losses during conduction, and it is possible to reduce switching losses by increasing the time change amount di / dt of the current generated during switching. Semiconductor switching elements with such high transconductance are generally prone to electrical oscillations. Therefore, by applying a wide-bandgap semiconductor to the semiconductor device according to Embodiment 1, the usefulness of the effect of the semiconductor device according to Embodiment 1 will be more clearly demonstrated.

[0019] Furthermore, in the semiconductor device according to Embodiment 1, the first power module 7a is provided with one first semiconductor switching element 11a, but a single power module may be provided with two or more semiconductor switching elements in order to output high power according to the target output power. In a configuration in which two or more semiconductor switching elements are connected in parallel inside a single power module, there is a risk of electrical vibration occurring between the semiconductor switching elements, and gate capacitors may be used to suppress such electrical vibration. Therefore, by applying a configuration in which two or more semiconductor switching elements are connected in parallel inside a single power module to the semiconductor device according to Embodiment 1, the usefulness of the semiconductor device according to Embodiment 1 will be more clearly demonstrated.

[0020] The first control signal input terminal 8a (gate terminal) of the first power module 7a is connected to the first resistor 12a, which is a gate resistor, and the other terminal of the first resistor 12a is connected to the gate voltage output terminal 14 of the drive circuit 13, which is a gate driver. That is, one terminal of the first resistor 12a is connected to the gate node 18a, and the other terminal of the first resistor 12a is connected to the gate voltage output terminal 14 of the drive circuit 13. The second control signal input terminal 8b (gate terminal) of the second power module 7b is connected to the second resistor 12b, which is a gate resistor, and the other terminal of the second resistor 12b is connected to the gate voltage output terminal 14 of the drive circuit 13, which is a gate driver. That is, one terminal of the second resistor 12b is connected to the gate node 18b, and the other terminal of the second resistor 12b is connected to the gate voltage output terminal 14 of the drive circuit 13. The drive circuit 13 outputs a switching control signal to the first control signal input terminal 8a of the first power module 7a via the first resistor 12a, and outputs a switching control signal to the second control signal input terminal 8b of the second power module 7b via the second resistor 12b, thereby driving the first power module 7a and the second power module 7b almost simultaneously. The first reference potential terminal 9a (source terminal) of the first power module 7a is connected to the source potential terminal 15 of the drive circuit 13 via source wiring, and the second reference potential terminal 9b (source terminal) of the second power module 7b is connected to the source potential terminal 15 of the drive circuit 13 via source wiring. By connecting the gate resistors, the first resistor 12a and the second resistor 12b, in this way, the impedance between the first control signal input terminal 8a of the first power module 7a and the second control signal input terminal 8b of the second power module 7b is increased, which has the effect of suppressing electrical oscillations between the first power module 7a and the second power module 7b. Furthermore, a configuration in which the first resistor 12a and the second resistor 12b are removed and a gate resistor is placed between the node connecting the first control signal input terminal 8a of the first power module 7a and the second control signal input terminal 8b of the second power module 7b and the gate voltage output terminal 14 is undesirable because it may generate electrical oscillations between the first power module 7a and the second power module 7b.

[0021] The first capacitor 16a, which is a gate capacitor, and the first filter 17a are connected in series. One terminal of the first capacitor 16a is connected to the gate node 18a, and the other terminal of the first filter 17a is connected to the source node 19. In other words, the first capacitor 16a is connected between the first control signal input terminal 8a and the first reference potential terminal 9a, and the first filter 17a is connected in series with the first capacitor 16a. The second capacitor 16b, which is a gate capacitor, and the second filter 17b are connected in series. One terminal of the second capacitor 16b is connected to the gate node 18b, and the other terminal of the second filter 17b is connected to the source node 19. In other words, the second capacitor 16b is connected between the second control signal input terminal 8b and the second reference potential terminal 9b, and the second filter 17b is connected in series with the second capacitor 16b. The first filter 17a and the second filter 17b suppress electrical vibrations that occur in the control terminal path from the first control signal input terminal 8a through the first capacitor 16a and the second capacitor 16b to the second control signal input terminal 8b. The first filter 17a and the second filter 17b have a frequency characteristic in which the impedance increases as the frequency increases. In the example shown in Figure 2, there are two filters, the first filter 17a and the second filter 17b, but it is also acceptable to have either the first filter 17a or the second filter 17b. As long as the first filter 17a is connected in series with the first capacitor 16a in the control terminal path from the first control signal input terminal 8a through the first capacitor 16a and the second capacitor 16b to the second control signal input terminal 8b, electrical vibrations that occur in the control terminal path can be suppressed.

[0022] Furthermore, in a configuration having a first resistor 12a and a second resistor 12b which are gate resistors, if a gate capacitor is connected between the gate voltage output terminal 14 and the source node 19, it behaves as if the gate capacitor were not connected. In such a state, the gate capacitor's function of reducing switching losses or suppressing sharp voltage changes by adjusting dv / dt is not performed.

[0023] Figure 3 is a circuit diagram of a semiconductor device according to the comparative example. Comparing the semiconductor device according to the comparative example in Figure 3 with the semiconductor device 5a according to Embodiment 1 in Figure 2, the semiconductor device according to the comparative example does not have the first filter 17a and the second filter 17b. The other configurations of the semiconductor device according to the comparative example are the same as those of the semiconductor device 5a according to Embodiment 1.

[0024] In the semiconductor device according to the comparative example shown in Figure 3, electrical oscillations may occur in the control terminal path from the first control signal input terminal 8a of the first power module 7a through the gate node 18a and the first capacitor 16a to the source node 19, and from the source node 19 through the second capacitor 16b and the gate node 18b to the second control signal input terminal 8b of the second power module 7b. This is because the impedance of the gate capacitors, the first capacitor 16a and the second capacitor 16b, is low in the high-frequency band. Therefore, in the band of about 10 MHz to 200 MHz, the impedance between the gate node 18a and the source node 19, and the impedance between the gate node 18b and the source node 19 become small, making it easy for electrical oscillations of about 10 MHz to 200 MHz to occur in the control terminal path. In other words, in the semiconductor device of Embodiment 1 shown in Figure 2, the frequency of electrical oscillations caused by the wiring between the first capacitor 16a and the second capacitor 16b in the control terminal path is, for example, 10 MHz to 200 MHz. Such electrical vibrations are a so-called inter-module resonance phenomenon, where charge is exchanged between the gates of power modules, and are one of the vibration phenomena caused by gate capacitors. In some cases, this can lead to malfunction of switching elements, failure of switching elements due to exceeding their voltage rating, or failure of components on the control board.

[0025] In the semiconductor device according to Embodiment 1 shown in Figure 2, since it is equipped with a first filter 17a and a second filter 17b, even if the gate capacitors, the first capacitor 16a and the second capacitor 16b, are provided, the impedance of the control terminal path can be increased in a bandwidth of about 10 MHz to 200 MHz, which includes the frequency of electrical oscillations in the control terminal path, thereby suppressing electrical oscillations.

[0026] Figure 4 shows the frequency characteristics of the impedance between the gate node 18a and the source node 19, and the impedance between the gate node 18b and the source node 19, in the semiconductor device according to the comparative example shown in Figure 3. The impedance decreases as the frequency increases. Figure 5 shows the frequency characteristics of the impedance between the gate node 18a and the source node 19, and the impedance between the gate node 18b and the source node 19, in the semiconductor device 5a of Embodiment 1 shown in Figure 2. The impedance is high in the bandwidth from several tens of MHz to about 200 MHz, and electrical oscillations in the bandwidth from several tens of MHz to about 200 MHz are suppressed in the semiconductor device 5a of Embodiment 1.

[0027] The frequency characteristics of the impedances of the first filter 17a and the second filter 17b should be such that the impedance near 0Hz is smaller than the impedance in the bandwidth of approximately 10 to 200MHz, which is the frequency of electrical oscillations occurring in the path including the control terminals, so as not to interfere with the role of the gate capacitors, the first capacitor 16a and the second capacitor 16b. For example, it is desirable that the impedance of the first filter 17a and the second filter 17b at frequencies below 1MHz is smaller than the impedance at the frequency of electrical oscillations occurring in the path including the control terminals. Furthermore, it is desirable that the magnitude of the impedance of the first filter 17a at 0Hz be smaller than the resistance value of the gate resistor, the first resistor 12a, and smaller than 1 ohm, and that the magnitude of the impedance of the second filter 17b at 0Hz be smaller than the resistance value of the gate resistor, the second resistor 12b, and smaller than 1 ohm.

[0028] If the impedance of the first filter 17a and the second filter 17b is large near 0Hz, for example, if the impedance of the first filter 17a and the second filter 17b is large at frequencies below 1MHz, the charging of the gate capacitors, the first capacitor 16a and the second capacitor 16b, will be slow, and they will behave as if the gate capacitors, the first capacitor 16a and the second capacitor 16b, were not connected. In this state, the gate capacitors will not perform their function of reducing switching or suppressing sharp voltage changes by adjusting dv / dt. Therefore, the impedance of the first filter 17a and the second filter 17b near 0Hz, for example, the impedance of the first filter 17a and the second filter 17b at frequencies below 1MHz, should be small. Furthermore, if the magnitude of the impedance of the first filter 17a and the second filter 17b at 0Hz is smaller than the resistance values ​​of the gate resistors, the first resistor 12a and the second resistor 12b, then even if there are large tolerances such as manufacturing variations in the resistance components of the first filter 17a and the second filter 17b, the switching speed of the first power module 7a and the second power module 7b will not be affected by manufacturing variations in the first filter 17a and the second filter 17b.

[0029] The first filter 17a and the second filter 17b may be bead elements, such as surface-mount type ferrite beads. Bead elements have frequency characteristics that increase impedance in the high-frequency band. By using bead elements as the first filter 17a and the second filter 17b, the impedance between the gate node 18a and the source node 19 increases from 10 MHz to 200 MHz, and the impedance between the gate node 18b and the source node 19 increases from 10 MHz to 200 MHz, thereby suppressing electrical oscillations. Furthermore, bead elements with various impedance frequency characteristics are available, so even if the mounting configuration changes and the frequency band of electrical oscillations changes, by selecting a bead element with appropriate characteristics, the impedance between the gate node 18a and the source node 19, and between the gate node 18b and the source node 19 can be increased in the desired frequency band to suppress electrical oscillations.

[0030] Furthermore, the first filter 17a and the second filter 17b may be coils constructed from printed circuit board wiring. By implementing the first filter 17a and the second filter 17b using coils constructed from printed circuit board wiring, it is possible to reduce the number of mounted components. Since the coil has a frequency characteristic in which the impedance increases from a low frequency band of about 0 Hz to a high frequency band, the impedance becomes large in the frequency band of electrical vibrations, and vibrations can be suppressed.

[0031] As described above, the semiconductor device according to Embodiment 1 includes a drive circuit 13 that outputs a switching control signal from a gate voltage output terminal 14, a first power module 7a that contains a first semiconductor switching element 11a and is equipped with a first reference potential terminal 9a and a first control signal input terminal 8a into which a switching control signal is input, a second power module 7b connected in parallel to the first power module 7a and containing a second semiconductor switching element 11b and is equipped with a second reference potential terminal 9b and a second control signal input terminal 8b into which a switching control signal is input, a first resistor 12a connected between the gate voltage output terminal 14 and the first control signal input terminal 8a, and the gate voltage output terminal 14 and the second control signal input terminal The circuit includes a second resistor 12b connected between the child 8b, a first capacitor 16a connected between the first control signal input terminal 8a and the first reference potential terminal 9a, a second capacitor 16b connected between the second control signal input terminal 8b and the second reference potential terminal 9b, and a first filter 17a connected in series with the first capacitor 16a in the control terminal path from the first control signal input terminal 8a through the first capacitor 16a and the second capacitor 16b to the second control signal input terminal 8b. The first filter 17a has a frequency characteristic in which the impedance increases as the frequency increases, so that electrical oscillations caused by the presence of a gate capacitor can be suppressed with a simple additional circuit.

[0032] Embodiment 2. Figure 6 is a circuit diagram of the semiconductor device 5a according to Embodiment 2. Comparing the circuit diagram of the semiconductor device 5a according to Embodiment 2 shown in Figure 6 with the circuit diagram of the semiconductor device 5a according to Embodiment 1 shown in Figure 2, a third resistor 20a and a fourth resistor 20b have been added. The other components of the semiconductor device according to Embodiment 2 are the same as those of the semiconductor device according to Embodiment 1.

[0033] The third resistor 20a is connected in series with the first capacitor 16a in the first loop path from the first control signal input terminal 8a through the first capacitor 16a to the first reference potential terminal 9a. In Figure 6, the third resistor 20a is connected between the first filter 17a and the source node 19. The fourth resistor 20b is connected in series with the second capacitor 16b in the second loop path from the second control signal input terminal 8b through the second capacitor 16b to the second reference potential terminal 9b. In Figure 6, the fourth resistor 20b is connected between the second filter 17b and the source node 19. Power modules generally have parasitic capacitances. The first power module 7a has a parasitic capacitance 71a, which is a gate-source parasitic capacitance Cgs, between the gate terminal, which is the first control signal input terminal 8a, and the source terminal, which is the first reference potential terminal 9a. It also has a parasitic capacitance 72a, which is a gate-drain parasitic capacitance Cgd, between the gate terminal, which is the first control signal input terminal 8a, and the drain terminal 10a. Furthermore, it has a parasitic capacitance 73a, which is a drain-source parasitic capacitance Cds, between the drain terminal 10a and the source terminal, which is the first reference potential terminal 9a. Similarly, the second power module 7b has parasitic capacitances 71b, 72b, and 73b. For example, in the semiconductor device according to the comparative example shown in Figure 3, a first capacitor 16a, which is a gate capacitor, is connected between the first control signal input terminal 8a and the first reference potential terminal 9a. This creates a first loop path that goes from the first capacitor 16a through the gate node 18a to the first control signal input terminal 8a, then through the parasitic capacitance 71a, and returns to the first reference potential terminal 9a, the source node 19, and the first capacitor 16a. In this first loop path, LC resonance, which is an electrical oscillation, occurs. When LC resonance occurs due to the connection of the gate capacitor, the voltage between the first control signal input terminal 8a, which is the gate terminal of the first power module 7a, and the first reference potential terminal 9a, which is the source terminal, oscillates. This affects the current between the drain terminal 10a and the first reference potential terminal 9a, which oscillates, potentially causing a sharp current change. If the surge generated by such a sharp current change exceeds the breakdown voltage of the semiconductor switching element, the semiconductor switching element may be destroyed.

[0034] As shown in the semiconductor device according to Embodiment 2 in Figure 6, by connecting the third resistor 20a in series with the first capacitor 16a in the first loop path from the first control signal input terminal 8a through the first capacitor 16a to the first reference potential terminal 9a, LC resonance superimposed on the gate-source current flowing through the parasitic capacitance 71a of the first power module 7a can be suppressed. As a result, LC resonance superimposed on the gate-source voltage of the first power module 7a can be suppressed, preventing damage to the semiconductor switching element. Similarly, the fourth resistor 20b can also suppress LC resonance superimposed on the gate-source voltage of the second power module 7b, preventing damage to the semiconductor switching element.

[0035] Figure 7 shows the time variation of the gate-source current of the first power module 7a, which is the current between the first control signal input terminal 8a and the first reference potential terminal 9a. The dotted line shows the time variation of the gate-source current of the first power module 7a in the comparative example shown in Figure 3, and the solid line shows the time variation of the gate-source current of the first power module 7a in Embodiment 2 shown in Figure 6. In the gate-source current of the comparative example (dotted line), LC resonance occurs due to the implementation of a gate capacitor, but in the gate-source current of Embodiment 2 (solid line), LC resonance is suppressed. Figure 8 shows the time variation of the gate-source voltage of the first power module 7a, which is the voltage between the first control signal input terminal 8a and the first reference potential terminal 9a. The dotted line shows the time variation of the gate-source voltage of the first power module 7a in the comparative example shown in Figure 3, and the solid line shows the time variation of the gate-source voltage of the first power module 7a in Embodiment 2 shown in Figure 6. In the comparative example shown by the dotted line, LC resonance occurs due to the implementation of the gate capacitor at the gate-source voltage, but in the embodiment 2 shown by the solid line, LC resonance is suppressed at the gate-source voltage.

[0036] In the semiconductor device of Embodiment 2 shown in Figure 6, the implementation is simplified by connecting a third resistor 20a between the first filter 17a and the source node 19, and a fourth resistor 20b between the second filter 17b and the source node 19. However, if the third resistor 20a is connected in series with the first capacitor 16a in the first loop path from the first control signal input terminal 8a through the first capacitor 16a to the first reference potential terminal 9a, and the fourth resistor 20b is connected in series with the second capacitor 16b in the second loop path from the second control signal input terminal 8b through the second capacitor 16b to the second reference potential terminal 9b, a similar effect of suppressing LC resonance, which is an electrical oscillation, can be obtained.

[0037] Furthermore, if the resistance value of the third resistor 20a is selected to be smaller than the resistance value of the gate resistor, the first resistor 12a, and greater than 1 ohm, the first filter 17a can suppress LC resonance, which is an electrical oscillation, without interfering with the role of the gate capacitor, the first capacitor 16a. Similarly, if the resistance value of the fourth resistor 20b is selected to be smaller than the resistance value of the gate resistor, the second resistor 12b, and greater than 1 ohm, the second filter 17b can suppress LC resonance, which is an electrical oscillation, without interfering with the role of the gate capacitor, the second capacitor 16b.

[0038] Figure 9 shows an example of the arrangement of the semiconductor device 5a on a substrate according to Embodiment 2 shown in Figure 6. Figure 9 shows the arrangement of the drive circuit 13, first resistor 12a, second resistor 12b, first capacitor 16a, first filter 17a, third resistor 20a, second capacitor 16b, second filter 17b, and fourth resistor 20b on the substrate 21. The first resistor 12a, second resistor 12b, first filter 17a, second filter 17b, third resistor 20a, fourth resistor 20b, first capacitor 16a, second capacitor 16b, and drive circuit 13 may be mounted on a single substrate as shown in Figure 9. The first filter 17a, second filter 17b, third resistor 20a, fourth resistor 20b, first capacitor 16a, and second capacitor 16b can be easily constructed using surface-mount type elements. For example, by configuring the first filter 17a and the second filter 17b using chip bead elements, the third resistor 20a and the fourth resistor 20b using chip resistor elements, and the first capacitor 16a and the second capacitor 16b using chip capacitor elements, the components can be easily mounted on the same substrate as the drive circuit 13, eliminating the need to provide additional space and avoiding an increase in the size of the semiconductor device due to the addition of electrical vibration suppression functions.

[0039] Figure 10 is a circuit diagram of a modified example of the semiconductor device 5a according to Embodiment 2. Comparing the circuit diagram of the modified example of the semiconductor device 5a according to Embodiment 2 shown in Figure 10 with the circuit diagram of the semiconductor device 5a according to Embodiment 2 shown in Figure 6, the connection positions of the first filter and the second filter are different. In the modified example shown in Figure 10, the first filter 17c is connected between the first control signal input terminal 8a and the gate node 18a of the first power module 7a, and the second filter 17d is connected between the second control signal input terminal 8b and the gate node 18b of the second power module 7b. That is, the first filter 17c is connected between the first control signal input terminal 8a and the first capacitor 16a of the first power module 7a, and the second filter 17d is connected between the second control signal input terminal 8b and the second capacitor 16b of the second power module 7b. At the frequency of electrical oscillations in the path between control terminals, the impedance between the first power module 7a and the gate node 18a increases, and the impedance between the second power module 7b and the gate node 18b also increases, so that electrical oscillations can be suppressed even in the modified semiconductor device 5a shown in Figure 10. In an actual circuit, the more effective option may be selected from the semiconductor device circuit shown in Figure 6 and the semiconductor device circuit shown in Figure 10, and the first and second filters may be placed at both the positions of the first filter 17a and the second filter 17b shown in Figure 7 and the positions of the first filter 17c and the second filter 17d shown in Figure 10.

[0040] Embodiment 3. Figure 11 is a circuit diagram of the semiconductor device 5a according to Embodiment 3. The semiconductor device 5a according to Embodiment 3 comprises only one power module, the first power module 7a. Also, similar to the semiconductor device 5a according to Embodiment 2 shown in Figure 6, a first resistor 12a is connected between the gate voltage output terminal 14 of the drive circuit 13 and the first control signal input terminal 8a, a first capacitor 16a is connected between the first control signal input terminal 8a and the first reference potential terminal 9a, and a third resistor 20a is connected in series with the first capacitor 16a in the first loop path from the first control signal input terminal 8a through the first capacitor 16a to the first reference potential terminal 9a.

[0041] In Embodiments 1 and 2, a semiconductor device equipped with two power modules, a first power module 7a and a second power module 7b, was described. However, if the semiconductor device is equipped with only one power module, the first power module 7a, then no electrical oscillation occurs between the power modules, and therefore, as shown in Figure 11, the configuration may not include the first filter 17a. In the semiconductor device 5a according to Embodiment 3 shown in Figure 11, the LC resonance, which is an electrical oscillation that occurs in the first loop path from the first capacitor 16a through the gate node 18a to the first control signal input terminal 8a, and then returns via the parasitic capacitance 71a to the first reference potential terminal 9a, source node 19, and first capacitor 16a, can be suppressed by the third resistor 20a.

[0042] Furthermore, each component constituting the semiconductor device 5a according to Embodiment 3 can be modified, numerically set, mounted, and selected in the same way as the semiconductor device 5a according to Embodiment 1 or Embodiment 2. For example, it is desirable that the resistance value of the third resistor 20a is smaller than the resistance value of the first resistor 12a and greater than 1 ohm. Also, the first semiconductor switching element 11a may be made of a wide-bandgap semiconductor. Moreover, the first resistor 12a, the third resistor 20a, the first capacitor 16a, and the drive circuit 13 may be mounted on a single substrate.

[0043] Although this application describes various exemplary embodiments, the various features, aspects, and functions described in one or more embodiments are not limited to the application of a particular embodiment, but can be applied individually or in various combinations to the embodiments. Accordingly, countless variations not illustrated are conceivable within the scope of the art disclosed herein. These include, for example, modifying, adding or omitting at least one component, or even extracting at least one component and combining it with components of other embodiments.

[0044] The various aspects of this disclosure are summarized below as an appendix.

[0045] (Note 1) A drive circuit that outputs a switching control signal from the gate voltage output terminal, A first power module containing a first semiconductor switching element and equipped with a first reference potential terminal and a first control signal input terminal into which the switching control signal is input, A second power module is connected in parallel to the first power module, contains a second semiconductor switching element, and is equipped with a second reference potential terminal and a second control signal input terminal to which the switching control signal is input. A first resistor connected between the gate voltage output terminal and the first control signal input terminal, A second resistor connected between the gate voltage output terminal and the second control signal input terminal, A first capacitor connected between the first control signal input terminal and the first reference potential terminal, A second capacitor connected between the second control signal input terminal and the second reference potential terminal, The control terminal path from the first control signal input terminal to the second control signal input terminal via the first capacitor and the second capacitor includes a first filter connected in series with the first capacitor, The semiconductor device is characterized in that the first filter has a frequency characteristic in which the impedance increases as the frequency increases. (Note 2) The system includes a second filter connected in series with the second capacitor between the second control signal input terminal and the second reference potential terminal, and having a frequency characteristic in which the impedance increases as the frequency increases. The semiconductor device according to Appendix 1, characterized in that the first filter is connected in series with the first capacitor between the first control signal input terminal and the first reference potential terminal. (Note 3) The semiconductor device according to Appendix 2, characterized in that the impedance of the first filter and the second filter at frequencies of 1 MHz or less is smaller than the impedance at frequencies of electrical oscillations occurring in the path including the control terminal path. (Note 4) The magnitude of the impedance of the first filter at 0 Hz is smaller than the resistance value of the first resistor. The semiconductor device according to Appendix 2 or 3, characterized in that the magnitude of the impedance of the second filter at 0 Hz is smaller than the resistance value of the second resistor. (Note 5) The semiconductor device according to any one of the appendices 2 to 4, characterized in that the first filter and the second filter have an impedance of 1 ohm or less at 0 Hz. (Note 6) The semiconductor device according to any one of the appendices 2 to 5, characterized in that the first filter and the second filter are bead elements. (Note 7) The semiconductor device according to any one of the appendices 2 to 5, characterized in that the first filter and the second filter are coils composed of printed circuit board wiring. (Note 8) A third resistor connected in series with the first capacitor in the first loop path from the first control signal input terminal through the first capacitor to the first reference potential terminal, The semiconductor device according to any one of the appendices 1 to 7, further comprising a fourth resistor connected in series with the second capacitor in a second loop path from the second control signal input terminal through the second capacitor to the second reference potential terminal. (Note 9) The resistance value of the third resistor is smaller than the resistance value of the first resistor. The semiconductor device according to Appendix 8, characterized in that the resistance value of the fourth resistor is smaller than the resistance value of the second resistor. (Note 10) The semiconductor device according to Appendix 9, characterized in that the resistance values ​​of the third resistor and the fourth resistor are greater than 1 ohm. (Note 11) The semiconductor device according to any one of the appendices 1 to 10, characterized in that the first semiconductor switching element and the second semiconductor switching element are made of a wide bandgap semiconductor. (Note 12) The semiconductor device according to any one of the appendices 2 to 7, characterized in that the first filter, the second filter, the drive circuit, the first resistor, the second resistor, the first capacitor, and the second capacitor are mounted on a single substrate. (Note 13) A drive circuit that outputs a switching control signal from the gate voltage output terminal, A first power module containing a first semiconductor switching element and equipped with a first reference potential terminal and a first control signal input terminal into which the switching control signal is input, A first resistor connected between the gate voltage output terminal and the first control signal input terminal, A first capacitor connected between the first control signal input terminal and the first reference potential terminal, A semiconductor device comprising a third resistor connected in series with the first capacitor in a first loop path from the first control signal input terminal through the first capacitor to the first reference potential terminal. (Note 14) The semiconductor device according to Appendix 13, characterized in that the resistance value of the third resistor is smaller than the resistance value of the first resistor. (Note 15) The semiconductor device according to Appendix 14, characterized in that the resistance value of the third resistor is greater than 1 ohm. (Note 16) The semiconductor device according to any one of the appendices 13 to 15, characterized in that the first semiconductor switching element is made of a wide-bandgap semiconductor. (Note 17) The semiconductor device according to any one of the appendices 13 to 16, characterized in that the drive circuit, the first resistor, and the first capacitor are mounted on a single substrate. [Explanation of Symbols]

[0046] 1 Inverter circuit, 2 DC power supply, 3 Motor, 4 Smoothing capacitor, 5a, 5b, 5c, 5d, 5e, 5f Semiconductor device, 6a, 6b, 6c Power output node, 7a First power module, 7b Second power module, 8a First control signal input terminal, 8b Second control signal input terminal, 9a First reference potential terminal, 9b Second reference potential terminal, 10a, 10b Drain terminal, 11a First semiconductor switching element, 11b Second semiconductor switching element, 12a First resistor, 12b Second resistor, 13 Drive circuit, 14 Gate voltage output terminal, 15 Source potential terminal, 16a First capacitor, 16b Second capacitor, 17a First filter, 17b Second filter, 17c First filter, 17d Second filter, 18a, 18b Gate node, 19 Source node, 20a Third resistor, 20b Fourth resistor, 21 Substrate, 71a, 71b, 72a, 72b, 73a, 73b Parasitic capacitance.

Claims

1. A drive circuit that outputs a switching control signal from the gate voltage output terminal, A first power module containing a first semiconductor switching element and equipped with a first reference potential terminal and a first control signal input terminal into which the switching control signal is input, A second power module is connected in parallel to the first power module, contains a second semiconductor switching element, and is equipped with a second reference potential terminal and a second control signal input terminal to which the switching control signal is input. A first resistor connected between the gate voltage output terminal and the first control signal input terminal, A second resistor connected between the gate voltage output terminal and the second control signal input terminal, A first capacitor connected between the first control signal input terminal and the first reference potential terminal, A second capacitor connected between the second control signal input terminal and the second reference potential terminal, In the control terminal path from the first control signal input terminal to the second control signal input terminal via the first capacitor and the second capacitor, a first filter is connected in series with the first capacitor, A third resistor connected in series with the first capacitor in the first loop path from the first control signal input terminal through the first capacitor to the first reference potential terminal, The device comprises a second loop path from the second control signal input terminal through the second capacitor to the second reference potential terminal, and a fourth resistor connected in series with the second capacitor, The first filter has a frequency characteristic in which the impedance increases as the frequency increases. The resistance value of the third resistor is smaller than the resistance value of the first resistor. A semiconductor device characterized in that the resistance value of the fourth resistor is smaller than the resistance value of the second resistor.

2. The system includes a second filter connected in series with the second capacitor between the second control signal input terminal and the second reference potential terminal, and having a frequency characteristic in which the impedance increases as the frequency increases. The semiconductor device according to claim 1, characterized in that the first filter is connected in series with the first capacitor between the first control signal input terminal and the first reference potential terminal.

3. The semiconductor device according to claim 2, characterized in that the impedance of the first filter and the second filter at frequencies of 1 MHz or less is smaller than the impedance at frequencies of electrical oscillations occurring in the path including the control terminal path.

4. The magnitude of the impedance of the first filter at 0 Hz is smaller than the resistance value of the first resistor. The semiconductor device according to claim 2, characterized in that the magnitude of the impedance of the second filter at 0 Hz is smaller than the resistance value of the second resistor.

5. The semiconductor device according to claim 2, characterized in that the first filter and the second filter have an impedance of 1 ohm or less at 0 Hz.

6. The semiconductor device according to claim 2, characterized in that the first filter and the second filter are bead elements.

7. The semiconductor device according to claim 2, characterized in that the first filter and the second filter are coils formed by printed circuit board wiring.

8. The semiconductor device according to claim 1, characterized in that the resistance values ​​of the third resistor and the fourth resistor are greater than 1 ohm.

9. The semiconductor device according to claim 1, characterized in that the first semiconductor switching element and the second semiconductor switching element are made of a wide bandgap semiconductor.

10. The semiconductor device according to claim 2, characterized in that the first filter, the second filter, the drive circuit, the first resistor, the second resistor, the first capacitor, and the second capacitor are mounted on a single substrate.

11. A drive circuit that outputs a switching control signal from a gate voltage output terminal, A first power module containing a first semiconductor switching element and equipped with a first reference potential terminal and a first control signal input terminal into which the switching control signal is input, A first resistor connected between the gate voltage output terminal and the first control signal input terminal, A first capacitor connected between the first control signal input terminal and the first reference potential terminal, The device comprises a first loop path from the first control signal input terminal through the first capacitor to the first reference potential terminal, and a third resistor connected in series with the first capacitor, A semiconductor device characterized in that the resistance value of the third resistor is smaller than the resistance value of the first resistor.

12. The semiconductor device according to claim 11, characterized in that the resistance value of the third resistor is greater than 1 ohm.

13. The semiconductor device according to claim 11, characterized in that the first semiconductor switching element is made of a wide bandgap semiconductor.

14. The semiconductor device according to claim 11, characterized in that the drive circuit, the first resistor and the first capacitor are mounted on a single substrate.

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