Surface-emitting laser, method for manufacturing a surface-emitting laser

Abstract

The extended vertical-cavity surface-emitting laser (VCSEL) includes an epitaxially laterally overgrown semiconductor portion, a III-nitride active region between a hole-injecting III-nitride layer and an electron-injecting III-nitride layer, and a nanoporous III-nitride layer on the electron-injecting III-nitride layer side.

Description

[Technical Field]

[0001] The present invention relates to a group III nitride vertical cavity surface-emitting laser (VCSEL) having a nanoporous GaN DBR, and to a method for manufacturing a group III nitride VCSEL having a nanoporous GaN DBR. [Background technology]

[0002] This application, as indicated throughout this specification, refers to numerous patent or non-patent publications by reference numbers in parentheses, i.e., []. A list of these publications, arranged according to these reference numbers, can be found below in sections titled “Non-Patent Literature” or “Patent Literature.” "List of citations" "Non-patent literature"

[0003] [NPL1] Appl.Phys.Lett.Volume 92, Page 141102 (2008) [NPL2] Appl.Phys.Express, Vol. 12, p. 44004 (2019) [NPL3] Sci.Rep. Vol. 8, p. 10350 (2018) [NPL4] Jpn.J.Appl.Phys.Vol.58, SC0806(2019) [NPL5] Appl.Phys.Express, Vol. 11, p. 112101 (2018) [NPL6] Appl.Phys.Lett.Volume 101, Page 151113 (2012) [NPL7] ACS Photonics, vol. 2, pp. 980-986 (2015) [NPL8] Sci.Rep. Vol. 7, p. 45344 (2017) [NPL9] Appl.Phys.Lett.Volume 112, Page 041109 (2018) [NPL10] Scr.Mater, Vol. 156, pp. 10-13 (2018) [NPL11] Appl.Phys.Express 2012, Vol. 5, p. 092104 [NPL12] Optics Express, Volume 27, Page 24717 (2019) [NPL13] Appl.Phys.Express, Volume 13, Page 041003 (2020) [NPL14] Appl.Phys.Express, Volume 14, Page 031002 (2021) [NPL15] Applied Phys. Lett. Volume 119, Page 142103 (2021) [NPL16] Crystals, Vol. 11, No. 12, pp. 1563, (2021) [NPL17] "Dry etching for coherent refractive index microlens arrays" by MBStern and TRJay, Opt.Eng. Vol. 33, pp. 3547-3551 (1994).

[0004] Surface-emitting lasers are also known as vertical-cavity surface-emitting lasers (VCSELs). A VCSEL comprises a semiconductor active region positioned between an n-side semiconductor region and a p-side semiconductor region, and two distributed Bragg reflectors called DBRs that function as high-reflectivity mirrors. The semiconductor active region, also known as the gain medium, is positioned between the two DBRs so that the semiconductor active region and the DBRs form an optical resonator. The n-side and p-side regions inject their respective carriers, namely electrons and holes, into the active region, where these carriers recombine to generate light. The light or electromagnetic radiation thus produced is reflected repeatedly by the DBRs and travels through the optical resonator, leading to laser oscillation. One of the DBRs in a VCSEL is a less reflective mirror and is used to emit the laser beam.

[0005] Gallium nitride (GaN) VCSELs have recently attracted increasing research attention due to their ability to emit light in the visible and ultraviolet (UV) regions. This opens up a variety of new application spaces in displays, solid-state lighting including automotive and residential lighting, transmission, and communications. One particularly exciting application is when blue-emitting GaN VCSELs are combined with phosphors to function simultaneously as both a spontaneous light source and a data transmission device. This application will treat all new AR / VR uses, smartphones, and conventional displays from a new perspective by adding communication capabilities to each light-emitting pixel.

[0006] While GaAs-based infrared VCSELs have incorporated mature manufacturing techniques, Group III nitride-based VCSELs remain industrially unfeasible due to technical challenges such as conductive dielectric Bragg reflectors (DBRs). Continuous-wave (CW) laser oscillation at 462 nm from electrically injected GaN VCSELs was first demonstrated in 2008 at a temperature of 77 K [NPL1]. Since then, there has been considerable progress in terms of power, efficiency, threshold current, laser oscillation wavelength, and room-temperature stability. However, industrial adoption has yet to be achieved. As mentioned above, one of the problems is the n-side DBR mirror, which is generally a dielectric DBR that causes thermal instability in device operation. Traditionally, after careful polishing of the host substrate, the dielectric DBR is deposited on the n-side of the VCSEL. On the host substrate, alternative methods such as epitaxial DBRs and nanoporous GaN DBRs are emerging, and VCSELs with long optical GaN resonators have been proposed in the literature for better thermal stability. While these methods were somewhat effective, the main concerns were issues such as the high cost of GaN substrates and the inability to obtain larger sizes of GaN substrates even at high prices. On the other hand, proposed epitaxial DBR methods increase growth time and hinder the maintenance of device layer quality, requiring the removal of expensive GaN substrates in cases such as long GaN resonators and nanoporous GaN DBR resonators.

[0007] VCSELs with long optical resonators and curved lenses refocus the electric field to the gain medium, thereby reducing diffraction losses due to the long resonator length [NPL2~NPL4]. Until 2022, Sony's long resonator design held performance records of 15.8 mW of power CW output, a threshold current of 0.25 mA, and a wall-plug efficiency (WPE) of 9.5%. Long optical GaN resonator VCSEL designs achieve superior results by utilizing a significant portion of the host substrate in the resonator design. The substrate is redesigned into a curved mirror after grinding off the unnecessary parts, which is also a cumbersome, time-consuming, and costly process. Curved mirrors are necessary in long optical resonator designs because they prevent diffraction and scattering losses. Since the typical gain in the active region of nitride VCSELs is ~1%, in long optical GaN resonators, diffraction losses greater than 10 micrometers can rapidly degrade the device performance of the resonator. Sony's curved mirror VCSEL resonators are ~28 micrometers. In short, this will result in the amount of polishing difficulty being maximized as the resonator approaches the active region. This procedure limits the expansion of the GaN resonator.

[0008] On the other hand, epitaxial designs using AlGaN / GaN or AlInN / GaN mirror pairs have recently attracted particular attention [NPL05~NPL06], the latter demonstrating superior performance due to AlInN's ability to lattice match GaN. However, achieving a moderate reflectivity (>99.5% on the emitting side) requires AlInN / GaN layers with more than 40 periods, and maintaining uniform, delicate growth conditions for better quality and improved yield can make the realization of epitaxial DBR designs difficult.

[0009] More recently, nanoporous GaN DBR (NP-GaN DBR) designs [NPL7 - NPL10] have also gained traction due to their relatively easy manufacturability, their lattice matching to GaN, and their high achievable refractive index differences. This high refractive index difference enables achieving a reflectivity of 99.5% with a realistic porosity of 36% in just 17 periods. Since the first NP-GaN DBR was first demonstrated in 2015, multiple groups have successfully achieved lasing with NP-GaN DBR designs. The NP-GaN DBR layer provides better thermal stability than dielectric DBR mirrors. However, common problems remain regarding the thinning and grinding of the expensive host GaN substrate after realizing the NP-GaN DBR layer on the substrate.

[0010] To push nitride VCSELs towards manufacturing, better crystal quality for the device layer and solutions for obtaining stability regarding heat dissipation are needed. Substrate removal techniques such as photoelectrochemical (PEC) [NPL11] and epitaxial lateral overgrowth (ELO)-assisted thermal separation [NPL12 - NPL16] are better options for future VCSEL designs. Since large-sized heterogeneous substrates can be utilized in the ELO method, designing a hybrid VCSEL consisting of an n-side NP GaN DBR and a p-side dielectric DBR would be a more preferable option.

Summary of the Invention

Problems to be Solved by the Invention

[0011] Considering all these drawbacks, an object of the present invention is to provide a group III nitride VCSEL having a nanoporous GaN DBR with improved device performance regarding thermal and optical properties, and a method for manufacturing a group III nitride VCSEL having a nanoporous GaN DBR.

Means for Solving the Problems

[0012] To overcome the limitations of the prior art described above, the present invention discloses a group-III nitride-based VCSEL that includes a group-III nitride active region between a p-type (hole-injecting) group-III nitride layer and an n-type (electron-injecting) group-III nitride layer, and a curved mirror or just a flat dielectric mirror designed over or above the p-side group-III nitride layer.

[0013] The ELO growth technique generally results in thicker group-III nitride layers, but in the inventors' design, the growth of the NP GaN DBR layer was performed after the thick ELO-based unintentionally doped layer. Thus, the actual thicknesses of the device layers, n-GaN, active region, p-AlGaN electron blocking layer, and p-GaN layer (and optionally the current spreading tunnel junction (p ,

[0017] / n ++ GaN)) can be controlled for either a short optical resonator (<10λ) or a large resonator (>10λ).

[0014] The VCSEL further includes one or more tunnel junction layers on the p-side group-III nitride layer, and the curved mirror or flat dielectric mirror is formed over or above the tunnel junction layer such that the tunnel junction layer is between the curved mirror and the p-type group-III nitride layer.

[0015] The VCSEL further includes a second n-type group-III nitride region over or above the tunnel junction layer, and the curved mirror or flat mirror includes the second n-type group-III nitride region and a second type group-III nitride region designed as a lens or left as a plane for DBR mirror arrangement.

[0016] The second group-III nitride n-type region functions as a current spreading layer and has an etched surface with curvature for the VCSEL with a long resonator and remains flat for the VCSEL with a short optical resonator. The second type group-III nitride region includes n-type GaN or unintentionally doped GaN.

[0017] The VCSEL further comprises one or more transparent conductive oxide (TCO) layers on a p-type group III nitride layer as an in-resonator contact layer, and the curved mirror is formed on or above the TCO layer. The TCO layer may be composed of indium tin oxide, ZnO.

[0018] In the case of a long resonator, the curved mirror contains a transparent dielectric material, the surface of the dielectric material is curved, and a DBR consisting of a dielectric thin film is placed on the surface of the dielectric material.

[0019] Furthermore, in the case of VCSELs with long resonators, the dielectric material (which is a transparent oxide or polymer) is removed by wet etching or dry etching after DBR deposition, and then the voids are either filled with a thermal conductive gas or left as voids.

[0020] The VCSEL further comprises a periodically selectively doped GaN layer on or above the ELO base layer. An NP-GaN planar DBR mirror is formed from the selectively doped GaN layer during the VCSEL manufacturing process.

[0021] The VCSEL further contains isolated island-like group III nitride ELO base layers to improve accessibility of chemicals for electrochemical etching, and pore formation is achieved by electrochemical etching in the selectively doped GaN layer.

[0022] The NP-GaN layer exhibits better thermal and electrical conductivity compared to dielectric DBR mirrors. Furthermore, the NP-GaN layer shares the same surface as the active layer, resulting in a configuration of a series of parallel NP-GaN layers separated by a non-porous GaN layer. The flat DBR mirror in this VCSEL design is a nanoporous DBR layer.

[0023] The crystal orientation of the group III nitride layer in VCSELs can be c-plane, semipolar, or nonpolar. [Brief explanation of the drawing]

[0024] [Figure 1A] Figure 1A is a schematic diagram showing a heterogeneous substrate having a Group III nitride template. [Figure 1B] Figure 1B is a schematic diagram showing dielectric mask aperture area patterning on a group III nitride growth layer. [Figure 1C] Figure 1C is a schematic diagram showing a stripe design in which each VCSEL device is housed. [Figure 2A] Figure 2A is a schematic diagram of the base ELO III nitride layer after growth. [Figure 2B] Figure 2B is a schematic diagram showing the growth of the edges on the ELO base. [Figure 2C] Figure 2C is a flattened ELO-based schematic diagram. [Figure 3A] Figure 3A is a schematic diagram of the VCSEL design with a processed short resonator before removal from the host substrate. [Figure 3B] Figure 3B shows the machined VCSEL. [Figure 3C] Figure 3C shows a top view and overhead view of a typical VCSEL chip. [Figure 4A] Figure 4A is a schematic diagram of a fabricated long resonator VCSEL design with GaN lenses before removal from the host substrate. [Figure 4B] Figure 4B shows a fabricated VCSEL with a GaN lens. [Figure 4C] Figure 4C shows a fabricated VCSEL with a dielectric lens. [Figure 4D] Figure 4D shows a machined VCSEL with an air lens. [Figure 4E] Figure 4E shows a typical top view and overhead view of a VCSEL chip. [Modes for carrying out the invention]

[0025] The teachings of the present invention can be readily understood by considering the following detailed description with reference to the accompanying drawings shown as examples. Referring to the accompanying drawings, a schematic concept illustrating the vertical-cavity surface-emitting laser (VCSEL) and the method for manufacturing the VCSEL according to the present disclosure is described below. For ease of understanding, where possible, the same reference numerals are used to indicate the same elements common to the figures.

[0026] In the following embodiments, an explanation is provided with reference to the drawings. The use of NP-GaN DBR flat mirrors on the ELO base layer, and curved or flat DBR mirrors on the p side of group III nitride VCSELs, has been proposed as a viable method for improving device performance in terms of thermal and optical aspects.

[0027] Technical Disclosure: The following disclosure is divided into four sections. The first section describes the tuning of the ELO base layer. The second section provides information on NP-GaN DBR and device layer growth. The third and fourth sections describe short and long VCSELs, respectively.

[0028] Section 1: Preparation of ELO-based preparations The ELO method for forming island-like group III nitride semiconductor layers may include growth by metal-organic chemical vapor deposition (MOCVD), hydride vapor deposition (HVPE), etc. The group III nitride semiconductor layers are sized to form one or more island-like group III nitride semiconductor layers. Alternatively, the ELO group III nitride layers may be initially coalesced so that they can later be separated into individual devices.

[0029] The ELO layer has two parts, one of which is an aperture region, which generally has more defects than its control region that extends onto the ELO mask. The control region extends bidirectionally from the aperture region onto the ELO mask and is called the ELO wing. The VCSEL light-emitting aperture is formed on the ELO wing. Furthermore, the present invention may use heterosubstrates to grow island-like group III nitride semiconductor layers that form bars. For example, the present invention may use GaN templates grown on heterosubstrates such as sapphire, Si, SiC, SiN, GaAs, Ga2O3, LiAlO2, and ScAlMgO4 (SAM).

[0030] Furthermore, the ELO method can significantly reduce dislocation density and stacking fault density when using non-Basel GaN crystal planes, which are important issues when using heterosubstrates. Therefore, the present invention can simultaneously solve many types of problems associated with the use of heterosubstrates. For example, in a laser device, the interface between the ELO mask and the group III nitride template layer may be smoothed to prevent light emission from the interface side.

[0031] Figures 1A, 1B, and 1C are schematic diagrams illustrating a method for providing a group III nitride substrate 10, such as GaN on Si, GaN on sapphire, GaN on ScAlMgO4(SAM), or a bulk GaN substrate. In the case of dissimilar substrates, a group III nitride template 11 may be deposited on the substrate 10, and the template 11 may be designed as a uniform layer on the host dissimilar substrate 10, or the template 11 may be designed only as an aperture area stripe 12. The group III nitride stripe 12 including the host substrate 10 is such as the stripe shown in the schematic diagram of Figure 1C. The aperture area stripe 12 may be modified to be limited to a single device by shortening its length, or modified to be limited to multiple devices by lengthening its length.

[0032] As shown in the schematic diagram of Figure 1C, a dielectric mask 13 is formed on or above the GaN substrate 10. Specifically, the dielectric mask 13 is either placed in direct contact with the substrate 10 or indirectly placed via a template layer grown by MOCVD or the like, and consists of a group III nitride semiconductor deposited on the substrate 10, leaving the aperture area stripe 12.

[0033] The dielectric mask 13 may be formed from an insulating film, such as an SiO2 film or SiN, deposited on the substrate 10 by methods such as plasma chemical vapor deposition (CVD), sputtering, or ion beam deposition (IBD). Subsequently, the SiO2 film is patterned by photolithography and etching using a predetermined photomask to include aperture areas as shown in Figures 1B and 1C. The design of this dielectric film has a significant impact on subsequent device processing and operation.

[0034] As shown in the schematic diagrams of Figures 2A, 2B, and 2C, an epitaxial group III nitride layer 14, such as a GaN-based layer, is grown on the GaN-based substrate and dielectric mask 13 by ELO. The growth of the ELO group III nitride layer 14 first occurs within the aperture area on the GaN-based substrate, and then laterally from the aperture area onto the dielectric mask. The growth of the ELO group III nitride layer is stopped or interrupted before the ELO group III nitride layers from adjacent aperture areas can coalesce on the dielectric mask. Alternatively, the growth of the ELO group III nitride layer may continue and coalesce with adjacent ELO group III nitride layers. The wings 15 of the ELO group III nitride layer are regions on either side of the aperture area where the defect density is reduced. In the ELO growth method, as shown in Figure 2B, the fill factor, which is the ratio between the aperture area and the dielectric mask, deviates significantly from 1, and as a result, group III nitride atoms may accumulate more at the edges of the group III nitride layer compared to the central part of the layer. This growth, observed at the edges, can be detrimental if it persists between the growth of the NP GaN layer and the VCSEL device layer. In Figure 2C, the group III nitride ELO base layer deposited in this manner is polished to obtain a more planar surface as desired. Since the surfaces of these layers are obtained using epitaxial growth, a small amount of chemical mechanical polishing, or dry or wet etching should suffice to obtain a planarized layer.

[0035] Section 2: NP-GaN DBR and Device Layer Growth on ELO Base The NP-GaN DBR can provide better thermal stability compared to dielectric DBRs, and their lattice matching ability to GaN is a desirable condition for growth and manufacturing. Moreover, since the NP-GaN DBRs give a high refractive index difference, they are a promising solution for GaN-based VCSELs. The formation of NP-GaN DBRs has been widely studied and the etching procedure is well understood. At a certain applied bias, the pore size and shape are controlled by the n-type doping and the crystal orientation of the layer exposed to the oxalic acid solution in electrochemical etching (EC). As the etching proceeds, first, the applied negative bias generates a hole inversion layer at the electrolyte / n-GaN interface. Second, the n-GaN surface is oxidized due to the presence of holes on the inverted surface. Third, the oxidized GaN decomposes into Ga 3+ and nitrogen gas, and finally, it freely moves into the electrolyte, leaving voids called nanoporous. After the planarization of the group III nitride layer 14, as shown in FIG. 3A, a semiconductor nanoporous GaN DBR section 16a is grown on the ELO base layer. The nanoporous GaN DBR section includes a periodically superlattice of unintentionally doped (UID) GaN and n + -GaN ([Si] ~10 19 / cm 3 ), and then the device layer includes a group III nitride n-GaN 17 layer, a group III nitride active layer 18, a group III nitride p-type electron blocking layer (EBL) 19, a p-type group III nitride layer 20, and a p ++ GaN layer 21. After this growth, the sample is treated with a chemical solution such as BHF and reintroduced into the MOCVD apparatus to grow the n ++ GaN 22 layer to complete the tunnel junction.

[0036] Next, reactive ion etching (RIE) is used to form n ++ / p ++An embedded tunnel junction opening is defined by etching deep into the p-GaN20 through the GaN layer. Finally, n-GaN and UID GaN layers are grown on top of the NP GaN layer. The controllability of the thickness of the newly regrown n-GaN and UID GaN layers results in either a short-resonator VCSEL or a long-resonator VCSEL. There are three specific subcategories identified under the long-resonator VCSEL: (i) GaN lenses, (ii) dielectric lenses, and (iii) air / gas lenses. The initially formed NP GaN layer is later transformed into a DBR mirror 16b using the EC process described above. Thus, the NP DBR layer is indistinguishable from the porous and non-porous layers by the electrochemical etching process.

[0037] Section 3: VCSELs with Short Resonators For example, in the case of a short-resonator VCSEL, the design assumes that after growing a superlattice of NP DBRs, the emission is from NP-GaN DBRs, and therefore the porosity and the number of DBR layers are optimized to achieve a value of ~99.5. Using n-GaN17, an active region18, p-AlGaN19 and p-GaN20, as well as a tunnel junction layer, a device layer for a short resonator with a thickness of less than 10λ was designed. Next, a current diffusion layer (n-GaN)25 for the embedded tunnel junction is adjusted to conform all design parameters according to the requirements of a short-resonator VCSEL. The current injection opening is formally defined during the tunnel junction embedding process, and then adjusted so that a slightly larger mesa contacts the n-GaN layer17 for metal contact. The isolated island-like nature of this etched large mesa and ELO bar helps to activate the p-type GaN more effectively. Next, an insulating layer23 is placed to avoid short circuits between the p-contact layer26 and the n-contact layer27. Next, a mesa is selectively opened by photolithography at the top of the device, centered around the current opening. After patterning, a 16-period dielectric DBR24 consisting of SiO2 / Ta2O5 periods is deposited on the top surface. Then, SiO2 or a protective film (not shown) is deposited to protect the device from NP DBR etching and provide electrical insulation.

[0038] The optical reflectivity of DBR mirror 16b is lower than that of dielectric DBR 24. For example, the optical reflectivity of DBR mirror 16b is 99.995 to 99.997. Also, for example, the optical reflectivity of dielectric DBR 24 is 99.998.

[0039] Next, the NP-GaN DBR16b was etched by EC etching, which involved immersion in oxalic acid under a bias voltage. Then, the p-contact pads and n-contact pads were selectively patterned by removing the insulating layer using photolithography, followed by the deposition of metal contacts, Ti / Au. The VCSEL device was then separated from the host substrate by either the thermal exfoliation, laser lift-off method, or chemical lift-off method described above, yielding the overall structure shown in Figure 3B. A heat sink 28 was then attached to the group III nitride layer 14 side, if necessary. As seen in Figure 3B, the NP-GaN DBR side is the light-emitting side, but a considerable amount of group III nitride layer still exists from the lift-off interface to the CMP line. This can be controlled during the CMP polishing itself, and unlike other procedures, the layer remaining in this invention is grown using ELO and is therefore crystalline pure, and the interface surface roughness is designed to be sub-nanometer on the lift-off side without the introduction of CMP or any polishing technique. In this particular invention, the dielectric mask is prepared to have a thickness of more than 300 nm, preferably a multilayer combination of SiO2 and SiN. The surface roughness of the dielectric mask is designed to be less than subnanometer (e.g., 2 nm) so that the same material can be replicated at the lift-off interface.

[0040] Figure 3C is a schematic diagram of typical dimensions of a VCSEL device, which is fabricated from a two-dimensional array of ELO bars on a host substrate. As shown in the small figure, since the emission was selected to be from the lower side, i.e., the NP-GaN DBR side, a complementary metal oxide semiconductor logic gate substrate may preferably be integrated on top of these devices.

[0041] advantage: 1. Parallel NP-GaN DBR layers provide better thermal stability than dielectric materials. 2. The separated ELO base layer approaches the NP layer, simplifying the deep groove definition procedure to facilitate p-GaN activation. 3. The lift-off interface did not require further polishing after removal from the host substrate.

[0042] Section 4: VCSELs with long resonators (i) GaN lens VCSEL For example, in the case of a VCSEL with a long resonator thickness exceeding 10λ, the design assumes that after growing a superlattice of NP DBR16b, the emission is from NP-GaN DBR16b, and therefore the porosity and the number of DBR layers are optimized to achieve a value of ~99.5. As shown, device layers for long resonators with thicknesses greater than 10λ were designed using n-GaN, an active region, p-AlGaN19 and p-GaN20, and tunnel junction layers 21 and 22. Next, the current diffusion layer 25 for the embedded tunnel junction is adjusted so that the design parameters conform to the requirements of a long resonator VCSEL. The only difference compared to a short resonator VCSEL is the thickness of the layer used to embed the tunnel junction. In this case, a fairly thick n-GaN27 and UID GaN layer 14 was placed. Figure 4A shows a typical design still remaining on the host substrate.

[0043] The current injection aperture is formally defined during the tunnel junction filling process. A photoresist lens is then formed by photoregistry flow, and an image is drawn onto a thick GaN layer using RIE to form a GaN lens 25A. Following this, a slightly larger mesa is adjusted to contact the n-GaN layer 17 for metal contact. The isolated island-like nature of this large mesa and ELO bar allows for more effective activation of the p-GaN 20. Next, an insulating layer 23 is placed to avoid short circuits between the p-contact layer 26 and the n-contact layer 27. Then, selectively, the mesa is opened by photolithography at the top of the device, centering on the current injection aperture above the curved GaN lens 25A. Next, a 16-period dielectric DBR 24 consisting of SiO2 / Ta2O5 periods is deposited on the top surface. Next, SiO2 or a protective film (not shown) is placed to protect the device from NP DBR etching and provide electrical insulation. Finally, EC etching is performed by immersing the sample in oxalic acid under a bias voltage to etch the NP DBR 16b. Next, the p-contact pads and n-contact pads were selectively patterned using photolithography, and metal contacts, Ti / Au, were deposited. The VCSEL device was then separated from the host substrate, resulting in the overall image shown in Figure 4B. As can be seen from the overall image, the NP-GaN DBR side is the light-emitting side, but unlike existing conventional devices, a considerable group III nitride layer still exists from the lift-off interface to the CMP line. In contrast to other procedures, the additional layer beneath the NP-GaN DBR16b in this invention is grown using ELO, thus having superior crystal quality, and this thickness can be controlled during the epitaxial or CMP process. Furthermore, the interface surface roughness is designed to be below sub-nanometer values ​​simply by designing the material and deposition technique of the dielectric mask 13, without introducing CMP or any polishing technique. The dielectric mask is adjusted to have a minimum thickness of 300 nm, preferably a multilayer combination of SiO2 and SiN. The surface roughness of the dielectric mask is designed to be below sub-nanometers so that the same can be replicated on the lift-off interface.

[0044] advantage: 1. Parallel NP-GaN DBR layers provide better thermal stability than dielectric materials. 2. The GaN lens in the thick resonator provides thermal stability to the structure. 3. The separated ELO base layer approaches the NP layer, simplifying the deep groove definition procedure to facilitate p-GaN activation. 4. The lift-off interface required no polishing after removal from the host substrate.

[0045] (ii) Dielectric lens VCSEL For example, in the case of a VCSEL with a long resonator thickness exceeding 10λ, the design assumes that after growing a superlattice of NP DBRs, the emission comes from NP-GaN DBR16b, and therefore the porosity and the number of DBR layers are optimized to achieve a value of ~99.5. Device layers for long resonators with thicknesses greater than 10λ pose problems for the active region 18 of the device. To fabricate a thick GaN lens 25A within a long resonator with a thickness of ~3μm, the growth of n-GaN25 is usually carried out at a higher temperature than the previously grown active region 18, and thus ultimately damages the quantum well in the active region. On the other hand, if the growth temperature of the thick GaN resonator is reduced, crystal defects can enter, thereby increasing light absorption and consequently stopping the laser oscillation function in the VCSEL. To counteract this, the lens material may be replaced with a dielectric material, which can be deposited at or near room temperature, preventing degradation of the active region 18. Dielectric material is deposited when the optical resonator thickness is less than 10λ, i.e., thicknesses like the short resonator VCSELs described in Section 3. A properly optimized dielectric lens material can be virtually lossless. Immediately after the optical resonator, a thickness similar to that of the short resonator is created by n-GaN 17, active region 18 and p-GaN 19, 20, as well as tunnel junctions 21, 22 and current diffusion layer 25, and the current injection aperture is formally defined during the filling process of tunnel junctions 21, 22. In this design, first, a thick dielectric material such as SiO2 is deposited on the GaN device layer of the short resonator. Then, a photoresist lens is formed by photoregistry flow, and an image is drawn on the deposited dielectric material using RIE to form a dielectric lens. Subsequently, a slightly larger mesa is adjusted to contact the n-GaN region for metal contact. The isolated island-like nature of this mesa and ELO bar allows for more effective activation of the p-GaN. Next, an insulating layer 23 is placed to avoid short circuits between the p-contact layer 26 and the n-contact layer 27. Then, selectively, the mesa is opened by photolithography at the top of the device, centering on the current aperture on the curved lens.Next, a 16-period dielectric DBR24 consisting of SiO2 / Ta2O5 periods was deposited on the dielectric lens 29. Then, SiO2 or a protective film (not shown) was placed to protect the device from NP DBR etching and provide electrical insulation. Next, the NP DBR16b was etched by EC etching by immersion in oxalic acid under a bias voltage. Next, the p-contact pads and n-contact pads were selectively patterned using photolithography and metal contacts, Ti / Au, were deposited. Next, the VCSEL device was separated from the host, resulting in the overall image shown in Figure 4C. As can be seen from the overall image, the NP-GaN DBR16b side is the light-emitting side, but unlike existing conventional devices, a considerable group III nitride layer is still present from the lift-off interface to the CMP line. In contrast to other procedures, the additional layer beneath the NP-GaN DBR16b in this invention is grown using ELO and therefore has superior crystal quality, and this thickness can be controlled during the epitaxial or CMP process. Furthermore, the interface surface roughness is designed to be below sub-nanometer values ​​simply by designing the dielectric mask material and deposition technique, without introducing CMP or any polishing technique. The dielectric mask 13 is adjusted to have a minimum thickness of 300 nm, preferably a multilayer combination of SiO2 and SiN. The surface roughness of the dielectric mask 13 is designed to be below sub-nanometers so that the same material can be replicated on the lift-off interface.

[0046] advantage: 1. Parallel NP-GaN DBR layers provide better thermal stability than dielectric materials. 2. A thick resonator fabricated with dielectric lenses is lossless. 3. The active layer is not damaged. 4. The separated ELO base layer approaches the NP layer, simplifying the deep groove definition procedure to facilitate p-GaN activation. 5. The lift-off interface required no polishing after removal from the host substrate.

[0047] (iii) Air Lens VCSEL This design is similar to a dielectric lens VCSEL, except that the curved surface is transferred onto a dielectric material. The dielectric material is deposited when the thickness of the optical resonator is less than 10λ, as is the thickness of the short-resonator VCSEL described in Section 3. A well-optimized dielectric lens material can be virtually lossless. Immediately after the optical resonator, a thickness similar to that of the short-resonator is created by n-GaN17, active region 18 and p-GaN19, 20, as well as tunnel junctions 21, 22 and current diffusion layer 25, and the current injection aperture is formally defined during the filling process of tunnel junctions 21, 22. In this design, first, a thick dielectric material such as SiO2 is deposited on the GaN device layer of the short-resonator. Then, a photoresist lens is formed by photoregistry flow, followed by direct deposition of the upper DBR on the photoresist, and then removal of the lower photoresist of the lens to form an air gap lens 30. The remaining manufacturing procedure is similar to that of the VCSEL device described above. The device is schematically shown in Figure 4D.

[0048] Figure 4E is a schematic diagram of typical dimensions of a VCSEL device, which is fabricated using a two-dimensional array of ELO bars on a host substrate. As shown in the small figure, since the light emission was selected to be from the lower side, i.e., the NP-GaN DBR16b side, a complementary metal oxide semiconductor logic gate substrate may preferably be integrated on top of these devices.

[0049] advantage: 1. Parallel NP-GaN DBR layers provide better thermal stability than dielectric materials. 2. Thick resonators made of dielectric materials are lossless. 3. The air inside the lens creates a better refractive index difference, thereby providing better reflection and simplifying the process. 4. The active layer is not damaged. 5. The separated ELO base layer approaches the NP layer, simplifying the deep groove definition procedure to facilitate p-GaN activation. 6. The lift-off interface required no polishing after removal from the host substrate.

[0050] Purpose illumination: GaN-based LEDs have brought about a dramatic transformation in residential and automotive lighting. Lighting combined with communication services is highly desired in future smart cities and smart infrastructure. VCSELs are a better alternative to LEDs and end-face-emitting laser diodes. However, the lack of suitable and profitable mass production technology has prevented GaN VCSELs from entering the market. The procedure developed in the above embodiment can be used to mass-produce VCSEL units applicable to lighting applications. Visible light communication:

[0051] Laser light for future potential data transfer and communication applications using Light Fidelity (LiFi). With the rapid increase in IoT devices, the demand for data transmission continues to expand. The RF spectrum is becoming saturated, and new frequencies are needed to keep up with the continuously increasing demand. Applying GaN VCSELs to existing LED configurations is simpler than replacing them with end-emitting lasers. Therefore, the devices described in the embodiments above can serve their purpose. Near-eye display:

[0052] Near-eye displays represent the next big wave in consumer electronics. These are key components of virtual reality (VR) and augmented reality (AR) technologies. Currently, micro-LEDs are the primary choice for displays. However, while progress in VCSEL research is limited, VCSELs will undoubtedly be introduced as miniature and near-eye displays. Relatively low light power is beneficial for maintaining eye safety. Low divergence and circular symmetry reduce the need for additional optical elements, thus resulting in compactness. The two-dimensional array integration capability of VCSELs is less complex than that of end-emitting lasers. Therefore, VCSEL products manufactured using the invention can be applied to these applications.

[0053] advantage 1. Use of a sufficiently long resonator with no excessive diffraction loss, having two reflective mirrors that define the VCSEL resonator. 2. Good thermal management due to a sufficiently long resonator and / or placement of contacts on the nitride layer. 3. GaN template included in the device teeth This relates to better thermal conductivity to the substrate material, thereby improving thermal performance. 4. It is possible to profit by using cheaper, larger template substrates such as GaN on sapphire. 5. High-quality, larger-sized GaN substrates are extremely expensive. This ELO technology can enable the use of dissimilar substrates in the manufacturing of VCSELs. 6. The present invention is expected to provide significant improvements in performance and reduction of manufacturing costs, as well as the elimination of complex procedures.

[0054] While the principles of the present invention have been described and illustrated in preferred embodiments, it will be understood by those skilled in the art that the present invention can be modified in arrangement and detail without departing from such principles. Accordingly, the inventors request all modifications and variations that fall within the spirit and scope of the following claims. [Explanation of Symbols]

[0055] 10 Group III nitride substrates 11 Group III Nitride Template 12 Opening Area Stripe 13 Dielectric Mask 14 UID GaN layer 15 Wing 16a Nanoporous GaN DBR section 16b NP DBR 17 n-GaN layer 18 Group III nitride active layer 19. Group III nitride p-type electron blocking layer (EBL) 20 p-type III-nitride layer 21 p ++ GaN layer 22 n ++ Ga N 23 Insulating layer 24 Dielectric DBR 25 Current Diffusion Layer (n-GaN) 26 p-contact layer 27 n-contact layer 28 Heatsink 29 Dielectric Lenses 30 Air Gap Lens

Claims

1. An epitaxially laterally overgrown semiconductor portion, composed of a group III nitride active region between a hole-injection group III nitride layer and an electron-injection group III nitride layer, and Electron injection group III nitride layer on the nanoporous group III nitride layer side, This includes an extended vertical-cavity surface-emitting laser (VCSEL).

2. The VCSEL according to claim 1, further comprising a curved mirror or a flat mirror on the hole-injection group III nitride layer side, and a flat mirror on the electron-injection group III nitride layer side.

3. The VCSEL according to claim 1, further comprising a nanoporous group III nitride GaN layer disposed between an unintentionally doped (UID) GaN layer and the group III nitride active region.

4. The VCSEL according to claim 3, wherein the UID GaN layer is substantially not included in the group III nitride template.

5. The VCSEL according to claim 3, wherein the UID GaN layer is formed by epitaxial lateral overgrowth.

6. The VCSEL according to claim 3, wherein the interface of the UID GaN layer is not included in the host substrate and is part of the VCSEL optical resonator.

7. The VCSEL according to claim 3, wherein the surface roughness of the interface between the UID GaN layer and the dielectric mask is less than or equal to a nanometer.

8. The VCSEL according to claim 7, wherein no chemical mechanical polishing (CMP), etching, or grinding was used to smooth the interface surface of the UID GaN layer.

9. The VCSEL according to claim 2, wherein the planar mirror on the hole injection group III nitride layer side constitutes a dielectric mirror for a short resonator VCSEL.

10. The VCSEL according to claim 2, wherein the curved mirror is positioned above or above the p-GaN layer and has a GaN lens.

11. The VCSEL according to claim 2, wherein the curved mirror is disposed on or above the p-GaN layer and has a dielectric lens.

12. The VCSEL according to claim 11, wherein the material of the dielectric lens includes a transparent oxide.

13. The VCSEL according to claim 11, wherein the material of the dielectric lens includes a polymer.

14. The VCSEL according to claim 2, wherein the curved mirror is positioned above or above the p-GaN layer and has an air lens.

15. The VCSEL according to claim 1, further comprising a curved surface DBR made of dielectric DBR.

16. The VCSEL according to any one of claims 1 to 15, wherein the crystal orientation of the group III nitride layer is c-plane, semipolar, or nonpolar.

17. Forming a group III nitride template on a substrate, Forming a dielectric mask on the group III nitride template, Forming UID GaN by epitaxial growth from the opening area of ​​the dielectric mask, and A method for manufacturing a vertical cavity surface-emitting laser (VCSEL), comprising forming a nanoporous GaN DBR on the UID GaN.

18. The method according to claim 17, wherein the nanoporous GaN DBR includes a plurality of DBR mirrors.

Images