Surface-emitting laser

Abstract

The enhanced vertical cavity surface emitting laser (VCSEL) includes an epitaxially laterally overgrown semiconductor portion comprised of a III-nitride active region between a hole-injection III-nitride layer and an electron-injection III-nitride layer, an angled p-type mirror on the hole-injection side, and a planar mirror angled relative to the III-nitride active region, the planar mirror including a nanoporous layer on the electron-injection side and a non-porous layer on the n-side.

Description

Technical Field

[0001] The present invention relates to a group-III nitride vertical-cavity surface-emitting laser (VCSEL) having a nanoporous GaN DBR.

Background Art

[0002] Throughout this application, numerous patents or non-patent publications are referenced by reference numbers within parentheses, i.e., []. A list of the publications arranged according to these reference numbers can be found below in the section entitled "Non-Patent Documents" or "Patent Documents". "Citation List" "Non-Patent Documents"

[0003] [NPL1] Appl.Phys.Lett. Vol. 92, p. 141102 (2008) [NPL2] Appl.Phys.Express Vol. 12, p. 044004 (2019) [NPL3] Sci.Rep. Vol. 8, p. 10350 (2018) [NPL4] Jpn.J.Appl.Phys. Vol. 58, SC0806 (2019) [NPL5] Appl.Phys.Express Vol. 11, p. 112101 (2018) [NPL6] Appl.Phys.Lett. Vol. 101, p. 151113 (2012) [NPL7] ACS Photonics, Vol. 2, pp. 980 - 986 (2015) [NPL8] Sci.Rep. Vol. 7, p. 45344 (2017) [NPL9] Appl.Phys.Lett. Vol. 112, p. 041109 (2018) [NPL10] Scr.Mater, Vol. 156, pp. 10-13 (2018) [NPL11] Appl.Phys.Express 2012, Vol. 5, p. 092104 [NPL12] Optics Express, Volume 27, Page 24717 (2019) [NPL13] Appl.Phys.Express, Volume 13, Page 041003 (2020) [NPL14] Appl.Phys.Express, Volume 14, Page 031002 (2021) [NPL15] Applied Phys. Lett. Volume 119, Page 142103 (2021) [NPL16] Crystals, Vol. 11, No. 12, pp. 1563, (2021) [NPL17] "Dry etching for coherent refractive index microlens arrays" by MBStern and TRJay, Opt.Eng. Vol. 33, pp. 3547-3551 (1994).

[0004] Surface-emitting lasers are also known as vertical-cavity surface-emitting lasers (VCSELs). A VCSEL comprises a semiconductor active region positioned between an n-side semiconductor region and a p-side semiconductor region, and two distributed Bragg reflectors (DBRs) that function as high-reflectivity mirrors. The semiconductor active region, also known as the gain medium, is positioned between the two DBRs to form an optical resonator. The n-side and p-side regions inject their respective carriers, namely electrons and holes, into the active region, where these carriers recombine to generate light. The light or electromagnetic radiation thus produced is reflected repeatedly by the DBRs and travels through the optical resonator, thereby causing laser oscillation. One of the DBRs in a VCSEL is a less reflective mirror and is used to emit the laser beam.

[0005] Gallium nitride (GaN) VCSELs have recently attracted increasing research attention due to their ability to emit light in the visible and ultraviolet (UV) regions. This opens up a variety of new application spaces in displays, solid-state lighting including automotive and residential lighting, sensing, and communications. Because VCSELs consume less energy and have faster modulation speeds, one of the most exciting applications is when blue-emitting GaN VCSELs coupled with phosphor devices function collectively as a spontaneous light source and data transmission device. This application will take AR / VR applications, smartphones, and conventional displays in a new light-emitting perspective by adding communication capabilities to each light-emitting pixel.

[0006] While GaAs-based infrared VCSELs have incorporated mature manufacturing techniques, Group III nitride-based VCSELs still lack industrial applicability. Continuous-wave (CW) laser oscillation at 462 nm from electro-injected GaN VCSELs was first demonstrated in 2008 at a temperature of 77 K [NPL1]. Since then, there has been considerable progress in terms of power, efficiency, threshold current, laser oscillation wavelength, and room-temperature stability. However, industrial applicability has not yet been achieved. One of the problems is the n-side DBR mirror, which is generally a dielectric DBR that causes thermal instability in device operation. Traditionally, after careful polishing of the host substrate, the dielectric DBR is deposited on the n-side of the VCSEL. On the host substrate, alternative methods such as epitaxial DBR and nanoporous GaN DBR are growing, and VCSELs with long optical GaN resonators have been proposed in the literature for better thermal stability.

[0007] While these methods were somewhat effective, even with long resonators and nanoporous GaN DBR resonators, it is necessary to address issues such as the high cost of GaN substrates, the increased growth time of epitaxial DBRs while maintaining the quality of the device layers, and methods for delaminating expensive GaN substrates.

[0008] VCSELs with long optical resonators and curved lenses refocus the electric field to the gain medium, thereby reducing diffraction losses due to the long resonator length [NPL2~NPL4]. Until 2022, Sony's long resonator design held performance records of 15.8mW CW output, a threshold current of 0.25mA, and a wall-plug efficiency (WPE) of 9.5%. Long optical GaN resonator VCSEL designs achieve superior results by utilizing a significant portion of the host substrate in the resonator design. The substrate is redesigned into a curved mirror after grinding off the unnecessary parts, which is also a cumbersome, time-consuming, and costly process. Curved mirrors are necessary in long optical resonator designs because they prevent diffraction and scattering losses. Since the typical gain in the active region of nitride VCSELs is ~1%, in long optical GaN resonators, diffraction losses greater than 10 micrometers can rapidly degrade the device performance of resonators. Sony's curved mirror VCSEL resonators are ~28 micrometers. In short, this will result in the amount of polishing difficulty being maximized as the resonator approaches the active region.

[0009] On the other hand, epitaxial designs using AlGaN / GaN or AlInN / GaN mirror pairs have recently attracted particular attention [NPL5~NPL6], the latter demonstrating superior performance due to AlInN's ability to lattice match GaN. However, achieving a moderate reflectivity (>99.5% on the emitting side) requires AlInN / GaN layers with more than 40 periods, and maintaining uniform, delicate growth conditions for better quality and improved yield can make the realization of epitaxial DBR designs difficult.

[0010] More recently, nanoporous GaN DBR (NP-GaN DBR) designs [NPL7~NPL10] have also gained appeal due to their relatively easy fabrication, lattice matching to GaN, and their highly feasible refractive index differences. This high refractive index difference allows for a realistic porosity of 36% and a reflectivity of 99.5% in just 17 cycles. Since the first NP-GaN DBR was demonstrated in 2015, several groups have successfully achieved laser oscillation using NP-GaN DBR designs. NP-GaN DBR layers offer better thermal stability than dielectric DBR mirrors. However, a common problem remains: thinning and grinding of the expensive host GaN substrate after realizing the NP-GaN DBR layer on the substrate.

[0011] An ideal VCSEL should be able to address the following concerns in an effective manner. 1) Group III nitride layer with better crystal quality Currently, most companies are focused on fabricating Group III nitride VCSELs on bulk GaN substrates. The best available Group III nitride bulk substrates are 10 6 Defects / cm 2 It has. The active volume of VCSELs is small, about 10 times smaller than that of conventional edge-emitting lasers. Therefore, it is preferable to have a crystal quality that is better than the existing bulk substrate quality. Furthermore, bulk GaN substrates are very expensive even at current existing quality, and therefore, the demand for better quality will drive up prices and further delay the market entry of group III nitride VCSELs. 2) Larger wafers required for better yield. Generally speaking, VCSELs are almost a copy of LED manufacturing. Most LEDs are manufactured on 6-inch or larger substrates. Also, for manufacturers, choosing larger substrates is a natural choice to enable better yield and competitive pricing. 3) Thermal stability achieved by providing a heat-conducting DBR mirror Another technical problem that has kept VCSELs away from the market is the placement of the n-side DBR mirror. Since VCSELs are surface-emitting lasers, they are thin along the substrate surface. Even if an expensive bulk group-III nitride substrate is first used to form the thin VCSEL device layer, the expensive group-III nitride substrate must be removed from the VCSEL device to place the n-side dielectric DBR mirror, or a DBR layer that does not damage the substrate material must be placed before forming the VCSEL device layer. There are several techniques to avoid VCSEL manufacturing problems. Long-resonator VCSELs: To avoid the need to remove the substrate to a level that reduces yield, Sony devised long-resonator VCSELs that still hold a significant amount of substrate within the optical resonator of the VCSEL. This design provides better thermal stability due to the long-resonator group-III nitride material, but this design has some practical limitations in the resonator length and the amount of the resonator's emission modes. Epitaxial DBR: As mentioned above, InGaN / GaN or AlN / GaN epitaxial DBRs have been proposed in the literature. Due to the low refractive index difference, ~40 pairs of In 0.82 Ga 0.18 N / GaN lattice-matched DBR mirror layers are required to obtain a reflectivity exceeding 99%. Long growth times and difficult control of the In and Al compositions are still concerns. Also, heat dissipation and vertical injection problems remain. Due to the low reflectivity, the emission side is the epitaxial DBR side, so the substrate region under the epitaxial DBR mirror requires some surface treatment and sometimes grinding to reduce absorption loss and scattering loss. Nanoporous (NP) DBR: Usually, nanoporous DBRs have a high reflectivity >99% and growth that is simply lattice-matched to GaN. Applicable to all crystal orientations of GaN. Furthermore, the reflectivity of the layer is adjustable. However, since the NP layer is configured parallel to the active layer of the device, it is not the best configuration for heat extraction and vertical carrier injection. 4) p-side intra-resonator current spreading layer VCSEL devices face problems on the p-side due to the higher activation energy required for p-type conductivity by standard, which is an increase in the resistance of the p-GaN layer. Researchers have minimized the thickness of the p-GaN layer of the VCSEL device to eliminate Joule heating and light absorption. Reducing the thickness of the p-GaN layer and disposing a current diffusion layer such as a transparent conductive oxide (TCO) like indium tin oxide, or more tunnel junctions, helps in the design, but light absorption remains a problem. Researchers have cleverly placed the conductive layer within the resonator in the minimum electromagnetic field of the device, but such fine requirements reduce the yield and increase the cost. Only a few of the above problems can be addressed by substrate removal techniques such as photoelectrochemical (PEC) [NPL11] and epitaxial lateral overgrowth (ELO)-assisted thermal exfoliation [NPL12 - NPL16], but not all. Summary of the Invention Problems to be Solved by the Invention

[0012] Taking all these drawbacks into consideration, an object of the present invention is to provide a group-III nitride VCSEL having a nanoporous GaN DBR and to make the nanoporous GaN DBR more functional to improve device performance with respect to thermal and optical characteristics. Means for Solving the Problems

[0013] To overcome the limitations of the prior art described above, the present invention discloses a group-III nitride-based VCSEL including a group-III nitride active region between a p-type (hole injection) group-III nitride layer and an n-type (electron injection) group-III nitride layer, and a flat dielectric mirror designed above or on the angled p-type group-III nitride layer.

[0014] ELO growth begins with the stepwise formation of a group III nitride crystal plane, and this plane can be maintained at all times by applying an appropriate growth mode with optimized parameters. Furthermore, by periodically adjusting the supply source and then doping the layer as needed, the growth plane can be more precisely modified in epitaxial lateral overgrowth. By combining ELO technology with a growth-controlled, tilted (semipolar) group III nitride layer with a designed doping level, a high-crystal-quality crystal plane can be obtained on a dielectric mask. These selectively doped layers subsequently form a porous group III nitride layer, resulting in a tilted NP-GaN DBR mirror.

[0015] The optical resonator thickness, including the device layer, n-GaN layer, active region, p-AlGaN electron blocking layer, and p-GaN layer (and optionally current-diffusing tunnel junction (p++ / n++GaN)), can be controlled during epitaxial growth.

[0016] The VCSEL further comprises one or more tunnel junction layers on a p-side group III nitride layer for current injection, and a dielectric DBR mirror is positioned away from the tunnel junction at a certain angle.

[0017] The VCSEL further includes one or more transparent conductive oxide (TCO) layers on a p-type group III nitride layer as an in-resonator contact layer, instead of a tunnel junction. The TCO layers may be composed of indium tin oxide, ZnO.

[0018] The VCSEL further includes a region for positioning a dielectric DBR mirror on or above a p-type group III nitride region, the p-type group III nitride layer being formed to form an angle with the active layer plane.

[0019] The VCSEL further comprises an angled p-type Group III nitride layer, which is one of the semipolar surfaces of the Group III nitride material obtained by either physical or chemical etching. Preferably, a combination of physical and chemical etching is used to smooth the surface for arranging the dielectric DBR mirror layer. The surface morphology of the etched semipolar surface on the p-GaN layer can be controlled by using an etching solution such as H3PO4, KOH, or an acidic or basic etching method similar to c-plane Ga polar etching with 5M NaOH. Alternatively, immersion in 98% H2SO4 helps to prepare a semipolar plane for arranging the dielectric DBR mirror layer.

[0020] The VCSEL further comprises a periodically selectively doped group III nitride layer on or above the dielectric mask. The selectively doped group III nitride layer is subsequently formed as a nanoporous layer, while the undoped bulk group III nitride layer inserted between the selectively doped layers remains nonporous. The VCSEL further comprises alternating nanoporous layers that are highly doped n-type compared to the nonporous bulk group III nitride layer.

[0021] The VCSEL is further composed of alternately arranged nanoporous and nonporous group III nitride layers, the combination of which forms a tilted n-type DBR mirror, with the layers oriented so that one of the group III nitride semipolar planes is a plane of semipolarity.

[0022] VCSELs are further constructed from periodically controlled layer growth in the preparation of selectively doped semipolar layers. Here, NH3, Ga metal, and n-type doping sources periodically change / alternate to create a sharp interface at the boundary between the nanoporous group III nitride layer and the nonporous group III nitride layer.

[0023] The VCSEL, further composed of a non-porous bulk group III nitride layer and a nanoporous group III nitride layer, has the same interface as the dielectric mask, which was later dissolved during the device fabrication process. This interface can provide inlets and outlets for vertical current injection and heat dissipation.

[0024] VCSELs are further designed to have a smooth (sub-nanometer) interface between the tilted group III nitride n-type DBR mirror and the dielectric mask. The dielectric mask material in the group III nitride layer growth is prepared using SiO2 or SiN, preferably a combination of both, by means such as sputtering, atomic layer deposition, or plasma-excited chemical vapor deposition (PECDV) or ion beam deposition.

[0025] The VCSEL further includes isolated island-like group III nitride ELO base layers that facilitate access for chemicals used in electrochemical etching, and pore formation is achieved by electrochemical etching in the selectively doped GaN layer.

[0026] The bulk nonporous group III nitride layer of the DBR mirror has better thermal and electrical conductivity compared to the nanoporous group III nitride layer. Therefore, when these layers are combined in an alternating periodic arrangement, the device is best suited to function as a DBR mirror, as well as a thermal heat sink and an electrical injector. The preferred crystal orientation of the host substrate for the present invention may be c-plane, semipolar, or nonpolar, but is preferably c-plane. [Brief explanation of the drawing]

[0027] [Figure 1A] Figure 1A is a schematic diagram showing a heterogeneous substrate having a Group III nitride template. [Figure 1B] Figure 1B is a schematic diagram showing dielectric mask aperture area patterning on a group III nitride growth layer. [Figure 1C] Figure 1C is a schematic diagram showing a stripe design in which each VCSEL device is housed. [Figure 1D] Figure 1D is a schematic diagram, and Figure 1D shows a triangular grid pattern. [Figure 1E] Figure 1E is a schematic diagram illustrating an alternative method for growing an ELO base layer using a patterned Group III nitride template. [Figure 1F] Figure 1F is a schematic diagram illustrating an alternative method for growing an ELO base layer using a patterned Group III nitride template. [Figure 2A] Figure 2A is a schematic diagram of the base ELO III nitride layer after growth. [Figure 2B] Figure 2B is a schematic diagram of the base ELO III nitride layer after growth. [Figure 2C] Figure 2C is a schematic diagram of the base ELO III nitride layer after growth. [Figure 2D] Figure 2D is a flattened ELO-based schematic diagram. [Figure 3A] Figure 3A illustrates various growth modes of ELO growth for group III nitride crystals. [Figure 3B] Figure 3B illustrates various growth modes of ELO growth for group III nitride crystals. [Figure 3C] Figure 3C illustrates various growth modes of ELO growth for group III nitride crystals. [Figure 3D] Figure 3D illustrates various growth modes of ELO growth for Group III nitride crystals. [Figure 3E] Figure 3E illustrates various growth modes of ELO growth for group III nitride crystals. [Figure 3F] Figure 3F illustrates various growth modes of ELO growth for group III nitride crystals. [Figure 3G] Figure 3G illustrates various growth modes of ELO growth for group III nitride crystals. [Figure 3H] Figure 3H illustrates various growth modes of ELO growth for group III nitride crystals. [Figure 3I] Figure 3I illustrates various growth modes of ELO growth for group III nitride crystals. [Figure 3J] Figure 3J illustrates various growth modes of ELO growth for group III nitride crystals. [Figure 3K] Figure 3K illustrates various growth modes of ELO growth for group III nitride crystals. [Figure 4A] Figure 4A shows flattened ELO base layers with bar-shaped and hexagonal structures, respectively, representing alternatingly doped group III nitride layers. [Figure 4B] Figure 4B shows flattened ELO base layers with bar-shaped and hexagonal structures, respectively, representing alternatingly doped group III nitride layers. [Figure 5A] Figure 5A is a schematic diagram of the processed VCSEL design before removal from the host substrate. [Figure 5B] Figure 5B shows a VCSEL that has been processed with vertical current injection. [Figure 5C] Figure 5C shows a VCSEL with a tunnel junction. [Figure 5D] Figure 5D shows a VCSEL with a tunnel joint and heat diffuser fabricated. [Figure 6A] Figure 6A is a schematic diagram of a fabricated VCSEL having two or more optical resonators in an ELO bar shape before removal from the host substrate. [Figure 6B] Figure 6B shows a VCSEL that has been processed with vertical current injection. [Figure 6C] Figure 6C shows a fabricated VCSEL with a hexagonal pattern having different optical resonators. [Figure 6D] Figure 6D shows a VCSEL with a processed hexagonal pattern that emits a ring-shaped light. [Figure 7A] Figure 7A shows typical tip dimensions for an ELO bar. [Figure 7B] Figure 7B shows wafer-scale integration of ELO bar VCSELs and hexagonal VCSELs. [Modes for carrying out the invention]

[0028] The teachings of the present invention can be readily understood by considering the following detailed description with reference to the accompanying drawings shown as examples. Referring to the accompanying drawings, a schematic concept illustrating the vertical-cavity surface-emitting laser (VCSEL) and the method for manufacturing the VCSEL according to the present disclosure is described below. For ease of understanding, where possible, the same reference numerals are used to indicate the same elements common to the figures.

[0029] In the following embodiments, an explanation is provided with reference to the drawings. The use of non-porous tilted DBR mirrors and nanoporous tilted DBR mirrors on ELO base layers, as well as p-side angled DBR mirrors on group III nitride VCSELs, has been proposed as a viable method for improving device performance in terms of thermal, optical, and electrical aspects. Technical Disclosure:

[0030] The following disclosure is divided into four sections. The first section describes the preparation of the ELO base layer. The second section provides information on the growth of porous and non-porous layers. The third section presents the VCSEL device manufacturing procedure and its advantages.

[0031] Section 1: Preparation of ELO-based preparations The ELO method for forming island-like group III nitride semiconductor layers may include growth by metal-organic chemical vapor deposition (MOCVD), hydride vapor deposition (HVPE), etc. The group III nitride semiconductor layers are sized to form one or more island-like group III nitride semiconductor layers. Alternatively, the ELO group III nitride layers may be initially coalesced so that they can later be separated into individual devices.

[0032] The ELO layer has two parts, one of which is an aperture region, which generally has more defects compared to its control region that extends onto the ELO mask. The control region extends bidirectionally from the aperture region onto the ELO mask and is called the ELO wing. The VCSEL light-emitting aperture is formed on the ELO wing. Furthermore, the present invention may use heterosubstrates to grow island-like group III nitride semiconductor layers that form bars. For example, the present invention may use GaN templates grown on heterosubstrates such as sapphire, Si, SiC, SiN, GaAs, Ga2O3, LiAlO2, and ScAlMgO4 (SAM).

[0033] Furthermore, the ELO method can significantly reduce dislocation density and stacking fault density when using non-Basel GaN crystal planes, which are important issues when using heterosubstrates. Therefore, the present invention can simultaneously solve many types of problems associated with the use of heterosubstrates. For example, in a laser device, the interface between the ELO mask and the group III nitride template layer may be smoothed to prevent light emission from the interface side.

[0034] Figures 1A, 1B, and 1C are schematic diagrams illustrating a method for providing a group III nitride substrate 10, such as GaN on Si, GaN on sapphire, or a bulk GaN substrate or GaN on ScAlMgO4(SAM). In the case of a dissimilar substrate 10, the group III nitride template 11 may be deposited on the substrate 10, the group III nitride template 11 may be a uniform layer on the host dissimilar substrate 10, or the template 11 may be arranged in an aperture area stripe 12. A group III nitride stripe design including the substrate 10 is the stripe shown in the schematic diagram of Figure 1C. The aperture area stripe 12 can be designed as a single device by shortening its length, or as multiple devices by lengthening its length. Alternatively, as shown in Figure 1D, a triangular grid of circular aperture spots may be designed on the dielectric mask 13, with the apertures exposing the underlying group III nitride layer.

[0035] As shown in the schematic diagrams of Figures 1C and 1D, a dielectric mask 13 is formed on or above a group III nitride template 11 including the substrate 10. Specifically, the dielectric mask 13 is either placed directly in contact with the substrate 10 or indirectly placed via a template layer grown by MOCVD or the like.

[0036] The dielectric mask 13 may be formed from an insulating film, such as an SiO2 film, deposited on the substrate 10 by methods such as plasma chemical vapor deposition (CVD), sputtering, or ion beam deposition (IBD). Subsequently, the SiO2 film is patterned by photolithography and etching using a predetermined photomask to include aperture areas as shown in Figures 1B and 1C. The design of this dielectric film has a significant impact on subsequent device processing and operation.

[0037] In an alternative method, the group III nitride template layer 11 on the substrate is initially designed as rectangular stripes or circular spots forming triangles, and then these are filled with the dielectric mask while partially exposing the top and side walls. The exposed group III nitride regions in Figure 1F or the growth-supported group III nitride regions in the substrate in Figure 1B form an ELO base layer as shown in Figure 1A or Figure 1E.

[0038] As shown in the schematic diagrams of Figures 2A to 2D, an epitaxial group III nitride layer 14, such as a GaN-based layer, grows on the GaN-based substrate and dielectric mask 13 by ELO. The growth of the ELO group III nitride layer 14 first occurs within the aperture area on the GaN-based substrate, and then laterally from the aperture area onto the dielectric mask 13. The growth of the ELO group III nitride layer is stopped or interrupted before the ELO group III nitride layers from adjacent aperture areas 12 can coalesce on the dielectric mask 13.

[0039] Alternatively, the growth of the ELO Group III nitride layer may continue and merge with adjacent ELO Group III nitride layers. Wing 15 of the ELO Group III nitride layer is the region on either side of the aperture area where the defect density is reduced. In the ELO growth method, as shown in Figure 2C, the fill factor, which is the ratio between the aperture area and the dielectric mask, can deviate significantly from 1, resulting in a greater accumulation of Group III nitride atoms at the edges of the Group III nitride layer compared to the central portion of the layer. This, observed as edge growth, can be detrimental if it persists during the growth of the device layer. In Figure 2D, the Group III nitride ELO base layer deposited in this manner is polished to obtain a flat surface. Since the surfaces of these layers are obtained using epitaxial growth, a small amount of chemical mechanical polishing, or dry or wet etching, should suffice to obtain a flattened layer.

[0040] Section 2: Growth of Nanoporous and Non-DBR Layers as ELO-Based The combination of nanoporous and nonporous layers as n-side DBR mirrors in VCSELs has been shown to be a promising solution for GaN-based VCSELs because it can provide better thermal stability compared to dielectric DBRs, their lattice matching ability with GaN is a desirable condition for growth and fabrication, and furthermore, nano and nonporous GaN DBRs provide a high refractive index difference. For example, a nanoporous DBR layer with a porosity in the range of 10% to 75% can provide a refractive index difference of 0.1 to 0.9, while the difference for dielectric DBRs is only about 0.7, and the difference for epitaxial DBRs is less than 0.2.

[0041] Furthermore, when the nanoporous layer and the nonporous layer are arranged in a plane parallel to the active region, the porosity is 10 to 1 W / (m²) as described above. ·It provides a thermal conductivity of K). It is not complicated that as porosity increases, thermal conductivity decreases when these layers are arranged in a parallel configuration with the device active region plane. Similarly, electrical conductivity decreases by 1000 (S / m) to 100 S / m as electrical resistance increases with increasing porosity. However, if the nanoporous and nonporous layers are arranged in a tilted configuration, such that thermal and electrical conductivity depend mainly on the bulk-interface of the nonporous layer, thermal and electrical conductivity can be greatly improved, and as a result, the function, yield, and lifetime of the VCSEL can be greatly improved. The formation of nanoporous group III nitride layers has been widely studied, and the etching procedure is well understood [NPL7]. Under a constant applied bias, the size and shape of the pores are controlled by the crystal orientation of the layer exposed to the oxalic acid solution in n-type doping and electrochemical etching (EC). As etching progresses, firstly, the applied negative bias creates a hole inversion layer at the electrolyte / n-GaN interface; secondly, the n-GaN surface is oxidized due to the presence of holes on the inversion surface; and thirdly, the oxidized GaN becomes Ga 3+ It then decomposes into nitrogen gas, which eventually moves freely into the electrolyte, leaving behind voids called nanoporous structures. In this invention, the formation of porous structures is carried out in a post-processing of the VCSEL device, however, initially, alternating arrangements of nanoporous and nonporous layers were carefully grown using different growth procedures during the growth of the ELO base layer.

[0042] Figure 3A shows a GaN crystal structure with all possible faces, simplifying the growth process. Faces perpendicular to the c faces, such as the (10-10)(m face) and (11-20)(a face), are nonpolar faces, while crystal faces oriented between the c faces and nonpolar faces, such as the (20-21)(r face), are semipolar faces.

[0043] In the initial stages of ELO growth, a base seed 30 having r-planes and c-planes, as shown in Figure 3B, is formed from the opening area 12 of the dielectric mask 13. Alternatively, the group III nitride template 11 on the substrate 10 is etched so that the r-plane and c-plane are exposed.

[0044] After forming the base seed 30, the growth supply parameters of the NH3- source and Ga- source are optimized so that the r-plane and c-plane crystal orientations grow at a better rate and in just the right amount of time, while suppressing the growth of undesirable crystal orientations. As time passes, by adding a dopant such as silicon-Si at specific time intervals, an interface can be formed between the doped and undoped layers of these crystal orientations.

[0045] Next, the doped crystal orientation is transformed into a porous group III nitride layer to form a DBR mirror. As can be seen, crystal plane orientation control can be performed in several ways. Figure 3C shows uniform growth of the c and r planes, resulting in a bulky group III nitride ELO base layer. In another embodiment, Figure 3D shows impure c-plane crystal growth while maintaining large wing growth by keeping r-plane growth lateral. C-plane crystal growth can be suppressed by supplying a small amount of nitrogen source, thus resulting in a growth mode with a low V / III ratio.

[0046] Similar to the edge growth described in the previous section, Figure 3E shows a non-uniform ELO base layer, and the colored or impure c-plane crystal orientations may be due to absorption by impurities such as carbon.

[0047] Figure 3G is an explanatory diagram of a different base seed 30, where the r-plane is the complementary plane to that in Figure 3B. The growth parameters were controlled so that the r-plane increased laterally on the dielectric mask, allowing for the formation of better ELO wings. C-plane crystal orientation growth can be controlled, and impurities are addressed. The conditions for the optimized ELO base layer are important.

[0048] Figures 3B–3K show normal and modified ELO growth methods. The main difference lies in the V / III ratio, i.e., by varying the NH3 flow rate while keeping the TMGa flow rate constant, or by keeping the V / III ratio as low as possible, one of the r-plane growths is promoted while equally suppressing the c-plane growth. High and low V / III ratios can adjust the growth anisotropy and promote lateral growth. Of course, planarization is a last resort for surface preparation before placing the VCSEL device layer on the ELO base.

[0049] Figures 3F and 3K show the planarized base. Nonporous and nanoporous Group III nitride layers with R-plane semiconductor crystal plane orientation of periodic superlattices are GaN and n+-GaN ([Si]~10 19 / cm 3 ) has.

[0050] Figures 4A and 4B show the ELO bar structure after planarization and the r-plane on the ELO wing of the hexagonal close-packed (HCP) structure, respectively. The device layers then include a group III nitride n-GaN layer 17, a group III nitride active layer 18, a group III nitride p-type electron blocking layer (EBL) 19, a p-type group III nitride layer 20, and a p++GaN layer 21, as shown in Figure 5A. Several current injection methods can be utilized for current injection in the VCSEL design of the present invention. Growth may be simply stopped at the p++GaN layer 21, or indium tin oxide may be used as a current diffusion layer, or the n++GaN layer may be grown on the p++GaN layer 21 after some surface treatment to utilize the tunnel junction.

[0051] This invention utilizes the inner layer of the resonator for current injection, but the radiation emitted from the active region is directed away from the contact layer inside the resonator. Therefore, the invention may or may not include the contact layer inside the resonator.

[0052] Section 3: VCSEL Manufacturing Procedure After the growth of the device layer containing the ELO base with a superlattice of NP DBR16, current injection is prepared. The current injection opening 31 is formally defined during the tunnel junction filling process if a tunnel junction is used; otherwise, the current injection region 31 is separated from the optical resonator region 32 by photolithography, preferably by defining a separate circular pattern on the ELO wing. A protective layer is then placed to cover the injection region 31 and the optical resonator region 32. Next, a slightly larger mesa is prepared on the area excluding the injection region 31 and the optical resonator region 32 for placing contact pads. Angle etching is performed on the p-type layer of the VCSEL's optical resonator region 32 to satisfy the requirements for alignment of the deflection of the bottom nanoporous DBR mirror. The etching angle is predetermined so that light deflected from the bottom nanoporous GaN DBR16 strikes the etched p-layer correctly. Since the etched region exposes the surface of the r-plane, the surface was smoothed using a chemical etching solution before placing the dielectric DBR mirror 24, and a 16-period dielectric DBR 24 consisting of SiO2 / Ta2O5 periods was deposited on this prepared surface.

[0053] Next, a protective film (not shown) of SiO2 was deposited to protect the device from nanoporous etching and provide electrical insulation 24. Then, the sample was subjected to EC etching by immersion in oxalic acid under a bias voltage, etching the doped n+GaN layer in the bottom ELO base layer to DBR. Next, the p-contact pads 33 connecting the current injection regions 31 were selectively patterned using photolithography, and then metal contacts Ti / Au were deposited. The resulting device is shown in Figure 5A.

[0054] Next, the VCSEL device is separated from the host substrate by exfoliation or by either laser lift-off or chemical lift-off, and the n-contact metal 34 is blanket-deposited to obtain the overall image shown in Figure 5B. The nanoporous GaN DBR region can be either on the light-emitting side or on the angled p-type layer side. In this invention, the interface between the n-contact pad 34 and the n-DBR 16 is prepared using ELO growth and is therefore crystalline pure, and the interface surface roughness is designed to be sub-nanometer (e.g., 2 nm) without introducing CMP or any polishing technique. The dielectric mask 13 used is ~300 nm thick and preferably a multilayer combination of SiO2 and SiN. The surface roughness of the dielectric mask 13 is designed to be sub-nanometer so that the same can be replicated on the lift-off interface. As can be seen from the overall image, the n-side DBR mirror 16 appears flat with the bulk nonporous group III nitride layer and nanoporous GaN layer forming the interface with the n-contact pad 34. Therefore, it is suggested that the heat dissipation of the device is primarily governed by the bulk nonporous GaN layer with better thermal conductivity. Similarly, the electrical conductivity resistance is primarily governed by the bulk nonporous GaN layer, and thus the described configuration allows for vertical current injection.

[0055] Figure 5C shows the tunnel junction configuration of the current injection region 31. Device layer growth continues up to p++GaN, after which a circular section 35 is defined to define a current aperture. If necessary, ion implantation is added to enhance current injection into the active region 18. The cut-off region of the device in tunnel junction implantation is shown in Figure 5C, and the shaded region 36 indicates the optical resonator region that does not directly overlap with the current injection region.

[0056] Figure 5D focuses on adding a thermal conductive layer to the tunnel junction device Figure 5C described above. After preparing angled p-GaN 24 for DBR mirror placement, and preparing the current injection region 31 and contact pad placement region, the AlN thermal diffusion layer 37 is sputtered. Next, as described above, the p-contact pad 33, dielectric DBR mirror 24, and 16-period dielectric DBR consisting of SiO2 / Ta2O5 periods are deposited on the upper surface of the device. Then, the VCSEL device is separated from the host substrate by thermal delamination, laser lift-off method, or chemical lift-off method, and the n-contact metal 34 is blanket-deposited to obtain the overall structure shown in Figure 5D.

[0057] Figures 6A to 6D show simplified modifications of the device described in Figures 5A and 5B, where at least two ELO wings are used to arrange the current injection regions. In the case of the ELO bar, two emission can be achieved by arranging two current injection regions on either side of the aperture area 12. Similarly, in the case of the hexagonal pattern, six emission 38 as seen in Figure 6C, or a continuous ring-shaped emission as shown in Figure 6D, is possible. As seen in Figure 6C, the base ELO layer is an n-type DBR mirror, but the direction of the light is changed toward the aperture region. Similarly, in Figure 6D, the current injection may be arranged in a ring, in which case the emission appears ring-shaped, but is shifted slightly inward toward the aperture region. The p-contact pad 33 is arranged on the outer circle as shown, and the n-contact pad 34 is placed on the n side after the VCSEL device has been removed from the host substrate.

[0058] Figure 7A illustrates typical chip dimensions for a single ELO bar, and Figure 7B shows several VCSEL devices with integrated ELO bars and hexagonal close-packed VCSEL units on a wafer.

[0059] advantage: 1. The contact layer inside the resonator does not overlap with the optical resonator. 2. Nanoporous DBR layer used for better heat sink performance. 3. The tilted arrangement of nanoporous DBRs reduces the electrical resistance of the device. 4. Angular emission is possible. 5. Better thermal management. 6. It is possible to profit by using cheaper, larger template substrates such as GaN on sapphire. 7. High-quality, larger-sized GaN substrates are extremely expensive. This ELO technology can enable the use of dissimilar substrates in the manufacturing of VCSELs. 8. The present invention is expected to provide significant improvements in performance and reduction of manufacturing costs, as well as the elimination of complex procedures.

[0060] Purpose illumination: GaN-based LEDs have brought about a dramatic transformation in residential and automotive lighting. Lighting combined with communication services is highly desired in future smart cities and smart infrastructure. VCSELs are a better alternative to LEDs and end-face-emitting laser diodes. However, the lack of suitable and profitable mass production technology has prevented GaN VCSELs from entering the market. The procedure developed in the above embodiment can be used to mass-produce VCSEL units applicable to lighting applications. Visible light communication:

[0061] Laser light for future potential data transfer and communication applications using Light Fidelity (LiFi). With the rapid increase in IoT devices, the demand for data transmission continues to expand. The RF spectrum is becoming saturated, and new frequencies are needed to keep up with the continuously increasing demand. Applying GaN VCSELs to existing LED configurations is simpler than replacing them with end-emitting lasers. Therefore, the devices described in the embodiments above can serve their purpose. Near-eye display:

[0062] Near-eye displays represent the next big wave in consumer electronics. These are key components of virtual reality (VR) and augmented reality (AR) technologies. Currently, micro-LEDs are the primary choice for displays. However, while progress in VCSEL research is limited, VCSELs will undoubtedly be introduced as miniature and near-eye displays. Relatively low light power is beneficial for maintaining eye safety. Low divergence and circular symmetry reduce the need for additional optical elements, thus resulting in compactness. The two-dimensional array integration capability of VCSELs is less complex than that of end-emitting lasers. Therefore, VCSEL products manufactured using the invention can be applied to these applications.

[0063] While the principles of the present invention have been described and illustrated in preferred embodiments, it will be understood by those skilled in the art that the present invention can be modified in arrangement and detail without departing from such principles. Accordingly, the inventors request all modifications and variations that fall within the spirit and scope of the following claims. [Explanation of Symbols]

[0064] 10 Group III nitride substrates 11 Group III Nitride Template 12 Opening Area Stripe 13 Dielectric Mask 14 Group III nitride layer 15 Wing 16 Nanoporous GaN DBR 17 n-GaN layer 18 Group III nitride active layer 19. Group III nitride p-type electron blocking layer (EBL) 20 p-type III-nitride layer 21 p ++ GaN layer 23 Insulating layer 24 Dielectric DBR 30 base seeds 31 Current injection region 32 Optical cavity region 33 p-contact pads 34 n-contact pads 35 circular sections 36. Shaded areas 37. Thermal diffusion layer 38 Luminous

Claims

1. An epitaxially laterally overgrown semiconductor region, composed of a group III nitride active region between a hole-injection group III nitride layer and an electron-injection group III nitride layer. A p-type mirror with an angled hole injection side, and A planar mirror, angled with respect to the group III nitride active region, includes a nanoporous layer on the electron injection side and a nonporous layer on the n side. This includes an extended vertical-cavity surface-emitting laser (VCSEL).

2. The VCSEL according to claim 1, wherein the planar mirror on the electron injection side includes a nanoporous group III nitride-based DBR.

3. The VCSEL according to claim 2, wherein the group III nitride-based DBR has an interface sandwiching alternating nanoporous regions and nonporous regions.

4. The VCSEL according to claim 2, wherein the group III nitride-based DBR is used for electron perpendicular current injection.

5. The VCSEL according to claim 2, wherein the group III nitride-based DBR is used for heat dissipation.

6. The interface of the group III nitride-based DBR is in contact with an n-contact pad, as described in claim 2.

7. The VCSEL according to claim 2, wherein the group III nitride-based DBR is formed by epitaxial lateral overgrowth.

8. The VCSEL according to claim 2, wherein the interface roughness between the group III nitride-based DBR and the dielectric mask is less than or equal to a nanometer.

9. The VCSEL according to claim 8, wherein chemical mechanical polishing (CMP), etching, and grinding are not used to smooth the surface of the group III nitride-based DBR.

10. The VCSEL according to claim 1, wherein the angled mirror on the p-type layer is a dielectric mirror.

11. The VCSEL according to claim 10, wherein the angled p-type layer is a semipolar surface of the group III nitride layer.

12. The VCSEL according to claim 11, wherein angled etching is used to obtain the semi-polar p-type layer.

13. The VCSEL according to claim 12, wherein a smooth surface is prepared for the semipolar angled p-type layer using a chemical treatment.

14. The VCSEL according to claim 1, wherein the current injection region is separated from the optical resonator region.

15. The VCSEL according to claim 14, wherein the current injection region includes a tunnel junction.

16. The VCSEL according to claim 1, wherein a heat diffuser is arranged on the p side of the VCSEL.

17. The VCSEL according to claim 2, wherein the group III nitride-based DBR directs light to the angled p-type layer-side mirror.

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