Switching power supply

Abstract

To provide a switching power supply device capable of suppressing insufficient charging of a bootstrap capacitor to prevent power supply stoppage.SOLUTION: When a voltage across both ends of a boot strap capacitor CB drops, a charging control unit 171 turns ON a transistor Q3 connected in series to a discharging resistor R3 to supply an output current of an output unit 11 to the discharging resistor R3. Alternately, when a voltage across both ends of the boot strap capacitor CB drops, the charging control unit 171 controls a low side NMOS transistor Q1 to be kept in an off state. Alternately, when a voltage across both ends of the boot strap capacitor CB drops, the charging control unit 171 lowers the duty cycle of a pulse signal outputted from a switch terminal TSW.SELECTED DRAWING: Figure 1

Description

Technical Field

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[0001] The present invention relates to a switching power supply device.

Background Art

[0002] In a switching power supply device, when driving an NMOS transistor on the high side, it is necessary to make the gate voltage higher than the source voltage. To achieve this, conventionally, a bootstrap section has been used (for example, Patent Document 1). The magnitude of the supply voltage from the bootstrap section is determined by the voltage across the bootstrap capacitor in the bootstrap section.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] For this reason, when the charging of the bootstrap capacitor is insufficient and the voltage across it drops, the high-side NMOS transistor cannot be turned on and off, and there is a problem that the operation of the switching power supply device stops and the power supply stops.

[0005] The present invention has been made in view of the above circumstances, and an object thereof is to provide a switching power supply device capable of suppressing insufficient charging of the bootstrap capacitor and suppressing power supply stop.

Means for Solving the Problems

[0006] In order to achieve the above object, the switching power supply device according to the present invention is characterized by the following [1] to 5 . ​A switching power supply device that controls an output section that outputs an output voltage obtained by converting the input voltage, A low-side NMOS transistor and a high-side NMOS transistor connected in series with each other, A control unit controls the output section by alternately turning on the low-side NMOS transistor and the high-side NMOS transistor, A bootstrap section generates a boot voltage that is shifted to the high-voltage side by the voltage across the bootstrap capacitor from the source potential of the high-side NMOS transistor in order to drive the high-side NMOS transistor, The system includes a charging control unit that controls the control unit to keep the low-side NMOS transistor permanently off when it is determined that the voltage across the bootstrap capacitor is low or likely to decrease. It must be a switching power supply. [2] A switching power supply device that controls an output section that outputs an output voltage obtained by converting the input voltage, A low-side NMOS transistor and a high-side NMOS transistor connected in series with each other, A control unit controls the output section by alternately turning on the low-side NMOS transistor and the high-side NMOS transistor, A bootstrap section generates a boot voltage that is shifted to the high-voltage side by the voltage across the bootstrap capacitor from the source potential of the high-side NMOS transistor in order to drive the high-side NMOS transistor, The system includes a charge control unit that, when it is determined that the voltage across the bootstrap capacitor is low or likely to low, controls the control unit to reduce the duty cycle of the on / off control of the low-side NMOS transistor and the high-side NMOS transistor, It must be a switching power supply. [3] [1] or [2] In the switching power supply device described above, The system further includes a voltage detection unit that outputs the result of comparing the voltage across the bootstrap capacitor with a threshold voltage. The charging control unit determines, based on the comparison result of the voltage detection unit, that the voltage across the bootstrap capacitor has decreased. It must be a switching power supply. [4] [1]~[ 3 In a switching power supply device described in any one of the items in ], The system includes a determination unit that determines at least one of the following: whether or not it is startup, whether or not the output voltage is overvoltage, and whether or not a pulse skip is occurring. The charging control unit determines, based on the determination result of the determination unit, that there is a possibility that the voltage across the bootstrap capacitor may decrease. It must be a switching power supply. [5] A switching power supply device that controls an output section that outputs an output voltage obtained by converting the input voltage, A low-side NMOS transistor and a high-side NMOS transistor connected in series with each other, A control unit controls the output section by alternately turning on the low-side NMOS transistor and the high-side NMOS transistor, A bootstrap section generates a boot voltage that is shifted to the high-voltage side by the voltage across the bootstrap capacitor from the source potential of the high-side NMOS transistor in order to drive the high-side NMOS transistor, A voltage detection unit that outputs the result of comparing the voltage across the bootstrap capacitor with a plurality of threshold voltages, Each time the voltage detection unit outputs a comparison result indicating that the voltage is below the threshold voltage, it sequentially executes a combination of at least two of the following: a first charge control that turns on a switch connected in series with the discharge resistor to supply the output current of the output unit to the discharge resistor; a second charge control that controls the control unit to keep the high-side NMOS transistor in the off state at all times; and a third charge control that controls the control unit to reduce the duty cycle of the on / off control of the low-side NMOS transistor and the high-side NMOS transistor. It must be a switching power supply. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a switching power supply device that can suppress insufficient charging of bootstrap capacitors and suppress power outages.

[0008] The present invention has been briefly described above. Furthermore, the details of the present invention will be further clarified by referring to the attached drawings and reading through the embodiments for carrying out the invention described below (hereinafter referred to as "embodiments"). [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a circuit diagram showing a DC / DC converter incorporating the switching power supply device of the present invention in the first embodiment. [Figure 2] Figure 2 is a time chart showing the on / off states of the high-side NMOS transistor, the low-side NMOS transistor, the potential at the switch terminal, the coil current, and the voltage across the bootstrap capacitor under normal conditions. [Figure 3] Figure 3 shows the time chart of the switch terminal potential, coil current, and voltage across the bootstrap capacitor when the duty cycle is high and the load current is low. [Figure 4] Figure 4 is a time chart of the output voltage and switch terminal potential shown in Figure 1 when the output voltage exceeds the target voltage. [Figure 5] FIG. 5 is a time chart of the potential of the switch terminal, the coil current, and the voltage across the bootstrap capacitor when current is supplied to the discharge unit shown in FIG. 1. [Figure 6] FIG. 6 is a time chart of the on / off of the low-side NMOS transistor, the on / off of the high-side NMOS transistor, the potential of the switch terminal, the coil current, and the voltage across the bootstrap capacitor when the low-side NMOS transistor is always off. [Figure 7] FIG. 7 is a circuit diagram showing a DC / DC converter incorporating the switching power supply device of the present invention in the second embodiment.

Embodiments for Carrying Out the Invention

[0010] (First Embodiment) The first embodiment of the present invention will be described below with reference to the respective drawings.

[0011] The DC / DC converter 1 of this embodiment supplies an output voltage VOUT obtained by stepping down an input voltage VIN to a load 2. The input voltage VIN is supplied from a DC power supply 3. The DC / DC converter 1 includes an output unit 11 that steps down the input voltage VIN and outputs it as an output voltage VOUT, a switching power supply device 12 that supplies a pulsed input voltage VIN to the output unit 11, and a bootstrap capacitor CB.

[0012] The output unit 11 includes a coil L1 and an output capacitor C1. The coil L1 is connected between the switch terminal TSW of the switching power supply device 12 and the load 2. One end of the load 2 is connected to the coil L1, and the other end is connected to the ground. One end of the output capacitor C1 is connected to the connection point of the coil L1 and the load 2, and the other end is connected to the ground.

[0013] The switching power supply unit 12 is composed of IC chips. The switching power supply unit 12 includes a low-side NMOS transistor Q1 (hereinafter sometimes abbreviated as "transistor Q1"), a high-side NMOS transistor Q2 (hereinafter sometimes abbreviated as "transistor Q2"), driver units (indicated as "DRV" in Figure 1) 131, 132, a bootstrap unit 14, an output voltage detection unit 15, an error detection unit 16, a PWM control unit 17 as a control unit, a discharge unit 18, and a boot voltage detection unit 19 as a voltage detection unit.

[0014] Transistors Q1 and Q2 are composed of N-channel power MOSFETs (metal-oxide semiconductor field-effect transistors). The source of the low-side NMOS transistor Q1 is connected to ground, and its drain is connected to the switch terminal TSW. The source of the high-side NMOS transistor Q2 is connected to the switch terminal TSW and the drain of transistor Q1, and its drain is connected to the input terminal TIN. The input voltage VIN supplied from the DC power supply 3 is input to the input terminal TIN.

[0015] As shown in Figure 2, when transistor Q2 is ON and transistor Q1 is OFF, the input voltage VIN is output from the switch terminal TSW. Conversely, when transistor Q2 is OFF and transistor Q1 is ON, the ground potential of 0V is output from the switch terminal TSW. By alternately controlling transistors Q1 and Q2 to be ON, a pulse signal (= pulsed input voltage VIN) with a high level being the input voltage VIN and a low level being 0V is output from the switch terminal TSW. By inputting this pulse signal to the output unit 11 and smoothing it with the coil L1 and output capacitor C1, an output voltage VOUT corresponding to the duty cycle of the pulse signal can be supplied to the load 2.

[0016] Furthermore, to prevent a short circuit in the DC power supply 3 when transistors Q1 and Q2 are switched on or off, a dead time DT is provided during which both transistors Q1 and Q2 are turned off. During the dead time DT, the potential of the switch terminal TSW is -0.7V, which is the potential lowered by 0.7V from the ground potential of 0V by the forward voltage of the parasitic diode of transistor Q1.

[0017] As shown in Figure 1, the driver unit 131 is connected to the gate of transistor Q1 and is a circuit that drives the on / off switching of transistor Q1. The driver unit 131 operates by receiving power from the gate drive power supply (labeled "LDO" in Figure 1) 141. The driver unit 131 outputs a pulse signal to the gate of transistor Q1 where the H level is the gate drive voltage VG (e.g., 5V) and the L level is the ground potential of 0. When the pulse signal output from the driver unit 131 is at the H level, transistor Q1 is turned on, and when it is at the L level, transistor Q1 is turned off.

[0018] The driver unit 132 is connected to the gate of transistor Q2 and is a circuit that drives the on / off switching of transistor Q2. When transistor Q2 is turned on, its source potential becomes equal to the input voltage VIN. For this reason, even if the gate drive voltage VG is supplied to the gate of transistor Q2 in the same way as transistor Q1, it is not possible to maintain the ON state of transistor Q2. Therefore, the driver unit 132 operates by receiving power from the bootstrap unit 14, which will be described later. The bootstrap unit 14 is a circuit that uses a bootstrap capacitor CB to generate a boot voltage VB by adding the voltage across the bootstrap capacitor CB to the potential of the switch terminal TSW (i.e., the source potential of transistor Q2). The voltage across the bootstrap capacitor CB is, under normal conditions, approximately equal to the gate drive voltage VG, as will be described later.

[0019] The driver unit 132 outputs a pulse signal to the gate of transistor Q2, where the high level is the boot voltage VB and the low level is the potential of the switch terminal TSW. Transistor Q2 turns on when the pulse signal output from the driver unit 132 is high, and turns off when it is low.

[0020] The bootstrap section 14 includes a gate drive power supply 141 and a diode D1. The gate drive power supply 141 generates and outputs a gate drive voltage VG from the input voltage VIN. The anode of the diode D1 is connected to the gate drive power supply 141, and one end of the bootstrap capacitor CB is connected to the cathode via the boot terminal TB. The other end of the bootstrap capacitor CB is connected to the switch terminal TSW.

[0021] When the driver unit 131 supplies a gate drive voltage VG (a high-level pulse signal) to the gate of transistor Q1, transistor Q1 turns on. When the driver unit 132 supplies the potential of the switch terminal TSW (a low-level pulse signal) to the gate of transistor Q2, transistor Q2 turns off. When transistor Q1 is on and transistor Q2 is off, the switch terminal TSW is at ground potential 0V. When the switch terminal TSW is at ground potential 0V, current from the gate drive power supply 141 is supplied to the bootstrap capacitor CB via diode D1, and the bootstrap capacitor CB is charged. As a result, as shown in Figure 2, the voltage across the bootstrap capacitor CB rises toward the gate drive voltage VG. In particular, during the dead time DT, the potential of the switch terminal TSW is -0.7V, so the bootstrap capacitor CB charges quickly.

[0022] Next, when the driver unit 131 supplies ground potential (L-level pulse signal) to transistor Q1, transistor Q1 turns off. When the driver unit 132 supplies boot voltage VB (H-level pulse signal) to transistor Q2, transistor Q2 turns on. During this switching, the potential of the switch terminal TSW, i.e., the source potential of transistor Q2, rises from ground to the input voltage VIN. However, although the bootstrap capacitor CB discharges slowly as shown in Figure 2, the voltage across it remains almost equal to the gate drive voltage VG, so the boot voltage VB is always equal to the source potential of transistor Q2 + the gate drive voltage VG, and transistor Q2 remains ON. In addition, due to the action of diode D1, current from the bootstrap capacitor CB does not flow into the gate drive power supply 141.

[0023] As shown in Figure 1, the output voltage detection unit 15 outputs a detection voltage VR corresponding to the output voltage VOUT to the error detection unit 16, which will be described later. The output voltage detection unit 15 has resistors R1 and R2. One end of resistor R1 is connected to ground, and the other end is connected to one end of resistor R2. The other end of resistor R2 is connected via the feedback terminal TFB to the connection point between coil L1 and capacitor C1 (= output of output unit 11). The detection voltage VR, obtained by dividing the output voltage VOUT by resistors R1 and R2, is output at the connection point of resistors R1 and R2.

[0024] The error detection unit 16 outputs an error signal VFB, which is an amplified error between the detected voltage VR and the reference voltage VREF, to the PWM control unit 17. The reference voltage VREF is set to be equal to the detected voltage VR output from the output voltage detection unit 15 when the output voltage VOUT reaches the target voltage. The PWM control unit 17 controls the driver units 131 and 132 so that pulse signals with a duty cycle corresponding to the error signal VFB are output from the driver units 131 and 132.

[0025] In the DC / DC converter 1 described above, there was a problem in that if the bootstrap capacitor CB was not sufficiently charged, the transistor Q2 could not be turned on, and the power supply would stop. The causes of insufficient charging of the bootstrap capacitor CB include the following: As shown in Figure 3, for example, when the potential difference between the input voltage VIN and the output voltage VOUT is small, the duty cycle of the pulse signal output from the switch terminal TSW becomes high. When the duty cycle becomes high, the time during which the potential of the switch terminal TSW is low (ground potential) becomes shorter, and the bootstrap capacitor CB becomes insufficiently charged.

[0026] Furthermore, when the load current flowing through load 2 (half of the ripple current ΔIL1 of coil L1 shown in Figure 2) is small, a reverse current is generated from capacitor C1 to coil L1 when transistor Q1 is on and transistor Q2 is off. Subsequently, when both transistors Q1 and Q2 are turned off (dead time DT), the reverse current flows to the input terminal TIN through the parasitic diode of transistor Q2. As a result, as shown in Figure 3, during dead time DT, the potential of the switch terminal TSW becomes the input voltage VIN + the forward voltage of the parasitic diode 0.7V (high level). Consequently, the charging time of the bootstrap capacitor CB is shortened, and the bootstrap capacitor CB is undercharged.

[0027] Furthermore, as shown in Figure 4, if the output voltage VOUT exceeds the target voltage, pulse skipping occurs in the pulse signal, the switching operation stops, and the switch terminal TSW enters a high-impedance state, resulting in insufficient charging of the bootstrap capacitor CB.

[0028] Therefore, in this embodiment, the DC / DC converter 1, as shown in Figure 1, includes a discharge unit 18, a boot voltage detection unit 19, and a charge control unit 171. The discharge unit 18 includes a discharge resistor R3 and a transistor Q3. The discharge resistor R3 is connected between the feedback terminal TFB and the drain of the transistor Q3. The source of the transistor Q3 is connected to ground, and the gate is connected to the charge control unit 171, which will be described later. When the transistor Q3 is turned on, the output current of the output unit 11 can be supplied to the discharge resistor R3.

[0029] In this embodiment, the boot voltage detection unit 19 includes a first voltage detector 191, a second voltage detector 192, and a third voltage detector 193. The first to third voltage detectors 191 to 193 detect the voltage across the bootstrap capacitor CB and output the comparison result between the detected voltage across the bootstrap capacitor CB and the first to third threshold voltages (for example, first threshold voltage = 4V, second threshold voltage = 3V, third threshold voltage = 2V) to the charge control unit 171.

[0030] Based on the comparison results of the first to third voltage detectors 191 to 193, the charge control unit 171 performs one of the following actions (A) to (C) to increase the charge amount of the bootstrap capacitor CB each time the voltage across the bootstrap capacitor CB falls below the first to third threshold voltages.

[0031] (A) The charge control unit 171 turns on transistor Q3, causing the output current of the output unit 11 to flow towards the discharge resistor R3. In this case, as is clear from comparing Figure 3 and Figure 5, the output current increases, preventing reverse current from flowing through the coil L1. Therefore, during the dead time DT when both transistors Q1 and Q2 are off, the potential of the switch terminal TSW can be set to an L level (-0.7V). This allows the charging time of the bootstrap capacitor CB to be extended, and the amount of charge of the bootstrap capacitor CB to be increased.

[0032] (B) As shown in Figure 6, the charge control unit 171 controls the driver unit 131 so that transistor Q1 is always off, and controls the driver unit 132 so that transistor Q2 is turned on and off with a duty cycle corresponding to the error signal VFB. In this case, as is clear from the comparison of Figure 3 and Figure 6, the dead time DT is always present when transistor Q2 is off, and the potential of the switch terminal TSW can be continuously kept at -0.7V. Therefore, the charging time of the bootstrap capacitor CB can be extended and charging can be accelerated, and the amount of charge of the bootstrap capacitor CB can be increased.

[0033] (C) The charging control unit 171 controls the driver units 131 and 132 to forcibly reduce the duty cycle of the pulse signals output from them. The PWM control unit 17 has a built-in oscillator and converts the pulse signal of the oscillator's oscillation frequency into a duty cycle corresponding to the error signal VFB and outputs it to the gates of transistors Q1 and Q2. Therefore, when the voltage across the bootstrap capacitor CB is low, the charging control unit 171 lowers the oscillator frequency and forcibly reduces the duty cycle of the pulse signals output from the driver units 131 and 132. In other words, it reduces the duty cycle of the on / off control of transistors Q1 and Q3. As a result, the charging time of the bootstrap capacitor CB can be extended and the amount of charge of the bootstrap capacitor CB can be increased. In this way, forcibly reducing the duty cycle may cause the output voltage VOUT to decrease, but the worst-case scenario of power supply interruption due to insufficient charge of the bootstrap capacitor CB can be avoided.

[0034] In this embodiment, the charge control unit 171 executes the first charge control described in (A) above when the voltage across the bootstrap capacitor CB falls below the first threshold voltage. The charge control unit 171 also executes the second charge control described in (B) above when the voltage across the bootstrap capacitor CB falls below the second threshold voltage. Furthermore, the charge control unit 171 executes the third charge control described in (C) above when the voltage across the bootstrap capacitor CB falls below the third threshold voltage.

[0035] According to the embodiment described above, when the voltage across the bootstrap capacitor CB decreases, the output current from the output unit 11 is passed through the discharge resistor R3 to increase the output current and thereby increase the charge level of the bootstrap capacitor CB. This suppresses insufficient charging of the bootstrap capacitor CB and prevents power outages.

[0036] According to the embodiment described above, when the voltage across the bootstrap capacitor CB drops, the low-side NMOS transistor Q1 can be kept off at all times, increasing the charge level of the bootstrap capacitor CB. This suppresses insufficient charging of the bootstrap capacitor CB and prevents power outages.

[0037] According to the embodiment described above, when the voltage across the bootstrap capacitor CB drops, the duty cycle of the pulse signals output from the driver units 131 and 132 can be forcibly reduced to increase the charge level of the bootstrap capacitor CB. This suppresses insufficient charging of the bootstrap capacitor CB and prevents power outages.

[0038] According to the embodiment described above, each time the voltage across the bootstrap capacitor CB falls below the first threshold voltage to the third threshold voltage, the charge control unit 171 sequentially executes the first charge control (A) to the third charge control (C). This makes it possible to suppress undercharging of the bootstrap capacitor CB with even greater precision and to suppress power outages.

[0039] In the first embodiment described above, steps (A) to (C) were performed in order each time the voltage across the bootstrap capacitor CB fell below the first to third threshold voltages, but this is not the only order. The order of steps (A) to (C) can be any order.

[0040] Furthermore, while the first embodiment described above provided three threshold voltages for the bootstrap capacitor CB, it is not limited to this. Alternatively, two threshold voltages may be provided, and two of (A) to (C) may be executed sequentially each time the voltage across the bootstrap capacitor CB falls below the threshold voltage. Alternatively, only one threshold voltage may be provided, and one of (A) to (C) may be executed each time the voltage across the capacitor CB falls below the threshold voltage.

[0041] Furthermore, in the first embodiment described above, the charge control unit 171 performed one of the first charge control (A) to the second charge control (C), but it is not limited to this. The charge control unit 171 may perform two or more of the first charge control (A) to the second charge control (C) simultaneously.

[0042] (Second Embodiment) Next, a specific second embodiment of the present invention will be described below with reference to Figure 7. In Figure 7, parts equivalent to the DC / DC converter 1 shown in Figure 1, which was already described in the first embodiment above, are denoted by the same reference numerals, and their detailed description is omitted.

[0043] As shown in the figure, the DC / DC converter 1B includes an output unit 11, a switching power supply unit 12B, and a bootstrap capacitor CB. The output unit 11 and the bootstrap capacitor CB are the same as in the first embodiment, so a detailed explanation is omitted here.

[0044] The switching power supply unit 12B includes, in addition to the transistors Q1 and Q2, driver units 131 and 132, bootstrap unit 14, output voltage detection unit 15, error detection unit 16, PWM control unit 17, discharge unit 18, and boot voltage detection unit 19 already described in the first embodiment, an overvoltage detection unit 20, a soft start detection unit 21, a pulse skip detection unit 22 as determination units, and an OR circuit 23.

[0045] In the first embodiment described above, the charge control unit 171 directly detected the voltage across the capacitor CB, determined that the voltage across the capacitor CB was decreasing, and executed the first charge control (A) to the third charge control (C) described above. However, it is not limited to this. The charge control unit 171 may also execute the first charge control (A) to the third charge control (C) described above if there is a possibility that the voltage across the capacitor CB will decrease.

[0046] The DC / DC converter 1 is equipped with a function that stops the switching operation of transistors Q1 and Q2 when the output voltage VOUT becomes overvoltage. When the switching operation is stopped, similar to the pulse skip described above, undercharging of the bootstrap capacitor CB may occur, and the voltage across the bootstrap capacitor CB may drop. Therefore, the switching power supply unit 12B of this embodiment is equipped with an overvoltage detection unit 20. The overvoltage detection unit 20 determines that there is an overvoltage when the detected voltage VR exceeds the overvoltage threshold and outputs this information to the OR circuit 23.

[0047] Furthermore, when the DC / DC converter 1 is started up, the bootstrap capacitor CB is often not charged, and the input voltage VIN may be low. Therefore, there is a high possibility that the voltage across capacitor CB will drop. To address this, the switching power supply unit 12B of this embodiment is equipped with a soft-start determination unit 21. The DC / DC converter 1 has a soft-start function that lowers the reference voltage VREF to a set value at startup and gradually raises it to the set value. The soft-start determination unit 21 determines that it is a soft-start if the reference voltage VREF is lower than the set value, and outputs this information to the OR circuit 23.

[0048] Furthermore, as mentioned above, if the output voltage VOUT exceeds the target voltage and a pulse skip occurs, the bootstrap capacitor CB may become undercharged, potentially causing a drop in the voltage across the bootstrap capacitor CB. Therefore, the switching power supply 12B of this embodiment is equipped with a pulse skip determination unit 22. The pulse skip determination unit 22 monitors the error signal VFB and, when it determines that the output voltage VOUT has reached the target voltage and a pulse skip has occurred, it outputs a message to that effect to the OR circuit 23.

[0049] The OR circuit 23 is connected to the charge control unit 171, and if it determines that one of the following has occurred—overvoltage, soft start, or pulse skip—it informs the charge control unit 171 of this fact. If one or more of the following have occurred, the charge control unit 171 determines that the bootstrap capacitor CB is undercharged or is likely to become undercharged, and executes at least one of the first charge control (A) to the second charge control (C) described above.

[0050] According to the embodiment described above, when there is a high probability that the voltage across the bootstrap capacitor CB will decrease, one of the first charge control (A) to the third charge control (C) is executed. This suppresses insufficient charging of the bootstrap capacitor CB and prevents power outages.

[0051] In addition, according to the second embodiment described above, the switching power supply 12B has three determination units: an overvoltage determination unit 20, a soft start determination unit 21, and a pulse skip determination unit 22, but it is not limited to this. The switching power supply 12B only needs to have at least one of the overvoltage determination unit 20, the soft start determination unit 21, and the pulse skip determination unit 22.

[0052] Furthermore, in the second embodiment described above, the switching power supply 12B had a boot voltage detection unit 19 and performed the first charge control (A) to the third charge control (C) based on a comparison between the voltage across the bootstrap capacitor CB and the threshold voltage, but it is not limited to this. The switching power supply 12B does not have to have a boot voltage detection unit 19, and may perform the first charge control (A) to the third charge control (C) only according to the determination result of the determination units 20 to 22.

[0053] Furthermore, the present invention is not limited to the embodiments described above, and can be modified, improved, etc., as appropriate. In addition, the material, shape, dimensions, number, placement, etc. of each component in the embodiments described above are arbitrary and not limited, as long as they can achieve the present invention.

[0054] According to the embodiment described above, the output unit 11 was configured as a step-down type, but it is not limited to this. The output unit 11 may also be configured as a step-up type that converts the input voltage to a step-up type. [Explanation of symbols]

[0055] 11 Output section 12 Switching power supply 14 Bootstrap section 17 PWM Control Unit (Control Unit) 19 Boot voltage detection unit (voltage detection unit) 20 Overvoltage detection unit (determination unit) 21. Soft Start Judgment Unit (Judgment Unit) 22 Pulse skip determination unit (determination unit) 171 Charging Control Unit CB Bootstrap Capacitor Q1 Low-side NMOS transistor Q2 High-side NMOS transistor Q3 Transistor (switch) R3 discharge resistance VB Boot Voltage VIN Input Voltage VOUT output voltage

Claims

1. A switching power supply device that controls an output section that outputs an output voltage obtained by converting the input voltage, A low-side NMOS transistor and a high-side NMOS transistor connected in series with each other, A control unit controls the output section by alternately turning on the low-side NMOS transistor and the high-side NMOS transistor, To drive the high-side NMOS transistor, a bootstrap section generates a boot voltage that is shifted to the high-voltage side by the voltage across the bootstrap capacitor from the source potential of the high-side NMOS transistor, The system includes a charging control unit that controls the control unit to keep the low-side NMOS transistor permanently off when it is determined that the voltage across the bootstrap capacitor is low or likely to decrease. Switching power supply.

2. A switching power supply device that controls an output section that outputs an output voltage obtained by converting the input voltage, A low-side NMOS transistor and a high-side NMOS transistor connected in series with each other, A control unit controls the output section by alternately turning on the low-side NMOS transistor and the high-side NMOS transistor, To drive the high-side NMOS transistor, a bootstrap section generates a boot voltage that is shifted to the high-voltage side by the voltage across the bootstrap capacitor from the source potential of the high-side NMOS transistor, The system includes a charge control unit that, when it is determined that the voltage across the bootstrap capacitor is low or likely to low, controls the control unit to reduce the duty cycle of the on / off control of the low-side NMOS transistor and the high-side NMOS transistor, Switching power supply.

3. In the switching power supply device according to claim 1 or 2, The system further includes a voltage detection unit that outputs the result of comparing the voltage across the bootstrap capacitor with a threshold voltage. The charging control unit determines, based on the comparison result of the voltage detection unit, that the voltage across the bootstrap capacitor has decreased. Switching power supply.

4. In a switching power supply device according to any one of claims 1 to 3, The system includes a determination unit that determines at least one of the following: whether or not it is startup, whether or not the output voltage is overvoltage, and whether or not a pulse skip is occurring. The charging control unit determines, based on the determination result of the determination unit, that there is a possibility that the voltage across the bootstrap capacitor may decrease. Switching power supply.

5. A switching power supply device that controls an output section that outputs an output voltage obtained by converting the input voltage, A low-side NMOS transistor and a high-side NMOS transistor connected in series with each other, A control unit controls the output section by alternately turning on the low-side NMOS transistor and the high-side NMOS transistor, To drive the high-side NMOS transistor, a bootstrap section generates a boot voltage that is shifted to the high-voltage side by the voltage across the bootstrap capacitor from the source potential of the high-side NMOS transistor, A voltage detection unit that outputs the result of comparing the voltage across the bootstrap capacitor with a plurality of threshold voltages, Each time the voltage detection unit outputs a comparison result indicating that the voltage falls below the threshold voltage, it sequentially executes a combination of at least two of the following: a first charge control that turns on a switch connected in series with the discharge resistor to supply the output current of the output unit to the discharge resistor; a second charge control that controls the control unit to keep the high-side NMOS transistor in the off state at all times; and a third charge control that controls the control unit to reduce the duty cycle of the on / off control of the low-side NMOS transistor and the high-side NMOS transistor. Switching power supply.

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