Manufacturing method for multilayer structures

Abstract

The characteristics of the PZT layer are improved with good throughput. [Solution] The method for manufacturing a multilayer structure comprises: a first epitaxial deposition step of forming a first layer oriented to the (100) plane on the (100) plane of a silicon substrate by sputtering; a second epitaxial deposition step of forming a second layer of Pt oriented to the (100) plane on the first layer by sputtering; and a third epitaxial deposition step of forming a third layer oriented to the (100) plane on the second layer by sputtering.

Description

[Technical Field]

[0001] This invention 、 Manufacturing method for multilayer structures to To relate to. [Background technology]

[0002] Pure zirconia (Pure-ZrO2) typically has a monoclinic crystal structure; to obtain a cubic crystal structure, it is necessary to use yttria-stabilized zirconia (YSZ).

[0003] Patent Document 1 describes a technique for growing cubic crystal films using YSZ. In Patent Document 1, to grow Pt or SrRuO3 on the (100) plane on a YSZ layer, a ceria (CeO2) film is placed between the ZrO2 and the upper layer, rotated by 45°, and Si <110> The epiphytic growth is parallel to the direction of growth. Patent Document 2 describes how to orient Pt to the (100) plane without using CeO2 by using ZrO2, and Si <100> It is described that epigenesis occurs parallel to this. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2005-005450 [Patent Document 2] U.S. Patent No. 11785854 [Overview of the project] [Problems that the invention aims to solve]

[0005] However, the technology described in Patent Document 1 increases the number of layers, which is undesirable for mass production. Furthermore, in the technology described in Patent Document 2, ZrO2 is usually monoclinic and has a kinetic energy of 10 -1 eV~10 -2 Compared to the eV deposition method, the sputtering method has a kinetic energy of 10 2eV ~ 10 3 Since it is as high as eV and the film is likely to be distorted, it is difficult to obtain cubic crystals with Pure-ZrO2. In the technology of Patent Document 2, two different chambers of evaporation and sputtering are required, which is not preferable.

[0006] The present invention has been made in view of the above circumstances, and aims to achieve the following objects. 1. To enable all film formation by sputtering and to make it possible to manufacture by in-situ continuous film formation. 2. To be able to manufacture a film oriented in the same direction as the silicon substrate. 3. To reduce the number of processes and improve the manufacturing efficiency.

Means for Solving the Problems

[0007] Piezoelectric elements using ferroelectrics such as lead zirconate titanate (Pb(Zr,Ti)O3: PZT) are applied to devices such as inkjet heads, micromirrors, gyro sensors, PMUT (Piezoelectric Micromachined Ultrasonic Transducer), vibration elements, elastic wave elements, and acceleration sensors in MEMS (MicroElectroMechanical Systems) technology. Among them, PZT films have attracted attention.

[0008] Each device using PZT has a preferable performance index (e 31,f ) 2 / ε [GPa], and the range is different for each device. The performance index (e 31,f ) 2 / ε [GPa] is defined by the piezoelectric constant e 31,f [C / m 2 , and the relative permittivity ε r . Here, for some devices, there is a requirement to increase the piezoelectric constant and decrease the permittivity. In this case, the performance index will not improve unless the two conditions are made compatible. For this purpose, it is preferable to epitaxially grow a c-axis oriented PZT film with a tetragonal composition.

[0009] In this context, it is generally difficult to orient tetragonal PZT thin films along the c axis by epitaxial growth on a Si substrate. This is attributed to the difference in thermal expansion coefficients between Si and PZT, and it is known that they inevitably preferentially orient along the a axis. In the technology described in Patent Document 1, the crystal orientation of the PZT film rotates, making it impossible to grow it in the same direction as Si. Furthermore, there was a demand to reduce the number of layers and enable epitaxial growth of tetragonal PZT-based thin films. At the same time, there was a demand to enable consistent in-situ film deposition and improve throughput.

[0010] The inventors of this application have diligently conducted research and have found a way to orient Pt to (100) without using CeO2, and also Si <100> This method, which involves epitaxial growth parallel to the grain, was discovered for the first time using the sputtering technique. Furthermore, this technology provides a process that allows all steps in the fabrication of PZT epitaxial films suitable for devices such as sensors to be carried out consistently by sputtering.

[0011] (1) A method for manufacturing a multilayer structure according to one aspect of the present invention is: A first epitaxial deposition process is performed in which a first layer (with or without a seed layer) oriented on the (100) plane of a silicon substrate is formed by sputtering, A second epitaxial deposition step is performed to form a second layer of Pt oriented in the (100) plane on the first layer by sputtering, A third epitaxial deposition step is performed in which a third layer (buffer layer) oriented in the (100) plane is formed on the second layer by sputtering, Having, This resolved the above issues. (2) The method for manufacturing the multilayer structure of the present invention is as described in (1) above, The first epitaxial film deposition step is: The process includes the steps of etching the surface of the silicon substrate and forming a film of YSZ (Y2O3- doped ZrO2; Y-ZrO2) as the first layer at a temperature of 700°C or higher to a thickness of 200 nm to 500 nm, The process includes a step of forming a film with YSZ as the first layer at a temperature of 650°C or higher to a thickness of 200 nm to 500 nm without removing the silicon oxide on the surface of the silicon substrate, or The process comprises the steps of: depositing a Zr seed layer to a thickness of 1.5 nm to 3.5 nm at 400°C or higher without removing silicon oxide from the surface of the silicon substrate; and depositing YSZ as the first layer on the seed layer to a thickness of 200 nm to 500 nm at 650°C or higher. The process comprises the steps of: depositing a Zr seed layer to a thickness of 1.5 nm to 3.5 nm at 400°C or higher without removing silicon oxide from the surface of the silicon substrate; and depositing YSZ as the first layer on the seed layer to a thickness of 18 nm to 67 nm at 650°C or higher. It is one of the following: It is possible. (3) The method for manufacturing the multilayer structure of the present invention is as described in (1) above, The first epitaxial film deposition step involves depositing YSZ as the first layer to a film thickness of 25 nm to 50 nm, The second epitaxial film formation step comprises a step of forming a film of Pt as the second layer at a temperature of 500°C or higher. It is possible. (4) The method for manufacturing the multilayer structure of the present invention is as described in (1) above, In the third epitaxial deposition step, the third layer (buffer layer) is SrRuO3 or LaNiO3. It is possible. (5) The method for manufacturing the multilayer structure of the present invention is as described in (1) above, The process includes a fourth epitaxial deposition step, in which, after the third epitaxial deposition step, a PZT layer oriented in the (100) plane is formed on the third layer by sputtering. It is possible. (6) The method for manufacturing the multilayer structure of the present invention is as described in (5) above, In the fourth epitaxial film deposition step, the PZT layer is doped with La and Ni. It is possible. (7) A multilayer structure according to another aspect of the present invention is manufactured by the method for manufacturing a multilayer structure described in (5) or (6) above. The first layer (with or without a seed layer) containing Zr oriented on the (100) plane is formed on the (100) plane of the silicon substrate. A second layer of Pt oriented in the (100) plane is formed on the first layer. A third layer (buffer layer) oriented in the (100) plane is formed on the second layer. The PZT layer oriented in the (100) plane is formed on the third layer. It is possible. (8) The method for manufacturing the multilayer structure of the present invention is as described in (7) above, The PZT layer has a piezoelectric constant e 31,f [Cm 2 The ratio is 10.0-11.9, the dielectric loss is 1.0%-1.8%, and the relative permittivity ε is 200-375 [dimensionless]. It is possible.

[0012] (1) A method for manufacturing a multilayer structure according to one aspect of the present invention is: A first epitaxial deposition process is performed in which a first layer (with or without a seed layer) oriented on the (100) plane of a silicon substrate is formed by sputtering, A second epitaxial deposition step is performed to form a second layer of Pt oriented in the (100) plane on the first layer by sputtering, A third epitaxial deposition step is performed in which a third layer (buffer layer) oriented in the (100) plane is formed on the second layer by sputtering, Having, This resolved the above issues.

[0013] In the above configuration, all layers can be manufactured by consistent in-situ sputtering, and all layers can be stacked and grown with the same plane orientation. This makes it possible to obtain a Pt layer oriented in the same (100) plane as silicon by epitaxial growth, which was not possible with conventional methods. Therefore, by forming a PZT layer on top of the Pt layer, it is possible to manufacture an epitaxial PZT film with a tetragonal composition and orientation in a predetermined direction, thereby improving the film properties of the PZT film, reducing the number of processes, and improving manufacturing efficiency.

[0014] (2) The method for manufacturing the multilayer structure of the present invention is as described in (1) above, The first epitaxial film deposition step is: The process includes the steps of etching the surface of the silicon substrate and forming a film of YSZ (Y2O3- doped ZrO2; Y-ZrO2) as the first layer at a temperature of 700°C or higher to a thickness of 200 nm to 500 nm, The process includes a step of forming a film with YSZ as the first layer at a temperature of 650°C or higher to a thickness of 200 nm to 500 nm without removing the silicon oxide on the surface of the silicon substrate, or The process comprises the steps of: depositing a Zr seed layer to a thickness of 1.5 nm to 3.5 nm at 400°C or higher without removing silicon oxide from the surface of the silicon substrate; and depositing YSZ as the first layer on the seed layer to a thickness of 200 nm to 500 nm at 650°C or higher. The process comprises the steps of: depositing a Zr seed layer to a thickness of 1.5 nm to 3.5 nm at 400°C or higher without removing silicon oxide from the surface of the silicon substrate; and depositing YSZ as the first layer on the seed layer to a thickness of 18 nm to 67 nm at 650°C or higher. It is one of the following: It is possible.

[0015] In the above configuration, by selecting the conditions for the first epitaxial deposition process from any of the above options, a cubic YSZ film capable of forming a Pt layer oriented to the (100) plane by epitaxial growth can be obtained. In particular, even when performing X-ray scans such as φ scan and 2θ scan, no side peaks other than (100) appear, meaning that a YSZ film oriented to the (100) plane can be obtained. Here, YSZ is ZrO2 doped with Y2O3-; Y-ZrO2. In particular, when a seed layer is used, it is preferable to perform RTA (Rapid Thermal Annealing) heat treatment after sputtering a zirconium metal film. Furthermore, the seed layer is not particularly limited in whether it is integrated with the first layer as a multilayer structure, or whether it is separable, detectable, and movable.

[0016] (3) The method for manufacturing the multilayer structure of the present invention is as described in (1) above, The first epitaxial film deposition step involves depositing YSZ as the first layer to a film thickness of 25 nm to 50 nm, The second epitaxial film formation step comprises a step of forming a film of Pt as the second layer at a temperature of 500°C or higher. It is possible.

[0017] In the above configuration, by applying the above conditions in the first and second epitaxial film deposition steps, it becomes possible to form a single-oriented Pt layer on the (100) plane across the entire film deposition surface. By forming a PZT layer on top of this Pt layer, it becomes possible to manufacture an epitaxial PZT film with a tetragonal composition and orientation in a predetermined direction, thereby improving the film properties of the PZT film, reducing the number of steps, and improving manufacturing efficiency.

[0018] (4) The method for manufacturing the multilayer structure of the present invention is as described in (1) above, In the third epitaxial deposition step, the third layer (buffer layer) is SrRuO3 or LaNiO3. It is possible.

[0019] In the above configuration, by forming a third layer (buffer layer) on (100)-oriented Pt, all layers can be deposited by consistent in-situ sputtering, and a tetragonal composition c-axis oriented epitaxial PZT film can be stacked and grown. Moreover, the piezoelectric constant e in the PZT layer 31,f [Cm 2 The ratio can be 10.0 to 11.9, the dielectric loss can be 1.0% to 1.8%, and the relative permittivity can be 200 to 375 [dimensionless]. Here, the SrRuO3 film thickness is preferably 15 nm to 25 nm.

[0020] (5) The method for manufacturing the multilayer structure of the present invention is as described in (1) above, The process includes a fourth epitaxial deposition step, in which, after the third epitaxial deposition step, a PZT layer oriented in the (100) plane is formed on the third layer by sputtering. It is possible.

[0021] In the above configuration, by making the process continuous in-situ up to the fourth epitaxial deposition step, the PZT layer oriented on the (100) plane has a piezoelectric constant e 31,f [Cm 2 The film can be deposited with a dielectric constant of 200-375 [dimensionless], where the dielectric loss is 1.0%-1.8% and the relative permittivity is 10.0-11.9. In this step, it is preferable that the PZT layer is formed at 575°C to 650°C during the fourth epitaxial deposition step.

[0022] (6) The method for manufacturing the multilayer structure of the present invention is as described in (5) above, In the fourth epitaxial film deposition step, the PZT layer is doped with La and Ni. It is possible.

[0023] In the above configuration, it is possible to significantly reduce tensile internal stress. This suppresses the occurrence of cracks in the PZT layer, making it possible to provide a PZT film that is suitable for practical use. Here, it is preferable that the PZT layer is doped with lanthanum (La) and nickel (Ni) as impurities in a range of 0.1 [at%] to 5 [at%] each.

[0024] (7) A multilayer structure according to another aspect of the present invention is manufactured by the method for manufacturing a multilayer structure described in (5) or (6) above. The first layer (with or without a seed layer) containing Zr oriented on the (100) plane is formed on the (100) plane of the silicon substrate. A second layer of Pt oriented in the (100) plane is formed on the first layer. A third layer (buffer layer) oriented in the (100) plane is formed on the second layer. The PZT layer oriented in the (100) plane is formed on the third layer. It is possible.

[0025] In the above configuration, a practical figure of performance (e) is achieved by reducing manufacturing costs. 31,f ) 2 A c-axis oriented PZT film with a tetragonal composition of approximately 33.9 / ε[GPa] can be obtained.

[0026] (8) The method for manufacturing the multilayer structure of the present invention is as described in (7) above, The PZT layer has a piezoelectric constant e 31,f [Cm 2 The ratio is 10.0-11.9, the dielectric loss is 1.0%-1.8%, and the relative permittivity ε is 200-375 [dimensionless]. It is possible.

[0027] In the above configuration, the dielectric loss is 0.01 to 0.018, and the practical figure of merit (e 31,f ) 2 A c-axis oriented PZT film with a tetragonal composition of approximately 33.9 / ε[GPa] can be obtained. [Effects of the Invention]

[0028] According to the present invention, it is possible to provide a method for manufacturing a multilayer structure that reduces the number of steps, improves manufacturing efficiency, enables all film deposition by sputtering, and allows for the production of a PZT film that can be deposited consistently in situ, thereby improving the film properties of the multilayer structure. [Brief explanation of the drawing]

[0029] [Figure 1] This is a schematic cross-sectional view showing a first embodiment of a multilayer structure according to the present invention. [Figure 2] This flowchart shows a first embodiment of the method for manufacturing a multilayer structure according to the present invention. [Figure 3] This is a schematic plan view showing a manufacturing apparatus used in the first embodiment of the method for manufacturing a multilayer structure according to the present invention. [Figure 4] This figure shows the shape of the X-ray diffraction peaks of each layer in the first embodiment of the multilayer structure according to the present invention. [Figure 5] This figure shows the shape of the X-ray diffraction peaks of each layer in the first embodiment of the multilayer structure according to the present invention. [Figure 6] This figure shows the thickness of the YSZ layer and the presence or absence of a (111) side peak in X-ray diffraction in the first embodiment of the multilayer structure according to the present invention. [Figure 7] This figure shows the thickness of the YSZ layer and the presence or absence of a (111) side peak in X-ray diffraction in the first embodiment of the multilayer structure according to the present invention. [Figure 8] This figure shows the film thickness of the YSZ layer, the deposition temperature of the Pt layer, and the orientation direction of Pt in X-ray diffraction in the first embodiment of the multilayer structure according to the present invention. [Figure 9] This figure shows the X-ray diffraction peaks of the YSZ layer. [Figure 10] This figure shows the X-ray diffraction peaks of the YSZ layer in the first embodiment of the multilayer structure according to the present invention. [Figure 11] Figure 10 shows the X-ray diffraction peaks of the YSZ layer. [Figure 12]This figure shows the X-ray diffraction peaks of a silicon substrate with a YSZ layer deposited on it, as shown in Figure 10. [Figure 13] This figure shows the X-ray diffraction peaks of the PZT layer in the first embodiment of the multilayer structure according to the present invention. [Figure 14] This figure shows the X-ray diffraction peaks of the PZT layer in the first embodiment of the multilayer structure according to the present invention. [Figure 15] This figure shows the X-ray diffraction peaks of the PZT layer in Figure 14. [Figure 16] This figure shows the internal stress distribution of the PZT layer in the first embodiment of the multilayer structure according to the present invention. [Figure 17] This figure shows the surface observation results of the PZT layer in Figure 16. [Figure 18] This figure shows the internal stress distribution of the PZT layer. [Figure 19] Figure 18 shows the surface observation results of the PZT layer. [Figure 20] This figure shows the relative permittivity of the PZT layer in the first embodiment of the multilayer structure according to the present invention. [Figure 21] This figure shows the dielectric loss of the PZT layer in the first embodiment of the multilayer structure according to the present invention. [Figure 22] This figure shows the piezoelectric constants e31 and f of the PZT layer in the first embodiment of the multilayer structure according to the present invention. [Figure 23] This figure shows the performance index of the PZT layer in the first embodiment of the multilayer structure according to the present invention. [Figure 24] This figure shows the X-ray diffraction peaks of the PZT layer in a second embodiment of the multilayer structure according to the present invention. [Figure 25] This figure shows the X-ray diffraction peaks of the PZT layer in a second embodiment of the multilayer structure according to the present invention. [Figure 26] This figure shows the X-ray diffraction peaks of the PZT layer in Figure 25. [Figure 27] This figure shows the results of an X-ray diffraction analysis of the changes in the PZT layer in the multilayer structure according to this embodiment due to changes in the film deposition temperature. [Modes for carrying out the invention]

[0030] Hereinafter, a method for manufacturing a multilayer structure according to the present invention and a first embodiment of the multilayer structure will be described with reference to the drawings. Figure 1 is a schematic cross-sectional view showing a multilayer structure in this embodiment. In the figure, reference numeral 100 denotes the multilayer structure.

[0031] As shown in Figure 1, the multilayer structure 100 according to this embodiment has a first layer 11, a second layer 12, a third layer 13, and a fourth layer 14 stacked on a silicon substrate 10.

[0032] The silicon substrate 10 is a silicon single crystal substrate. The (100) plane of the silicon substrate 10 is the stacking plane. The lattice constant of silicon is 5.431 angstroms.

[0033] The first layer 11 is deposited on the silicon substrate 10. The first layer 11 contains zirconium. The first layer 11 is yttria-stabilized zirconia (YSZ; Y2O3- doped ZrO2; Y-ZrO2). The (100) plane of the first layer 11 is oriented as a (100) plane relative to the Si(100) plane. The arrangement of the (100) planes of the first layer 11 is the same as that of the silicon substrate 10. The lattice constant of YSZ is 5.139 angstroms.

[0034] The second layer 12 is deposited on the first layer 11. The second layer 12 is a platinum (Pt) layer. The second layer 12 is oriented with respect to the (100) plane of the first layer 11. The (100) plane of the second layer 12 is oriented with respect to the YSZ(100) plane. The arrangement of the (100) plane of the second layer 12 is the same as that of the silicon substrate 10 and the first layer 11. The lattice constant of Pt is 3.920 angstroms.

[0035] The third layer 13 is deposited on the second layer 12. The third layer 13 is a buffer layer. The third layer 13 is a strontium ruthenate (SRO; SrRuO3) film. The third layer 13 is oriented with respect to the (100) plane of the second layer 12. The (100) plane of the third layer 13 is oriented with respect to the Pt(100) plane. The arrangement of the (100) plane of the third layer 13 is the same as that of the silicon substrate 10, the first layer 11, and the second layer 12. The lattice constant of SrRuO3 is 3.930 angstroms.

[0036] The fourth layer 14 is deposited on the third layer 13. The fourth layer 14 is a PZT layer. The fourth layer 14 is a tetragonal c-axis oriented lead zirconate titanate (Pb(Zr,Ti)O3:PZT) film. The fourth layer 14 is a PZT film doped with lanthanum (La) and / or nickel (Ni) as impurities in a range of 0.1 [at%] to 5 [at%], each. The fourth layer 14 is oriented in the (100) plane relative to the (100) plane of the third layer 13. The arrangement of the (100) planes of the fourth layer 14 is the same as that of the silicon substrate 10, the first layer 11, the second layer 12, and the third layer 13. The lattice constant of PZT is approximately 3.9 angstroms, which is the same as that of a typical simple perovskite oxide.

[0037] In this embodiment, the multilayer structure 100 has a first layer 11, a second layer 12, and a third layer 13 stacked on a silicon substrate 10, and a fourth layer 14 is stacked on the third layer 13, thereby reducing the piezoelectric constant e 31,f [Cm 2 ], a PZT layer can be obtained in which the dielectric constant ε [F / m] is within a predetermined range.

[0038] Figure 2 is a flowchart showing the manufacturing method of the multilayer structure in this embodiment. Figure 3 is a schematic plan view showing the manufacturing apparatus used in the manufacturing method of the multilayer structure in this embodiment. As shown in Figure 2, the manufacturing method of the multilayer structure according to this embodiment includes a substrate preparation step S00, a first epitaxial deposition step S01 for forming a first layer 11, a second epitaxial deposition step S02 for forming a second layer 12, a third epitaxial deposition step S03 for forming a third layer 13, and a fourth epitaxial deposition step S04 for forming a fourth layer 14.

[0039] The substrate preparation step S00 involves preparing a single-crystal silicon substrate 10. Here, the (100) plane of the silicon substrate 10 is designated as the lamination plane. As described later, different surface treatments are performed on the silicon substrate 10 depending on the conditions in the first epitaxial deposition step S01. Specifically, as a surface treatment of the silicon substrate 10, an etching process can be performed to remove the native oxide film. Alternatively, the state in which the native oxide film is not removed can be maintained. Regardless of whether or not the native oxide film is removed, a surface cleaning process can be performed. In this case, etching or other methods can be selected as the cleaning process.

[0040] The first epitaxial deposition process S01 involves epitaxially depositing a first layer 11 onto the laminated surface of the silicon substrate 10. The first epitaxial deposition process S01 is carried out using the manufacturing apparatus 1 shown in Figure 3. As shown in Figure 3, the manufacturing apparatus (sputtering apparatus) 1 comprises a load / unload chamber 2, a plurality of deposition chambers 4, and a transport chamber 3 located between the deposition chambers 4 and the load / unload chambers 2.

[0041] The sputtering apparatus 1 is a vacuum processing apparatus. The manufacturing apparatus 1 can perform sputtering film deposition on a silicon substrate 10 in each deposition chamber 4. The sputtering apparatus 1 is arranged so that multiple chambers 2, 4 surround the transport chamber 3. Partition valves are formed between each chamber 2, 4 and the transport chamber 3. The sputtering apparatus 1 can move the silicon substrate 10 between the load / unload chamber 2, the multiple deposition chambers 4 (chambers), and the transport chamber 3 while maintaining a vacuum-reduced, sealed state.

[0042] The load / unload chamber 2 is a load chamber for loading silicon substrates 10 from the outside into the sputtering apparatus 1. The load / unload chamber 2 is an unload chamber for unloading silicon substrates 10 from the inside into the sputtering apparatus 1 to the outside. The load / unload chamber 2 is configured to be usable for both loading and unloading operations. The sputtering apparatus 1 may also be configured with multiple load / unload chambers 2, each performing loading and unloading operations separately.

[0043] The load / unload chamber 2 may be equipped with a positioning member capable of setting and aligning the placement position of the silicon substrate 10 brought in from outside the sputtering apparatus 1. The load / unload chamber 2 is equipped with a rough vacuum exhaust device (rough vacuum exhaust means, low vacuum exhaust device) such as a rotary pump to roughly evacuate the inside. The transport chamber 3 is equipped with a rough vacuum exhaust device (rough vacuum exhaust means, low vacuum exhaust device) such as a rotary pump for roughly evacuating the inside. A transport device (transport robot) 3a is located inside the transport chamber 3.

[0044] The conveying device 3a includes a rotating shaft, a robot arm attached to the rotating shaft, a robot hand formed at one end of the robot arm, and a vertical movement device for moving the robot hand up and down. The robot arm consists of first and second active arms that can bend relative to each other, and first and second driven arms. The conveying device 3a can move the silicon substrate 10, which is the object to be conveyed, between each of the chambers 2 and 4 and the conveying chamber 3.

[0045] Each of the multiple deposition chambers 4 is configured to perform sputtering deposition. The multiple deposition chambers 4 may all have the same configuration. However, each of the multiple deposition chambers 4 is configured to process different deposition steps separately. Hereinafter, the deposition chambers 4 of the manufacturing apparatus 1 will be described assuming that each corresponds to the first epitaxial deposition step S01 to the fourth epitaxial deposition step S04, but the invention is not limited to this configuration.

[0046] Furthermore, the multiple deposition chambers 4 may be configured to perform different deposition processes, or they may be configured to process different deposition processes within the same chamber by means of changing targets, as will be described later. Furthermore, one of the film deposition chambers 4 can be configured to allow processes other than sputtering, such as etching, heat treatment, or substrate processing using a predetermined gas atmosphere.

[0047] Each deposition chamber 4 includes a substrate holding mechanism 41, a deposition mechanism 42, and a gas atmosphere adjustment mechanism 43. In Figure 3, the substrate holding mechanism 41, the deposition mechanism 42, etc., are shown schematically and are not limited to those shown in the figure. The substrate holding mechanism 41 receives the silicon substrate 10 that has been transported by the transport device 3a. The substrate holding mechanism 41 holds the silicon substrate 10 inside the deposition chamber 4. The substrate holding mechanism 41 can transport the silicon substrate 10 inside the deposition chamber 4. The substrate holding mechanism 41 hands over the silicon substrate 10 to the transport device 3a.

[0048] The substrate holding mechanism 41 holds the silicon substrate 10 so as to face the target 42a of the film deposition mechanism 42 during film deposition. The substrate holding mechanism 41 can set the distance between the silicon substrate 10 and the film deposition mechanism 42 during film deposition. The substrate holding mechanism 41 can apply bias power to the silicon substrate 10 during film deposition. The substrate holding mechanism 41 has a temperature control unit that can set the temperature of the silicon substrate 10 during film deposition. The temperature control unit includes a built-in heat-generating element and a heating power supply. For example, SiC is used as the heat-generating element. The heat-generating element may be located at the bottom of the silicon substrate 10. The temperature control unit may also have a cooling unit. For example, it can be configured to circulate a temperature-controlled cooling medium inside the cooling unit.

[0049] The film deposition mechanism 42 is located inside the film deposition chamber 4. The film deposition mechanism 42 performs epitaxial film deposition. The film deposition mechanism 42 supplies the film deposition material for the epitaxial film deposition process. The film deposition mechanism 42 includes a target 42a, a cathode electrode (backing plate) 42b, and a power supply 42c.

[0050] Target 42a supplies the film deposition material corresponding to the film deposition process. Target 42a is manufactured in a predetermined shape according to the composition of the film to be deposited on the surface of the silicon substrate 10. Target 42a is positioned inside the film deposition chamber 4, facing the silicon substrate 10. Target 42a is attached to the cathode electrode 42b. The cathode electrode 42b is positioned above the deposition chamber 4 via an insulating member. The cathode electrode 42b is electrically insulated from the wall of the deposition chamber 4. The wall of the deposition chamber 4 is at ground potential. One side of the cathode electrode 42b is locally exposed inside the deposition chamber 4. The target 42a is fixed in close contact with the center of the exposed area on one side of the cathode electrode 42b. The target 42a and the cathode electrode 42b are electrically connected.

[0051] The power supply (sputtering power supply) 42c applies a negative potential sputtering voltage to the backing plate 42b. The sputtering power supply 42c is located outside the deposition chamber 4. The sputtering power supply 42c is electrically connected to the cathode electrode 42b, and the sputtering power supply 42c is capable of applying an AC voltage to the target 42a via the cathode electrode 42b.

[0052] The gas atmosphere adjustment mechanism 43 includes a gas introduction mechanism and a high vacuum evacuation mechanism. The gas introduction mechanism introduces the sputtering gas and deposition gas corresponding to the film deposition process into the film deposition chamber 4. The high vacuum evacuation mechanism evacuates the inside of the film deposition chamber 4. The high vacuum evacuation mechanism is, for example, a turbomolecular pump. The gas atmosphere adjustment mechanism 43 can set the pressure inside the film deposition chamber 4 during film deposition. The film deposition mechanism 42 may have a magnetron magnetic circuit. The magnetron magnetic circuit forms a predetermined magnetic field on the target 42a. The magnetron magnetic circuit is positioned on the opposite side of the cathode electrode 42b from the target 42a, i.e., on the other side of the cathode electrode 42b.

[0053] The first epitaxial deposition step S01 is performed, for example, in the deposition chamber 4 in the lower right of Figure 3. In this case, plasma treatment such as etching is possible in the deposition chamber 4 in the lower right. Also, in the deposition chamber 4 in the lower right, the target 42a has a composition that enables epitaxial deposition of the first layer 11. The target 42a can be a single target made of yttria-stabilized zirconia. Alternatively, the target 42a may be a plurality of targets having a target containing zirconium oxide or zirconia and a target containing yttrium, etc.

[0054] In this case, in the lower right deposition chamber 4, the gas atmosphere adjustment mechanism 43 sets the required deposition conditions, namely the gas atmosphere and pressure range. Simultaneously, the deposition mechanism 42 sets the required deposition power. The substrate holding mechanism 41 also sets the required deposition temperature and vial power. In the first epitaxial deposition process S01, the inside of the deposition chamber 4 in the lower right is depressurized by the gas atmosphere adjustment mechanism 43, and thereafter, vacuum evacuation is continued to maintain the vacuum atmosphere inside the deposition chamber 4 in the lower right.

[0055] Then, Ar gas is introduced as a sputtering gas into the deposition chamber 4 in the lower right from the gas atmosphere adjustment mechanism 43. Simultaneously, high frequency (negative high frequency power) is applied to the cathode electrode 42b from the sputtering power supply 42c to cause a discharge at the cathode electrode 42b. This turns the Ar gas introduced into the deposition chamber 4 into plasma, generating positive ions such as Ar ions and forming a plasma space. The positive ions in the formed plasma space sputter the target 42a held by the cathode electrode 42b. The constituent elements of the sputtered target 42a are emitted from the target 42a and, in a neutral or ionized state, are sputtered onto the (100) surface of the silicon substrate 10 held by the substrate holding mechanism 41.

[0056] Specifically, the first epitaxial film deposition process may include a step of etching the surface of the silicon substrate 10, and a step of epitaxially depositing YSZ (Y2O3- doped ZrO2; Y-ZrO2) as the first layer 11 to a thickness of 200 nm to 500 nm at 700°C or higher. In this case, the etching process removes the native oxide film 10a by dry etching, for example, using plasma. Alternatively, the native oxide film 10a can be removed by wet etching, and then dry etching can be performed using plasma. In this case, the YSZ film deposition conditions involve using 100% Ar gas as the supply gas and applying a plasma generation power of 1500W.

[0057] Alternatively, the first epitaxial deposition step may include a step of epitaxially depositing YSZ as the first layer 11 to a thickness of 200 nm to 500 nm at 650°C or higher, without removing the silicon oxide (native oxide film) 10a on the surface of the silicon substrate 10. In this case, the YSZ film is deposited while the native oxide film 10a remains. The YSZ deposition conditions in this case are to use 100% Ar gas as the supply gas and apply a plasma generation power of 1500W. In this case, after forming the YSZ film, RTA treatment can be performed in a vacuum at a processing temperature of 650°C. After the RTA treatment, the native oxide film 10a becomes integrated with the YSZ and the first layer 11. Alternatively, it is possible to perform a pre-treatment to form silicon oxide on the surface of the silicon substrate 10.

[0058] Alternatively, the first epitaxial film deposition step may include a step of depositing a Zr seed layer 11a to a thickness of 1.5 nm to 3.5 nm at 400°C or higher without removing the silicon oxide 10a on the surface of the silicon substrate 10, and a step of epitaxially depositing YSZ as the first layer 11 on the seed layer 11a to a thickness of 200 nm to 500 nm at 650°C or higher. In this case, the seed layer 11a and YSZ are deposited while the native oxide film 10a remains. The conditions for depositing the seed layer 11a in this case can be as follows: zirconium metal is used as the target, 100% Ar gas is used as the supply gas, and the plasma generation power is set to a plasma generation condition of 0.3 kW. In this case, the YSZ film deposition conditions involve using YSZ ceramics as the target, 100% Ar gas as the supply gas, and applying a plasma generation power of 1500W. In this case, after forming the YSZ film, RTA treatment can be performed in a vacuum at a processing temperature of 650°C. After the RTA treatment, the native oxide film 10a and the seed layer 11a become integrated with the YSZ and the first layer 11.

[0059] Alternatively, the first epitaxial film deposition process may include a step of depositing a Zr seed layer 11a to a thickness of 1.5 nm to 3.5 nm at 400°C or higher without removing the silicon oxide 10a on the surface of the silicon substrate 10, and a step of depositing YSZ as the first layer on the seed layer 11a to a thickness of 18 nm to 67 nm at 650°C or higher. In this case, the seed layer 11a and YSZ are deposited while the native oxide film 10a remains. The conditions for depositing the seed layer 11a in this case can be set to a plasma generation power of 0.3 kW, using zirconium metal as the target, 100% Ar gas as the supply gas, and zirconium metal as the target.

[0060] In this case, the YSZ film deposition conditions involve using YSZ ceramics as the target, 100% Ar gas as the supply gas, and applying a plasma generation power of 1500W. In this case, RTA treatment can be performed after the YSZ film is deposited. After RTA treatment, the native oxide film 10a and the seed layer 11a become integrated with the YSZ and the first layer 11.

[0061] Once the film deposition in the first epitaxial deposition process S01 is complete, the voltage application from the sputtering power supply 42c to the cathode electrode 42b is stopped, and the introduction of sputtering gas into the deposition chamber 4 from the gas atmosphere adjustment mechanism 43 is stopped. In the first epitaxial deposition process S01, the (100) plane of the first layer 11, which is a cubic YSZ structure, is deposited with respect to the (110) plane of the silicon substrate 10. <100> The film can be formed so that it is oriented in a specific direction. After the deposition of the first layer 11 by the first epitaxial deposition process S01 is completed, the silicon substrate 10 is moved through the transport chamber 3 to the deposition chamber 4 in the upper right.

[0062] The second epitaxial deposition step S02 involves epitaxially depositing a second layer 12 on top of the first layer 11. The second epitaxial deposition process S02 is carried out similarly, for example, in the deposition chamber 4 in the upper right of Figure 3. In this case, in the deposition chamber 4 in the upper right, the target 42a has a composition that allows for epitaxial deposition of the second layer 12. In this case, the target 42a can be a single target made of platinum. Also in this case, in the deposition chamber 4 in the upper right, the gas atmosphere adjustment mechanism 43 sets the gas atmosphere and pressure range, which are the necessary deposition conditions. At the same time, the deposition mechanism 42 sets the necessary deposition power. The substrate holding mechanism 41 also sets the necessary deposition temperature and vial power. In this case, the Pt deposition conditions can be set with Pt as the target, 100% Ar gas as the supply gas, and 0.5 kW applied as the plasma generation power.

[0063] The second epitaxial deposition step S02 includes a step of depositing Pt as the second layer at a temperature of 500°C or higher. At this time, in the first epitaxial deposition step S01, the first layer 11 can be deposited to a thickness of 25 nm to 50 nm.

[0064] In the above configuration, by applying the above conditions in the first and second epitaxial film deposition steps, it becomes possible to form a single-oriented Pt layer on the (100) plane across the entire film deposition surface. By forming a PZT layer on top of this Pt layer, it becomes possible to manufacture an epitaxial PZT film with a tetragonal composition and orientation in a predetermined direction, thereby improving the film properties of the PZT film, reducing the number of steps, and improving manufacturing efficiency.

[0065] In the second epitaxial deposition process S02, the (100) plane of the second layer 12, which is Pt with a cubic crystal structure, is deposited on the (110) plane of the silicon substrate 10 and the (100) plane of the first layer 11, which is YSZ. <100> The film can be formed so as to be oriented in a specific direction. The Pt(100) plane of the second layer 12 is not rotated in-plane with respect to the (100) plane of the first layer 11, which is YSZ, and the (110) plane of the silicon substrate 10. After the deposition of the second layer 12 in the second epitaxial deposition process S02 is completed, the silicon substrate 10 is moved to the upper deposition chamber 4 via the transport chamber 3.

[0066] The third epitaxial deposition step S03 involves epitaxially depositing a third layer 13 on top of the second layer 12. The third epitaxial deposition step S03 is performed, for example, in the upper deposition chamber 4 in Figure 3. In this case, the target 42a in the upper deposition chamber 4 has a composition that allows for epitaxial deposition of the third layer 13. In this case, the target 42a can be a single target made of strontium ruthenate (SRO; SrRuO3). Alternatively, multiple targets may be used to allow for the deposition of strontium ruthenate.

[0067] In this case, in the deposition chamber 4 above, the gas atmosphere adjustment mechanism 43 sets the required deposition conditions, namely the gas atmosphere and pressure range. Simultaneously, the deposition mechanism 42 sets the required deposition power. The substrate holding mechanism 41 also sets the required deposition temperature and vial power. In this case, the deposition conditions can be set with SrRuO3 as the target, using Ar gas and O2 gas as the supply gas, and applying a plasma generation power of 1500W. Furthermore, the film thickness of the third layer 13 is preferably about 20 nm, or 15 nm to 25 nm.

[0068] In the third epitaxial deposition process S03, the (100) plane of the third layer 13, which is SrRuO3 with a cubic crystal structure, is deposited on the (110) plane of the silicon substrate 10, the YSZ(100) plane of the first layer 11, and the Pt(100) plane of the second layer 12. <100> The film can be formed so as to be oriented in a particular direction. The SrRuO3(100) plane of the third layer 13 is not rotated in-plane with respect to the SrRuO3(100) plane of the second layer 12, the YSZ(100) plane of the first layer 11, and the (110) plane of the silicon substrate 10. After the deposition of the third layer 13 in the third epitaxial deposition process S03 is completed, the silicon substrate 10 is moved to the deposition chamber 4 in the upper left via the transport chamber 3.

[0069] In the fourth epitaxial deposition step S04, a fourth layer 14, which is PZT, is epitaxially deposited on the third layer 13, which is a buffer layer. The fourth epitaxial deposition step S04 is performed, for example, in the deposition chamber 4 in the upper left of Figure 3. In this case, in the deposition chamber 4 in the upper left, the target 42a has a composition that allows for epitaxial deposition of the fourth layer 14. In this case, the target 42a is lead zirconate [Pb(Zr]] doped with lanthanum (La) and / or nickel (Ni) as impurities. x Ti 1-x A single target consisting of [O3:PZT] may be used. Alternatively, multiple targets may be used to deposit lead zirconate titanate doped with lanthanum (La) and / or nickel (Ni) as impurities.

[0070] In this case, in the deposition chamber 4 in the upper left, the gas atmosphere adjustment mechanism 43 sets the required deposition conditions, namely the gas atmosphere and pressure range. Simultaneously, the deposition mechanism 42 sets the required deposition power. The substrate holding mechanism 41 also sets the required deposition temperature and vial power. In this case, the PZT deposition conditions can be set to 575°C or higher and a plasma generation power of 2.75kW, using La / Ni-containing PZT as the target and Ar / O2 gas as the supply gas.

[0071] In the fourth epitaxial deposition process S04, the (100) plane of the fourth layer 14, which is PZT with a cubic crystal structure, is deposited on the (110) plane of the silicon substrate 10, the YSZ(100) plane of the first layer 11, the Pt(100) plane of the second layer 12, and the SrRuO3(100) plane of the third layer 13. <100> The film can be formed so as to be oriented in a specific direction. The PZT(100) plane of the fourth layer 14 is not rotated in-plane with respect to the SrRuO3(100) plane of the third layer 13, the SrRuO3(100) plane of the second layer 12, the YSZ(100) plane of the first layer 11, and the (110) plane of the silicon substrate 10.

[0072] In this embodiment, the first epitaxial deposition process S01 to the fourth epitaxial deposition process S04 are carried out in situ within the manufacturing apparatus 1. This allows for the production of a c-axis oriented PZT film with a tetragonal composition as the fourth layer 14. This PZT film of the fourth layer 14 has a piezoelectric constant e 31,f [Cm 2 The ratio is 10.0-11.9, the dielectric loss is 1%-1.8%, the relative permittivity ε is 200-375 [dimensionless], and the practical figure of merit (e 31,f ) 2 The / ε[GPa] is approximately 33.9. Furthermore, since the fourth layer 14 is formed by sputtering to dope with lanthanum (La) and / or nickel (Ni) when depositing the crystallized PZT film, it is possible to suppress crack formation by making the total internal force in the PZT film on the compression side rather than the tensile side.

[0073] In this embodiment, a tetragonal c-axis oriented PZT film can be obtained using a single manufacturing apparatus 1, without mixing different film deposition methods such as sputtering and vapor deposition, thereby reducing manufacturing costs. This multilayer structure 100 is suitably used in piezoelectric elements, gyro sensors, PMUTs, and the like, for example, in which a PZT film with high piezoelectricity and voltage resistance is formed on a CMOS substrate having aluminum wiring.

[0074] The following describes the examination of each layer of the multilayer structure in this embodiment.

[0075] Figure 4 shows the X-ray diffraction peaks of each layer in the multilayer structure according to this embodiment. Figure 5 shows the X-ray diffraction peaks of each layer in the multilayer structure according to this embodiment. The conditions for depositing a YSZ layer on a silicon substrate, a Pt layer on the YSZ layer, a SrRuO3 layer on the Pt layer, and a PZT layer on the SrRuO3 layer are as follows: • Target YSZ composition: 12%Y2O3-88%ZrO2, deposition temperature: 700℃, supply gas: Ar100%, film thickness: 30nm • Target: Pt, deposition temperature: 600°C, supply gas: 100% Ar gas, film thickness: 100 nm • Target SrRuO3 composition: SrRuO3, deposition temperature: 600°C, supply gas: O2 / (Ar+O2)=20%, film thickness: 20nm Target PZT composition: La,Ni doped PZT; deposition temperature: 625°C; supply gas: O2(Ar+O2)=2.5%; film thickness: 2μm This multilayer structure was analyzed by X-ray diffraction.

[0076] In this embodiment, the four peaks in Si(110) in the φ scan of the silicon substrate 10 shown in Figure 4(a) coincide with the four peaks in YSZ(110) in the φ scan of the first layer 11 shown in Figure 4(b), the four peaks in Pt(110) in the φ scan of the second layer 12 shown in Figure 4(c), the four peaks in SrRuO3(110) in the φ scan of the third layer 13 shown in Figure 5(d), and the four peaks in PZT(110) in the φ scan of the fourth layer 14 shown in Figure 5(e).

[0077] Furthermore, the PZT in the 2θ-ω scan of the fourth layer 14 can be seen to be a cubic crystal oriented along the c axis, as shown in Figure 5(f). Therefore, it can be seen that in the multilayer structure 100 according to this embodiment, the first layer 11 to the fourth layer 14 are all cubic and oriented in the same plane orientation.

[0078] Figure 6 shows the film thickness of the YSZ layer in the multilayer structure according to this embodiment, and the presence or absence of a (111) side peak in X-ray diffraction. Figure 6 shows the case where the YSZ layer thickness is 200 nm to 500 nm. The conditions for depositing a YSZ layer on a silicon substrate are: target YSZ composition; 12%Y2O3-88%ZrO2; deposition temperature; 700°C; supply gas; Ar100%; and film thickness of 20 nm. In this case, it can be seen that when etching, i.e., removing the native oxide film 10a on the surface of the silicon substrate 10, is performed and the deposition temperature is 600°C, a large side peak other than (100) appears. Furthermore, it can be seen that when the native oxide film 10a is removed and the deposition temperature is 650°C, a small amount of side peaks other than (100) appear. Moreover, even when the native oxide film 10a is removed, no side peaks other than (100) appear when the deposition temperature is 700°C.

[0079] When the YSZ layer thickness is 200nm to 500nm, if the YSZ layer is deposited without etching, leaving the native oxide film 10a on the surface of the silicon substrate 10, it can be seen that a large side peak other than (100) appears when the deposition temperature is 600°C. Similarly, it can be seen that no side peaks other than (100) appear when the deposition temperature is 650°C or 700°C. When the YSZ layer thickness is 200nm to 500nm, if etching is not performed and the native oxide film 10a on the surface of the silicon substrate 10 is left intact, and a zirconium metal film is deposited as a seed layer 11a before the YSZ layer is deposited, it can be seen that no side peaks other than (100) appear at a deposition temperature of 650°C.

[0080] Figure 7 shows the film thickness of the YSZ layer in the multilayer structure according to this embodiment, and the presence or absence of the (111) side peak in X-ray diffraction. Figure 7 shows the case where the YSZ layer thickness is 60 nm or less. The deposition conditions for forming a YSZ layer on a silicon substrate are: target YSZ composition; 12%Y2O3-88%ZrO2; deposition temperature; 700°C; and supply gas; 100% Ar. In this case, if the YSZ layer is deposited without etching, leaving the native oxide film 10a on the surface of the silicon substrate 10, it can be seen that a large side peak other than (100) appears when the deposition temperature is 650°C. Similarly, it can be seen that a small amount of side peaks other than (100) appear when the deposition temperature is 700°C. When the thickness of the YSZ layer is 60 nm or less, if a zirconium metal is deposited as a seed layer 11a before the YSZ layer is deposited, it can be seen that no side peaks other than (100) appear at deposition temperatures of 650°C and 700°C.

[0081] Figure 8 shows the film thickness of the YSZ layer, the deposition temperature of the Pt layer, and the orientation direction of Pt in X-ray diffraction in the multilayer structure according to this embodiment. A Pt layer is deposited on top of a YSZ layer. The deposition conditions for the YSZ and Pt layers are as follows: Target YSZ composition: 12%Y2O3-88%ZrO2, deposition temperature: 700°C, supply gas: Ar100%.

[0082] When the Pt layer is deposited at 500°C, a peak indicating (111) orientation occurs when the YSZ layer thickness is 20 nm. When the Pt layer is deposited at 500°C, a peak indicating (200) orientation occurs when the YSZ layer thickness is 30 nm; that is, it is formed in (100) orientation, but at the same time, a peak indicating (111) orientation occurs. When the Pt layer is deposited at 500°C, a peak indicating (111) orientation occurs when the YSZ layer thickness is 60 nm. However, when the Pt layer is deposited at 500°C, and the YSZ layer thickness is 40 nm, only the peak indicating (200) orientation is generated, and the peak indicating (111) orientation is not generated. In other words, the Pt layer is oriented to the (100) plane.

[0083] Similarly, when the Pt layer is deposited at 600°C, a peak indicating (111) orientation occurs when the YSZ layer thickness is 20 nm. When the Pt layer is deposited at 600°C, a peak indicating (200) orientation occurs when the YSZ layer thickness is 30 nm; that is, it is formed in (100) orientation, but at the same time, a peak indicating (111) orientation occurs. When the Pt layer is deposited at 600°C, a peak indicating (111) orientation occurs when the YSZ layer thickness is 60 nm. However, when the deposition temperature of the Pt layer is 600°C, and the thickness of the YSZ layer is 40 nm, only the peak indicating (200) orientation is generated, and the peak indicating (111) orientation is not generated. In other words, it can be seen that the Pt layer is oriented to the (100) plane.

[0084] Figure 9 shows the X-ray diffraction peaks of the YSZ layer. A silicon substrate with an intact native oxide film was epitaxially grown as a seed layer of metal Zr at 400°C on the (100) plane. After being left in air for one week, YSZ was epitaxially deposited to a thickness of 50 nm. Verification was performed by X-ray diffraction (2θ).

[0085] As a result, as shown in Figure 9, it was found that YSZ is oriented not only in (200) but also in (111). This is likely because YSZ is oxidized in air, resulting in the formation of 111 crystals. Therefore, it can be seen that YSZ does not become fully (100) oriented simply by forming a seed layer. In Figure 9, 1-C is the wafer center position of Sample 1, and 1-E is the wafer edge position of Sample 1. 2-C is the wafer center position of Sample 2, and 2-E is the wafer edge position of Sample 2.

[0086] Figure 10 shows the X-ray diffraction peaks of the YSZ layer in the multilayer structure according to this embodiment. Figure 11 shows the X-ray diffraction peaks of the YSZ layer in Figure 10. Figure 12 shows the X-ray diffraction peaks of the silicon substrate on which the YSZ layer in Figure 10 is deposited. Similarly, a Zr metal was epitaxially grown as a seed layer at 400°C on the (100) plane of a silicon substrate that had not had its native oxide film removed. After being left in a vacuum for one week, YSZ was epitaxially deposited to a thickness of 50 nm. Verification was performed by X-ray diffraction (2θ) and X-ray diffraction (φ).

[0087] As a result, as shown in Figure 10, it was found that YSZ has a (200) single orientation. This is likely because the YSZ is not oxidized in air, and therefore no 111 crystals are formed. Consequently, it can be seen that by forming a seed layer and then depositing YSZ in situ, a completely uniform (100) orientation is achieved. In Figure 10, 2+18nm, 2+28nm, 2+48nm, 2+98nm, and 2+198nm represent the seed layer thickness (nm) + YSZ thickness (nm), respectively. Furthermore, as shown in Figures 11 and 12, it can be seen that the YSZ(110) plane shows a peak that coincides with the (110) plane of the silicon substrate.

[0088] Figure 13 shows the X-ray diffraction peaks of the PZT layer in the multilayer structure according to this embodiment. As a multilayer structure, a YSZ layer was deposited on a silicon substrate, a Pt layer was deposited on the YSZ layer, and a SrRuO3 layer was deposited on the Pt layer. The deposition conditions were the same as those in Figures 4 and 5. Furthermore, a PZT layer was deposited on the SrRuO3 layer to form a multilayer structure. During this process, the deposition temperature was varied from 450°C to 625°C, and each PZT layer was analyzed by X-ray diffraction. When the deposition temperature was 575°C, the peak of the SrRuO3 layer was 98.2°. As a result, it was observed that the peak of the PZT layer shifted to a lower angle as the deposition temperature increased, as shown in Figure 13. Furthermore, it was found that the c-axis could be observed in the PZT layer when the deposition temperature rose to 625°C.

[0089] Figure 14 shows the X-ray diffraction peak (2θ-ω) of the PZT layer in the multilayer structure according to this embodiment. Figure 15 shows the X-ray diffraction peak (φ scan) of the PZT layer in Figure 14. Similar to the PZT layer in Figure 13, a PZT layer was formed as a multilayer structure on an 8-inch wafer silicon substrate, and its in-plane distribution was observed. As a result, as shown in Figures 14 and 15, it can be seen that the YSZ layer, Pt layer, SrRuO3 layer, and PZT layer are all formed almost uniformly on the wafer surface, oriented to the (100) plane.

[0090] Figure 18 shows the internal stress distribution of the PZT layer in the multilayer structure according to this embodiment. Similarly, as a multilayer structure, a YSZ layer, a Pt layer, a SrRuO3 layer, and a PZT layer were deposited on a silicon substrate, and the internal stress in the PZT layer was measured. The PZT layer was doped with La and Ni at 3 atm%, respectively. The results are shown in Figure 18. Here, internal stress was measured using the FLX-2320-R thin-film stress measuring device manufactured by Toho Technology Co., Ltd. Furthermore, the surface of this PZT layer was observed using a microscope to check for the presence or absence of cracks. The results are shown in Figure 19.

[0091] As a result, it was found that no cracks occurred in the PZT film, and the average internal stress in the PZT layer was +80 MPa. Here, the positive sign of the internal stress value indicates that the internal stress is applied on the tensile side, i.e., in the tensile direction.

[0092] Figure 16 shows the internal stress distribution of the PZT layer. For comparison, PZT layers without La and Ni doping were fabricated in the same manner, and the internal stress in the PZT layers was measured. The results are shown in Figure 16. Furthermore, the surface of the undoped PZT layer was observed using a microscope to check for the presence or absence of cracks. The results are shown in Figure 17. As a result, it was found that cracks occurred in the undoped PZT layer, and that the stress was relieved by these cracks, resulting in an average internal stress of +32 MPa. Here, the positive sign of the internal stress value indicates that the internal stress is applied on the tensile side, i.e., in the tensile direction. Figure 17 shows an image with cracks and no doping, Figure 19 shows an image without cracks and with doping, Figure 16 shows the stress with cracks and no doping, and Figure 18 shows the stress without cracks and with doping. When cracks occur, the dielectric strength drops significantly, which is undesirable.

[0093] The results shown in Figures 18 and 19 indicate that by applying a predetermined amount of doping, the internal stress of the PZT layer shifts more toward the compressive direction, allowing for relaxation of tensile stress and preventing crack formation.

[0094] Figure 20 shows the relative permittivity of the PZT layer in the multilayer structure according to this embodiment. Similarly, a multilayer structure consisting of a YSZ layer, a Pt layer, a SrRuO3 layer, and a PZT layer was fabricated on a silicon substrate, and the dielectric constant of the PZT layer was measured. The results are shown in Figure 20. Here, the dielectric constant was measured using an Agilent Technologies 4284A LCR analyzer after the MIM structure was formed. In Figure 20, the horizontal axis (position) represents the radial position of the Φ200 mm wafer.

[0095] From the results shown in Figure 20, the relative permittivity ε of the PZT layer in the multilayer structure according to this embodiment is 200 to 375 [ Dimensionless It can be seen that ]. In contrast, it can be seen that the dielectric constant of polycrystalline PZT deposited by sputtering is 1000 to 1200. It can be seen that the dielectric constant can be lowered in the PZT layer of the multilayer structure according to the present invention.

[0096] Figure 21 shows the dielectric loss of the PZT layer in the multilayer structure according to this embodiment. Similarly, a multilayer structure consisting of a YSZ layer, a Pt layer, a SrRuO3 layer, and a PZT layer was fabricated on a silicon substrate, and the dielectric loss in the PZT layer was measured. The results are shown in Figure 21. Here, dielectric loss was measured using an Agilent Technologies 4284A LCR analyzer after the MIM structure was formed. In Figure 21, the horizontal axis (position) represents the radial position of the Φ200mm wafer.

[0097] From the results shown in Figure 21, the dielectric loss of the PZT layer in the multilayer structure according to this embodiment is 1%~1.8% It can be seen that... In contrast, in polycrystalline PZT deposited by vapor deposition, Dielectric loss but 3%~5% It is known that in the PZT layer of the multilayer structure according to this embodiment, Dielectric loss It can be seen that it can be lowered.

[0098] Figure 22 shows the piezoelectric constant e of the PZT layer in the multilayer structure according to this embodiment. 31,f This is a diagram. Similarly, as a multilayer structure, a YSZ layer, a Pt layer, a SrRuO3 layer, and a PZT layer are fabricated on a silicon substrate, and the piezoelectric constant e in this PZT layer is 31,f The following was measured. The results are shown in Figure 22. Here, the piezoelectric constant e 31,f The measurement was performed by inverse piezoelectric measurement using a laser Doppler after the cantilever was fabricated. In Figure 22, the vertical axis represents the displacement of the cantilever, and the horizontal axis represents the applied AC voltage.

[0099] From the results shown in Figure 22, the piezoelectric constant e of the PZT layer in the multilayer structure according to this embodiment 31,f 10.0~11.9 [C / m 2 ], 10.9[C / m 2 It can be seen that it is around this level. The piezoelectric constant becomes smaller, but the relative permittivity also becomes smaller, which improves the figure of merit for sensor applications.

[0100] Figure 23 shows the performance index of the PZT layer in the multilayer structure according to this embodiment. Similarly, as a multilayer structure, a YSZ layer, a Pt layer, a SrRuO3 layer, and a PZT layer are deposited on a silicon substrate, and the figure of merit (e) of this PZT layer is determined. 31,f ) 2 The value of / ε was measured. The results are shown in Figure 23. Here, the performance index (e 31,f ) 2 The measurement of / ε is e 31 The value was calculated from the measurement results of the voltage and the relative permittivity. In Figure 22, the vertical axis represents the displacement of the cantilever, and the horizontal axis represents the applied AC voltage.

[0101] From the results shown in Figure 23, the figure of merit (FOM; Figure of Merit) of the PZT layer in the multilayer structure according to this embodiment is (e 31,f ) 2 It can be seen that / ε is approximately 10.0~11.9 [GPa] and 33.9 [GPa]. In contrast, for polycrystalline PZT deposited by the sputtering method, the figure of merit (e 31,f ) 2 It is known that / ε is approximately 21.3 [GPa]. In the PZT layer of the multilayer structure according to this embodiment, the figure of merit (e 31,f ) 2 It can be seen that / ε can be made larger.

[0102] Furthermore, this embodiment offers the advantage of reducing dielectric loss to 1-1.8%.

[0103] Hereinafter, a method for manufacturing a multilayer structure according to the present invention and a second embodiment of the multilayer structure will be described with reference to the drawings. In this embodiment, the difference from the first embodiment described above is in the respect to the third layer, and other components corresponding to the first embodiment described above are denoted by the same reference numerals and their descriptions are omitted.

[0104] In this embodiment, the third layer 13 is a lanthanum nickel oxide (LaNiO3) film. The third layer 13 is deposited on the second layer 12. The third layer 13 is a buffer layer. The third layer 13 is oriented with respect to the (100) plane of the second layer 12. The (100) plane of the third layer 13 is oriented with respect to the Pt(100) plane. The arrangement of the (100) plane of the third layer 13 is the same as that of the silicon substrate 10, the first layer 11, and the second layer 12. The lattice constant of LaNiO3 is 3.857 angstroms.

[0105] In this embodiment, the third epitaxial deposition step S03 involves epitaxially depositing a third layer 13 on the second layer 12. The third epitaxial deposition process S03 is performed, for example, in the upper deposition chamber 4 in Figure 3. In this case, the target 42a in the upper deposition chamber 4 has a composition that allows for epitaxial deposition of the third layer 13. In this case, the target 42a can be a single target made of lanthanum nickelate (LaNiO3). Alternatively, multiple targets may be used to allow for the deposition of lanthanum nickelate. In this case, the gas atmosphere adjustment mechanism 43 in the upper deposition chamber 4 sets the required deposition conditions, namely the gas atmosphere and pressure range. At the same time, the deposition mechanism 42 sets the required deposition power. The substrate holding mechanism 41 also sets the required deposition temperature and vial power. In this case, the Pt deposition conditions can be set with LaNiO3 as the target, supply gas: O2(Ar+O2)=60%, gas partial pressure: 0.5Pa, and plasma generation power: 0.5kW.

[0106] In this embodiment, the third epitaxial film deposition step S03 involves forming a buffer layer 13 made of LaNiO3 by sputtering. This buffer layer 13 can be formed by the Pulse-DC sputtering method. Here, a LaNiO3 target is used as the sputtering target 42a, and the temperature of the silicon substrate 10 can be set to approximately 550°C or higher during pulse sputtering (frequency 50kHz, off time 5μsec) in a sputtering gas such as argon gas. For example, it can be set to 525°C to 725°C. The thickness of the buffer layer 13, which is made of LaNiO3, can be set to 100 nm or less. If the thickness of the buffer layer 6, which is made of LaNiO3, exceeds 100 nm, it may not be possible to form a perovskite single-phase film. Furthermore, the film thickness of the third layer 13 is preferably about 20 nm, or 15 nm to 25 nm.

[0107] Furthermore, in this embodiment, the PZT layer as the fourth layer 14 can be formed by the RF sputtering method. In the fourth epitaxial growth process S04, a PZT target doped with a nickel (Ni)-containing metal is used as the sputtering target. Examples of nickel (Ni)-containing metals include nickel or lanthanum-nickel alloy (LaNi5). In other words, a nickel-doped PZT target or a lanthanum-nickel alloy-doped PZT target can be used. The doping amount is preferably set to 0.1 atm% to 5 atm% relative to 100 atm% of PZT, more preferably to 0.5 atm% to 5 atm% relative to 100 atm% of PZT, and even more preferably to 1 atm% to 3 atm% relative to 100 atm% of PZT.

[0108] Figure 24 shows the X-ray diffraction peaks of the PZT layer in the multilayer structure according to this embodiment. As a multilayer structure, a YSZ layer was deposited on a silicon substrate, a Pt layer was deposited on the YSZ layer, and a LaNiO3 layer was deposited on the Pt layer. The deposition conditions for all layers except the LaNiO3 layer were the same as those for the first embodiment shown in Figures 4 and 5. Furthermore, a PZT layer was deposited on the LaNiO3 layer to form a multilayer structure. In this case, when the deposition temperature was 625°C, the peak of PZT(004) by X-ray diffraction was 96.800°. As a result, as shown in Figure 24, when a LaNiO3 layer was used as the third layer, it was found that the c-axis of the PZT layer could be observed at a deposition temperature of 625°C, similar to the SrRuO3 layer shown in Figure 13.

[0109] Figure 25 shows the X-ray diffraction peak (2θ-ω) of the PZT layer in the multilayer structure according to this embodiment. Figure 26 shows the X-ray diffraction peak (φ scan) of the PZT layer in Figure 25. Similar to the PZT layer in Figure 24, a PZT layer was formed on a silicon substrate as a multilayer structure, and its in-plane distribution was observed. As a result, as shown in Figures 25 and 26, it can be seen that the YSZ layer, Pt layer, LaNiO3 layer, and PZT layer are all epitaxially grown oriented to the (100) plane.

[0110] Figure 27 shows the results of an X-ray diffraction analysis of the changes in the PZT layer in the multilayer structure according to this embodiment due to changes in the deposition temperature. This figure shows the X-ray diffraction peak (2θ). As a multilayer structure, a YSZ layer was deposited on a silicon substrate, a Pt layer was deposited on the YSZ layer, and a LaNiO3 layer was deposited on the Pt layer. The deposition conditions for all layers except the LaNiO3 layer were the same as those shown in Figure 24. Furthermore, a PZT layer was deposited on the LaNiO3 layer to form a multilayer structure. In this case, the deposition temperature of the LaNiO3 layer was varied from 350°C to 650°C, and the results of X-ray diffraction analysis of each PZT layer are shown in Figure 27. Here, at a deposition temperature of 350°C, a side peak of LaNiO3(110) was observed. X-ray diffraction results show that the LaNiO3 layer exhibits a (100) peak when the substrate temperature is above 550°C.

[0111] In this embodiment, the same effects as those of the above-described embodiment can be achieved. Furthermore, this embodiment offers the advantage of being able to use the same buffer layer for both poly-PZT and epi-PZT.

[0112] In the present invention, the following can be achieved. 1. In the sputtering method, Y-doped ZrO2 (YSZ) is required to form a cubic crystal of ZrO2. 2. It was found that either A or B below is acceptable for promoting YSZ (epitaxial growth). A. Silicon surface etching => YSZ (700℃ or higher) B. With natural oxide film => YSZ (over 650℃) 3. However, in thin films with a YSZ of 60 nm or less, the YSZ(111) side peak is detected using the above methods A / B. 4. To achieve a single YSZ(100) orientation when the YSZ is 60 nm or less, C. It was found that the native oxide film must be a seed layer (Zr) and then a YSZ layer (650°C or higher). 5. The optimal seed layer thickness is 2 nm. (Try 1.5 nm, 2 nm, 3 nm, and 5 nm.) 6. At room temperature, YSZ(111) is detected in the seed layer. At 400°C, BKM is detected. 7. In the seed layer => open to the atmosphere => YSZ film deposition process, YSZ(111) is detected, therefore in-situ processing is essential. 8. Orient Pt into a single Pt(100), and Pt <100> Si <100> For epitaxial growth to occur parallel to the grain, the YSZ needs to be thinner than 60 nm. In other words, the YSZ needs to be deposited using the method described in section 4.C. Furthermore, the YSZ needs to be thicker than 20 nm and thinner than 60 nm. If the YSZ is 20 nm or 60 nm, the Pt will grow on the Pt(111) plane. (TEM data) 9. To epitaxially grow a single layer of Pt(100), the deposition temperature of the Pt layer must be higher than 500°C. 10. There are optimal conditions for buffer layer SRO. Film thickness also has an effect, with 20nm being BKM. 11. When PZT is epitaxially grown under undoped conditions, cracks occur due to large tensile stresses. In contrast, by depositing the film using RF sputtering with La and Ni doping, the film stress in PZT can be reduced, making it possible to deposit a crack-free epitaxial film. To epitaxially grow a PZT film along the c-axis, a deposition temperature higher than 575°C is required. As a result, a fully integrated process using sputtering has become possible.

[0113] Furthermore, in the present invention, it is also possible to individually select and combine each of the configurations in the above-described embodiments. [Industrial applicability]

[0114] Examples of applications of the present invention include devices in MEMS (MicroElectroMechanical Systems) technology such as inkjet heads, micromirrors, gyro sensors, PMUTs (Piezoelectric Micromachined Ultrasonic Transducers), vibration elements, elastic wave elements, and acceleration sensors. [Explanation of symbols]

[0115] 100...Multilayer structure 10…Silicon substrate 10a...Native oxide film 11…Layer 1 (YSZ) 12…Second layer (Pt) 13…Third layer (buffer layer) 14…4th layer (PZT) 11a... Seed layer

Claims

1. A first epitaxial deposition step is performed to form a first layer oriented on the (100) plane of a silicon substrate by sputtering, A second epitaxial deposition step is performed to form a second layer of Pt oriented in the (100) plane on the first layer by sputtering, A third epitaxial deposition step is performed in which a third layer oriented in the (100) plane is formed on the second layer by sputtering, It has, The first epitaxial film deposition step is The process includes the steps of etching the surface of the silicon substrate and forming a film with YSZ as the first layer at a temperature of 700°C or higher to a thickness of 200 nm to 500 nm, The process includes a step of forming a film with YSZ as the first layer at a temperature of 650°C or higher to a thickness of 200 nm to 500 nm without removing the silicon oxide on the surface of the silicon substrate, or The process comprises the steps of: forming a Zr seed layer to a thickness of 1.5 nm to 3.5 nm at 400°C or higher without removing silicon oxide from the surface of the silicon substrate; and forming a YSZ film on the seed layer as the first layer to a thickness of 200 nm to 500 nm at 650°C or higher. The process includes the steps of: forming a Zr seed layer to a thickness of 1.5 nm to 3.5 nm at 400°C or higher without removing silicon oxide from the surface of the silicon substrate; and forming a YSZ film on the seed layer as the first layer to a thickness of 18 nm to 67 nm at 650°C or higher. It is one of the following: A method for manufacturing a multilayer structure characterized by the following:

2. A first epitaxial deposition step is performed to form a first layer oriented on the (100) plane of a silicon substrate by sputtering, A second epitaxial deposition step is performed to form a second layer of Pt oriented in the (100) plane on the first layer by sputtering, A third epitaxial deposition step is performed in which a third layer oriented in the (100) plane is formed on the second layer by sputtering, It has, The first epitaxial film deposition step involves depositing YSZ as the first layer to a film thickness of 25 nm to 50 nm, The second epitaxial film formation step comprises a step of forming a film of Pt as the second layer at a temperature of 500°C or higher. A method for manufacturing a multilayer structure characterized by the following:

3. In the third epitaxial film formation step, the third layer is SrRuO ３ , or LaNiO ３ That is, A method for manufacturing a multilayer structure according to claim 1 or 2.

4. The process includes a fourth epitaxial deposition step, in which, after the third epitaxial deposition step, a PZT layer oriented to the (100) plane is formed on the third layer by sputtering. A method for manufacturing a multilayer structure according to claim 1 or 2.

5. In the fourth epitaxial film deposition step, the PZT layer is doped with La and Ni. A method for manufacturing a multilayer structure according to feature 4.

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