Digital protection control system and digital protection control method

Abstract

To solve the problem in which: in a protection control system in which a MU and an IED are separated from each other, when a sampling period of the MU and the period of processing executed by the IED are different from each other, desired characteristics as the IED may not be obtained.SOLUTION: A digital protection control system has a first digital filter, a second digital filter, and a protection control operation unit. Upon input of first data obtained by sampling a measured value of an electric power system with a first sampling frequency, the first digital filter removes a folding component at the first sampling frequency from the first data and outputs second data obtained by sampling the measured value with a second sampling frequency. Upon input of the second data, the second digital filter removes a low-order harmonic component of the electric power system included in the input second data. The protection control operation unit performs protection control processing on the electric power system on the basis of the second data from which the low-order harmonic component is removed, and outputs a result of the processing.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a digital protection control system, and particularly to a digital protection control system suitable for converting data of analog input quantities sampled at different sampling rates into data of a desired sampling rate and performing protection control calculations.

Background Art

[0002] For removing faults such as short circuits and ground faults occurring in transmission lines, buses, transformers, and generators constituting a power system, protection devices installed for each element operate on faults occurring within their protection ranges, and the section of the power system including the fault point is disconnected by a circuit breaker.

[0003] In a protection device, voltage and current signals indicating the state of the system are captured, converted into digital values, and then a digital operation function is used to discriminate system accidents through software processing.

[0004] In current digital protection control systems, conversion from analog signals to digital data is performed at an electrical angle of 3.75°. After removing low-order harmonic signal components unnecessary for protection control calculations using a digital filter, data for protection control calculations is generated every 30° of electrical angle, and protection and sequence processing are generally executed. Due to these calculations enabling accurate protection control processing, they are applied to many substations and contribute to the stable operation of the power system.

[0005] On the other hand, as a digital protection control system utilizing digital communication technology, it has evolved into a system configuration for a digital substation that is divided into an analog input section called a merging unit (hereinafter referred to as MU) and a protection control calculation section (hereinafter referred to as IED), and connected between them by digital communication called a process bus, and standardization towards wiring reduction and digitization is progressing.

[0006] In this digital substation, as mentioned earlier, the functions are separated into MU and IED, and connections may be made between products from different vendors. Therefore, the interface between these components becomes a crucial aspect when building the system.

[0007] In the communication interface between the MU and IED, particularly in the part where analog sample values ​​(hereinafter referred to as SV) are generated within the MU, the sampling frequency (sampling rate) to be adopted is an important specification among vendors. In Japan, sampling at an electrical angle of 3.75° is common and standardized among vendors, but in MUs manufactured according to international standards such as IEC61850 and IEC61869, an electrical angle of 4.5° is defined as the standard sampling frequency.

[0008] Therefore, simply combining it with a MU that transmits data at a sampling rate different from the domestic specifications results in the problem of not being able to meet the desired characteristics. Furthermore, in order to match the sampling rate to the international standard, it becomes necessary to change the protection control calculation algorithm based on the electrical angle of 30°. Against this backdrop, a configuration has been proposed in which the SV value received in the IED is corrected to the sampling rate required by the existing calculation algorithm before processing.

[0009] International Publication No. 2018 / 042587 (Patent Document 1) proposes a method in which, in an IED, after receiving SV data from MU, an upconversion unit is provided to increase the sampling rate, interpolate (preceding interpolation) the SV data at a high sampling rate, and then periodically extract data points at arbitrary sample times that can be changed from the time series data to generate low-sampling-rate time series data for protective relay calculations.

[0010] In Electrical Collaborative Research, Vol. 71, No. 1 (Non-Patent Literature 1), it is shown that if the algorithm of a protective relay is to be adapted to the 4.5° sampling standard prevalent among overseas manufacturers, a tremendous amount of effort is required to redesign and re-verify the relay algorithm. [Prior art documents] [Patent Documents]

[0011] [Patent Document 1] International Publication No. 2018 / 042587 [Non-patent literature]

[0012] [Non-Patent Document 1] Electrical Cooperative Research, Vol. 71, No. 1, Japan Electrical Cooperative Research Association, 2015. [Overview of the project] [Problems that the invention aims to solve]

[0013] As mentioned above, domestic protection control systems are generally implemented with an electrical angle of 3.75°. However, when combined with MUs that comply with international standards such as IEC61850 and IEC61869, timing coordination is not possible, leading to problems in correctly recognizing SV data and failing to obtain the desired characteristics as an IED.

[0014] While it is possible to address the 4.5° electrical angle by revising the IED's processing, the existing protection control calculation algorithm, which is based on SV data with a 3.75° electrical angle, cannot be directly applied. Therefore, all related protection control calculation algorithms must be revised, which will require a massive amount of work and verification time, resulting in a significant impact.

[0015] As mentioned above, Patent Document 1 discloses a method for converting the sampling rate by providing an upconversion unit, which can be used even if the sampling frequency of the MU is different.

[0016] However, in this Patent Document 1, in order to convert the sampling rate, it is necessary to include an upconversion unit to first increase the sampling rate, which increases the circuit size. Furthermore, because the sampling rate conversion process must be performed at the speed of the upsampling, this process must be completed in a short time, which presents a challenge in that it limits the number of receiving channels of SV data that can be processed.

[0017] Furthermore, Non-Patent Literature 1 indicates that if the protection relay algorithm is to be adapted to the 4.5° sampling standard used by overseas manufacturers, a tremendous amount of effort will be required to redesign and re-verify the relay algorithm. It also states that consideration should be given to easily applying existing software assets during the process, but it does not disclose any information that goes into specific methods. [Means for solving the problem]

[0018] To solve at least one of the above problems, the present invention provides a digital protection control system comprising a first digital filter, a second digital filter, and a protection control calculation unit, wherein the first digital filter, upon input of first data obtained by sampling measured values ​​of a power system at a first sampling frequency, removes aliasing components at the first sampling frequency from the first data and outputs second data sampled at a second sampling frequency; the second digital filter, upon input of the second data, removes low-order harmonic components of the power system contained in the input second data; and the protection control calculation unit performs protection control processing of the power system based on the second data from which the low-order harmonic components have been removed, and outputs the result. [Effects of the Invention]

[0019] According to one aspect of the present invention, it is possible to convert the sampling rate at a 3.75° period without converting the SV data to a high sampling rate associated with resampling within the IED. Therefore, since there is no need to provide high-speed conversion arithmetic means for conversion, miniaturization and low power consumption of the conversion means of the IED can be achieved. As a result, since software assets that perform existing protection control arithmetic based on an electrical angle of 3.75° can be reused, proven protection control arithmetic processing can be applied as it is, and there is an effect that cost reduction can be achieved while maintaining reliability. In addition, since a system configuration combined with MUs having different sampling rates can be constructed, there is an effect that the flexibility of system construction can be improved.

[0020] Problems, configurations, and effects other than those described above will be clarified by the description of the following embodiments.

Brief Description of Drawings

[0021] [Figure 1] The processing block configuration example of the entire system of the protection control function according to Embodiment 1 of the present invention is shown. [Figure 2] The configuration example of the digital filter that removes the folding component of resampling according to Embodiment 1 of the present invention is shown. [Figure 3] The operation timing example of the digital filter that removes the folding component of resampling according to Embodiment 1 of the present invention is shown. [Figure 4] The timing example of time synchronization according to Embodiment 1 of the present invention is shown. [Figure 5] The hardware block configuration example of the IED for realizing the protection control function according to Embodiment 1 of the present invention is shown. [Figure 6] The processing flow example of signal processing according to Embodiment 1 of the present invention is shown. [Figure 7] The characteristic example of the digital filter that removes the folding component according to Embodiment 1 of the present invention is shown. [Figure 8] The characteristic example of the digital filter that removes the low-order harmonic component according to Embodiment 1 of the present invention is shown. [Figure 9]An example of a waveform from the signal processing according to Embodiment 1 of the present invention is shown. [Figure 10] This shows an example of the overall processing block configuration of the protection control function according to Embodiment 2 of the present invention. [Figure 11] An example of a waveform from signal processing according to Embodiment 2 of the present invention is shown. [Figure 12] This shows the relationship between sampling timing, input data, and filter coefficients. [Modes for carrying out the invention]

[0022] First, an overview of the embodiments of the present invention will be described.

[0023] In the first embodiment of the present invention (Example 1), the aforementioned problems are solved. Instead of performing upsampling by taking SV data sampled at an electrical angle of 4.5° from the MU as input and increasing the sampling rate, the equivalent of upsampling is performed by switching the filter coefficients that determine the characteristics of a band-limiting filter, which is provided as a first digital filter to remove aliasing errors (hereinafter referred to as aliasing).

[0024] Even if zero data is interpolated through upsampling, the result of the digital filter calculation will still be zero. Therefore, to avoid performing this calculation, a first digital filter, a band-limiting filter, is configured to operate in a polyphase configuration.

[0025] In this way, the generation of data to be upsampled to a period shorter than 3.75° before the protection control calculation using the 3.75° electrical angle data is eliminated.

[0026] In the system disclosed herein, a grandmaster clock (hereinafter referred to as GMC) is installed on the same domain LAN to synchronize the sampling of the entire system between multiple MUs that transmit SV data with an electrical angle of 4.5° and IEDs that resample this SV data to 3.75° and perform protection control calculations. This allows for stable resampling without unnecessary timing deviations when resampling in the above configuration.

[0027] Furthermore, in the second embodiment of the present invention (Example 2), based on Example 1 described above, the first digital filter for removing aliasing is replaced with a digital filter for removing harmonics executed by the protection control calculation unit. This allows the functions of this digital filter to be combined, enabling aliasing to be removed as well, and eliminating the delay of the aliasing removal digital filter.

[0028] Next, embodiments of the present invention will be described in detail with reference to the drawings as appropriate. [Examples]

[0029] Figure 1 shows an example of the overall processing block configuration of the protection control function according to Embodiment 1 of the present invention. The function of the overall processing will be explained using Figure 1.

[0030] In Figure 1, the substation protection control system S1 consists of multiple merging units (MUs) 101a, 101b, and 101c, and a protection control unit (IED) 100. The merging units (MUs) 101a, 101b, and 101c receive analog voltage and current signals L100a, L100b, and L100c from substation equipment such as circuit breakers, and send A / D-converted analog instantaneous value data (SV data) to the process bus L100. The protection control unit (IED) 100 performs protection control calculations and issues operation command signals to the MUs for operating substation equipment such as circuit breakers.

[0031] In the configuration described above, multiple MU101a units and the IED100 exchange time synchronization packets with the Grand Master Clock (GMC) 102, which synchronizes the time of the entire substation, and reflect this in the sampling synchronization control to operate in a way that achieves a predetermined synchronization accuracy.

[0032] The GMC102 acts as a synchronization master, exchanging synchronization packets with the slave MU101a, 101b, 101c, and IED100 at a fixed period, for example, every second, in order to synchronize according to standardized procedures such as the international standard IEC61588. By adjusting their own clock timings, the MU101a, 101b, 101c and IED100 synchronize their time, so that the starting points of the data are aligned in units of the least common multiple (22.5° × n: n is an integer) between the 4.5° operating MU101a, 101b, and 101c and the 3.75° operating IED100.

[0033] The IED100 consists of an input means 1, a synchronization control means 2, a first digital filter (DF1) 3, a filter coefficient output means 4, a data buffer means 8, a second digital filter means (DF2) 9, a protection control calculation / SEQ processing means 10, and an output means 11.

[0034] Input means 1 receives SV data obtained by A / D conversion of analog input signals L100a to L100c taken in by each MU from the main unit. Synchronization control means 2 extracts a synchronization control packet from the signal L101 received and processed by input means 1 and performs synchronization control. The first digital filter 3 removes aliasing components. Filter coefficient transmission means 4 transmits the filter coefficients L105 necessary for the filter calculation performed by the first digital filter 3. Data buffer means 8 stores the filter calculation output data L106 of the first digital filter 3 and transmits the stored data L107. The second digital filter means 9 transmits a signal L108 from which the low-harmonic signal components of the power system contained in the data L107 have been removed. Protection control calculation / SEQ processing means 10 performs protection control calculation and sequence processing using the data from which the low-harmonic components have been removed. Output means 11 transmits operation command signals to power equipment such as MU 101a based on the processing results.

[0035] In the IED100, the consistent processing function from input means 1 to data buffer 8 is comprised of hardware such as a field-programmable gate array (hereinafter referred to as FPGA).

[0036] Therefore, the synchronization control means 2 synchronizes with the GMC 102 in time using, for example, a time synchronization control method defined in IEC 61588, and provides a timing control signal L103 to the first digital filter 3 and a timing control signal L104 to the filter coefficient output means 4, so that the hardware circuits of the first digital filter 3 and the filter coefficient output means 4 operate in conjunction.

[0037] The filter coefficient transmission means 4 implemented in the IED100 consists of a filter coefficient group 5, a selection means 6, and a phase calculation means 7. The filter coefficient group 5 stores filter coefficients with predetermined combination configurations. The phase calculation means 7 detects the current timing phase based on the timing control signal L104. The selection means 6 selects one filter coefficient from the filter coefficient group 5 based on the phase detected by the phase calculation means 7 and provides it to the filter means 3. These operations also operate based on time-synchronized signals.

[0038] Furthermore, although not shown in Figure 1, the series of operations from the second digital filter means (DF2) 9 to the output means 11 are implemented by the CPU software. The hardware configuration of these components will be described later using diagrams (see Figure 5).

[0039] Figure 12 shows the correspondence between sampling timing, input data, and filter coefficients in an embodiment of the present invention.

[0040] Specifically, Figure 12 illustrates the operation of an interpolation filter, which is commonly used to remove aliasing after upsampling.

[0041] Generally, this interpolation filter consists of a Finite Impulse Response (FIR) type low-pass filter (LPF) that does not have a feedback loop.

[0042] As shown in Figure 12, the data passing through this filter enters from the left and exits to the right. The top-to-bottom direction in the figure indicates the flow of time. In the figure, Xn represents the input data, where n in Xn represents the order of the input data, a negative value indicates input data before X0, X-1 is the input data immediately before X0, and X-7 is the input data seven times before X0. hn(h0~h47) represents the filter coefficients of the interpolation filter.

[0043] This example shows the case where L=6, i.e., upsampling by a factor of 6.

[0044] The upsampling function (referred to here as an upsampler) inserts zero data between each of the input data X0, X1, X2...Xn. In this example, five zero data points are inserted. Here, an interpolation filter, an FIR-type LPF, performs the following calculation. As an example, the cases of an electrical angle of 0° and 3.75° are shown in the following formulas.

[0045] (Equation 1) In the case of an electrical angle of 0°: Yn=h0 (X0)+h6 (X-1)+h12 (X-2)+h18 (X-3)+ h24·(X-4)+h30·(X-5)+h36·(X-6)+h42·(X-7) For an electrical angle of 3.75°: Yn=h5·(X0)+h11·(X-1)+h17·(X-2)+h23·(X-3)+ h29·(X-4)+h35·(X-5)+h41·(X-6)+h47·(X-7)

[0046] Here, as shown in the figure, zero data is inserted between each data point in the input data. Therefore, the filter operation in this range becomes filter coefficient - zero data, and the result of the operation is zero.

[0047] Therefore, calculations only need to be performed on the portion where input data exists. Furthermore, while a short-period filter calculation interpolated with zero data can be obtained as a result, the time step for the data used to convert the sampling rate only needs to be 3.75° electrical angle; finer granularity calculation results are not required.

[0048] For example, when configuring an aliasing rejection filter for a 48-tap FIR type LPF, there are 48 filter coefficients from h0 to h47. However, to obtain calculation results for every 3.75° electrical angle, when the electrical angle is 0°, calculations using the coefficients h0, h6, h12, h18, h24, h30, h36, and h42 are sufficient, and calculations using the other coefficients are unnecessary.

[0049] Similarly, to obtain the calculation result after an electrical angle of 3.75° has elapsed, the calculation should be performed using the coefficients h5, h11, h17, h23, h29, h35, h41, and h47.

[0050] By performing this calculation while changing the filter coefficient every 3.75° of electrical angle, it becomes unnecessary to insert zero data and perform upsampling, thus eliminating the need to shorten the calculation period. In other words, the upsampling operation due to zero data can be eliminated.

[0051] Next, Figures 1 and 2 will be used to explain the filtering operation for aliasing removal.

[0052] Figure 2 shows an example configuration of a digital filter that removes resampling aliasing according to Embodiment 1 of the present invention.

[0053] First, Figure 2(a) shows the details of the filter coefficient output means 4 in Figure 1.

[0054] In Figure 2(a), the filter coefficient group 20 is composed of six combinations of filter coefficients 200 to 205. This corresponds to the filter coefficient group 5 in Figure 1. The filter coefficient selection circuit 21 corresponds to the selection means 6 in Figure 1, and based on the results of the phase calculation by the phase calculation means 7 in Figure 1, it selects the necessary coefficient group from multiple (in this embodiment, six elements) filter coefficient groups and sets them in the filter coefficient storage register 22.

[0055] Furthermore, it is necessary to prepare a set of filter coefficients equal to the value obtained by dividing the least common multiple (electrical angle 22.5° in this embodiment) between the sampling period of the input data of the first digital filter (DF1) 3 (electrical angle 4.5° in this embodiment) and the sampling period of the output data (electrical angle 3.75° in this embodiment) by the latter period (6 in this embodiment).

[0056] This setting operation is performed cyclically at regular intervals of 3.75° of electrical angle.

[0057] Figure 2(b) shows the configuration of an FIR-type LPF for aliasing rejection. This FIR-type LPF corresponds to the first digital filter (DF1)3 shown in Figure 1.

[0058] In Figure 2(b), the FIR-type LPF consists of delay units 23a to 23d that delay the input data with each calculation period, multipliers 24a to 24e that multiply the input data and the delayed input data by filter coefficients, and an adder circuit 25 that adds up the calculation results of each multiplier. The summation result becomes the output Y(n) of the aliasing rejection filter.

[0059] Here, if we set the number of taps in the FIR-type LPF to 48, the total number of filter coefficients will be 48, from h0 to h47. The combinations of filter coefficients in each group of filter coefficients are as follows, and the filter operation is divided by phase. In other words, the aliasing removal filter is made multiphase.

[0060] Coefficient Gr1…h0,h6,h12,h18,h24,h30,h36,h42 Coefficient Gr2…h1,h7,h13,h19,h25,h31,h37,h43 Coefficient Gr3…h2,h8,h14,h20,h26,h32,h38,h44 Coefficient Gr4…h3,h9,h15,h21,h27,h33,h39,h45 Coefficient Gr5…h4,h10,h16,h22,h28,h34,h40,h46 Coefficient Gr6…h5,h11,h17,h23,h29,h35,h41,h47

[0061] The hardware that performs the calculation has the configuration shown in Figure 2(b), and takes in a selected group of filter coefficients at time intervals corresponding to the phase and performs the calculation.

[0062] The filter coefficients are determined by pre-designing the frequency-gain characteristics for aliasing rejection, calculating the coefficients for each tap from h0 to h47, and storing them in a coefficient storage area.

[0063] Figure 3 shows an example of the operating timing of a digital filter that removes aliasing components of resampling according to Embodiment 1 of the present invention.

[0064] Referring to Figure 3, an example of the operating timing of the aliasing rejection filter shown in Figure 2 will be explained. Figure 3(a) shows the sampling timing for an electrical angle of 4.5°, where data is extracted at intervals of T1, which is a period of 4.5°.

[0065] Figure 3(b) shows an example of data update timing for an electrical angle of 4.5°. Here, an example from Data(t0) to Data(t4) is shown, but the data should be updated in accordance with the timing shown in Figure 3(a).

[0066] Figure 3(c) shows the data update timing for an electrical angle of 3.75°, and Figure 3(d) shows the timing for calculating the aliasing rejection filter every 3.75° of electrical angle. This series of operations is repeated cyclically.

[0067] At timing t0 in Figure 3(d), the coefficient Gr1_200 is taken from the filter coefficient group at the beginning of the process, and the filter operation shown in Figure 2(b) is performed.

[0068] The following shows the combinations of eight data points used in the filtering operation of the aliasing rejection filter at each time step. The X-7 to X5 entries in DF(t0) to DF(t7) represent SV data sampled at an electrical angle of 4.5°. In other words, each SV data point is updated every 4.5° of electrical angle. Note that Figure 3 shows DF(t0) to DF(t5) and X0 to X-4, while the others are omitted.

[0069] For example, X-7 represents data acquired 7 samples before time X0, DF(t1) represents calculations using data from X0 to X-7 with an electrical angle of 4.5°, and DF(t2) represents calculations using data from X1 to X-6 with an electrical angle of 4.5°. For example, DF(t2) represents 1 sample after DF(t1) with an electrical angle of 3.75°.

[0070] DF(t0)…X0,X-1,X-2,X-3,X-4,X-5,X-6,X-7 DF(t1)…X0,X-1,X-2,X-3,X-4,X-5,X-6,X-7 DF(t2)…X1,X0,X-1,X-2,X-3,X-4,X-5,X-6 DF(t3)…X2,X1,X0,X-1,X-2,X-3,X-4,X-5 DF(t4)…X3,X2,X1,X0,X-1,X-2,X-3,X-4 DF(t5)…X4,X3,X2,X1,X0,X-1,X-2,X-3 DF(t6)…X5,X4,X3,X2,X1,X0,X-1,X-2 DF(t7)…X5,X4,X3,X2,X1,X0,X-1,X-2

[0071] The aliasing rejection filter repeatedly performs filtering operations using the multiple SV data shown above. Due to the relationship between the periods of electrical angles 4.5° and 3.75°, within the least common multiple of electrical angle 22.5°, data for electrical angles 4.5° is obtained 5 times and data for electrical angles 3.75° is obtained 6 times.

[0072] Therefore, in the example above, DF(t0) and DF(t1), and DF(t6) and DF(t7), two of the six calculation patterns for an electrical angle of 3.75° will use the same SV data for an electrical angle of 4.5°. However, the filter coefficients used in the aliasing removal filter calculation are updated and calculated every 3.75° of electrical angle.

[0073] If the electrical angles of 4.5° and 3.75° are not synchronized, that is, if the data update timing slips, calculations based on the above timing relationship become impossible, and the desired characteristics cannot be obtained. Therefore, synchronization between the MU on the data transmitting side and the IED on the receiving side is essential. In other words, synchronization control is necessary so that the synchronization point aligns at the electrical angle of 22.5°, which is the least common multiple of the electrical angles of 4.5° and 3.75°.

[0074] While this can be achieved by synchronous control at an electrical angle of 22.5°, it can also be handled by controlling it at a constant period (e.g., a 1s period) using a common time synchronization protocol, taking into account the frequency deviation of the clock oscillators implemented in the MU and IED.

[0075] Next, we will explain the time synchronization method using Figure 4.

[0076] Figure 4 shows an example of time synchronization timing according to Embodiment 1 of the present invention.

[0077] Figure 4(a) describes the time synchronization of a two-terminal configuration consisting of a master station and a slave station.

[0078] Here, the main station corresponds to GMC102 shown in Figure 1. On the other hand, the subordinate stations correspond to MU101a~101c and IED100 shown in Figure 1.

[0079] This time synchronization method is defined in IEEE 1588 or IEC 61588, and its significance lies in its application to stably perform sampling rate conversion. Therefore, only a brief overview of its operation will be provided. Furthermore, the following method is merely an example; other methods that can achieve high-precision time synchronization may be adopted.

[0080] First, the master station sends a transmission packet (SYNC) L401 to the slave station to control synchronization.

[0081] Next, the master station transmits the time data t1, which indicates when the SYNC signal was sent, to the slave station in the following transmission packet (Follow Up) L402.

[0082] Meanwhile, the slave station retrieves the time t0 when it received the first transmit packet (SYNC) L401 and the transmission time data t1 in the next transmit packet (Follow Up) L402.

[0083] Next, the slave station sends a transmission packet (DELAY REQUEST) L403 to the master station to perform synchronization control. At this time, the slave station obtains the transmission time t2.

[0084] Next, the master station transmits the time t3 at which it received packet (DELAY REQUEST) L404 to the slave station in the next packet (DELAY RESPONSE) L404.

[0085] The subordinate station obtains the time t3 from the above packet (DELAY RESPONSE) L404.

[0086] Through this series of operations, the slave station can acquire time data from t0 to t3. Then, by performing the calculation shown in the following formula from this time data, the slave station can obtain delay time tdx and offset time toff, which are data used to correct the sampling timing difference between the master station and the slave station.

[0087] (Equation 3) tdx = ((t1-t0)+(t3-t2)) / 2

[0088] (Equation 4) toff = (t2 - t1) - tdx

[0089] From equations 3 and 4 above, by controlling toff to approach 0, the slave station can be controlled so that its sampling time is the same as that of the master station.

[0090] Thus, this can be achieved by periodically sending and receiving packets to measure the communication delay time, but sampling synchronization control is also possible even if it is done irregularly.

[0091] Generally, this time synchronization control cycle is performed at a 1-second interval in the following IEEE standard, PowerProfile (IEEE Standard Profile for Use of IEEE 1588 Precision Time Protocol in Power System Applications IEEE1588 PowerProfile).

[0092] By synchronizing the time between the MU and IED in this way, the electrical angles of 4.5° and 3.75°, which serve as the reference timing for both, can be synchronized to a 1-second period. Because the synchronization is at 1-second intervals, the electrical angles of 4.5° and 3.75° will each run free for 1 second, but due to the initial value deviation of the clock, synchronization deviations of more than one sample per second will generally not occur. This can be addressed by selecting components with clock accuracy that will not cause synchronization deviations.

[0093] Figure 4(b) shows an example circuit for controlling the activation signals at electrical angles of 3.75° and 30° by time synchronization, with the slave station being an IED100.

[0094] In Figure 4(b), the synchronous control circuit consists of a clock generator 40, frequency divider counters 41 and 42, a register 43 for storing offset values ​​to control the synchronization timing of the slave station, and a signal generation circuit (combinational circuit) 44.

[0095] The offset values ​​obtained using equations 3 and 4 are stored in register 43. By setting the counter's setting value to a value corresponding to the offset, the operating cycle until the counter's time-up can be controlled. As a result, the 3.75° electrical angle start signal and the 30° electrical angle interrupt signal of the signal generation circuit are controlled.

[0096] Figure 4(c) shows an example of the timing of a synchronous control circuit.

[0097] Figure 4(c) shows the periodic timing 45 for synchronous control (1 pps) of the GMC102, an example timing 46 in the IED100, and an interrupt signal 47 for an electrical angle of 30° in the IED100.

[0098] As mentioned earlier, in the period timing 45 of the GMC's synchronous control (1pps), the normal period T4 is 1 second.

[0099] Timing example 46 in IED100 shows that an activation signal is generated every 3.75° of electrical angle, which is synchronized with the 1pps timing mentioned above.

[0100] The interrupt signal 47 for an electrical angle of 30° in the IED100 is also synchronized with the timing of 1pps.

[0101] Figure 5 shows an example of the hardware block configuration of the IED100 for realizing the protection control function according to Embodiment 1 of the present invention.

[0102] In Figure 5, the IED hardware consists of communication means 50a and 50b, SERDES means (Serializer / Deserializer) 51a and 51b, PCS (Physical Coding Sublayer) means 52a and 52c, receiving FIFO means 53a and transmitting FIFO means 53b, digital filter (DF1) 55, filter coefficient memory means 56, timing control means 57, arithmetic means (CPU) 59, memory means 58, program memory 60, and CPU bus 500.

[0103] Communication means 50a and 50b communicate with MU101a~101c. SERDES means 51a and 51b convert serial signals to parallel signals, or parallel signals to serial signals. PCS means 52a and 52c encode frames. Receiving FIFO means 53a and transmitting FIFO means 53b have hardware timestamp functions and set and enter received and transmitted data. Digital filter (DF1) 55 is configured as an anti-aliasing filter. Filter coefficient memory means 56 stores the filter coefficients of the digital filter 55. Timing control means 57 performs timing control for operating the above circuit means. CPU 59 performs various calculations. Memory means 58 stores information for operating the CPU 59. Program memory 60 stores the program for the CPU 59.

[0104] As explained with reference to Figure 1, the operation of the second digital filter means (DF2) 9, the protection control calculation SEQ processing means 10, and the output means 11 shown in Figure 1 is realized by the CPU 59 executing a program stored in the program memory 60. The digital filter 55 corresponds to the first digital filter (DF1) 3 shown in Figure 1, and the filter coefficient memory 56 is included in the filter coefficient output means 4 shown in Figure 1.

[0105] Furthermore, the filter coefficient memory 56 shown in Figure 5 incorporates a filter coefficient group 5, which stores filter coefficients in a predetermined combination configuration as shown in Figure 1, and a selection means 6, which selects one filter coefficient from the filter coefficient group 5 based on the phase calculated by the phase calculation means 7 and provides it to the filter means 3.

[0106] Furthermore, the timing control means 57 supplies timing signals to each part based on the synchronization information of the time synchronization means (for example, a high-precision time synchronization means based on the IEEE 1588 standard) 54. Since this time synchronization means 54 performs synchronization control by exchanging synchronization packets with the GMC 102 shown in Figure 1, it is in a state of high-precision synchronization with the MU 101a to 101c shown in Figure 1.

[0107] Figure 6 shows an example of the signal processing flow according to Embodiment 1 of the present invention.

[0108] Figure 6(a) shows the response from signal reception to aliasing rejection filter calculation, and Figure 6(b) shows the response of protection control and sequence processing including low-harmonic rejection digital filter.

[0109] In Figure 6(a), the IED100 waits for startup with an electrical angle period of 3.75° in step S001, and after startup, performs the operations S002 to S006. All of these processes are performed by hardware. In step S002, the IED100 reads input data with an electrical angle of 4.5° from the receiving FIFO53a, performs a phase calculation for coefficient selection in step S003, selects a group of filter coefficients based on the phase calculation result in step S004, and sets the selected group of filter coefficients in the coefficient register of the aliasing rejection LPF.

[0110] Subsequently, in step S005, the IED100 calculates the aliasing removal LPF and stores the calculation result of the aliasing removal LPF at a 3.5° period in step S006. This series of operations is repeated cyclically every 3.75° of electrical angle.

[0111] Figure 6(b) shows the operation flow when the CPU, as shown in Figure 5, 59, receives an interrupt signal to initiate the 30° electrical angle processing and starts operating.

[0112] In Figure 6(b), the IED100 reads out eight input data (SV data) that have been resampled to an electrical angle of 3.75° in step S007. In step S008, it performs a digital filter operation (DF2) to remove low-order harmonic components that are unnecessary for protection control calculations. In step S009, it stores the calculation results in memory, performs protection control calculations in step S010, and uses the results to perform the sequence processing in step S011. In step S012, it outputs display-related data, and in step S013, it outputs data such as trip signals to the MU (GOOSE communication). This series of processes is performed cyclically every 30° of electrical angle.

[0113] Figure 7 shows an example of the characteristics of a digital filter that removes aliasing components according to Embodiment 1 of the present invention.

[0114] As described above, the first digital filter (DF1)3 in this embodiment is composed of an FIR-type LPF. As shown in the characteristics (gain-frequency characteristics)70 of this filter, it removes frequency components higher than the Nyquist frequency of the electrical angle 4.5° sampled data with low frequencies before and after resampling, thereby eliminating the influence of aliasing error components that enter the signal band.

[0115] The cutoff frequency of the LPF is set to fc1, and the start frequency of the stopband is set to fst, ensuring the necessary attenuation gs to remove aliasing components.

[0116] fB0 represents the passband, fB1 represents the transition region from the passband to the stopband, and fB2 represents the respective frequency bands of the stopband. The start frequency of the stopband is set to half the lower end of the sampling frequency used for sampling rate conversion to eliminate the effects of aliasing.

[0117] For example, if the system frequency is 60 Hz, then 2400 Hz, which is half of the first sampling frequency of 4800 Hz, is set as the stopband start frequency fst.

[0118] Figure 8 shows an example of the characteristics of a digital filter that removes low-order harmonic components according to Embodiment 1 of the present invention.

[0119] Specifically, Figure 8 shows a filter characteristic 80 that removes low-order harmonic signal components generated during a grid fault, which are necessary for protection control calculations, in accordance with the aliasing rejection filter characteristic 70 shown in Figure 7.

[0120] This filter characteristic 80 is within the passband fB0 of the filter characteristic 70, and is an example of a bandpass filter that uses the fundamental wave f0, which is the system frequency, as the center frequency, and the frequency between the low-frequency side fBP1 and the high-frequency side fBP2 as the passband 81, removing frequencies lower than fBP1 and frequencies higher than fBP2 (stopband 81).

[0121] In the event of a grid fault, low-order harmonics (such as the 3rd, 5th, and 7th harmonics) of the fundamental wave f0 are generated by the capacitance component C to ground and the reactance component L. Since these harmonic components are unnecessary for protection control calculations based on the fundamental wave, they are removed by this filter.

[0122] In this example, we explained using a bandpass filter characteristic, but it is not limited to bandpass filters; lowpass filters or lowpass notch filters can also be used.

[0123] Figure 9 shows an example of a waveform of signal processing according to Embodiment 1 of the present invention.

[0124] Specifically, Figure 9 shows examples of signal waveforms for each part in the configuration of Figure 1 on a time axis. Figure 9(a) shows the input signal L100a, Figure 9(b) shows the output signal L106 of the aliasing rejection digital filter, and Figure 9(c) shows an example of the output signal after passing through the low-harmonic digital filter and converting it to electrical angle 30° data for application to protection control calculations.

[0125] The time interval of the input signal in Figure 9(a) is 4.5°, which corresponds to a signal period T90. The time interval of the output signal of the aliasing rejection digital filter in Figure 9(b) is 3.75°, which corresponds to a period T91. When the aliasing rejection digital filter is configured as an FIR type LPF, a delay time T92 occurs depending on the number of taps in the filter.

[0126] The signal applied to the protection control calculation in Figure 9(c) is output every 30° of electrical angle with a period T93, resulting in a delay time T94 for the low-harmonic rejection filter. Thus, although a delay time is introduced by the aliasing rejection digital filter configured for sampling rate conversion, which was not previously available, sampling rate conversion is still achievable.

[0127] In Example 1, as described above, the aliasing rejection filter (i.e., the first digital filter (DF1)3) and the low-harmonic rejection filter (i.e., the second digital filter (DF2)9) are separated. Therefore, regardless of the characteristics of the former filter, a filter with arbitrary characteristics can be adopted as the latter filter. For example, a filter with a different configuration from the former filter, such as an IIR (Infinite Impulse Response) type filter, can be adopted as the latter filter, and characteristics other than a bandpass filter can be set. Therefore, in Example 1, there is a high degree of design freedom for the second digital filter (DF2)9, and a filter with arbitrary characteristics tailored to the application of the IED100 can be implemented. [Examples]

[0128] Next, Embodiment 2 of the present invention will be described with reference to Figures 10 and 11. The system configuration of Embodiment 2 is the same as that of Embodiment 1 shown in Figures 1 to 9, except for the differences described below, so the explanation will be omitted.

[0129] Figure 10 shows an example of the overall processing block configuration of the protection control function system according to Embodiment 2 of the present invention.

[0130] In comparison with the IED100 of Example 1 shown in Figure 1, the IED100 of Example 2 shown in Figure 10 has its digital filter (DF1) 3, which is a digital filter for aliasing rejection for sampling rate conversion, replaced by a digital filter (DF2) 9 provided for low-harmonic rejection. Example 2 is characterized in that this digital filter (DF2) 9 serves both the function of removing aliasing components and the function of removing low-harmonic components that are unnecessary for protection control calculations.

[0131] Aside from the differences in configuration described above, the system configuration of Example 2 is the same as that shown in Figure 1, so the explanation of each functional block will be omitted.

[0132] As shown in the configuration of Figure 10, the function of removing aliasing components and low-order harmonic components unnecessary for protection control calculations can be combined. Therefore, the delay caused by the filter response of the first digital filter (DF1) 3 in Figure 1 is eliminated, and the response time can be shortened. For this reason, it is suitable for protection control systems that require high-speed response.

[0133] The digital filter (DF2) 9 of Example 2 can be constructed using an FIR type filter similar to the first digital filter (DF1) 3 of Example 1. However, its characteristics are changed from filter characteristic 70 to filter characteristic 80 in the example gain-frequency characteristics of the filter shown in Figure 8. That is, the filter coefficient group 5 is calculated in advance and held in the filter coefficient output means 4 so that filter characteristic 80 can be obtained.

[0134] Ideally, a digital filter for aliasing rejection should pass almost all signals below half the resampled signal frequency (below the Nyquist frequency). However, for protection control, since the algorithm is based on the fundamental frequency, low-order harmonic signal components other than the fundamental frequency are attenuated, so there is no need to have a flat characteristic below the Nyquist frequency.

[0135] Furthermore, although the aliasing rejection filter in this embodiment was described using a 48-tap example similar to that in Embodiment 1, the number of taps is not limited to 48; as long as the required attenuation characteristics can be met, the number of taps is not restricted.

[0136] Figure 11 shows an example of a waveform of signal processing according to Embodiment 2 of the present invention.

[0137] Specifically, Figure 11 shows examples of signal waveforms for each part in the configuration of Embodiment 2 on a time axis. Figure 11(a) shows an input signal L100a, etc., and Figure 11(b) shows an example of an output signal when the signal has passed through a low-harmonic digital filter and is converted to electrical angle 30° data for application to protection control calculations.

[0138] As shown in Figure 11, a delay time occurs in Example 2 as well, due to the filter characteristics for low-harmonic rejection. However, since Example 2 does not have a standalone function for aliasing rejection using a digital filter, the delay time in this filter can be eliminated, and the signal response speed can be made faster than in Example 1.

[0139] The ability to increase response speed is also effective in reducing the device completion time of protection and control systems, enabling resampling for protection and control systems in ultra-high voltage systems where operating time is critical, thus expanding the range of applications.

[0140] In both Example 1 and Example 2 described above, when SV data with a sampling rate of 4.5° electrical angle is input, the sampling rate can be converted to 3.75° electrical angle. Therefore, the post-conversion processing can be performed using a proven protection control algorithm.

[0141] In this embodiment, we described the conversion of the sampling rate from an electrical angle of 4.5° to an electrical angle of 3.75°. However, the same method can be used to convert the sampling rate without upsampling, as long as the sampling rate is predetermined, not limited to an electrical angle of 4.5°.

[0142] Furthermore, the system of the embodiment of the present invention may be configured as follows.

[0143] (1) A digital protection control system (e.g., IED100, or a protection control system S1 including the same) comprising: a first digital filter (e.g., the first digital filter (DF1)3 and filter coefficient output means 4 in Figure 1); a second digital filter (e.g., the second digital filter (DF2)9); and a protection control calculation unit (e.g., a protection control calculation SEQ processing unit 10), wherein when the first digital filter receives first data obtained by sampling measured values ​​of a power system at a first sampling frequency (e.g., a frequency corresponding to an electrical angle of 4.5°), it removes the aliasing component at the first sampling frequency from the first data and outputs second data sampled at a second sampling frequency (e.g., a frequency corresponding to an electrical angle of 3.75°); when the second digital filter receives the second data, it removes the low-order harmonic components of the power system contained in the input second data; and the protection control calculation unit performs protection control processing of the power system based on the second data from which the low-order harmonic components have been removed, and outputs the result.

[0144] This eliminates the need to convert SV data to a higher sampling rate through resampling within the IED, as the resampling rate can be converted at a 3.75° cycle. This eliminates the need for high-speed conversion calculations, allowing for miniaturization and lower power consumption of the IED's conversion mechanism. As a result, existing software assets for protection control calculations based on an electrical angle of 3.75° can be reused, allowing proven protection control calculation processes to be applied directly. This maintains reliability while reducing costs. Furthermore, the ability to construct system configurations combined with MUs of different sampling rates improves system design flexibility.

[0145] (2) The digital protection control system described in (1) above, wherein the first digital filter is composed of a non-recurrent digital filter (for example, the FIR filter shown in Figure 2(b)) that has a function to switch filter coefficients according to the timing of processing.

[0146] This allows the resampling rate to be converted to a 3.75° period without having to convert the SV data to a higher sampling rate through resampling within the IED.

[0147] (3) A digital protection control system as described in (2) above, wherein the first digital filter comprises a plurality of delay means (e.g., delayers 23a to 23d), a plurality of multiplication means (e.g., multipliers 24a to 24e), an addition means (e.g., an addition circuit 25), and a filter coefficient memory (e.g., a filter coefficient memory 56 constituting the filter coefficient output means 4), wherein the plurality of delay means are connected in series (e.g., the arrangement of delayers 23a to 23d shown in Figure 2(b)), the first data is input to each of the plurality of multiplication means, and each of the plurality of multiplication means controls the data input to the plurality of delay means and each of the plurality of delay means The data output from is multiplied (for example, the processing of multipliers 24a to 24e shown in Figure 2(b)), the adder adds the outputs of the plurality of multipliers (for example, the processing of the adder circuit 25 shown in Figure 2(b)), the filter coefficient memory holds a plurality of filter coefficient groups (for example, coefficients Gr1 to Gr6), each of the plurality of filter coefficient groups includes a plurality of coefficients multiplied by the plurality of multipliers, and the first digital filter selects the filter coefficient group to apply to the plurality of multipliers according to the phase of the input data (for example, the selection of filter coefficient group shown in Figure 3(d)).

[0148] This allows the resampling rate to be converted to a 3.75° period without having to convert the SV data to a higher sampling rate through resampling within the IED.

[0149] (4) The digital protection control system described in (3) above, wherein the delay amount of each of the plurality of delay means is the period of the first sampling frequency, the filter coefficient memory holds a number of filter coefficient groups (e.g., coefficients Gr1 to Gr6) equal to the value obtained by dividing the least common multiple (e.g., electrical angle 22.5°) of the period of the first sampling frequency (e.g., electrical angle 4.5°) and the period of the second sampling frequency (e.g., electrical angle 3.75°) by the period of the second sampling frequency (e.g., 6), and each filter coefficient of the plurality of filter coefficient groups is determined so that the first digital filter operates as a low-pass filter with a band above the lower Nyquist frequency (e.g., fst in Figure 7) of the first sampling frequency and the second sampling frequency as a stopband, and the first digital filter switches the filter coefficient group applied to the plurality of multiplication means from the plurality of filter coefficient groups for each period of the second sampling frequency.

[0150] This allows the resampling rate to be converted to a 3.75° period without having to convert the SV data to a higher sampling rate through resampling within the IED.

[0151] (5) A digital protection control system as described in (4) above, further comprising: communication means (e.g., communication IF 50a); serial / parallel conversion means (e.g., SERDES 51a); coding means (e.g., PCS 52a); synchronization control means (e.g., synchronization control means 2 and 54); a processor (e.g., CPU 59); a program memory (e.g., program memory 60); and a work memory (e.g., memory 58), wherein the communication means receives data of the measured values ​​of the power system, sampled at the first sampling frequency and digitally converted, as a serial signal via a network connected to the communication means, and the serial / parallel conversion means processes the serial signal. The parallel signal is converted into a parallel signal, the coding means converts the parallel signal with a predetermined code, the synchronization control means synchronizes with the master clock connected to the network and transmits control signals to each part of the digital protection control system, the data converted by the coding means is input to the first digital filter as the first data, the first digital filter switches the filter coefficient group applied to the multiplication means according to the timing of the control signal received from the synchronization control means, and the second digital filter and the protection control calculation unit are realized by the processor executing a program stored in the program memory.

[0152] This allows for the configuration of a protective control system through an appropriate combination of hardware and software.

[0153] (6) The digital protection control system described in (1) above, wherein the second digital filter is a band-pass filter, a low-pass filter, or a low-pass notch filter that passes a predetermined frequency band (for example, the passband 81 in Figure 8) that includes the frequency of the power system.

[0154] This allows existing software assets for protection control calculations to be reused, enabling the application of proven protection control calculation processes.

[0155] (7) A digital protection control system as described in (1) above, comprising: a protection control unit (e.g., IED100) having a first digital filter, a second digital filter, and a protection control calculation unit; a plurality of merging units (e.g., MU101a~101c) connected to the protection control unit via a network; and a ground master clock (e.g., GMC102) connected to the network, wherein each merging unit samples the measured value of the power system at the first sampling frequency, converts it to digital, and transmits it to the protection control unit via the network; and each merging unit and the protection control unit control the sampling and the operation of the first digital filter, respectively, based on a synchronized time achieved by exchanging synchronization information with the ground master clock.

[0156] This ensures reliable time synchronization between the data transmitting MU and the receiving IED, allowing for stable sampling rate conversion.

[0157] (8) A digital protection control system comprising a digital filter (for example, the second digital filter (DF2)9 in Figure 10) and a protection control calculation unit, wherein when first data obtained by sampling measured values ​​of a power system at a first sampling frequency is input to the digital filter, the digital filter removes aliasing components at the first sampling frequency and low-order harmonic components of the power system included in the first data from the first data and outputs second data sampled at a second sampling frequency, and the protection control calculation unit performs protection control processing of the power system based on the second data and outputs the result.

[0158] This eliminates the delay time caused by having a separate digital filter for aliasing removal, thereby increasing the signal response speed.

[0159] It should be noted that the present invention is not limited to the embodiments described above, and various modifications are included. For example, the embodiments described above are explained in detail for a better understanding of the present invention, and are not necessarily limited to those having all of the configurations described. Furthermore, it is possible to replace parts of the configuration of one embodiment with the configuration of another embodiment, and it is possible to add configurations from other embodiments to the configuration of one embodiment. In addition, it is possible to add, delete, or replace parts of the configuration of each embodiment with other configurations.

[0160] Furthermore, each of the above configurations, functions, processing units, and processing means may be implemented in hardware, either partially or entirely, by designing them as integrated circuits, for example. Alternatively, each of the above configurations and functions may be implemented in software by a processor interpreting and executing programs that implement each function. Information such as programs, tables, and files that implement each function can be stored in storage devices such as non-volatile semiconductor memory, hard disk drives, and SSDs (Solid State Drives), or in computer-readable non-temporary data storage media such as IC cards, SD cards, and DVDs.

[0161] Furthermore, the control lines and information lines shown are those deemed necessary for explanatory purposes, and do not necessarily represent all control lines and information lines in the actual product. In practice, it can be assumed that almost all components are interconnected. [Explanation of Symbols]

[0162] S1 Protection Control System 1. Receiving input means 2 Synchronization control means 3. Digital filter for aliasing removal 4. Aliasing Removal Digital Filter Coefficient Means 5 Filter coefficients 6. Selection of filter coefficients 7. Phase calculation means 8 data buffers 9. Low-harmonic rejection filter 10 Protection control calculation SEQ processing means 11 Output means 20. Filter coefficients of the aliasing removal filter 200-205 filter coefficients divided into multiple phases 21 Filter coefficient selection circuit 22 Filter coefficient storage register 22 Multipliers 23a~23d 1-sample delay unit 24a~24e Multiplier 25 Adder 40 Clock Generator 41 counters 42 Signal generation circuit 43 Offset Storage Register 45 1PPS sync signal 46 Electrical angle 3.75° startup timing 47 Electrical angle 30° startup timing 50a, 50b communication interfaces 51a, 51b Serializer / deserializer means 52a, 52b PCS 53a, 53b Receive FIFO memory 54 Synchronous control circuit 55 Aliasing Removal Filter 56 Filter coefficient memory 57 Timing control circuit 58 Work Memory 59 CPU 60 Program Memory 500 CPU bus 70 Example of Gain-Frequency Response of Aliasing-Removing Digital Filter 80. Example of Gain-Frequency Characteristics of a Low-Order Harmonic Rejection Filter 81 Passband of a low-harmonic rejection filter 82 Stopband of Low-Order Harmonic Rejection Filter 120 Operation of the interpolation filter

Claims

1. A digital protection control system, It comprises a first digital filter, a second digital filter, and a protection control calculation unit. When the first digital filter receives first data obtained by sampling the measured values ​​of the power system at a first sampling frequency, it removes the aliasing component at the first sampling frequency from the first data and outputs second data sampled at a second sampling frequency. When the second data is input to the second digital filter, it removes the low-order harmonic components of the power system contained in the input second data. The digital protection control system is characterized in that the protection control calculation unit performs protection control processing of the power system based on the second data from which the low-order harmonic components have been removed, and outputs the result.

2. A digital protection control system according to claim 1, The digital protection control system is characterized in that the first digital filter is composed of a non-recurrent digital filter that has a function to switch filter coefficients according to the timing of processing.

3. A digital protection control system according to claim 2, The first digital filter includes a plurality of delay means, a plurality of multiplication means, an addition means, and a filter coefficient memory. The plurality of delay means are connected in series, and the first data is input, Each of the plurality of multiplication means performs multiplication on the data input to the plurality of delay means and the data output from each of the plurality of delay means. The addition means adds the outputs of the plurality of multiplication means, The filter coefficient memory holds a plurality of filter coefficient groups, Each of the aforementioned plurality of filter coefficient groups includes a plurality of coefficients that are multiplied by the plurality of multiplication means, A digital protection control system characterized in that the first digital filter selects the group of filter coefficients to be applied to the plurality of multiplication means according to the phase of the input data.

4. A digital protection control system according to claim 3, The delay amount of each of the plurality of delay means is the period of the first sampling frequency. The filter coefficient memory holds a number of filter coefficient groups equal to the value obtained by dividing the least common multiple of the period of the first sampling frequency and the period of the second sampling frequency by the period of the second sampling frequency, as the plurality of filter coefficient groups. Each filter coefficient in the group of filter coefficients is determined so that the first digital filter operates as a low-pass filter with a stopband above the lower of the first and second sampling frequencies, the Nyquist frequency. A digital protection control system characterized in that the first digital filter switches the group of filter coefficients applied to the plurality of multiplication means from among the plurality of filter coefficient groups for each period of the second sampling frequency.

5. A digital protection control system according to claim 4, It further comprises communication means, serial / parallel conversion means, coding means, synchronization control means, processor, program memory, work memory, The communication means receives the measured data of the power system, sampled at the first sampling frequency and digitally converted, as a serial signal via the network connected to the communication means. The serial / parallel conversion means converts the serial signal into a parallel signal, The coding means converts the parallel signal with a predetermined code, The synchronization control means synchronizes with the master clock connected to the network and transmits control signals to each part of the digital protection control system. The data converted by the coding means is input to the first digital filter as the first data. The first digital filter switches the group of filter coefficients applied to the multiplication means according to the timing of the control signal received from the synchronization control means. A digital protection control system characterized in that the second digital filter and the protection control calculation unit are realized by the processor executing a program stored in the program memory.

6. A digital protection control system according to claim 1, The digital protection control system is characterized in that the second digital filter is a band-pass filter, a low-pass filter, or a low-pass notch filter that allows a predetermined frequency band including the frequency of the power system to pass through.

7. A digital protection control system according to claim 1, A protection control unit having the first digital filter, the second digital filter, and the protection control calculation unit, Multiple merging units connected to the protection control unit via a network, The network includes a grandmaster clock connected to the aforementioned network, Each merging unit samples the measured values ​​of the power system at the first sampling frequency, converts them to digital, and transmits them to the protection control unit via the network. A digital protection control system characterized in that each merging unit and the protection control unit controls the sampling and the operation of the first digital filter, respectively, based on a time synchronized by exchanging synchronization information with the grand master clock.

8. A digital protection control system, It has a digital filter and a protection control calculation unit, When the digital filter receives first data obtained by sampling the measured values ​​of the power system at a first sampling frequency, it removes the aliasing component at the first sampling frequency and the low-order harmonic components of the power system contained in the first data from the first data, and outputs second data sampled at a second sampling frequency. The digital protection control system is characterized in that the protection control calculation unit performs protection control processing of the power system based on the second data and outputs the result.

9. A digital protection control method performed by a digital protection control system, The digital protection control system comprises a first digital filter, a second digital filter, and a protection control calculation unit. Digital protection control methods are The first digital filter, upon receiving first data obtained by sampling measured values ​​of a power system at a first sampling frequency, outputs second data obtained by removing the aliasing component at the first sampling frequency from the first data and sampling at a second sampling frequency. The second digital filter, upon receiving the second data, performs the following steps: remove the low-harmonic components of the power system contained in the input second data; A digital protection control method characterized in that the protection control calculation unit performs protection control processing of the power system based on the second data from which the low-order harmonic components have been removed, and outputs the result.

Images