Data storage device and method for unbalanced mapping for variable readout resolution

Abstract

This invention provides a data storage device and method for unbalanced mapping for variable readout resolution. [Solution] In a data storage device, when data is received from a host to be stored in a multi-level memory (e.g., a quad-level cell (QLC)) that is stored using a mapping that balances the bit error rate (BER) between different pages in the memory, the controller determines whether the data is intended to be read with dynamic read resolution 610, and if it determines that the data is not intended to be read with dynamic read resolution, it communicates with the memory and has the data written with a standard mapping (e.g., a 4-3-4-4 mapping) 620, and if it determines that the data is intended to be read with dynamic read resolution, it communicates with the memory and has the data written with a non-standard mapping (e.g., a 1-2-4-8 mapping) 630.

Description

Technical Field

[0001] The memory of a data storage device can include memory cells that store more than 1 bit of data per cell. For example, a quad-level cell (QLC) can store 4 bits of data. The 4 bits of data within a QLC cell belong to 4 pages (lower page, middle page, upper page, and top page), and using mapping, data can be stored in various logical pages. For example, using 4-4-3-4 mapping, data is written to the QLC cell such that the lower page, middle page, and top page can be read by sensing the cell voltage in 4 steps, and the upper page can be read by sensing the cell voltage in 3 steps. With this mapping, the number of transitions between adjacent states is approximately evenly divided among the logical pages. Since the bits representing adjacent states differ from each other by only 1 bit, this mapping can be used to balance the bit error rate (BER) between pages.

Brief Description of the Drawings

[0002] [Figure 1A] It is a block diagram of a data storage device according to an embodiment. [Figure 1B] It is a block diagram illustrating a memory module according to an embodiment. [Figure 1C] It is a block diagram illustrating a hierarchical memory system according to an embodiment. [Figure 2A] It is a block diagram illustrating the components of a controller of a data storage device illustrated in FIG. 1A according to an embodiment. [Figure 2B] It is a block diagram illustrating the components of a data storage device illustrated in FIG. 1A according to an embodiment. [Figure 3] It is a block diagram of a host and a data storage device according to an embodiment. [Figure 4] It is a diagram of a 4-3-4-4 bit error rate (BER) equalization mapping according to an embodiment. [Figure 5] This is a diagram of the 1-2-4-8 non-balanced mapping in one embodiment. [Figure 6] This is a flowchart of one embodiment of a method for writing data received from a host. [Figure 7] This is a flowchart of one embodiment of a method for remapping previously written data. [Modes for carrying out the invention]

[0003] The following embodiments generally relate to data storage devices and methods for unbalanced mapping for variable read resolution. In one embodiment, a data storage device is provided comprising a memory having multilevel memory cells and one or more processors. The one or more processors are configured individually or in combination to determine whether it is necessary to provide a lower-resolution version of the data, and to store the data in memory using a first mapping if it is determined that it is not necessary to provide a lower-resolution version of the data, and to store the data in memory using a second mapping if it is determined that it is necessary to provide a lower-resolution version of the data, the lower-resolution version of the data is provided by reading only the lower pages of the data, and the memory sense operations required to read the lower pages are less when the data is stored using the second mapping than when the data is stored using the first mapping.

[0004] Another embodiment provides a method to be performed in a data storage device having multilevel memory cells. This method includes determining whether the data is designated for reading at dynamic read resolution, and, depending on whether it is determined that the data is designated for reading at dynamic read resolution, storing the data in memory using a non-BER (bit error rate) balanced mapping, wherein the memory sense operations required to read the lower pages of the data are less when the data is stored using a non-BER balanced mapping than when it is stored using a BER balanced mapping.

[0005] In yet another embodiment, a data storage device is provided comprising a memory having multilevel memory cells, and means for selecting a mapping from a plurality of mappings based on whether the data is specified for variable read resolution, and writing the data to the memory using the selected mapping.

[0006] Other embodiments are also possible, and each embodiment can be used individually or in combination. Accordingly, various embodiments are described herein with reference to the accompanying drawings.

[0007] Embodiment The following embodiments relate to data storage devices (DSDs). As used herein, “data storage device” refers to a non-volatile device that stores data. Examples of DSDs include, but are not limited to, hard disk drives (HDDs), solid state drives (SSDs), tape drives, and hybrid drives. Illustrative details of DSDs are provided below.

[0008] Examples of data storage devices suitable for use in implementing aspects of these embodiments are shown in Figures 1A and 1C. Note that these are merely examples, and other implementations may be used. Figure 1A is a block diagram illustrating a data storage device 100 according to one embodiment. Referring to Figure 1A, the data storage device 100 in this example includes a controller 102 coupled to a non-volatile memory, which may consist of one or more non-volatile memory dies 104. As used herein, the term die refers to a collection of non-volatile memory cells and associated circuits for managing the physical operation of those non-volatile memory cells, formed on a single semiconductor substrate. The controller 102 interfaces with a host system and transmits command sequences for read, program, and erase operations to the non-volatile memory dies 104. Also as used herein, the phrases “communicate with” or “coupled with” may mean directly communicating / coupled, or indirectly communicating / coupled through one or more components, which may or may not be illustrated or described herein. The communication / coupled may be wired or wireless.

[0009] The controller 102 (which may be a non-volatile memory controller (e.g., a flash, resistive random-access memory (ReRAM), phase-change memory (PCM), or magnetoresistive random-access memory (MRAM) controller)) may include one or more components configured individually or in combination to perform certain functions, including but not limited to those described herein and illustrated in the flowcharts. For example, as shown in Figure 2A, the controller 102 may include one or more processors 138 configured individually or in combination to perform functions, including but not limited to those described herein and illustrated in the flowcharts, by executing computer-readable program code stored in one or more non-temporary memories 139 (e.g., random access memory (RAM) 116 or read-only memory (ROM) 118) inside and / or outside the controller 102. As another example, one or more components may include, but are not limited to, circuitry such as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0010] In one exemplary embodiment, the non-volatile memory controller 102 is a device that manages data stored in non-volatile memory and communicates with a host, such as a computer or electronic device having any suitable operating system. In addition to the specific functions described herein, the non-volatile memory controller 102 may have a variety of other functions. For example, the non-volatile memory controller may format the non-volatile memory to ensure that the memory is functioning properly, map out faulty non-volatile memory cells, and allocate spare cells to replace future failed cells. Some portions of the spare cells may be used to operate the non-volatile memory controller and hold firmware (and / or other metadata used for housekeeping and tracking) to implement other features. While operating, the host can communicate with the non-volatile memory controller when it needs to read data from or write data to the non-volatile memory. If the host provides a logical address from which data is read / written, the non-volatile memory controller can translate the logical address received from the host into a physical address in the non-volatile memory. Non-volatile memory controllers can also perform a variety of memory management functions, including, but are not limited to, wear leveling (distributing writes to avoid wearing out specific blocks of memory that would otherwise be repeatedly written to) and garbage collection (moving only valid pages of data to new blocks after a block is full, so that full blocks can be erased and reused).

[0011] The non-volatile memory die 104 may include any suitable non-volatile storage medium, including resistive random-access memory (ReRAM), magnetoresistive random-access memory (MRAM), phase-change memory (PCM), NAND flash memory cells, and / or NOR flash memory cells. The memory cells may take the form of solid-state (e.g., flash) memory cells and may be programmable once, multiple times, or many times. The memory cells may also be single-level cells (SLC), multiple-level cells (MLC) (e.g., dual-level cells, triple-level cells (TLC), quad-level cells (QLC), etc.), or other memory cell level technologies currently known or to be developed may be used. Furthermore, the memory cells may be manufactured in two-dimensional or three-dimensional manner.

[0012] The interface between the controller 102 and the non-volatile memory die 104 may be any preferred flash interface, such as toggle mode 200, 400, or 800. In one embodiment, the data storage device 100 may be a card-based system such as a Secure Digital (SD) or Micro Secure Digital (microSD) card. In another embodiment, the data storage device 100 may be part of an embedded data storage device.

[0013] In the example illustrated in Figure 1A, the data storage device 100 (sometimes referred to herein as a storage module) includes a single channel between the controller 102 and the non-volatile memory die 104; however, the subject matter described herein is not limited to having a single memory channel. For example, in some architectures (such as those shown in Figures 1B and 1C), depending on the capabilities of the controller, two, four, eight or more memory channels may exist between the controller and the memory device. In any of the embodiments described herein, even if a single channel is shown in the drawings, two or more channels may exist between the controller and the memory die.

[0014] Figure 1B illustrates a storage module 200 including a plurality of non-volatile data storage devices 100. Thus, the storage module 200 may include a host and a storage controller 202 that interfaces with a data storage device 204 containing the plurality of data storage devices 100. The interface between the storage controller 202 and the data storage devices 100 may be a bus interface such as a serial advanced technology attachment (SATA), peripheral component interconnect express (PCIe) interface, double-data-rate (DDR) interface, or serial attached small-scale compute interface (SAS / SCSI). In one embodiment, the storage module 200 may be a solid-state drive (SSD) or a non-volatile dual in-line memory module (NVDIMM), as found in server PCs or portable computing devices such as laptop computers and tablet computers.

[0015] Figure 1C is a block diagram illustrating a hierarchical storage system. The hierarchical storage system 250 includes a plurality of storage controllers 202, each controlling its own data storage device 204. A host system 252 can access the memory in the storage system 250 via a bus interface. In one embodiment, the bus interface may be a Non-Volatile Memory Express (NVMe) or Fibre Channel over Ethernet (FCoE) interface. In one embodiment, the system illustrated in Figure 1C may be a rack-mountable mass storage system accessible by multiple host computers, such as those found in data centers or other locations where mass storage is required.

[0016] Referring again to Figure 2A, the controller 102 in this example also includes a front-end module 108 that interfaces with the host, a back-end module 110 that interfaces with one or more non-volatile memory dies 104, and various other components or modules, including, but not limited to, a buffer manager / bus controller module that manages buffers in RAM 116 and controls internal bus arbitration of the controller 102. The modules may include one or more processors or components, as considered above. ROM 118 can store system boot code. Although illustrated separately in Figure 2A, in other embodiments, one or both of RAM 116 and ROM 118 may be located within the controller 102. In yet another embodiment, parts of RAM 116 and ROM 118 may be located both within and outside the controller 102.

[0017] The front-end module 108 includes a host interface 120 and a physical layer interface (PHY) 122 that provide an electrical interface with the host or a next-level storage controller. The choice of host interface 120 may depend on the type of memory being used. Examples of host interface 120 include, but are not limited to, SATA, SATA Express, serially attached small computer system interface (SAS), Fibre Channel, universal serial bus (USB), PCIe, and NVMe. The host interface 120 typically facilitates the transfer of data, control signals, and timing signals.

[0018] The backend module 110 includes an error correction code (ECC) engine 124 that encodes data bytes received from the host and decodes and error-corrects data bytes read from the non-volatile memory. The command sequencer 126 generates command sequences, such as program and erase command sequences, which are sent to the non-volatile memory die 104. The RAID (Redundant Array of Independent Drive) module 128 manages the generation of RAID parity and the recovery of failed data. RAID parity can be used as an additional level of integrity protection for data written to the memory device 104. In some cases, the RAID module 128 may be part of the ECC engine 124. The memory interface 130 provides command sequences to the non-volatile memory die 104 and receives status information from the non-volatile memory die 104. In one embodiment, the memory interface 130 may be a double data rate (DDR) interface, such as a toggle mode 200, 400, or 800 interface. In this example, the controller 102 also includes a media management layer 137 and a flash control layer 132 that controls the overall operation of the backend module 110.

[0019] The data storage device 100 also includes other discrete components 140, such as an external electrical interface, external RAM, resistors, capacitors, or other components that can interface with the controller 102. In an alternative embodiment, one or more of the physical layer interface 122, RAID module 128, media management layer 138, and buffer management / bus controller are optional components that are not required for the controller 102.

[0020] Figure 2B is a block diagram illustrating the components of the non-volatile memory die 104 in more detail. The non-volatile memory die 104 includes peripheral circuits 141 and a non-volatile memory array 142. The non-volatile memory array 142 includes non-volatile memory cells used to store data. The non-volatile memory cells may be any suitable non-volatile memory cells, including two-dimensional and / or three-dimensional ReRAM, MRAM, PCM, NAND flash memory cells and / or NOR flash memory cells. The non-volatile memory die 104 further includes a data cache 156 that caches data and address decoders 148, 150. In this example, the peripheral circuits 141 include a state machine 152 that provides status information to the controller 102. The peripheral circuits 141 may also comprise one or more components configured individually or in combination to perform certain functions, including but not limited to the functions described herein and illustrated in the flowchart. For example, as shown in Figure 2B, the memory die 104 may comprise one or more processors 168 configured individually or in combination to execute computer-readable program code stored in one or more non-temporary memories 169, stored in a memory array 142, or stored outside the memory die 104. As another example, one or more components may include, but are not limited to, circuitry such as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0021] In addition to, or instead of, one or more processors 138 (or, more generally, components) within controller 102 and one or more processors 168 (or, more generally, components) within memory die 104, data storage device 100 can include another set of one or more processors (or, more generally, components). Generally, one or more processors (or, more generally, components) within data storage device 100 are individually or combinatorially configured to perform various functions, including but not limited to the functions described herein and illustrated in the flowcharts, regardless of where they are located and regardless of how many there are. For example, one or more processors (or components) can be located within controller 102, memory device 104, and / or other locations within data storage device 100. Also, different functions can be performed using different processors (or components), or combinations of processors (or components). Further, the means for performing the functions can be implemented using a controller comprising one or more components (e.g., the processors or other components described above).

[0022] Returning again to FIG. 2A, flash control layer 132 (referred to herein as flash translation layer (FTL)) processes flash errors and interfaces with the host. In particular, the FTL, which can be an algorithm within the firmware, is responsible for the internal memory management and converts writes from the host into writes to memory 104. The FTL can be needed because memory 104 can have limited durability, can be written to only a plurality of pages, and / or cannot be written unless erased as a block. The FTL understands these potential limitations of memory 104 that may not be visible to the host. Thus, the FTL attempts to convert writes from the host into writes to memory 104.

[0023] The FTL may include a logical-to-physical address (L2P) map (which may also be referred to herein as a table or data structure), and an allocated cache memory. In this way, the FTL converts a logical block address (“LBA”) from the host to a physical address within the memory 104. The FTL can include other features such as power-off recovery (so that the data structure of the FTL can be recovered in case of sudden power loss), and wear leveling (so that wear across memory blocks is uniform to prevent excessive wear of certain blocks that would lead to a greater likelihood of failure), without limitation.

[0024] Referring back to the drawings, FIG. 3 is a block diagram of a host 300 and a data storage device 100 in one embodiment. The host 300 can take any suitable form, including but not limited to a computer, a mobile phone, a tablet, a wearable device, a digital video recorder, a monitoring system, etc. The host 300 (here, a computing device) in this embodiment includes one or more processors 330 and one or more memories 340. In one embodiment, the computer-readable program code stored in the one or more memories 340 configures the one or more processors 330 to perform the operations described herein as being executed by the host 300. Thus, the actions performed by the host 300 may sometimes be referred to herein as being performed by an application (computer-readable program code) running on the host 300. For example, the host 300 can be configured to send data (e.g., initially stored in the host's memory 340) to the data storage device 100 for storage in the memory of the data storage device.

[0025] In one embodiment, the memory 104 of the data storage device 100 may include a matrix of memory cells. Each of these cells may be a single-level cell (SLC) capable of storing one bit per cell, or a multi-level cell (MLC) capable of storing more than one bit per cell, depending on the storage technology. When an MLC memory stores three or four bits per cell, the memory may be called a triple-level cell (TLC) memory or a quad-level cell (QLC) memory, respectively. The following examples describe QLC memory, but it should be understood that any suitable memory technology currently available or to be developed in the future may be used. For example, other technologies with different numbers of bits per cell (e.g., TLC) may be used.

[0026] A QLC cell can be organized into multiple pages and blocks, providing multiple methods for storing and retrieving data. In this example, write and read operations are performed at the page level, with each page being 16KB. The four bits within a QLC cell belong to four pages: a low page, a middle page, a high page, and a top page. With four 16KB pages, each page can hold 4,096 data samples, and each sample (e.g., a single element of a 32-bit vector) is 32 bits (i.e., each sample is stored in 32 cells, and each bit is stored in a separate cell). When a write operation is performed on a QLC cell, all four pages can be made available. The contents of the four bits in a QLC cell can be represented as voltage values ​​at the charge gate of the QLC cell. This voltage representation of the bit value can be arranged to minimize the number of steps required for voltage sensing operations to detect individual bits of the stored numerical value.

[0027] Logical bit mapping (encoding schemes) can be used to store data on various logical pages of a multibit memory cell. For example, bit error rate (BER) balanced mapping can be used to equalize both the reliability of the logical pages (i.e., the vulnerability of multiple different logical pages to erroneous bit flips) and the read latency from those different logical pages. For example, the 4-4-3-4 encoding mechanism is a standard bit mapping for QLC cells (e.g., used in BiCS5 memory arrays). In the 4-4-3-4 encoding mechanism (see Figure 4), data is written to the QLC cell such that the lower, middle, and upper pages can be read by sensing the cell voltage in four steps, and the upper page can be read by sensing the cell voltage in three steps. This standard mapping can be a gray mapping, where the bits representing adjacent states differ by only one bit from each other. This property of gray mapping also improves memory reliability because the number of transitions between adjacent states is divided almost equally among the logical pages. This mapping is sometimes called a balanced mapping, but it should be noted that this “balanced” mapping is not actually balanced in that the middle page has three transitions and the other pages have four transitions. Also, although a 4-3-4-4 mapping is used in this example, this problem can occur with other well-balanced mappings as well. U.S. Patent Application No. 19 / 035,315 (Atty Dkt No. 10519 / 4282 (WDA-8004-US)), filed on 23 January 2025, titled “Data Storage Device and Method for Bit Error Rate (BER) Balancing Based on Dynamic Sense Time,” incorporated herein by reference, describes a method for mitigating the inherent BER difference between logical pages in a “balanced” mapping. While the standard 4-3-4-4 mapping has advantages in terms of reliability, the inventors have recognized that using a non-standard mapping (e.g., 1-2-4-8) may be advantageous in certain situations.More specifically, while using non-standard mappings may result in lower reliability of stored data compared to using standard mappings, they can significantly reduce latency and power consumption, which may be desirable in some applications. In one embodiment, the data storage device 100 is configured to select a mapping (e.g., a standard 4-3-4-4 mapping or a non-standard 1-2-4-8 mapping) to use for writing data to memory 104 when data is received from host 300 or when previously stored data is rewritten to memory 104 using a different mapping. This provides the data storage device 100 with variable read resolution capabilities.

[0028] In some use cases, the flexibility of the data storage device 100, which allows for multi-resolution readouts from memory 104, can be beneficial. For example, using different resolutions / quantizations may be useful for machine learning models (e.g., using dynamic / lower resolutions to represent model parameters with different numbers of bits). Another exemplary use case is reading images from memory 104 at a relatively low resolution for preliminary visualization purposes (e.g., image downsampling, such as when a smaller image ("thumbnail") is used to represent a full-size image stored in memory 104).

[0029] Challenges may arise in enabling faster reading of low-resolution data from memory 104. For example, in the context of machine learning / artificial intelligence, if 1 / 2 / 4 / 8 / 32 / 64 bits are used per model parameter value, more bits are needed to represent each model parameter. While calculations may be more accurate, they can consume memory and become computationally expensive. As another example, in the context of image / video data, 1 to 32 bits can be used to represent each image pixel. Below is a list of some common color depths and the corresponding number of bits per pixel. 1 bit: Black and white (2 colors) 8-bit: 256 colors (grayscale) 16-bit: 65,536 colors (high color) 24-bit: 16.7 million colors (true color) 32-bit: 4.3 billion colors (with an alpha channel for transparency)

[0030] In one embodiment, an improved approach is provided based on storing data using a non-standard mapping (e.g., an unbalanced 1-2-4-8 gray mapping) so that reading a lower-resolution version of the data can be performed with significantly lower latency (e.g., about one-third) and power consumption compared to reading data stored using a standard mapping (e.g., a 4-2-4-4 mapping). The following examples illustrate the comparison between standard and non-standard, or between a 4-2-4-4 mapping and a 1-2-4-8 mapping, but it should be noted that any suitable mapping may be used. Accordingly, the terms “first mapping” and “second mapping” may be used herein, and no particular type of mapping (e.g., 4-2-4-4 or 1-2-4-8) should be included in the claims unless expressly stated in the claims. Also, the following examples illustrate QLC memory, but these embodiments may be used for any suitable type of memory.

[0031] In one implementation example, the data storage device 100 can use non-standard, unbalanced grayscale mapping to enable faster and lower-energy readouts of frequently used low-resolution data. By providing several resolution / quantization "gears" / options for reading data from memory 104, these embodiments offer flexible trade-offs for skillfully adjusting between read latency / power and the resolution of the read data. In one implementation example, ultrafast readouts for low-resolution data (e.g., up to 1.5 times faster than full-resolution readouts) can be provided by using special bit mapping that enables efficient adjustment between read latency / power and the resolution / quantization of the read content.

[0032] In one embodiment, the data storage device 100 can use an unbalanced BER mapping for scenarios involving dynamic read resolution. In one implementation example, a 1-2-4-8 unbalanced bit mapping is used for partitions that support a flexible trade-off between read latency / power and read resolution. In some scenarios, an unbalanced mapping may be undesirable because the latencies of the logical pages are not equal. However, even in such situations, an unbalanced mapping can be used to provide an efficient solution for faster reading of low-resolution content. Several measures can be used to mitigate the unbalanced BER caused by using this unconventional mapping, as described below.

[0033] Referring again to the drawings, Figure 5 is a diagram of a 1-2-4-8 unbalanced mapping in one embodiment. In this mapping, lower pages have only one transition between adjacent states, middle pages have two transitions, upper pages have four transitions, and top-level pages have eight transitions. This 1-2-4-8 mapping involves one sense operation for lower pages, two sense operations for middle pages, four sense operations for upper pages, and eight sense operations for top-level pages. Such a mapping can result in unequal properties for logical pages. Logical pages may have a greater number of transitions between zero and one, making them more vulnerable to bit errors and potentially leading to higher read latency (due to the increased number of associated sense operations required to read their data).

[0034] In typical application examples, the preferred configuration is to ensure equal latency and reliability across multiple different logical pages, and therefore, BER balanced bit mapping may be desirable. However, in use cases where faster readouts at lower resolution are desired, unbalanced bit mapping (e.g., 1-2-4-8 mapping) may be useful.

[0035] In one example, the controller 102 places the most significant bit of each model parameter or image pixel into the lower page. This data arrangement enables modular resolution readout, which can optimize latency and power consumption for frequently used cases. For example, if the high-resolution representation of a deep neural network model's parameters contains 32 bits, those bits can be stored using a full-resolution model where each parameter is placed in 4 bits within 8 cells. Overall, this provides 32 bits per parameter. To apply fast, low-resolution readout of the model, the controller 102 can apply only one sense operation to the memory 104 to read only the lower page. In such a readout, the parameter read is 8 bits. In cases where a slightly higher resolution readout is desired, the controller 102 can apply three sense operations to read the lower and middle pages to obtain a 16-bit value of the same parameter. The data storage device 100 can perform readouts at 24-bit or 32-bit resolution in a similar manner.

[0036] Reading lower pages involves only one sense operation, while full-resolution reading from a QLC device involves applying 15 sense operations. Thus, low-resolution high-speed reading (of lower pages only) dramatically accelerates the reading operation and reduces power consumption. If low-resolution information is sufficient in most cases and high-resolution information is rarely needed, these embodiments can significantly improve the overall performance of the data storage device 100 and reduce power consumption.

[0037] While the differing read latencies of different logical pages in unbalanced grayscale mapping are useful in many use cases, various approaches can be taken to address the increase in BER that may be encountered when using unbalanced 1-2-4-8 mapping. One approach is to apply the same amount of error correction code (ECC) parity protection to all logical pages and limit the decryption capability, which is usually declared according to higher-level pages that typically have higher BER values. Another approach is to apply the same amount of ECC parity protection to all logical pages. In this way, in the usually rare case of decryption failure in higher-level logical pages (e.g., due to increased vulnerability to bit flips), the decryption process can return the read data as is. If such cases are read frequently enough, this technique may be acceptable for relevant applications such as thumbnail previews and even inference using low-resolution machine learning models (especially if users often notice a decrease in the predictive performance of low-resolution models).

[0038] Another approach uses different parity assignments for each logical page so that ECC protection is balanced across pages. This solution can be relatively more complex than the approach described above because it needs to support various codeword sizes. Yet another approach uses a non-uniform voltage assignment of states, such that states near the active read threshold of the top-level page are further apart than "active states" of lower-level pages. Active states of logical pages with a greater number of transitions between internal logical states (and more active states) can be placed in a larger voltage window space, while active states of lower-level pages can be placed closer to each other, for example, to better balance the overall BER level of the pages.

[0039] Another approach involves applying adapted sensing accuracy to a specific page BER level. For example, lower pages with lower BER levels can use more relaxed sense timing (in addition to having a single threshold, it can be even faster), while top pages with eight read thresholds and therefore higher induced BERs can be read with longer sense timing, thereby resulting in more accurate sensing that can reduce and balance the BER. Sensing timing can be controlled by lengthening or shortening the stabilization time of the bit line voltage (VBL) and control gate voltage (Vcg), and by lengthening or shortening the sense amplifier integration time, thereby controlling the BER of the page being sensed. In this way, the BERs of different pages can be balanced to some extent.

[0040] In one embodiment, the controller 102 of the data storage device 100 can determine whether to use a first or second mapping (e.g., a standard 4-3-4-4 mapping or a non-standard 1-2-4-8 mapping) when storing data received from the host 300. A flowchart 600 in Figure 6 illustrates this embodiment. As shown in Figure 6, when the data storage device 100 receives data from the host 300 to store in the memory 104 of the data storage device 100, the controller 102 of the data storage device 100 determines whether the data is intended to be read at dynamic read resolution (610). This determination can be made in any suitable way. For example, the host 300 can provide instructions to the data storage device 100 either explicitly (e.g., using flags, vendor-specific codes, explicit instructions from the host 300 about the required mapping type (i.e., whether the data should be read faster at a lower resolution) or implicitly (e.g., by identifying the application on the host 300 that is sending the data, by requesting that the data be stored in a logical partition designated for low-resolution reading).

[0041] If the controller 102 determines that the data is not intended to be read with dynamic read resolution, the controller 102 communicates with the memory 104 and has it write the data using a standard mapping (e.g., 4-3-4-4 mapping) (620). However, if the controller 102 determines that the data is intended to be read with dynamic read resolution, the controller 102 communicates with the memory 104 and has it write the data using a non-standard mapping (e.g., 1-2-4-8 mapping) (630).

[0042] Additionally or alternatively, the controller 102 of the data storage device 100 may remap previously written data. This embodiment is shown in flowchart 700 of Figure 7. As shown in Figure 7, after data has been programmed into memory 104 using a standard mapping (e.g., 4-3-4-4 mapping) (710), and there is an ongoing operation (720), the controller 102 determines whether it is necessary to support dynamic read resolution (730). The controller 102 may make this determination by any appropriate method. For example, the controller 102 may make this determination according to internal observations of general use or in response to an explicit instruction from the host 300. If the controller 102 determines that it is not necessary, the method loops back to 720 and no data remapping occurs. However, if the controller 102 determines that it needs to support dynamic read resolution, the controller 102 generates another copy of the data (740) and stores that copy in a different location in memory 104 using a non-standard mapping (e.g., a 1-2-4-8 mapping) (750). The original copy of the data may be retained or discarded.

[0043] There are several advantages associated with this embodiment. For example, these embodiments can provide an efficient method for storing data in the memory of a data storage device so that the data can be read at several levels of granularity / resolution / quantization and at several speeds. In one implementation example, the accelerated read rate of the lower-resolution version of the stored data that the data storage device can provide is up to 16 times faster than that of conventional QLC memory. Also, using dynamic or lower resolution for machine learning model weights can provide advantages over other possible solutions to the aforementioned problem. One such possible solution is to store several copies of the model parameters in memory, each copy contained in a different resolution. This solution reduces the overall throughput for loading the model parameters at the expense of cost (i.e., the memory volume required to hold the model). However, using dynamic or lower resolution for machine learning model weights can provide latency reductions that are not obtainable with this solution.

[0044] Another possible solution to the aforementioned problem is to place the data on different logical pages and make only some of the logical pages readable. Therefore, if low-resolution readout is required, only a single logical page may be sensed and transferred, which may contain low-resolution data (e.g., the most significant bits of the weights in a machine learning model, or low-resolution pixel data in an image). This is described in more detail in U.S. Patent Application No. 18 / 945,932, incorporated herein by reference. However, in some environments, the embodiments described above may offer advantages over the approach described in that patent document.

[0045] Finally, as mentioned above, any suitable type of memory can be used. Semiconductor memory devices include volatile memory devices such as dynamic random access memory ("DRAM") or static random access memory ("SRAM") devices, non-volatile memory devices such as resistive random access memory ("ReRAM"), electrically erasable programmable read-only memory ("EEPROM"), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory ("FRAM"), and magnetoresistive random access memory ("MRAM"), as well as other semiconductor elements capable of storing information. Each type of memory device may have a different configuration. For example, flash memory devices may be configured in a NAND or NOR configuration.

[0046] Memory devices can be formed from passive and / or active elements in any combination. As a non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity switching memory elements such as antifuses and phase-change materials, and optionally steering elements such as diodes. Furthermore, as a non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements with charge storage regions such as floating gates, conductive nanoparticles, or charge-storage dielectric materials.

[0047] Multiple memory elements may be configured to be connected in series or so that each element is individually accessible. As a non-limiting example, flash memory devices in a NAND configuration (NAND memory) typically contain memory elements connected in series. A NAND memory array may be configured such that the array consists of multiple memory strings, each string comprising multiple memory elements that share a single bit line and are accessed as a group. Alternatively, memory elements may be configured so that each element is individually accessible (e.g., a NOR memory array). NAND and NOR memory configurations are examples, and memory elements may be configured in other ways.

[0048] Semiconductor memory elements located within and / or on the substrate may be arranged in two or three dimensions, such as in a two-dimensional memory structure or a three-dimensional memory structure.

[0049] In a two-dimensional memory structure, semiconductor memory elements are arranged on a single plane or at the single memory device level. Typically, in a two-dimensional memory structure, memory elements are arranged on a plane (e.g., the xz plane) that extends substantially parallel to the main plane of the substrate supporting the memory elements. The substrate may be a wafer on which layers of memory elements are formed, either above or within it, or a carrier substrate to which the memory elements are attached after they have been formed. In non-limiting embodiments, the substrate may include a semiconductor such as silicon.

[0050] Memory elements may be arranged in an ordered array, such as multiple rows and / or columns, at the level of a single memory device. However, memory elements may be arranged in an irregular or non-orthogonal configuration. Each memory element may have two or more electrodes or contact lines, such as bit lines and word lines.

[0051] A three-dimensional memory array is arranged such that memory elements occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional structure (i.e., in the x, y, and z directions, where the y direction is substantially perpendicular to the main surface of the substrate, and the x and z directions are substantially parallel to the main surface of the substrate).

[0052] As a non-limiting embodiment, a three-dimensional memory structure may be arranged vertically as a stack of multiple two-dimensional memory devices. As another non-limiting example, a three-dimensional memory array may be arranged as multiple vertical columns (e.g., columns substantially perpendicular to the main plane of the substrate, i.e., extending in the y-direction) where each column has multiple memory elements within each column. The columns may be arranged in a two-dimensional configuration, e.g., in the xz plane, resulting in a three-dimensional arrangement of memory elements having elements on multiple vertically stacked memory planes. Other configurations of three-dimensional memory elements can also constitute a three-dimensional memory array.

[0053] As a non-restrictive example, in a three-dimensional NAND memory array, memory elements may be joined together to form a NAND string within a single horizontal (e.g., xz) memory device level. Alternatively, memory elements may be joined together to form a vertical NAND string that spans multiple horizontal memory device levels. Other three-dimensional configurations can be envisioned where some NAND strings contain memory elements within a single memory level, and others contain memory elements that span multiple memory levels. Three-dimensional memory arrays can further be designed in NOR and ReRAM configurations.

[0054] Typically, in a monolithic three-dimensional memory array, one or more memory device levels are formed on a single substrate. If necessary, the monolithic three-dimensional memory array may further have one or more memory layers, at least partially, within a single substrate. In non-limiting embodiments, the substrate may include a semiconductor such as silicon. In a monolithic three-dimensional array, the layers constituting each memory device level of the array are typically formed on layers of memory device levels beneath the array. However, adjacent memory device level layers in a monolithic three-dimensional memory array may be shared, or there may be intervening layers between the memory device levels.

[0055] In this case as well, two-dimensional arrays can be formed separately and then packaged together to form a non-monolithic memory device having multiple memory layers. For example, a non-monolithic stacked memory can be constructed by forming memory levels on separate substrates and then stacking the memory levels on top of each other. The substrates may be thinned or removed from the memory device levels before stacking, but since the memory device levels are initially formed on separate substrates, the resulting memory array is not a monolithic three-dimensional memory array. Furthermore, multiple two-dimensional or three-dimensional memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked chip memory device.

[0056] Related circuitry is typically required for the operation of memory elements and for communication with them. As a non-limiting example, a memory device may have circuitry used to control and drive memory elements to achieve functions such as programming and reading. This related circuitry may be on the same board as the memory elements and / or on a separate board. For example, a controller for memory read / write operations may be located on a separate controller chip and / or on the same board as the memory elements.

[0057] Those skilled in the art will recognize that the present invention is not limited to the two-dimensional and three-dimensional structures described, but encompasses all relevant memory structures within the spirit and scope of the invention, as described herein and understood by those skilled in the art.

[0058] The detailed description above is intended to be understood not as a definition of the invention, but as an illustration of selected forms that the invention may take. Only the following claims, including all equivalents, are intended to define the scope of the claimed invention. Finally, it should be noted that any aspect of the embodiments described herein may be used individually or in combination with others.

Claims

1. A data storage device, Memory including multi-level memory cells, The system comprises one or more processors, and the one or more processors are Determine if a lower-resolution version of the data needs to be provided. In accordance with the determination that it is not necessary to provide a lower-resolution version of the aforementioned data, the data is stored in the memory using the first mapping. In response to determining that it is necessary to provide a lower-resolution version of the aforementioned data, the system is configured, individually or in combination, to store the data in the memory using a second mapping, the lower-resolution version of the data being provided by reading only the lower pages of the data, and the memory sense operations required to read the lower pages are less when the data is stored using the second mapping than when the data is stored using the first mapping. Data storage device.

2. The data storage device according to claim 1, wherein the first mapping includes a 4-4-3-4 mapping and the second mapping includes a 1-2-4-8 mapping.

3. The data storage device according to claim 1, wherein the first mapping includes a bit error rate (BER) balanced mapping, and the second mapping includes a non-BER balanced mapping.

4. The data storage device according to claim 1, wherein the determination is performed in response to the data being received from the host.

5. The data storage device according to claim 1, wherein the determination is performed in response to the remapping of the data previously stored in the memory using a different mapping.

6. The data storage device according to claim 1, wherein the most significant bit of the data is stored in the lower page.

7. The data storage device according to claim 1, wherein the low-resolution version of the data includes a low-resolution version of the parameters of a machine learning model.

8. The data storage device according to claim 1, wherein the low-resolution version of the data includes a low-resolution version of an image.

9. The data storage device according to claim 1, wherein the memory includes a three-dimensional memory.

10. A method for a data storage device including a multilevel memory cell, Determine whether the data is specified for reading at dynamic read resolution, A method comprising: determining that the data is designated for reading at dynamic read resolution, storing the data in the memory using a non-BER (bit error rate) balanced mapping, wherein the memory sense operations required to read one or more pages of the data for low-resolution reading are less when the data is stored using a non-BER balanced mapping than when it is stored using a BER balanced mapping.

11. The further includes performing actions to mitigate the non-equilibrium BER caused by using the non-BER equilibrium mapping, The method according to claim 10.

12. This further includes reading a higher resolution of the data by reading more pages of the data from the memory, The method according to claim 11.

13. The method according to claim 10, wherein the data includes an image.

14. The method according to claim 10, wherein the data includes parameters of a machine learning model.

15. The method according to claim 10, wherein the determination is performed in response to the data being received from the host.

16. The method according to claim 10, wherein the determination is performed in response to the remapping of the data previously stored in the memory using a different mapping.

17. The method according to claim 10, wherein the data is explicitly specified by the host for reading at dynamic read resolution.

18. The method according to claim 10, wherein the data is implicitly specified by the host for reading at dynamic read resolution.

19. The method according to claim 10, wherein the BER equilibrium mapping includes a 4-4-3-4 mapping and the non-BER equilibrium mapping includes a 1-2-4-8 mapping.

20. A data storage device, Memory including multi-level memory cells, Based on whether the aforementioned data is specified for variable readout resolution, select a mapping from multiple mappings. The system includes means for writing the data to the memory using the selected mapping. Data storage device.

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