Component carrier and method for manufacturing a component carrier

Abstract

The present invention provides a component carrier and a method for manufacturing a component carrier. The component carrier (100) comprises a carrier body (102) having holes (104) partially filled with a metallic structure (106) defined by outer dimples (108); conductive dimple filling (110) that at least partially fills the dimples (108); a dielectric layer structure (112) on at least a portion of the carrier body (102) and a portion of the dimple filling (110); and conductive elements (114) extending through the dielectric layer structure (112) and in contact with the dimple filling (110).

Description

Technical Field

[0001] The present invention relates to a component carrier and a method for manufacturing a component carrier.

Background Art

[0002] In the context of increasing the product functionality of component carriers with one or more components, increasing miniaturization of such components, and increasing the number of components connected to a component carrier such as a printed circuit board or a component carrier, powerful array-like components or packages having a plurality of components are increasingly being used, which have a plurality of contacts or connections, and the spacing between these contacts is becoming increasingly smaller. In particular, component carriers must be mechanically robust, electrically reliable, and operable even under severe conditions.

[0003] Conventional techniques for forming component carriers still have problems. D

Summary of the Invention

[0004] The object of the present invention is to form a compact and highly reliable component carrier type package.

[0005] This object is solved by the subject matter according to the independent claims. Further embodiments are described by the dependent claims.

[0006] According to an exemplary embodiment of the present invention, there is provided a component carrier comprising a carrier body having holes partially filled with a metal structure defined by outer dimples, a conductive dimple filling at least partially filling the dimples, a dielectric layer structure over at least a part of the carrier body and a part of the dimple filling, and a conductive element extending through the dielectric layer structure and contacting the dimple filling.

[0007] According to another exemplary embodiment of the present invention, a method for manufacturing a component carrier is provided, the method comprising the steps of: providing a carrier body having holes partially filled with a metallic structure defined by outer dimples; at least partially filling the dimples by conductive dimple filling; forming a dielectric layer structure on at least a portion of the carrier body and a portion of the dimple filling; and forming conductive elements extending through the dielectric layer structure and in contact with the dimple filling.

[0008] In the context of this application, the term “component carrier” may particularly refer to any support structure capable of housing one or more components on and / or within it in order to provide mechanical support and / or electrical and / or thermal connections. In other words, a component carrier may be configured as a mechanical and / or electronic and / or thermal carrier for components. In particular, a component carrier may be one of printed circuit boards, organic or inorganic interposers, and IC (integrated circuit) boards. A component carrier may also be a hybrid board combining different types of the above and / or other types of component carriers.

[0009] In the context of this application, the term “carrier body” may particularly refer to a physical structure (e.g., a plate-type structure) that provides mechanical stability for holding the components of a component carrier. For example, a carrier body may be a base structure that is processed during the manufacturing process of a component carrier to form the components of the component carrier on and within it. A carrier body may comprise a core with options of multiple layers (e.g., signal layers) including an electrically insulating layer and a conductive layer, or a mere mechanical support body without electrical function. A carrier body may comprise inorganic and / or organic materials.

[0010] In the context of this application, the term “hole in carrier body” may particularly refer to an opening in the carrier body. Such holes may be through-holes extending throughout the entire carrier body, blind holes extending into the carrier body but having closed bottoms, or grooves, cavities (e.g., for embedding components), or recesses of any shape. During the execution of a method for filling holes in a carrier body with a conductive material according to an exemplary embodiment, at least 10 holes in the carrier body, and in particular at least 100 holes, may be partially or entirely filled with the conductive material.

[0011] In the context of this application, the term “metallic structure” may particularly refer to a solid metal filling a portion of the pores in a carrier body. Preferably, the metallic structure is a plated metallic structure that can be formed by plating. Plating the pores in the carrier body may include electroless deposition or sputtering, followed by electroplating (particularly galvanic plating). When multiple plating stages are performed, the interfaces between different plated portions of the plated metallic structure can be identified based on a cross-sectional analysis of the plated metallic structure. Towards the outside of the plated pore, the plated metallic structure may be defined by concave recesses, which may be represented as dimples. Dimples may be present, in particular, when the aspect ratio of the pore (i.e., the ratio between the length and minimum diameter of the pore filled with the plated metallic structure) is high, for example, at least 5. However, the metallic structure may also be formed by processes other than plating. For example, the metallic structure may be formed by conductive paste filling, i.e., a metallic paste structure. The metallic structure may also be formed as a plated through-hole that is filled with resin and then capped. Furthermore, it is possible to form the metallic structure by electroplating.

[0012] In the context of this application, the term “outer dimple” may particularly refer to a recess defined by a concave region of the metal structure in a hole in a carrier body, and also defined by a plane corresponding to the main surface of the carrier body. When plating holes in a carrier body with a metal such as copper, the outermost part of the hole may remain unfilled, especially in the case of high aspect ratios. Such an outermost part may be defined by a concave surface of the metal structure. The empty volume of the hole adjacent to the concave surface may be indicated as a dimple.

[0013] In the context of this application, the term “conductive dimple filling” may specifically refer to an additional filling medium that fills at least a portion of the outer dimples. Such a filling step may be, for example, a further plating stage or another metal deposition or plug-in step (such as printing or dispensing). Conductive dimple filling may fill the dimples partially or, preferably entirely. Those skilled in the art will understand that conductive dimple filling can be distinguished from the metallic structure by cross-sectional analysis of the pore filling.

[0014] In the context of this application, the term “dielectric layer structure” may specifically refer to a planar electrical insulating structure. For example, such a layer structure may be a continuous layer, a patterned layer, or a plurality of discontinuous islands in a common plane. It may include organic and / or inorganic materials.

[0015] In the context of this application, the term “conducting element” may particularly refer to a physical structure made of a conductive and / or thermal conductive material and configured to provide electrical and / or thermal connectivity in a component carrier. For example, a conducting element may be a metallic material (e.g., copper) or a non-metallic material (e.g., graphite). In particular, a conducting element may be a solid material such as a solid metallic material. For example, a conducting element may be configured as a metal via (e.g., tapered metal via or metal laser via), a pillar, a bump, etc. A conducting element may have a tapered termination section terminating on a planar front surface. A tapered shape may be advantageous for filling. However, a linear shape of the conducting element is also possible (e.g., when forming a hole by chemical-mechanical drilling). In particular, a conducting element may extend longitudinally to the carrier body. Multiple conducting elements may extend parallel to each other, for example, to different dimple fillings.

[0016] In the context of this application, the term “contact” may particularly refer to direct contact between two connected entities that are in contact with each other without any additional intermediate material in between. Such direct physical contact may also establish a direct physical connection between the connected entities described above. In particular, direct physical contact between the front surface of a conductive element and the planar outer surface of a conductive dimple filling may create a suitable electrical and / or thermal connection between the conductive element and the conductive dimple filling at a longitudinal level corresponding to the main surface of the pore.

[0017] In the context of this application, the term “main surface” of a body may, in particular, refer to one of the two largest opposite surfaces of the body, or the outermost opposite surface of the body. The main surfaces may be connected by circumferential sidewalls. The thickness of a body, such as a carrier body, may be defined by the distance between two opposite main surfaces.

[0018] According to exemplary embodiments of the present invention, a component carrier comprises a carrier body having one or more holes extending therein. Metal structures may be inserted into one or more holes and partially filled, preferably by plating, or alternatively, by paste filling or metal column pinning. The portion of the holes not filled with metal structures may be defined by outer dimples. The dimple volume may then be at least partially filled with conductive dimple filling. Advantageously, a conductive element may be connected to the conductive dimple filling by direct physical contact, thereby establishing a reliable electrical and / or thermal connection (e.g., a reliable copper-copper connection) between the conductive element and the conductive dimple filling. This is because a direct metal-to-metal connection (e.g., copper-to-copper) may be preferable for performing electrical and thermal transfer. The described manufacturing architecture may make it possible to form electrical and / or thermal connections with conductive dimple filling in the holes of the carrier body in a simple and reliable manner. Advantageously, such connections can be produced quickly and easily on an industrial scale with high yield for a wide variety of applications.

[0019] Detailed description of exemplary embodiments Further exemplary embodiments of the component carrier and method are described below.

[0020] In an embodiment, at least one hole is at least one through-hole extending throughout the entire carrier body. By forming one or more through-holes in the carrier body and filling them with metal, it may be possible to bring (e.g., plated) metal into contact at the opposite ends of the holes of the two conductive elements. Thus, a connection between the two sides can also be formed with less effort and higher reliability.

[0021] In embodiments, the carrier body is an inorganic carrier body that includes or is composed of glass, ceramic, or semiconductor, such as silicon. In the context of this application, the term “inorganic carrier body” may particularly refer to a carrier structure that includes an inorganic material. In particular, the dielectric material of the inorganic carrier body, or even the entire inorganic carrier body, may be made exclusively, or at least substantially exclusively, of an inorganic material. In another embodiment, the inorganic carrier body may include an inorganic dielectric material, and additionally, another dielectric material and / or other inorganic material. The inorganic compound may be a compound lacking carbon-hydrogen bonds or a compound that is not an organic compound. For example, the inorganic carrier body may include glass, such as silicon-based glass, particularly soda-lime glass and / or borosilicate glass and / or aluminosilicate glass and / or lithium silicate glass and / or alkali-free glass. In another example, the inorganic carrier body may include ceramic material, such as aluminum nitride and / or aluminum oxide and / or silicon nitride and / or boron nitride and / or tungsten containing ceramic material. However, in another embodiment, the inorganic carrier body may include semiconductor materials, such as silicon and / or germanium and / or silicon oxide and / or germanium oxide and / or silicon carbide and / or gallium nitride. In a further embodiment, the inorganic carrier body may include elemental metals and / or metal alloys, such as copper and / or tin and / or bronze. However, in another embodiment, the inorganic carrier body may include inorganic materials not listed in the above examples, such as MoS2, CuGaO2, AgAlO2, LiGaTe2, AgInSe2, CuFeS2, and BeO.

[0022] Carrier bodies containing or composed of glass are most preferred. Such carrier bodies may contain or consist of silicon dioxide. In particular, glass carrier bodies may have glass as their main component. For example, glass carrier bodies may be in block, strip, or plate form. The main material component of a glass carrier body (especially the material component of a glass carrier body that provides the highest weight percentage) is glass, particularly silicon-based glass. For example, at least 90% by weight of a glass carrier body may be glass. For example, a glass carrier body may consist of glass alone. However, it is also possible for a glass carrier body to contain one or more additional other materials. Advantageously, a glass carrier body may have a very flat surface, and as a result, a planarization stage during processing may not be necessary, and fine line processing on it can be fully supported. Furthermore, a glass carrier body may have a high degree of thermal stability, and as a result, undesirable phenomena caused by heat, such as thermal stress, warping, shrinkage, and delamination, do not significantly affect the component carrier. This allows the entire component carrier to be stabilized, and changes in the dimensions of the component carrier are controllable (e.g., less shrinkage). Furthermore, glass materials can exhibit low DK and low DF behavior with good dielectric properties, and therefore can support low-loss high-frequency (especially radio frequency RF) and high-speed applications, as well as high-performance computing applications with good signal integrity and low loss.

[0023] In the embodiments, the surface roughness Ra of the carrier body is not greater than 100 nm, and especially not greater than 50 nm, particularly when embodied as a glass body. Such a low roughness Ra ensures that the wiring structure can be formed on this surface of the glass carrier body with the highest spatial accuracy. Therefore, the embodiments described may be particularly suitable for high-density integration (HDI) applications and / or fine line patterning.

[0024] In embodiments, the carrier body is an organic carrier body comprising or consisting of a resin in particular. In the context of this application, the term “organic carrier body” may particularly refer to a block, strip, or plate-shaped structure comprising a dielectric material having an organic compound. In particular, the dielectric material of the organic carrier body may consist exclusively, or at least substantially exclusively, of an organic material. In another embodiment, the organic carrier body may comprise an organic dielectric material and / or additionally another dielectric material. The organic compound may be a compound containing carbon-hydrogen bonds. For example, the organic carrier body may include an organic resin material, an epoxy material, and the like. For example, the organic carrier body may be an organic integrated circuit (IC) substrate or a printed circuit board (PCB). In particular, an integrated circuit substrate dielectric may be a dielectric used in an organic integrated circuit substrate.

[0025] For example, the thickness of the dielectric layer structure can range from 5 μm to 20 μm, for instance, 10 μm. Such a small thickness can allow fine line patterns on the dielectric layer structure to benefit from the high smoothness of the carrier body directly beneath the thin dielectric layer structure.

[0026] In the embodiment, at least two conductive elements are provided, each extending in direct physical contact from one of the two opposite ends of at least one hole extending throughout the entire carrier body to the dimple filling. Thus, each of the two opposite ends, and the exposed end portion of the dimple filling adjacent to the main surface on the opposite side of, for example, a plate-shaped carrier body, can be thermally and / or electrically contacted by the respective conductive elements abutting upon (preferably without protruding into) them. Thus, a symmetrical contact structure can be formed on both sides of the carrier body, which can limit warping.

[0027] In one embodiment, a photoimaging dielectric (PID) may be used to form a pattern. Next, copper pillars or bumps may be formed to connect the carrier body to the dimple filling of through-glass vias (TGVs) or other holes.

[0028] In an embodiment, the dielectric layer structure is configured as a stress relief layer. In the context of the present application, the term "stress relief layer" particularly refers to a structure configured to relieve stress from an interface between a carrier body (particularly a glass plate) and a further build-up (such as an organic laminate) or an electronic component, or stress generated from the formation of through holes (such as TGVs) in the carrier body. Such stress can occur when connecting components with very different coefficients of thermal expansion (CTEs) during production under low temperature and / or high temperature conditions. Without wishing to be bound by a particular theory, the stress generation process is currently thought to act as follows: Cracks can propagate under tensile stress. Resin can bring about compressive stress at cracks on glass. The CTE of glass can be very low (such as about 3 ppm / K), and the Young's modulus of glass is very high. In contrast, the CTE of copper can be about 17 ppm / K. The CTE of resin can be higher or lower than that of copper. The Young's modulus of resin can be relatively low. By adopting a copper interface, when copper traces (thin and narrow) are directly on glass, the stress on the traces at the interface should be high. When a pattern on the dielectric layer is directly bonded to glass, the gap between glass and copper is larger. In particular, by adjusting material properties such as the CTE value and / or Young's modulus value of the stress relief layer, the stress can be reduced or even eliminated. Such a sudden change in material properties at the above interface can cause mechanical and / or thermal stress that can lead to undesirable phenomena such as warping, peeling, cracking, and separation between different components. The stress-reducing dielectric interface can at least reduce the applied stress. For example, the dielectric layer structure configured as a stress relief layer can be a resin layer or a polymer layer.

[0029] In an embodiment, the depth of the dimples is in the range of 1 μm to 20 μm, particularly in the range of 3 μm to 10 μm. These depths of the dimples may be relatively small, but filling them by dimple filling can significantly improve the accuracy of establishing contact by the conductive elements. Generally, during dimple filling, controlling the depth with a specified accuracy can be achieved by plating, for example, together with a specific chemical composition (which may include one or more additives), the flow of chemicals in the tank, plating current control, rocking or vibration, etc.

[0030] In an embodiment, the holes have a ratio between the length and the minimum diameter of at least 2, particularly at least 5, more particularly at least 7. In particular, in the presence of holes with such a large aspect ratio, it can be a conventional problem to fill such holes completely enough with a conductive material. However, exemplary embodiments of the present invention can utilize the dimples generated by hole filling and combine it with a metal structure. Thereby, the labor and cost of manufacturing can be reduced, while ensuring a very reliable electrical and / or thermal connection. This can be achieved with a metal-to-metal (e.g., copper-to-copper) interconnect.

[0031] In an embodiment, the holes have an hourglass shape. Alternatively, the holes may have a continuous taper shape.

[0032] In this context, the hourglass shape can be formed by through-holes having two connected tapered sections with opposite taper directions (compared to FIG. 12). Such an hourglass shape can be obtained by forming each hole by laser drilling from the main surfaces on both opposite sides of the carrier body.

[0033] In an alternative embodiment, each hole may have a frustum shape (compared to FIG. 11). Such a continuous taper shape can be created by laser drilling from only one main surface of the carrier body. Next, the hole can be tapered towards the side of the carrier body facing away from the laser light source.

[0034] In general, laser-induced selective etching may be advantageous for through-glass via (TGV) drilling. Therefore, glass structures can be modified by laser treatment. Wet etching can also be performed. Other possible methods include laser treatment alone, electrical discharge machining (EDM) with auxiliary electrodes, reactive ion etching, powder blasting, mechanical drilling, and spark-assisted chemical engraving.

[0035] In embodiments, the component carrier includes a metal layer directly patterned on the carrier body. The patterned metal layer may be positioned between the metal structure and the dielectric layer structure, and / or between the carrier body and the dielectric layer structure. For example, the component carrier may include a metal layer directly patterned on the carrier body beneath the dielectric layer structure. Correspondingly, the method may comprise the step of forming a metal layer directly patterned on the carrier body. Advantageously, such a patterned metal layer sandwiched between the carrier body and the dielectric layer structure can improve adhesion between the extremely smooth glass carrier body surface and the dielectric layer structure. This can significantly improve the mechanical reliability of the component carrier. Preferably, the dielectric layer structure may be formed partially on the patterned metal layer and partially on the carrier body in the gaps between different sections of the patterned metal layer. This can improve engagement between the dielectric layer structure and the patterned metal layer and ensure direct contact of the dielectric layer structure with the carrier body, thereby resulting in a strong buffering effect of the dielectric layer structure on the carrier body.

[0036] In other embodiments, the patterned metal layer may be unnecessary and can be omitted, particularly since it may not be necessary to have electrical connections for this layer.

[0037] In embodiments, the patterned metal layer is configured as an adhesive interface layer to facilitate adhesion between the carrier body and the dielectric layer structure. For example, the patterned metal layer may be present for the purpose of facilitating adhesion between these metal (e.g., copper) layers. The dielectric layer structure, as a carrier body (e.g., glass) and a patterned metal layer, can provide fixed points. This can also generally allow for better handling of the core (preferably glass). Handling inorganic materials (such as glass) is always a challenge.

[0038] In one embodiment, the patterned metal layer includes transversely narrow sections and transversely wide sections, the transversely narrow sections being closer to the dimples than the transversely wide sections (see, for example, Figure 5). The transversely narrow sections may also be closer to the axis of the metallized hole or via than the transversely wide sections (depending on the via shape).

[0039] In the embodiment, the laterally narrow section is in direct physical contact with the dimple filling. Such a configuration has been found to be particularly effective from the viewpoint of promoting adhesion. In such a configuration, the particularly efficient fixing effect is thought to enhance the adhesion between the dielectric layer structure and the carrier body mediated by the patterned metal layer.

[0040] In embodiments, the component carrier includes a wiring structure to provide electrical wiring functionality, where the patterned metal layer is electrically isolated from the wiring structure. Therefore, the patterned metal layer can be electrically inactive, i.e., an electrical dummy structure, and can function solely as an adhesion-promoting layer to improve the handling of the carrier body. It can also provide a heat dissipation function. In contrast, the wiring structure can provide electrical functionality in terms of the functionality of the component carrier. For example, the wiring structure can be configured to transmit electrical signals and / or power. For example, the wiring structure may include horizontal electrical structures (traces, pads, etc.) and / or vertical electrical structures (vias, pillars, etc.). In embodiments, the wiring structure may have a line spacing ratio in the range of 2 μm / 2 μm to 10 μm / 10 μm, particularly 5 μm / 5 μm. Thus, fine line patterning with very small dimensions is possible on the carrier body. This is especially possible when the carrier body is made of glass, due to the extreme smoothness of such a glass body.

[0041] In embodiments, the component carrier comprises a wiring structure connected to a conductive element (which may be a wiring structure having the characteristics described in the preceding paragraph) for providing an electrical wiring function. For example, the electrical wiring function may be for creating a conductive connection between an electronic component (which may be surface-mounted on the component carrier) and a mounting base (on which the component carrier is mounted) via a metallic structure, with at least one conductive element in at least one hole, dimple filling, and

[0042] In embodiments, the component carrier comprises a wiring structure (which may have the characteristics described in the preceding paragraphs) for providing electrical wiring functionality, wherein the patterned metal layer has a higher roughness than the wiring structure. The higher roughness of the patterned metal layer compared to the wiring structure may be the result of a roughening process that selectively roughens the surface of the patterned metal layer to improve adhesion with the dielectric layer structure. In contrast, a smooth surface of the wiring structure may be desirable for conducting electrical signals and / or power with low loss. In particular, with respect to high-frequency signals, the skin effect may result in electrical high-frequency signals propagating only in thin skin or surface portions of the wiring structure. High signal quality can be achieved when such surface portions do not have significant ripple due to their high smoothness.

[0043] In embodiments, a patterned metal layer is configured to shield components embedded in a carrier body (see, for example, Figure 16). The patterned metal layer can function as shielding for embedded components (such as capacitors, inductors, or radio frequency semiconductor chips) embedded in the glass core or elsewhere within the component carrier. For example, in radio frequency applications, embedded components (such as RF chips) may be sensitive to electromagnetic radiation (particularly RF radiation) from the environment. At the same time, such embedded components may be electromagnetic radiation emitters that emit electromagnetic radiation that can interfere with the function of other components or electronic materials. The electrical reliability of the component carrier can be further improved by configuring a patterned metal layer that contributes to shielding electromagnetic radiation from propagation between the embedded component and the outside of the component carrier. For example, the patterned metal layer may form a conductive cage around or as part of the embedded electronic component to shield electromagnetic radiation. When the patterned metal layer is configured for shielding, it may be made of, for example, a metal or a magnetic material.

[0044] In embodiments, at least a portion of the patterned metal layer has a ring shape. In particular, the narrower section described above may be annular or ring-shaped. The patterned metal layer may also have other shapes, such as a hexagonal shape. If there is no ring structure, the design may be as shown in Figure 13 or Figure 14, for example.

[0045] In embodiments, the carrier body has a thickness in the range of 300 μm to 1000 μm, particularly in the range of 500 μm to 800 μm. A carrier body having such a large thickness may be able to provide sufficient robustness and rigidity to effectively suppress warping, especially when made of glass.

[0046] In embodiments, the component carrier comprises electronic components mounted on or above the carrier body and electrically coupled to at least one conductive element. One or more electronic components may be surface-mounted. In the context of this application, the term “electronic component” may particularly refer to a member that performs an electronic task. Such electronic components may be active components, such as semiconductor chips, which include a semiconductor material as a primary or base material. Electronic components may also be passive components, such as capacitors or inductors. Preferably, the electronic component includes a semiconductor chip. The semiconductor chip may be based on a type IV semiconductor, such as silicon or germanium, or a type III to V semiconductor material, such as gallium arsenide. In particular, the semiconductor component may be a semiconductor chip such as a bare die or a molded die. A bare die may be an unencapsulated (particularly unmolded) component of a semiconductor material (such as silicon) having at least one monolithic integrated circuit element (such as a diode or transistor). Furthermore, semiconductor materials suitable for photonic packages are also possible. For example, an electronic component surface-mounted on a package may be HBM (high-bandwidth memory) or a silicon interposer.

[0047] In the embodiment, at least one conduction element has a frustoconical shape. Thus, the conduction element may be tapered toward the carrier body. When a laser is used in conjunction with subsequent plating to form the conduction element as a metal via (more precisely, a metal laser via), the shape obtained may correspond to that of a laser via. The laser via may have a shape in which the bottom is much smaller than the top.

[0048] In another embodiment, at least one conducting element has a cylindrical shape. When using an excimer laser, the taper of the via can be much smaller, or even zero. When using exposure, the structure can be more linear, for example, nearly or exactly linear.

[0049] In embodiments, the component carrier comprises a plurality of conductive elements arranged side by side (see, for example, Figure 1). Each of the conductive elements may be constructed as described above. Different conductive elements may be constructed in correspondence, for example, all as metal vias that extend to but not into their respective dimple fillings. The side by side conductive elements can be manufactured by a common manufacturing process and therefore very efficiently. Conductive elements extending to multiple identical (preferably glass) carrier bodies may even enable the component carrier to perform complex electronic tasks.

[0050] In embodiments, the method comprises the steps of forming conductive elements by laser drilling recesses to dimple filling, and then filling the laser-drilled recesses with a metallic material, particularly by plating. Such plating steps may include, for example, electroless plating, sputtering, galvanic plating, and the like.

[0051] In embodiments, the method comprises a step of roughening the patterned metal layer before forming a dielectric layer structure thereon. For example, such a roughening step may be carried out by etching, polishing, or chemical treatment. A further roughened surface of the patterned metal layer may additionally enhance the adhesion of the dielectric layer structure to the exposed surface of the patterned metal layer. Figures 12 to 15 show corresponding embodiments.

[0052] In embodiments, the package comprises a mounting base, particularly a printed circuit board (PCB), on which a component carrier is mounted. Such a mounting base can mechanically and electrically connect the component carrier and its surface-mounted components to peripheral electronic devices.

[0053] In one embodiment, the component carrier comprises a stack of at least one electrically insulating layer structure and at least one conductive layer structure. For example, the component carrier may be a stack of the above-mentioned electrically insulating layer structure and conductive layer structure formed by applying mechanical pressure and / or thermal energy. The above-mentioned stack can provide a large mounting surface for further components and nevertheless provide a plate-like component carrier that is very thin and compact.

[0054] In some embodiments, the component carrier is plate-shaped. This contributes to a compact design, and nevertheless, the component carrier provides a large substrate on which components are mounted. In particular, naked dies, as an example for electronic components, can be surface-mounted on a thin plate such as a printed circuit board.

[0055] In one embodiment, the component carrier is configured as one of a group consisting of a printed circuit board, a substrate (particularly an IC substrate), and an interposer.

[0056] In the context of this application, the term “printed circuit board” (PCB) may mean, in particular, a plate-like component carrier formed by laminating several conductive layer structures with several electrically insulating layer structures, for example, by applying pressure and / or supplying thermal energy. Preferred materials for PCB technology include conductive layer structures made of copper, while the electrically insulating layer structures may have resin and / or glass fiber, so-called prepreg or FR4 material. The various conductive layer structures may be connected to one another in a desired manner by forming holes through the lamination, for example by laser drilling or mechanical drilling, and by partially or completely filling them with conductive material (particularly copper), thereby forming vias or other arbitrary through-hole connections. The filled holes may connect the entire stack (through-hole connections extending through multiple layers or the entire stack), or the filled holes may connect at least two conductive layers, called vias. Similarly, optical interconnections may be formed through individual layers of the stack to receive an electro-optical circuit board (EOCB). Printed circuit boards (PCBs) are typically configured to house one or more components on opposite surfaces of a plate-shaped PCB. These components can be connected to their respective main surfaces by soldering. The dielectric portion of the PCB may be made of a resin with reinforcing fibers (such as glass fiber).

[0057] In the context of this application, the term “substrate” may, in particular, mean a small component carrier. A substrate can be a relatively small component carrier that can mount one or more components on a PCB and act as a connecting medium between one or more chips and further PCBs. For example, a substrate may be substantially the same size as the components (particularly electronic components) mounted on it (e.g., in the case of a chip-scale package (CSP)). More specifically, a substrate can be understood as a carrier for electrical connections or electrical networks, and a component carrier equivalent to a printed circuit board (PCB), but with a very high density of connections arranged transversely and / or longitudinally. Transverse connections may be, for example, conduction paths, while longitudinal connections may be, for example, drill holes. These transverse and / or longitudinal connections can be located within the substrate and can be used to provide electrical, thermal, and / or mechanical connections, in particular, between housed or unhoused components (such as bare dies) of an IC chip and a printed circuit board or intermediate printed circuit board. Thus, the term “substrate” also includes “IC substrate.” The dielectric portion of the substrate may be made of a resin containing reinforcing particles (reinforcing spheres, especially glass spheres).

[0058] The substrate or interposer may have, or may consist of, a layer of at least glass, silicon (Si), and / or an epoxy-based build-up material (such as an epoxy-based build-up film) or a polymer compound (which may or may not contain photomolecules and / or thermosensitive molecules) such as polyimide or polybenzoxazole.

[0059] In embodiments, at least one electrically insulating layer structure comprises at least one of the group consisting of resins or polymers such as epoxy resins, cyanate ester resins, benzocyclobutene resins, melamine derivatives, polybenzoxabenzoyl (PBO), bismaleimide triazine resins, polyphenylene derivatives (e.g., polyphenylene ether, PPE-based), polyimide (PI), polyamide (PA), liquid crystalline polymer (LCP), polytetrafluoroethylene (PTFE), bisbenzocyclobutene (BCB), and / or combinations thereof. Reinforcing structures such as webs, fibers, spheres, or other types of filler particles, made of glass (multilayer glass), for example, can also be used to form composite materials. Semi-cured resins impregnated with the above-mentioned resins and combined with reinforcing agents, such as fibers, are called prepregs. These prepregs are often named after properties that describe their flame retardant properties, such as FR4 or FR5. Typically, prepregs, particularly FR4, are preferred for rigid PCBs, but other materials, especially epoxy build-up materials (such as build-up films) or photoimaging dielectric materials, may also be used. For high-frequency applications, high-frequency materials such as polytetrafluoroethylene, liquid crystalline polymers, and / or cyanate ester resins may be preferred. In addition to these polymers, low-temperature co-fired ceramics (LTCC) or other low, ultra-low, or extremely low DK materials may be applied within the component carrier as an electrically insulating structure.

[0060] In embodiments, at least one conductive layer structure comprises at least one of the group consisting of copper, aluminum, nickel, silver, gold, palladium, tungsten, titanium, and magnesium. Copper is usually preferred, but other materials or coated versions thereof are also possible, particularly those coated with superconducting materials or conductive polymers, such as graphene or poly(3,4-ethylenedioxythiophene) (PEDOT), respectively.

[0061] At least one component may be selected from a group consisting of a non-conductive inlay, a conductive inlay (such as a metal inlay, preferably including copper or aluminum), a heat transfer unit (e.g., a heat pipe), an optical guide element (e.g., an optical waveguide or optical conduction connection), an electronic component, or a combination thereof. The inlay may be, for example, a metal block with or without an insulating material coating (IMS inlay) that can be surface-mounted for the purpose of promoting heat dissipation. Suitable materials are defined according to their thermal conductivity, which should be at least 2 W / mK. Such materials are often based on, but are not limited to, metals, metal oxides and / or ceramics, such as copper, aluminum oxide (Al2O3), or aluminum nitride (AlN). Other shapes with increased surface area are also frequently used to increase heat exchange capacity.Furthermore, the components include active electronic components (having at least one pn junction mounting), passive electronic components such as resistors, inductors or capacitors, electronic chips, storage devices (e.g., DRAM or other data memory), filters, integrated circuits (such as field-programmable gate arrays (FPGAs), programmable array logic (PALs), generic array logic (GALs), and complex-programmable logic devices (CPLDs)), signal processing components, power management components (field-effect transistors (FETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, junction field-effect transistors (JFETs), or insulated-gate field-effect transistors). These can include transistors (IGFETs), all based on semiconductor materials such as silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), gallium oxide (Ga2O3), indium gallium arsenide (InGaAs), and / or any other suitable inorganic compound; optoelectronic interface elements; light-emitting diodes; photocouplers; voltage converters (e.g., DC / DC converters or AC / DC converters); encryption components; transmitters and / or receivers; electromechanical transducers; sensors; actuators; micro-electromechanical systems (MEMS); microprocessors; capacitors; resistors; inductances; batteries; switches; cameras; antennas; logic chips; and energy harvesting units. However, other components can be surface-mounted on component carriers. For example, they can be used as magnetic element components. Such magnetic elements may be permanent magnetic elements (ferromagnetic elements, antiferromagnetic elements, multiferroic elements, or ferrimagnetic elements, e.g., ferrite cores) or paramagnetic elements. However, the component may be an IC substrate, an interposer, or a further component carrier, for example, in a board-in-board configuration. The component may be surface-mounted on the component carrier.Furthermore, other components, particularly those that generate and emit electromagnetic radiation and / or are sensitive to electromagnetic radiation propagating from the environment, may also be used as components.

[0062] In the embodiment, the component carrier is a stacked component carrier. In such embodiment, the component carrier is a multilayer compound that is stacked and connected together by applying pressure and / or heat.

[0063] After processing the internal layer structure of the component carrier, the main surfaces on one or both sides of the processed layer structure can be covered symmetrically or asymmetrically (particularly by lamination) with one or more further electrically insulating and / or conductive layer structures. In other words, the build-up can be continued until the desired number of layers is obtained.

[0064] After the formation of the stacks of the electrical insulating layer structure and the conductive layer structure is complete, it is possible to proceed with surface treatment of the resulting layer structure or component carrier.

[0065] In particular, an electrically insulating solder resist may be applied to the main surface opposite one or both of the layer stacks or component carriers, from a surface treatment standpoint. For example, by forming such a solder resist over the entire main surface and then patterning the layer of solder resist, one or more conductive surface portions used to electrically couple the component carriers to peripheral electronic equipment can be exposed. Surface portions of the component carriers that remain covered with solder resist, especially copper-containing surface portions, can be efficiently protected from oxidation or corrosion.

[0066] Regarding surface treatment, it is also possible to selectively apply a surface finish to the exposed conductive surface portion of the component carrier. Such a surface finish may be a conductive cover material on exposed conductive layer structures (such as pads, conductive tracks, etc., particularly containing or composed of copper) on the surface of the component carrier. If such exposed conductive layer structures are left unprotected, the exposed conductive component carrier material (particularly copper) may oxidize, potentially reducing the reliability of the component carrier. The surface finish can then be formed, for example, as an interface between the surface-mounted component and the component carrier. The surface finish serves to protect the exposed conductive layer structures (particularly copper circuits) and to enable bonding processes with one or more components, for example, by soldering. Examples of materials suitable for surface finishing include organic solderability protectants (OSPs), electroless nickel-substituted gold plating (ENIG), electroless nickel-substituted palladium-substituted gold plating (ENIPIG), gold (particularly hard gold), chemical tin, nickel gold, and nickel palladium.

[0067] The embodiments defined above and further embodiments of the present invention will become apparent from the examples of embodiments described below, and will be described with reference to these examples of embodiments. [Brief explanation of the drawing]

[0068] [Figure 1] A cross-sectional view of a component carrier according to an exemplary embodiment of the present invention is shown.

[0069] [Figure 2] Figure 5 shows a cross-sectional view of a structure obtained while performing a method for manufacturing the component carrier shown in Figure 5, according to another exemplary embodiment of the present invention. [Figure 3] Figure 5 shows a cross-sectional view of a structure obtained while performing a method for manufacturing the component carrier shown in Figure 5, according to another exemplary embodiment of the present invention. [Figure 4]Figure 5 shows a cross-sectional view of a structure obtained while performing a method for manufacturing the component carrier shown in Figure 5, according to another exemplary embodiment of the present invention. [Figure 5] Figure 5 shows a cross-sectional view of a structure obtained while performing a method for manufacturing the component carrier shown in Figure 5, according to another exemplary embodiment of the present invention.

[0070] [Figure 6] Figure 11 shows a plan view of a structure obtained while performing a method for manufacturing a component carrier according to another exemplary embodiment of the present invention. [Figure 7] Figure 11 shows a plan view of a structure obtained while performing a method for manufacturing a component carrier according to another exemplary embodiment of the present invention. [Figure 8] Figure 11 shows a plan view of a structure obtained while performing a method for manufacturing a component carrier according to another exemplary embodiment of the present invention. [Figure 9] Figure 11 shows a plan view of a structure obtained while performing a method for manufacturing a component carrier according to another exemplary embodiment of the present invention. [Figure 10] Figure 11 shows a plan view of a structure obtained while performing a method for manufacturing a component carrier according to another exemplary embodiment of the present invention. [Figure 11] Figure 11 shows a plan view of a structure obtained while performing a method for manufacturing a component carrier according to another exemplary embodiment of the present invention.

[0071] [Figure 12] A cross-sectional view of a component carrier according to a different exemplary embodiment of the present invention is shown. [Figure 13] A cross-sectional view of a component carrier according to a different exemplary embodiment of the present invention is shown. [Figure 14] A cross-sectional view of a component carrier according to a different exemplary embodiment of the present invention is shown. [Figure 15]A cross-sectional view of a component carrier according to a different exemplary embodiment of the present invention is shown.

[0072] [Figure 16] A cross-sectional view of a component carrier according to an exemplary embodiment of the present invention is shown. [Modes for carrying out the invention]

[0073] The diagrams within the drawings are schematic. Similar or identical elements are given the same reference numerals in different drawings.

[0074] Before exemplary embodiments are described in further detail with reference to the drawings, some basic considerations are summarized based on which exemplary embodiments of the present invention were developed.

[0075] Adhesion can be a challenge when forming packages on glass. For example, silane treatment of the glass before polymer coating or lamination has been considered. Another conventional challenge is the formation of through-glass vias (TGVs). Metal filling can be conventionally difficult, especially at high aspect ratios of TGVs or larger vias. Problems such as difficulty in filling, remaining voids, thickness variations, underfill overload, delamination, and cracking may occur.

[0076] According to embodiments of the present invention, a component carrier for mounting at least one electronic component on and / or in is formed based on a carrier body (preferably a glass carrier body) having one or more holes partially filled with a metallic structure (e.g., plated copper). Outer dimples defining the metallic structure are partially or entirely filled with conductive dimple fillers (e.g., further copper material). A dielectric layer structure is applied on at least a portion of the carrier body and a portion of the dimple fillers. Such a dielectric layer structure may be formed directly on the carrier body to buffer stress. Furthermore, conductive elements may be formed to extend through the dielectric layer structure to the dimple fillers, resulting in direct physical contact. As a result, the conductive elements may be in direct contact with the dimple fillers. In a simple manner, this makes it possible to establish direct physical contact between the conductive elements and the dimple fillers. Thus, improved reliability of the electrical and / or thermal coupling between them can be achieved. Such connections are reliable even when the filling of the holes by the metallic structure is incomplete, for example, in the case of high aspect ratios.

[0077] More specifically, exemplary embodiments of the present invention can preferably improve the handling of the glass carrier body and streamline the manufacturing process. Preferably, a patterned metal layer can be formed directly on the carrier body (such as further plated copper on the glass) and can efficiently function as an adhesion promoter for the dielectric layer structure. Such an adhesion-promoting effect has been found to be achievable even on extremely smooth glass surfaces with a roughness Ra of less than 50 nm, for example. To create reliable interconnections through high aspect ratio TGVs, the peripheral area of ​​the dimpled TGV can be etched to isolate the TGV interconnections. A copper layer pattern can be formed on the polymer layer on the glass. The TGV can then be interconnected to the upper pad by metallized laser vias. In particular, a pattern on the glass can be formed after the TGV filling has been formed in a SAP (semi-additive processing) step.

[0078] The formation of through-glass vias (TGVs) or other holes in a glass carrier or another carrier body can preferably be achieved by laser drilling and etching. Next, an electroless copper plating process may be performed to form a metal film on the surface. Subsequently, electrolytic copper plating may be performed to complete the formation of the metal structure. Then, a dry film may be laminated on the acquired structure. Dry film openings may be created, then a patterned metal layer is formed, followed by lithography, electrolytic copper plating, and etching processes. There may be an additional step to roughen the surface of the patterned metal layer to promote adhesion between the dielectric layer and the glass to be attached later. The dielectric layer may be attached, for example, by lamination of resin sheets. It may also be a photoimaging dielectric material. It may also be possible to form a pattern including vias and traces simultaneously by exposure or an excimer laser, followed by electrolytic plating or other metal deposition processes. An excimer laser can do this even for ordinary dielectric materials. Laser vias extending through the dielectric layer may be formed. By a semi-additive process (SAP), laser vias can be filled with metal, thereby forming conductive elements.

[0079] Descriptively speaking, the resin sheet can function as a stress-relieving layer between the glass material of the carrier body and the copper pattern on top. Furthermore, the copper structure can function as an adhesive interface layer between the glass and dielectric layers such as polymer.

[0080] In embodiments, vias may be formed on copper-filled TGVs and connected to patterns on and / or within the polymer dielectric layer. To maintain the insulation of the vias, the copper around and / or on the TGVs may be etched. The shaped copper surface may act as an adhesion promoter between the carrier and dielectric layers, which may be embodied as a glass core. Advantageously, copper-plated glass with a resin sheet in between can act as a stress buffer for traces on and / or within the dielectric, contributing to easier handling of the glass panel. This is because the resin sheet can balance the CTE gap between the glass and copper (especially the traces) and help regulate stress on the traces. Briefly, the plated copper can act as a mechanical buffer and an adhesion promoter layer, as it can provide fixed points between the dielectric layer and the glass. Additionally, it can provide handling points for traces or patterned metal layers (such as copper) and glass, and traces or patterned metal layers (copper) and resin. This may enable proper interconnection between high aspect ratio TGVs and adjacent layers. In particular, the component carrier according to the exemplary embodiment of the present invention may enable easier handling of the panel. The risk of glass breakage due to stress during processing can be reduced. Furthermore, it may be unnecessary to provide a separate adhesion promoter (such as a silane coupling agent that can be used to alter the chemical structure of the glass surface). Moreover, the manufacturing architecture of the exemplary embodiment of the present invention is suitable for glass substrate structures having through-glass vias with a high aspect ratio. Advantageously, a copper dummy layer can be provided that improves glass protection and can function as an adhesive layer, supporting via shapes interconnected with the TGV.

[0081] Exemplary uses of exemplary embodiments of the present invention relate to mobile phones, servers, and computing applications, particularly component carriers for high-performance computing (HPC) and related electronic devices.

[0082] Exemplary embodiments of the present invention may enable overcoming conventional drawbacks of dielectric bonding on a glass body. This can be achieved by a patterned metal layer configured as an adhesive interface layer to facilitate bonding between the glass carrier body and the dielectric layer structure.

[0083] Another conventional drawback is the requirement for long plating times when filling through-glass vias with metallic materials, resulting in incomplete metal filling or large aspect ratios (i.e., the ratio between the panel length or thickness and the minimum diameter). According to exemplary embodiments, an efficient TGV metal filling process, particularly for high aspect ratios (e.g., at least 7 or at least 8), can be provided by a combination of partial filling of the holes with plated metal, followed by at least partial filling of the remaining dimples, and finally, insertion of conductive elements into the dimple filling. As a result, a glass carrier body with TGV-filled copper can be provided, which can also be manufactured in a reliable manner, for example, for high aspect ratios of at least 7. Advantageously, this can be achieved by a patterned copper adhesive layer that can be partially placed on the glass. A dielectric layer, such as a resin layer, can function as a stress-relieving layer that can be partially placed on the glass. Furthermore, the upper copper vias can function as conductive elements for contacting the metal TGV filling.

[0084] For example, conductive elements (particularly metal vias) may be formed in contact with metallized holes (such as metal-filled through-glass vias) in a carrier body (preferably embodied as a glass plate). The conductive elements may be connected to a metal pattern on a dielectric layer (such as a polymer layer). To maintain the insulation of each via, the metal pattern (particularly copper) around each hole may be etched. Advantageously, the shaped metal surface may act as an adhesion promoter between the glass core and the dielectric layer. Furthermore, the dielectric layer bonded to the metal-plated glass may function as a stress buffer, simplifying the handling of the glass panel.

[0085] To streamline the manufacturing process and improve glass handling, plated copper on the glass can be used as an adhesion promoter. To create interconnections with high aspect ratio TGVs, the peripheral area of ​​the template TGV can be etched to isolate the TGV interconnections. This allows a pattern to be formed on the polymer layer formed on the glass / copper layer. The TGVs can then be interconnected to the upper pads via laser vias.

[0086] Figure 1 shows a cross-sectional view of a component carrier 100 according to an exemplary embodiment of the present invention.

[0087] The component carrier 100 shown includes a central carrier body 102 having a plurality of longitudinally extending through-holes 104 that extend throughout the entire carrier body 102. The carrier body 102 may be embodied as a glass plate. The through-holes 104 that extend longitudinally through the carrier body 102 may therefore be through-glass vias (TGVs). They may be formed in the carrier body 102 by laser drilling from the main surface opposite the carrier body 102. As a result, the through-holes 104 have an hourglass shape composed of two connected tapered sections with opposite tapering directions.

[0088] Referring again to Figure 1, each hole 104 is partially filled with a plated metal structure 106 defined by the outer dimples 108 on both sides. Each plated metal structure 106 has a concave surface adjacent to each dimple 108. For example, the plated metal structure 106 may include solid copper formed by electroless plating, or by chemical or physical vapor deposition (for forming a thin seed layer), followed by electroplating (for creating a thick bulk copper on top of it). As shown, conductive dimple fillers 110 (for example, also made of copper) fill each dimple 108 and can be created, for example, by a further plating process. The dimple fillers 110 may extend to each of the main surfaces on the opposite side of the carrier body 102. Thus, each dimple filler 110 extends to the same longitudinal level as the carrier body 102 on both the lower and upper sides.

[0089] Furthermore, each conductive element 114 may extend through dielectric layer structures 112 formed on each main surface of the carrier body 102. Each dielectric layer structure 112 may cover a portion of the surface of the carrier body 102 and a portion of the dimple filling 110. Each conductive element 114 may be, for example, a copper-filled laser via. Each conductive element 114 may be in direct contact with its assigned dimple filling 110. For example, the flange or front surface of each conductive element 114 may abut the outer horizontal surface of its respective dimple filling 110. Thus, it may be possible for the conductive element 114 not to extend into the dimple filling 110 with which it contacts. More specifically, for each through-hole 104, two opposite conductive elements 114 may be provided, each extending into its assigned dimple filling 110 with direct physical contact. More specifically, each hole 104 has a dimple filling 110 as an upper end section connected by an upper conducting element 114, and a further dimple filling 110 as an opposite lower end section connected by a lower conducting element 114. The taper directions of the upper and lower conducting elements 114 may be opposite to each other, and as a result, both may be tapered toward the carrier body 102. In the shown embodiment, the conducting element 114 is made of solid copper and is therefore conductive and thermally conductive. In the embodiment of Figure 1, each conducting element 114 is embodied as a tapered metal via having a frustoconical shape and tapering toward the carrier body 102. Such tapered vias may be formed by laser drilling followed by copper plating.

[0090] As shown in Figure 1, the upper dielectric layer structure 112 is positioned directly on the main surface above the carrier body 102. The dielectric layer structure 112 may be, for example, a resin layer, a prepreg layer, or a layer made of a photoimaging dielectric. As shown, all upper conductive elements 114 extend collectively through the upper dielectric layer structure 112 to their respective conductive dimple fillings 110.

[0091] Correspondingly, the lower dielectric layer structure 112 is directly positioned on the lower main surface of the carrier body 102. The lower dielectric layer structure 112 may be thicker than the upper dielectric layer structure 112. The lower dielectric layer structure 112 may be, for example, a layer made of a resin layer, a prepreg layer, or a photoimaging dielectric. As shown, all lower conductive elements 114 extend through the lower dielectric layer structure 112 as a whole to their respective conductive dimple fillings 110.

[0092] As shown, the redistribution structure 154 is formed on the upper dielectric layer structure 112 and on the upper main surface of the carrier body 102 as part of a build-up 156. The redistribution structure is not formed below the lower dielectric layer structure 112 and below the lower main surface of the carrier body 102 as part of a further build-up 158. The upper dielectric layer structure 112 may form part of the redistribution structure 154.

[0093] The wiring structures 118 can be formed on and on the exposed surfaces of each dielectric layer structure 112, 112. As shown, at least some of the wiring structures 118 can form part of a laminated layer stack that additionally includes one or more electrical insulating layer structures 170. The latter may include, for example, an organic laminate, a resin, or optionally reinforced particles such as glass fibers. For example, the electrical insulating layer structure 170 may be a resin sheet, a prepreg sheet, etc.

[0094] For example, a metal layer may be formed (e.g., by plating, particularly copper plating) or attached (e.g., as a metal foil, particularly copper foil) to the outside of each dielectric layer structure 112, 112. The metal layer may then be patterned by, for example, lithography and etching processes to obtain the wiring structure 118 shown in Figure 1. As already mentioned, the component carrier 100 includes a plurality of conductive elements 114 arranged laterally and facing each other longitudinally. Each of these conductive elements 114 may be coupled to the respective wiring structure 118.

[0095] Referring further to Figure 1, the dimensions of the wiring structure 118 on the outer surface of the lower dielectric layer structure 112 may be coarser than those on the outer surface of the upper dielectric layer structure 112. In other words, the integration density, i.e., the number of conductive elements of the wiring structure 118 per unit area or volume, may be greater on the upper dielectric layer structure 112 than on the lower dielectric layer structure 112.

[0096] As shown, the upper and lower buildups 156, 158 of the carrier body 102 may be asymmetrical (wherein other embodiments, symmetrical configurations may be possible, and BGA (ball grid array) or LGA (land grid array) configurations may be implemented). The reason for this asymmetry is that the upper side is configured to comply with the requirements of semiconductor chip technology, as the electronic component 120 is mounted on the upper side. On the other hand, the lower side of the component carrier 100 may need to be mounted on a mounting base 160 such as a PCB, so the lower side shall comply with the requirements of PCB technology or similar. However, the remarkable rigidity of the glass carrier body 102 may result in an acceptable degree of warping despite the asymmetry. Warping can be further reduced by forming appropriately designed buildups 156, 158.

[0097] Multiple electronic components 120 are surface-mounted on a build-up 156 on a carrier body 102 and electrically coupled to conductive elements 114 by a wiring structure 118. More generally, one or more electronic components 120 may be surface-mounted on a component carrier 100. In particular, the electronic components 120 shown may be, for example, semiconductor chips for RF (radio frequency) applications.

[0098] The conductive pads 178 of the electronic component 120 may be electrically connected to the wiring structure 118 of the build-up 156 by a solder structure 180 such as a solder ball or another interconnection structure (sintered material, metal-to-metal bonding (e.g., copper-to-copper), hybrid bonding, wire bonding, etc.).

[0099] Furthermore, a surface finish 172 (ENIG or ENEPIG, solder resist, etc.) may optionally be applied to the upper side of the build-up 156 and / or the lower side of the build-up 158. The outer electrical insulating layer structure is formed as a surface finish 172, which is embodied as a solder resist. The solder resist can support the correct soldering of the component carriers 100 on the conductive pads 176 of the underlying mount base 160 (e.g., a printed circuit board) by solder structures 180 such as solder balls. Correspondingly, the solder resist can support the correct soldering of the electronic components 120 on the build-up 156 by solder structures 180.

[0100] Advantageously, each dielectric layer structure 112 can be configured as a stress-relieving layer, that is, configured to relieve stress between the upper and lower materials. In particular, by adjusting the material properties of each stress-relieving layer, such as the coefficient of thermal expansion (CTE) and / or Young's modulus, interfacial stress can be reduced or even eliminated. Such stress can result from different material properties above and below the stress-relieving layer. Such abrupt changes in material properties can generate mechanical and / or thermal stresses that can lead to undesirable phenomena such as warping, delamination, and cracking. Therefore, dielectric layer structures 112 that also function to relieve stress can improve the reliability of the component carrier 100.

[0101] However, direct adhesion of the dielectric layer structures 112 to the extremely smooth glass surface of the carrier body 102 (e.g., having a roughness Ra not exceeding 50 nm) can be a challenge. To improve adhesion between each dielectric layer structure 112 and the carrier body 102 made of glass, a patterned metal layer 116 can be formed directly on the carrier body 102 between the carrier body 102 and the dielectric layer structures 112. For example, the patterned metal layer 116 may be provided solely for the purpose of improving adhesion between each dielectric layer structure 112, but may be electrically inactive in itself. Therefore, the patterned metal layer 116 may also be electrically isolated from the wiring structure 118.

[0102] Figures 2 to 5 show cross-sectional views of structures obtained while performing a method for manufacturing the component carrier 100 shown in Figure 5, according to another exemplary embodiment of the present invention.

[0103] Referring to Figure 2, a cross-sectional view of the carrier body 102, which is materialized as a glass plate, is shown.

[0104] The through-hole 104 is formed to extend longitudinally through the carrier body 102. More precisely, two types of through-holes 104 are shown in Figure 2: A first embodiment of such a through-hole 104 is a through-hole having an hourglass shape (see reference numeral 131). The through-hole 104 with an hourglass shape may be formed as a through-hole 104 having two connected tapered sections with opposite tapered directions. Such an hourglass shape may be obtained by forming each hole 104 by laser drilling from both opposite main surfaces of the carrier body 102. A second embodiment of such a through-hole 104 is a through-hole having a continuous tapered shape (see reference numeral 133). The type of through-hole 104 described later may have a frustoconical shape. Such a continuous tapered shape may be created by laser drilling from only one main surface of the carrier body 102. The hole 104 may then be tapered toward the side of the carrier body 102 facing away from the laser light source (not shown).

[0105] Referring here to an embodiment in which the hole 104 has an hourglass shape, the minimum diameter D in its central portion may be, for example, 50 μm. The length L of the through hole 104 may correspond to the thickness of the carrier body 102. This thickness is preferably in the range of 500 μm to 750 μm, or even up to 1000 μm, for example, 800 μm. Therefore, a thick glass plate can be used as the carrier body 102. When a carrier body 100 made of glass and having a thickness of 100 μm is used, the minimum diameter D may also be smaller, for example, 20 μm or less.

[0106] Referring here to an embodiment in which the hole 104 has a continuous tapered shape, the maximum diameter S1 may be, for example, 100 μm, while the minimum diameter S2 may be, for example, 50 μm (in a carrier body thickness of, for example, 800 μm). Thus, in both embodiments, the through hole 104 has a remarkably high aspect ratio, i.e., the ratio between the length L and the minimum diameter D or S2, which is, for example, greater than 7.

[0107] Since the carrier body 102 is made of glass, it may have an extremely smooth surface, for example, with a roughness not exceeding 100 nm. This is advantageous in one respect because it allows for fine line patterning on and immediately above it. On the other hand, this is a challenge because adhesion on such a smooth surface can be problematic.

[0108] Referring to Figure 3, a cross-sectional view shows a carrier body 102 with a through-hole 104, where the through-hole 104 is partially filled with a plated metal structure 106 defined by outer dimples 108 at both ends. Thus, a plating process can be performed to partially fill the through-hole 104 with the plated metal structure 106. For example, such a plating process may include electroless plating to form a thin seed layer of copper on the wall of the carrier body 102 defining the through-hole 104. Furthermore, the plating process may then include one or more electroplating stages (such as one or more galvanic plating stages) to deposit bulk copper on the seed layer. Due to the high aspect ratio of the through-hole 104, the respective void volumes, i.e., the upper and lower dimples 108, may remain above and below the plated metal structure 106. On the upper and lower sides, the plated metal structure 106 is defined by concave surfaces. As shown in detail at 137 in Figure 3, the depth B of the dimple 108 may be in the range of, for example, 3 μm to 10 μm. The above depth can be controlled by correspondingly adjusting the plating process or the shape of the through-glass via. The depth of the laser via and the via plating cloth may affect the depth.

[0109] Furthermore, the metal layer 116 may be formed directly on the carrier body 102 during the plating process described above, or by a separate metal deposition process. Preferably, the metal layer 116 may be formed after the through-holes 104 have been filled by the plated metal structure 106. The metal layer 116 may also be made of copper. Furthermore, a mask 135 is applied to each of the metal layers 116 in preparation for the patterning process. For example, the mask 135 may be a patterned dry film laminate.

[0110] Referring to Figure 4, each portion of the metal layer 116 exposed with respect to the mask 135 (which may be a polymerized dry film) can be removed, for example, by etching or another material removal process. The mask 135 can then be removed (see Figure 4). As a result, the patterned metal layer 116 is obtained on each main surface of the carrier body 102. Advantageously, the patterned metal layer 116 is configured as an adhesive interface layer to facilitate adhesion between the carrier body 102 and each dielectric layer structure 112 subsequently formed thereon. Optionally, to further enhance adhesion, the patterned metal layer 116 may be roughened before the dielectric layer structure 112 is formed thereon.

[0111] As shown in Figure 4, both the upper and lower dimples 108 in Figure 3 can be filled with conductive dimple fillers 110, which may be made of copper, for example. For example, the dimple fillers 110 may be created by a further plating process or by another metal deposition process (e.g., printing or dispensing). The dimple fillers 110 can also be formed together with the metal layer 116 in the same plating process. The dimple fillers 110 can completely fill the through-holes 104 and may be, for example, coplanar with the upper and lower main surfaces of the carrier body 102.

[0112] Referring to Figure 5, each dielectric layer structure 112 is formed partially on the respective patterned metal layer 116, partially on the carrier body 102, and partially on the dimple filling 110. For example, each dielectric layer structure 112 may be a resin layer or a prepreg layer. As already mentioned above, the adhesion of each dielectric layer structure 112 can be significantly improved by the respective patterned metal layer 116 compared to a scenario in which the dielectric layer structures 112 are formed directly on the very smooth surface of the glass-type carrier body 102. Thus, by sandwiching each patterned metal layer 116, the mechanical integrity of the manufactured component carrier 100 can be significantly improved.

[0113] Subsequently, the acquired structure can be subjected to laser drilling. More specifically, laser holes are formed that extend throughout each dielectric layer structure 112 to a metal dimple filling 110 (which may function as, for example, a laser stop layer).

[0114] After each laser hole is formed in each dielectric layer structure 112, the laser holes can be filled with a conductive material by plating, thereby forming each conductive element 114. As shown, each conductive element 114 extends through its respective dielectric layer structure 112, thereby contacting the dimple filling 110. This ensures reliable electrical and thermal coupling between each conductive element 114 and the dimple filling 110.

[0115] Subsequently, further metallic material may be deposited or, as a metal foil, attached to the exposed surfaces of each conductive element 114 and the assigned dielectric layer structure 112. The further metallic material may be patterned to form a wiring structure 118. The wiring structure 118 may be electrically coupled to the conductive elements 114 for the transmission of electrical signals and / or power. However, at least a portion of the patterned metallic layer 116 that promotes adhesion may be electrically decoupled from the conductive elements 114 and the wiring structure 118. Thus, at least a portion of the patterned metallic layer 116 that promotes adhesion may be electrically inactive and provided for the specific purpose of improving adhesion for the dielectric layer structure 112 that is subsequently formed.

[0116] As a result of the described manufacturing process, a component carrier 100 is provided having a glass-type carrier body 102 whose through-holes 104 are at least partially filled with a plated metal structure 106. Conductive dimple filling 110 fills dimples 108 at the outer end of the plated metal structure 106. Each dielectric layer structure 112 is formed on each of the two opposite main surfaces of the carrier body 102, on a portion of the dimple filling 110, and as a stress-relieving structure on the patterned metal layer 116, in particular on the corners of the dimple filling 110. Conductive elements 114 extend through both dielectric layer structures 112 to establish direct physical contact with the dimple filling 110 on both sides of the carrier body 102.

[0117] Advantageously, each of the patterned metal layers 116 includes a laterally narrow section 139 and a laterally wide section 141, with the laterally narrow section 139 being closer to the dimples 108 than the laterally wide section 141. This configuration of the patterned metal layers 116 has been found to provide very beneficial properties in terms of promoting adhesion for the dielectric layer structure 112. Furthermore, the laterally narrow section 139 can be in direct physical contact with the dimple filling 110. The patterned metal layers 116 can provide a certain interlock configuration. The highly resin-rich regions surrounding the vias can be made small, or even minimized. The TGV can be isolated by another entity, and it is not important whether the patterned metal layers 116 are connected to the TGV or not. As already mentioned above, the wiring structures 118, which provide electrical wiring functions on the one hand and at least the laterally wide section 141 of the patterned metal layers 116 on the other hand, are electrically isolated from each other. Therefore, the laterally wide sections 141 of the patterned metal layer 116 may, from an electrical standpoint, be non-connected dummy structures that function solely to promote adhesion. Also for this reason, the patterned metal layer 116 may have a higher roughness than the wiring structure 118.

[0118] Figures 6 to 11 show plan views of structures obtained while performing a method for manufacturing the component carrier 100 shown in Figure 11, according to another exemplary embodiment of the present invention.

[0119] Referring to Figure 6, a plan view of the corresponding structure in Figure 2 is shown.

[0120] Referring to Figure 7, a plan view of the structure in Figure 6 after the seed layer 151 has been formed by, for example, electroless deposition is shown. The seed layer 151 may be made of a metal such as copper.

[0121] Referring to Figure 8, a plan view of the structure in Figure 7 after galvanic plating and patterning is shown. As a result, a patterned metal layer 116 and dimple filling 110 can be formed. As shown, the patterned metal layer 116 includes a ring structure around the metallized holes 104. In other words, Figure 8 shows the structure after plating and patterning.

[0122] Referring to Figure 9, a plan view of the structure in Figure 8 is shown after the patterned metal layer 116, dimple filling 110, and dielectric layer structure 112 have been formed on the glass carrier body 102. This can be done by laminating a resin layer on top of the structure in Figure 8.

[0123] Referring to Figure 10, a plan view of the structure shown in Figure 9 is obtained after laser drilling to form through holes 143 in the dielectric layer structure 112 for forming conductive elements 114.

[0124] Referring to Figure 11, a plan view of the structure in Figure 10 after the formation and construction of further metal structures is shown. More specifically, the above-mentioned further metal structures may include conduction elements 114 in the through-holes 143 and wiring structures 118 connected to the conduction elements 114 and forming traces on the surface of the component carrier 100 shown in Figure 11.

[0125] Figures 12 to 15 show cross-sectional views of a component carrier 100 according to different exemplary embodiments of the present invention.

[0126] Referring to Figure 12, a component carrier 100 with the properties shown in Figure 5 is shown, where the through-hole 104 has a continuous tapered shape. The surface of the patterned metal layer 116 was roughened (e.g., by polishing, etching, or chemical treatment) to facilitate adhesion of the dielectric layer structure 112.

[0127] The component carrier 100 shown in Figure 13 differs from the component carrier 100 shown in Figure 12 in that, according to Figure 13, the through hole 104 is hourglass-shaped rather than having a continuous tapered shape as shown in Figure 12.

[0128] The component carrier 100 shown in Figure 14 differs from the component carrier 100 shown in Figure 12 in that, according to Figure 14, the laterally narrow section 139 of the patterned metal layer 116 is omitted.

[0129] The component carrier 100 shown in Figure 15 differs from the component carrier 100 shown in Figure 13 in that, according to Figure 15, the laterally narrow section 139 of the patterned metal layer 116 is omitted.

[0130] Figure 16 shows a cross-sectional view of a component carrier 100 according to an exemplary embodiment of the present invention.

[0131] In the embodiment shown in Figure 16, the patterned metal layer 116 is configured to shield a component 120 embedded in the carrier body 102. For example, the component 120 may be a high-frequency component that requires shielding from electromagnetic radiation from the environment. The patterned metal layer 116, together with a further metallic or magnetic structure 159, can form a shielding cage to shield the component 120 from electromagnetic radiation.

[0132] It should be noted that the term "includes" does not exclude other elements or steps, and "a" or "an" does not exclude plurals. Furthermore, elements described in relation to different embodiments may be combined.

[0133] It should also be noted that reference numerals in the claims should not be interpreted as limiting the scope of the claims.

[0134] Implementation of the present invention is not limited to the preferred embodiments shown in the figures and described above. Rather, numerous variations are possible that utilize the solutions shown and the principles of the present invention, even in the case of essentially different embodiments.

Claims

1. A carrier body having holes partially filled with a metal structure defined by external dimples; Conductive dimple filling that at least partially fills the outer dimples; A dielectric layer structure on at least a portion of the carrier body and a portion of the conductive dimple filling; and Conductive elements extending through the dielectric layer structure and in contact with the conductive dimple filling A component carrier equipped with these features.

2. The component carrier according to claim 1, wherein the dielectric layer structure is configured as a stress release layer.

3. The component carrier according to claim 1 or 2, wherein the depth of the outer dimple is in the range of 1 μm to 20 μm.

4. The component carrier according to claim 3, wherein the depth of the outer dimple is in the range of 3 μm to 10 μm.

5. The component carrier according to claim 1 or 2, wherein the hole has a ratio between at least two lengths and a minimum diameter.

6. The component carrier according to claim 5, wherein the hole has a ratio between at least 5 in length and 5 in minimum diameter.

7. The component carrier according to claim 6, wherein the hole has a ratio between at least 7 lengths and minimum diameters.

8. The component carrier according to claim 1 or 2, wherein the hole has an hourglass shape or a continuous tapered shape.

9. The component carrier according to claim 1 or 2, further comprising a patterned metal layer directly on the carrier body.

10. The component carrier according to claim 9, wherein the patterned metal layer is patterned between the metal structure and the dielectric layer structure, and / or between the carrier body and the dielectric layer structure.

11. The component carrier according to claim 9, wherein the patterned metal layer is configured as an adhesive interface layer for promoting adhesion between the carrier body and the dielectric layer structure.

12. The component carrier according to claim 9, wherein the patterned metal layer includes a laterally narrow section and a laterally wide section, the laterally narrow section being closer to the outer dimple than the laterally wide section.

13. The component carrier according to claim 12, wherein the laterally narrow section is in direct physical contact with the conductive dimple filling.

14. The component carrier according to claim 9, comprising a wiring structure for providing an electrical wiring function, wherein the patterned metal layer is electrically isolated from the wiring structure.

15. The component carrier according to claim 9, wherein the patterned metal layer is configured to shield components embedded in the carrier body.

16. The component carrier according to claim 9, wherein at least a portion of the patterned metal layer has a ring shape.

17. The component carrier according to claim 9, comprising a wiring structure for providing an electrical wiring function, wherein the patterned metal layer has a higher roughness than the wiring structure.

18. A method for manufacturing a component carrier: A step of providing a carrier body having a hole partially filled with a metal structure defined by an external dimple; A step of filling the outer dimples at least partially by conductive dimple filling; The steps of forming a dielectric layer structure on at least a portion of the carrier body and on a portion of the conductive dimple filling; and A step of forming a conductive element that extends through the dielectric layer structure and comes into contact with the conductive dimple filling. A method for providing this.

19. The method according to claim 18, further comprising the step of forming a patterned metal layer directly on the carrier body.

20. The method according to claim 19, further comprising the step of roughening the patterned metal layer before forming the dielectric layer structure thereon.

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