Electronic circuits and power converters

Abstract

To provide electronic circuitry and a power converter, capable of suppressing degradation in performance due to transmission of a signal through electromagnetic field coupling.SOLUTION: Electronic circuitry according to the present embodiment includes: a clock generation circuit configured to generate a first clock signal; a first conversion circuit configured to convert an input signal into a first signal having a frequency corresponding to the first clock signal on the basis of the first clock signal; a first electromagnetic field coupler configured to transmit the first signal by electromagnetic field coupling; a second electromagnetic field coupler configured to transmit the first clock signal by the electromagnetic field coupling; and a second conversion circuit configured to convert the first signal transmitted by the first electromagnetic field coupler into a second signal having a frequency corresponding to the input signal, on the basis of the first clock signal transmitted by the second electromagnetic field coupler.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This embodiment relates to an electronic circuit and a power converter. [Background technology]

[0002] Electronic circuits have been developed that transmit analog signals from an input to an output through isolation. One example of such an electronic circuit is a method that converts an analog signal into a high-frequency signal, transmits it through isolation using electromagnetic field coupling, and restores it to the original analog signal. However, previously proposed electronic circuits have raised concerns such as a narrow input range and a decrease in the signal-to-noise ratio of the restored signal. There is also concern that the overall system performance may be limited by this input range. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] U.S. Patent No. 8,378,663 [Patent Document 2] Japanese Patent Publication No. 2021-42996 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] This embodiment aims to provide an electronic circuit and a power converter that suppress performance degradation caused by transmitting signals via electromagnetic field coupling. [Means for solving the problem]

[0005] The electronic circuit according to this embodiment includes a clock generation circuit that generates a first clock signal; a first conversion circuit that converts an input signal into a first signal having a frequency corresponding to the first clock signal based on the first clock signal; a first electromagnetic field coupling unit that transmits the first signal by electromagnetic field coupling; a second electromagnetic field coupling unit that transmits the first clock signal by electromagnetic field coupling; and a second conversion circuit that converts the first signal transmitted by the first electromagnetic field coupling unit into a second signal having a frequency corresponding to the input signal based on the first clock signal transmitted by the second electromagnetic field coupling unit. [Brief explanation of the drawing]

[0006] [Figure 1] This figure shows an example configuration of an isolation amplifier as an electronic circuit according to the first embodiment. [Figure 2] A schematic diagram showing the analog signal, which is the input signal. [Figure 3] A diagram illustrating an example of two differential clock signals. [Figure 4] (A) and (B) are diagrams showing example configurations of frequency converters, respectively. [Figure 5] A diagram showing an example of a high-frequency signal. [Figure 6] Figures (A) to (D) show examples of the configuration of the electromagnetic field coupling section. [Figure 7] This figure shows an example configuration of an isolation amplifier as an electronic circuit according to the second embodiment. [Figure 8] This figure shows an example configuration of an isolation amplifier as an electronic circuit according to the third embodiment. [Figure 9] This diagram illustrates an example of converting a transmitted clock signal into a DC voltage signal based on the phase-adjusted clock signal. [Figure 10] A diagram showing an example of a comparator circuit configuration. [Figure 11] A diagram illustrating an example of the operation flow for clock phase adjustment. [Figure 12] A diagram showing an example of a timing chart for each signal in a comparison circuit. [Figure 13]This figure shows an example configuration of an isolation amplifier as an electronic circuit according to the fourth embodiment. [Figure 14] A diagram illustrating an example of the operational flow for adjusting the gain of an amplifier. [Figure 15] This figure shows an example configuration of a power converter using an isolation amplifier as an electronic circuit according to the fifth embodiment. [Modes for carrying out the invention]

[0007] Embodiments of the present invention will be described below with reference to the drawings.

[0008] (First Embodiment) Figure 1 shows an example configuration of an isolation amplifier 100 as an electronic circuit according to the first embodiment. The isolation amplifier 100 is a circuit that transmits an analog signal, which is an input signal supplied to the input side, to the output side via isolation. In the following description, the input side of the analog signal (left side in the figure) is referred to as the primary side, and the output side of the analog signal (right side in the figure) is referred to as the secondary side, with the isolation barrier 90 as the boundary.

[0009] The primary and secondary sides use independent reference potentials GND1 and GND2, and independent power supplies VDD1 and VDD2, respectively. For example, the primary side (left side of the diagram) is the high-voltage side, and the secondary side (right side of the diagram) is the low-voltage side. Terminals GND_T1 and GND_T2 are provided on the primary and secondary sides to which the reference potentials GND1 and GND2 are supplied. In addition, terminals VDD_T1 and VDD_T2 are provided on the primary and secondary sides to which the power potential is supplied from power supplies VDD1 and VDD2.

[0010] The primary side is provided with input terminals INP and INN, to which analog signals to be transmitted to the secondary side are input. Input terminals INP and INN are connected to, for example, one end and the other end of an element whose voltage or current is to be measured, and the analog signal V at the one end and the other end is input. P1 , V N1The following is input: In other words, the voltages from one end and the other end of the target element are input between input terminals INP and INN.

[0011] Figure 2 shows the analog signal V input to input terminals INP and INN. P1 , V N1 The input signal is schematically shown. Analog signal V P1 , V N1 This is the input signal to isolation amplifier 100. Analog signal V P1 , V N1 The difference (amplitude of the input signal) represents the voltage of the element being measured. In this example, the input terminal INN is connected to a reference potential, but the location to which the input terminal INN is connected is not limited to the reference potential.

[0012] Examples of elements to be measured include transistors and resistors. The input analog signal is an arbitrary waveform ranging from several tens of Hz to several tens of MHz. The input analog signal is input to the modulation unit 10 (first conversion circuit). The modulation unit 10 is a first conversion circuit that increases the frequency (high-frequency conversion) of the input signal. The modulation unit 10 includes a frequency converter 11. The frequency converter 11 may also be called a mixer, chopper, or sampling circuit.

[0013] The clock generation circuit 20 is located on the primary side. The clock generation circuit 20 generates clock signals CLKA and CLKB, which are square waves. Clock signals CLKA and CLKB correspond to the first clock signals generated by the clock generation circuit 20.

[0014] FIG. 3 shows examples of clock signals CLKA and CLKB. The clock signals CLKA and CLKB are signals including periodic rectangular pulses. The clock signals CLKA and CLKB are differential clock signals. That is, CLKB is a signal obtained by inverting CLKA. When CLKA is at a high level, CLKB is at a low level, and when CLKA is at a low level, CLKB is at a high level. The periods (frequencies) of the clock signals CLKA and CLKB are the same, for example, several hundred MHz. The amplitudes of the clock signals CLKA and CLKB are the same or substantially the same.

[0015] The clock generation circuit 20 supplies the clock signals CLKA and CLKB to the modulation unit 10 and transmits them to the secondary side via the electromagnetic field coupling unit 2.

[0016] The frequency converter 11 in the modulation unit 10, based on the clock signals CLKA and CLKB supplied from the clock generation circuit 20, P1 V N1 (input signals) to a higher frequency. That is, the frequency converter 11 converts the analog signals V P1 V N1 according to the periods (frequencies) of the clock signals CLKA and CLKB to generate high-frequency signals V P2 V N2 . The high-frequency signals V P2 V N2 have frequencies corresponding to the clock signals CLKA and CLKB. In this embodiment, the operation of converting a signal to a higher frequency based on a clock signal as described above is called modulating the signal. The high-frequency signals V P2 V N2 are output to the electromagnetic field coupling unit 1. The high-frequency signals V P2 V N2 correspond to the first signals generated by converting the frequencies of the input signals. The first signals have frequencies corresponding to the first clock signals.

[0017] FIG. 4 shows two configuration examples of the frequency converter 11 in the modulation unit 10. In either configuration, the analog signal V, which is the input signal input between the terminal INA and the terminal INB,P1 , V N1 By sampling (modulating) these signals in opposite directions according to the clock signals CLKA and CLKB, the high-frequency signal V P2 , V N2 The generated high-frequency signal V is produced. P2 , V N2 Of these, the high-frequency signal V P2 This is output from terminal OUTA, and the high-frequency signal V N2 It is output from terminal OUTB.

[0018] Figure 4(A) shows an example configuration of a frequency converter 11 using NMOS transistors. When the clock signal CLKA is high level and CLKB is low level, NMOS transistors M1 and M2 are turned on and NMOS transistors M3 and M4 are turned off, and a signal in phase with the input signal is output from terminals OUTA and OUTB of the frequency converter 11. That is, the input signal V P1 The sampled signal is output from terminal OUTA of the frequency converter 11, and the input signal V N1 The sampled signal is output from terminal OUTB of the frequency converter 11. When the clock signal CLKA is low level and CLKB is high level, NMOS transistors M1 and M2 are off and M3 and M4 are on, and a signal in the opposite phase to the input signal is output from terminals OUTA and OUTB of the frequency converter 11. That is, the input signal V P1 The sampled signal is output from terminal OUTB of the frequency converter 11, and the input signal V N1 The sampled signal is output from terminal OUTA of the frequency converter 11. In this way, the high-frequency signal V is output from terminal OUTA. P2 The signal generated and output from terminal OUTB is a high-frequency signal V N2 This is generated.

[0019] Figure 4(B) shows an example configuration of a frequency converter 11 using NMOS transistors and PMOS transistors. When the clock signal CLKA is at a high level and CLKB is at a low level, the NMOS transistor M n1 PMOS transistor M p1, NMOS transistor M n2 PMOS transistor M p2 When the NMOS transistor M is turned on, n3 PMOS transistor M p3 , NMOS transistor M n4 PMOS transistor M p4 This is turned off. As a result, a signal in phase with the input signal is output from terminals OUTA and OUTB of the frequency converter 11. When the clock signal CLKA is low level and CLKB is high level, the NMOS transistor M n1 PMOS transistor M p1 , NMOS transistor M n2 PMOS transistor M p2 When it is off, the NMOS transistor M n3 PMOS transistor M p3 , NMOS transistor M n4 PMOS transistor M p4 This is turned on. As a result, a signal that is in the opposite phase to the input signal is output from terminals OUTA and OUTB of the frequency converter 11.

[0020] Figure 5 shows the high-frequency signal V output from terminal OUTA. P2 An example is shown. Depending on the clock signals CLKA and CLKB, the input signal V P1 , V N1 When these are sampled from each other, the high-frequency signal V P2 A high-frequency signal V is generated. N2 Similarly, the input signal V N1 , V P1 When these are sampled from each other, the high-frequency signal V N2 This is generated.

[0021] The electromagnetic field coupling unit 1 insulates the primary and secondary sides, and receives the high-frequency signal V from the modulation unit 10. P2 , V N2This is a transmission unit that transmits the signal to the secondary side via insulation. The electromagnetic field coupling unit 1 includes, for example, a capacitor or a transformer. When a high-frequency signal is transmitted from the primary side to the secondary side, the phase of the signal input to the electromagnetic field coupling unit 1 rotates (fluctuations) due to the characteristics of the electromagnetic field coupling unit 1.

[0022] Figure 6 shows four examples of the configuration of the electromagnetic field coupling unit 1. Figure 6(A) shows an example of the configuration of the electromagnetic field coupling unit 1 using a capacitor. The electromagnetic field coupling unit 1 has two input terminals A1 and B1 and two output terminals A2 and B2. A high-frequency signal V is input to terminal A1. P2 The signal is input, and a high-frequency signal V is input to terminal B1. N2 A single capacitor C11 is provided between terminals A1 and A2, and the high-frequency signal V is input to terminal A1. P2 The signal is transmitted to the output terminal B1 via capacitor C11. A single capacitor C21 is provided between terminals B1 and B2, and the high-frequency signal V is input to terminal B1. N2 The current is transmitted to the output terminal B2 via capacitor C21. Capacitors C11 and C21 function as insulating barriers that insulate the input and output sides. More specifically, the dielectric portion (insulating part) between the two opposing plates of the capacitor, such as a silicon oxide film or polyimide film, functions as an insulating barrier. The configuration in Figure 6(A) allows for a smaller area of ​​the electromagnetic field coupling section compared to the configuration of the electromagnetic field coupling section using a transformer, which will be described later. The capacitances of capacitors C11 and C21 are the same as an example, but configurations with different capacitances are also possible.

[0023] Figure 6(B) shows an example configuration of the electromagnetic field coupling unit 1 using multiple capacitors. The configuration in Figure 6(B) is the same as in Figure 6(A), but with capacitors C11 and C21 replaced by multiple capacitors connected in series. Multiple capacitors C11 and C12 are connected in series between terminals A1 and A2. Multiple capacitors C21 and C22 are connected in series between terminals B1 and B2. Capacitors C11, C12, C21, and C22 function as insulating barriers that insulate the input side and the output side. In the single capacitor configuration in Figure 6(A), if the capacitor breaks down, there is a possibility of conduction between the primary and secondary sides. However, by connecting multiple capacitors in series, insulation is maintained even if one of the multiple capacitors breaks down. This improves safety. The capacitances of capacitors C11 and C21 are the same as an example, but different configurations are also possible. The capacitances of capacitors C12 and C22 are the same as an example, but different configurations are also possible.

[0024] Figure 6(C) shows an example configuration of the electromagnetic field coupling unit 1 using a transformer. Coil L11 is connected between input terminals A1 and B1, and coil L12 is connected between output terminals A2 and B2. Coils L11 and L12 face each other to form a single transformer T11. Transformer T11 functions as an insulating barrier that insulates the input side from the output side. More specifically, the dielectric portion between coils L11 and L12 (e.g., an air layer, silicon oxide film, polyimide film, etc.) functions as an insulating barrier. Compared to the electromagnetic field coupling unit using a capacitor shown in Figure 6(A) or Figure 6(B), common-mode characteristics such as CMRR or CMTI can be improved.

[0025] Figure 6(D) shows an example of the configuration of the electromagnetic field coupling unit 1 using multiple transformers. Coil L11 is connected between input terminals A1 and B1, and coil L11 faces coil L12 to form transformer T11. Furthermore, coils L13 are provided at both ends of coil L12, and coil L13 faces coil L14 connected between output terminals A2 and B2 to form transformer T12. As a result, transformers T11 and T12 are connected in multiple layers. Transformers T11 and T12 function as insulating barriers, including boundaries that insulate the input side and the output side. In the case of a single transformer configuration in Figure 6(C), if the transformer experiences dielectric breakdown, there is a possibility that the primary and secondary sides will become conductive. However, by connecting multiple transformers, insulation is maintained even if one of the multiple transformers experiences dielectric breakdown. This improves safety.

[0026] The electromagnetic field coupling unit 2 is a transmission unit that isolates the primary and secondary sides and transmits the clock signal input from the clock generation circuit 20 to the secondary side via isolation. The electromagnetic field coupling unit 2 includes, for example, a capacitor or a transformer. When the clock signal is transmitted from the primary side to the secondary side, the phase of the signal input to the electromagnetic field coupling unit 2 is rotated due to the characteristics of the electromagnetic field coupling unit 2. An example of the configuration of the electromagnetic field coupling unit 2 is the same as in Figures 6(A) to 6(D). In the configuration shown in Figures 6(A) to 6(D), the clock signals CLKA and CLKB are input to terminals A1 and B1, respectively, and the input clock signals CLKA and CLKB are transmitted via isolation and output from terminals A2 and B2.

[0027] In this embodiment, the configuration of the electromagnetic field coupling unit 2 is assumed to be the same as that of the electromagnetic field coupling unit 1. This makes it possible to make the amount of phase rotation (phase delay) generated in the electromagnetic field coupling units 1 and 2 the same or approximately the same. However, it is not excluded to use different configurations for the electromagnetic field coupling units 1 and 2. The amount of phase rotation (phase delay) generated in the electromagnetic field coupling units 1 and 2 may be the same or approximately the same even if they have different configurations. It is also possible for the amount of phase rotation generated in the electromagnetic field coupling units 1 and 2 to be different.

[0028] The waveform shaping circuit 30 shapes the clock signals CLKA and CLKB transmitted via the electromagnetic field coupling unit 2. The amplitude of the clock signal received on the secondary side via the electromagnetic field coupling unit 2 fluctuates (e.g., attenuation) due to the characteristics of the electromagnetic field coupling unit 2. The waveform shaping circuit 30 adjusts (shapes) the amplitude of the clock signal transmitted via the electromagnetic field coupling unit 2 to match the amplitude of the clock signal used on the secondary side. For example, it amplifies the amplitude of the clock signal received on the secondary side so that it has the same amplitude as the clock signals CLKA and CLKB generated by the clock generation circuit 20. In this case, the waveform shaping circuit 30 includes an amplifier that amplifies the amplitude of the clock signal received on the secondary side. Alternatively, if the amplitude of the clock signal used on the secondary side is small, the waveform shaping circuit 30 may be a circuit that clips the amplitude of the clock signal received on the secondary side. Alternatively, as another example, in a configuration where a transformer is used in the electromagnetic field coupling unit 2, a configuration in which the voltage of the transmitted signal increases during transmission is also conceivable. In this case, it is also possible to clip the voltage of the transmitted signal so that it has the same amplitude as the clock signals CLKA and CLKB generated by the clock generation circuit 20.

[0029] The phase adjustment circuit 40 adjusts the phase of the clock signals CLKA and CLKB that have been shaped by the waveform shaping circuit 30. The phase adjustment circuit 40 is composed of, for example, a delay circuit. When the waveforms of the clock signals CLKA and CLKB are shaped by the waveform shaping circuit 30, a phase delay occurs in the clock signals CLKA and CLKB. Therefore, during waveform shaping, the phase of the clock signals CLKA and CLKB is affected by the high-frequency signal V transmitted via the electromagnetic field coupling unit 1. P2 , V N2 It is delayed relative to the high-frequency signal V. The phase adjustment circuit 40 adjusts (compensates for) the phase of the clock signals CLKA and CLKB by this delay, thereby adjusting the phase of the clock signals CLKA and CLKB relative to the high-frequency signal V. P2 , V N2 The phase-adjusted clock signals CLKA1 and CLKB1 are input to the demodulation unit 50. The phase-adjusted clock signals CLKA1 and CLKB1, which have been phase-adjusted by the phase adjustment circuit 40, correspond to the second clock signal.

[0030] The demodulation unit 50 comprises a frequency converter 51, an amplifier 52, and a low-pass filter (LPF) 53. The demodulation unit 50 is a second conversion circuit that converts (reduces the frequency of) the high-frequency signal (first signal) input to the demodulation unit 50 based on a phase-adjusted clock signal input from the phase adjustment circuit 40. As a result, the demodulation unit 50 generates an output signal (second signal) having a frequency corresponding to the input signal. In this embodiment, the process of reducing the frequency of the input signal based on the clock signal is called demodulating the signal. The output signal corresponds to an analog signal in which the high-frequency signal input to the demodulation unit 50 has been restored to a frequency similar to that of the original input signal. The output signal is also called the restored signal. The demodulation unit 50 will be described in detail below.

[0031] The frequency converter 51 in the demodulation unit 50 receives the high-frequency signal V through the electromagnetic field coupling unit 1. P2 , V N2 This is converted (demodulated) based on the phase-adjusted clock signals CLKA1 and CLKB1 input from the phase adjustment circuit 40. This results in an analog signal V having a frequency corresponding to the input signal. P3 , V N3 It generates a high-frequency signal V. P2 , V N2 By sampling in opposite directions based on the clock signals CLKA1 and CLKB1, the analog signal V P3 , V N3 Generates.

[0032] Analog signal V P3 , V N3 Based on the first clock signal transmitted by the electromagnetic field coupling unit 2, the first signal (high-frequency signal V) transmitted by the electromagnetic field coupling unit 1 is used. P2 , V N2 This corresponds to the fifth signal obtained by converting the frequency of the input signal (analog signal V). The fifth signal is the input signal (analog signal V). P1 , V N1 It has a frequency corresponding to ).

[0033] As with the frequency converter 11, the configuration example of the frequency converter 51 can use the configurations shown in FIGS. 4(A) or 4(B). In the configurations shown in FIGS. 4(A) or 4(B), high-frequency signals V P2 , V N2 are input to terminals INA and INB, respectively, and clock signals CLKA1 and CLKB1 are input instead of clock signals CLKA and CLKB. As a result, analog signals V P2 , V N2 obtained by converting the high-frequency signals V P3 , V N3 are output from terminals OUTA and OUTB, respectively.

[0034] The amplifier 52 amplifies the analog signals V P3 , V N3 and outputs them to the low-pass filter 53.

[0035] The low-pass filter 53 attenuates or reduces high-frequency components (high-frequency components included in the clock signals CLKA1, CLKB1 and the high-frequency signals V P3 , V N3 ) from the amplified analog signals V P2 , V N2 . As a result, analog signals V P4 , V N4 serving as output signals (second signals) are generated. The low-pass filter 53 outputs the analog signals V P4 , V N4 from output terminal OUTP and output terminal OUTN.

[0036] The modulation unit 10, clock generation circuit 20, waveform shaping circuit 30, phase adjustment circuit 40, and demodulation unit 50 in FIG. 1 may be configured by circuits or processors such as an ASIC (application specific integrated circuit) or FPGA (Field-Programmable Gate Array). Alternatively, some or all of these elements may be executed by a CPU that executes a program.

[0037] As described above, according to this embodiment, by generating a clock signal on the primary side, the input signal can be modulated by a clock signal having the amplitude of the power supply voltage, thereby widening the input range of the input signal.

[0038] Furthermore, according to this embodiment, by making the configuration of the electromagnetic field coupling unit 1 and the electromagnetic field coupling unit 2 identical, the amount of phase rotation (phase delay) generated in the electromagnetic field coupling unit 1 with respect to the high-frequency signal output from the modulation unit 10 becomes the same as or approximately the same as the amount of phase rotation generated in the electromagnetic field coupling unit 2 with respect to the clock signal. Therefore, the phase adjustment range of the clock signal supplied to the demodulation unit 50 can be narrowed.

[0039] Furthermore, according to this embodiment, in the secondary side demodulation unit 50, demodulation is performed using a clock signal whose phase has been adjusted by the phase adjustment circuit 40, thereby reducing the phase difference between the high-frequency signal input to the demodulation unit 50 and the phase-adjusted clock signal. As a result, the high-frequency signal can be demodulated with the maximum amplitude. This makes it possible to maximize the signal-to-noise ratio of the analog signal (restored signal) restored by demodulation.

[0040] (modified version) If the phase delay corresponding to the amount of phase adjustment required by the phase adjustment circuit 40 can be absorbed by the electromagnetic field coupling unit 2 and the waveform shaping circuit 30, the phase adjustment circuit 40 can be omitted. In this case, the position delay in the electromagnetic field coupling unit 1 and the phase delay in the electromagnetic field coupling unit 2 and the waveform shaping circuit 30 become the same or approximately the same. This eliminates the need for the phase adjustment circuit 40 and reduces the circuit size. Alternatively, the clock generation circuit 20 may be omitted, and the clock signals CLKA and CLKB may be directly supplied from outside the isolation amplifier 100. The clock signals CLKA and CLKB may also be generated using a frequency multiplier circuit, frequency divider circuit, Phase Locked Loop (PLL), etc., based on the clock signal supplied from outside the isolation amplifier 100.

[0041] (Second Embodiment) In the first embodiment described above, the phase of the clock signal input to the demodulation unit 50 was adjusted, but in the second embodiment, the phase of the high-frequency signal input to the demodulation unit 50 is adjusted. The configurations of the electromagnetic field coupling units 1 and 2 are the same, and the phase delay amount of the electromagnetic field coupling unit 1 and the phase delay amount of the electromagnetic field coupling unit 2 are assumed to be the same.

[0042] Figure 7 shows an example configuration of an isolation amplifier 200 as an electronic circuit according to the second embodiment. The configuration of the primary side is the same as in the first embodiment. On the secondary side, a phase adjustment circuit 240 is provided between the electromagnetic field coupling unit 1 and the demodulation unit 50. No phase adjustment circuit is provided between the waveform shaping circuit 30 and the demodulation unit 50.

[0043] The phase adjustment circuit 240 receives the high-frequency signal V from the electromagnetic field coupling unit 1. P2 , V N2 The phase of the delay is delayed by the same amount or approximately the same amount as the delay phase of the clock signals CLKA and CLKB generated by the waveform shaping circuit 30. The phase adjustment circuit 240 delays the high-frequency signal V P5 , V N5 The high-frequency signal V is output to the demodulation unit 50. P5 , V N5 is a high-frequency signal V P2 , V N2 This corresponds to the sixth signal with its phase adjusted.

[0044] The clock signals CLKA and CLKB, shaped by the waveform shaping circuit 30, are input to the demodulation unit 50. The high-frequency signal V is input to the demodulation unit 50. P5 , V N5 Therefore, the phase difference between the clock signals CLKA and CLKB input to the demodulation unit 50 is small or zero, so the high-frequency signal V P5 , V N5 This allows for demodulation with the maximum or largest amplitude. Therefore, the signal-to-noise ratio (SNR) can be maximized or increased.

[0045] (Third embodiment) Figure 8 shows an example configuration of an isolation amplifier 300 as an electronic circuit according to the third embodiment. The primary side configuration is the same as in the first embodiment, and the configuration of the demodulation unit 50_1, which demodulates the high-frequency signal transmitted via the electromagnetic field coupling unit 1, is the same as the demodulation unit 50 of the first embodiment. The configurations of the electromagnetic field coupling units 1 and 2 are the same, and the phase delay amount from the electromagnetic field coupling unit 1 to the demodulation unit 50_1 is the same as the phase delay amount from the electromagnetic field coupling unit 2 to the demodulation unit 50_2.

[0046] Similar to the first embodiment, the secondary side is provided with a waveform shaping circuit 30 and a phase adjustment circuit 40, and furthermore, a demodulation unit 50_2 is provided. The clock signals CLKA and CLKB transmitted to the secondary side via the electromagnetic field coupling unit 2 are input to the waveform shaping circuit 30 and also to the demodulation unit 50_2. The clock signals CLKA1 and CLKB1, whose phases have been adjusted by the phase adjustment circuit 40, are input to the demodulation unit 50_1 and also to the demodulation unit 50_2.

[0047] The demodulation unit 50_2 (third conversion circuit) converts the clock signals CLKA and CLKB input via the electromagnetic field coupling unit 2 based on the phase-adjusted clock signals CLKA1 and CLKB1 input from the phase adjustment circuit 40. This generates DC voltage signals (DC voltage signals or first DC voltage signals) corresponding to the amplitudes of the clock signals CLKA and CLKB. In this embodiment, this conversion of clock signals to DC voltage signals is also called clock signal demodulation. The demodulation unit 50_2 includes a frequency converter 51_2, an amplifier 52_2, and a low-pass filter 53_2.

[0048] The configuration of the frequency converter 51_2, amplifier 52_2, and low-pass filter 53_2 is the same as that of the frequency converter 51_1, amplifier 52_1, and low-pass filter 53_1 in the demodulation unit 50_1. Therefore, the configuration example of the frequency converter 51_2 can be the same as that of the frequency converter 51_1, using the configuration shown in Figure 4(A) or Figure 4(B).

[0049] In the configuration shown in Figure 4(A) or Figure 4(B), clock signals CLKA and CLKB transmitted by the electromagnetic field coupling unit 2 are input to terminals INA and INB, respectively. The input clock signals CLKA and CLKB are sampled based on the clock signals CLKA1 and CLKB1 input from the phase adjustment circuit 40 to obtain non-pulsed signals DA and DB. Signals DA and DB correspond to the non-pulsed third signals generated by the frequency converter 51_2.

[0050] Signals DA and DB are amplified by amplifier 52_2, and the amplified signals DA and DB are input to low-pass filter 53_2. The low-pass filter 53_2 attenuates or reduces the high-frequency components (high-frequency components contained in the clock signals CLKA1, CLKB1 and CLKA, CLKB) from the amplified signals DA and DB, and the attenuated or reduced signal becomes the DC voltage signal V P6 , V N6 It is output as a DC voltage signal V. P6 , V N6 The DC voltage signal V is input to the comparator circuit 60. P6 , V N6 This corresponds to a first DC voltage signal having an amplitude corresponding to the clock signals CLKA and CLKB.

[0051] Figure 9 shows that the demodulation unit 50_2 converts the clock signals CLKA, CLKA based on the clock signals CLKA1, CLKB1 input from the phase adjustment circuit 40, resulting in a DC voltage signal V P6 , V N6 An example of the output is shown below. DC voltage signal V P6 , V N6 The difference corresponds to ΔDC.

[0052] The comparison circuit 60, in response to the trigger signal from the control circuit 70, takes into account the currently input DC voltage signal V P6 , V N6 The difference between and the previously input DC voltage signal V P6 , V N6 The difference is compared, and a signal indicating the comparison result is sent to the control circuit 70. Details of the comparison circuit 60 will be described later.

[0053] The control circuit 70 changes the phase adjustment amount of the phase adjustment circuit 40, and the DC voltage signal V before the change P6 , V N6 The difference and the modified DC voltage signal V P6 , V N6 The difference is compared with the comparison circuit 60, and the comparison result is obtained. The control circuit 70 repeatedly changes the phase adjustment amount and obtains the comparison result, and based on each comparison result, determines the phase adjustment amount to be set in the phase adjustment circuit 40. The phases of the high-frequency signal input to the demodulation unit 50_1 and the clock signal are matched, and the output signal (restored signal) V from the demodulation unit 50_1 is obtained. P4 , V N4 The amplitude can be maximized or increased.

[0054] Figure 10 shows an example configuration of the comparator circuit 60. The comparator circuit 60 comprises sample-and-hold circuits 61 and 62 (labeled S / H in the drawing), a comparator 63, and a latch circuit 64.

[0055] The sample-and-hold circuit 61 receives a signal (sampling command signal) SMPL1 from the control circuit 70 that represents a command to hold the voltage, and receives the input DC voltage signal V P6 , V N6 The difference is ΔV HOLD1 It will be kept as such.

[0056] The sample-and-hold circuit 62 receives a signal (sampling command signal) SMPL2 from the control circuit 70 that represents a command to hold the voltage, and receives the input DC voltage signal V P6 , V N6 The difference in voltage is ΔV HOLD2 The signal is held as such. The control circuit 70 makes the timing of sending signal SMPL1 and the timing of sending signal SMPL2 different, thereby allowing the sample-and-hold circuits 61 and 62 to hold the voltage difference at different phase adjustment amounts.

[0057] The comparator 63 measures the voltage difference ΔV input from the sample-and-hold circuit 61. HOLD1 And the difference ΔV of the voltage input from the sample-and-hold circuit 62 HOLD2The difference ΔV is compared with the signal VCMP, which is output to the latch circuit 64. HOLD2 The difference is ΔV HOLD1 If it is greater than ΔV, the signal VCMP is a high-level signal, and the difference ΔV HOLD1 The difference is ΔV HOLD2 If the difference ΔV is greater, the signal VCMP is a low-level signal. However, this relationship can also be reversed. HOLD1 and difference ΔV HOLD2 Comparing these two is equivalent to comparing the voltage of the first DC voltage signal obtained when different phase adjustment amounts are set.

[0058] The latch circuit 64 receives a signal LATCH from the control circuit 70 indicating a latch instruction, latches (holds) the signal VCMP, and sends the latched signal AMPDET to the control circuit 70. The signal LATCH is, for example, a digital signal with bits 0 or 1. Based on the signal AMPDET, the control circuit 70 calculates ΔV HOLD1 and ΔV HOLD2 It is possible to recognize the relative sizes of things.

[0059] Figure 11 shows an example of the operation flow of clock phase adjustment performed by the comparison circuit 60, phase adjustment circuit 40, and control circuit 70. Clock phase adjustment is performed when the power is turned on or when a phase adjustment execution signal is input from an external source. Alternatively, clock phase adjustment is performed periodically at arbitrary intervals by a timer or the like.

[0060] The control circuit 70 sets the phase adjustment amount of the phase adjustment circuit 40 to the first candidate value (DLY_0) among multiple candidate values ​​DLY_0 to DLY_N (S101). The control circuit 70 stores the candidate value (DLY_0) in parameter α.

[0061] When the phase adjustment amount of the phase adjustment circuit 40 is set to a candidate value (DLY_0), the comparison circuit 60 receives the DC voltage signal V input from the demodulation unit 50_2. P6 , V N6 The difference in voltage is ΔV HOLD1 The sample is then held by the sample-and-hold circuit 61 (S102).

[0062] The control circuit 70 switches the candidate value of the phase adjustment amount in the phase adjustment circuit 40 to another candidate value (DLY_1) (S103, S104). When the phase adjustment amount of the phase adjustment circuit 40 is set to the candidate value (DLY_1), the comparison circuit 60 receives the DC voltage signal V input from the demodulation unit 50_2. P6 , V N6 The difference is ΔV HOLD2 The sample is then held by the sample-and-hold circuit 62 (S105).

[0063] The comparison circuit 60 is the difference ΔV HOLD1 and difference ΔV HOLD2 Compare with (S106). ΔV HOLD2 ΔV HOLD1 If it is greater than (DLY_1), the control circuit 70 updates the parameter α with the candidate value of the current phase adjustment amount (S107). The control circuit 70 also updates the difference ΔV held in the sample-and-hold circuit 62. HOLD2 The difference ΔV is applied to the sample-and-hold circuit 61. HOLD2 It is held as (same step S107). More specifically, the control circuit 70 controls the DC voltage signal V at the current candidate value of the phase adjustment amount (DLY_1). P6 , V N6 The DC voltage signal V is input to the sample-and-hold circuit 61. P6 , V N6 The difference in voltage is ΔV HOLD1 The sample is then held by the sample-and-hold circuit 61.

[0064] By repeating steps S103 to S107 for all remaining candidate values ​​of the phase adjustment amount (DNY_M: M is 3 to N), the parameter α is determined by the DC voltage signal V P6 , V N6 The phase adjustment amount that maximizes the difference is stored. The control circuit 70 determines the phase adjustment amount stored in parameter α to the set value DLYSET of the phase adjustment amount in the phase adjustment circuit 40.

[0065] Figure 12 shows an example of the timing charts for each signal in the comparator circuit 60. Figure 12 shows timing charts TA, TB-1, and TB-2. Timing chart TA is the timing chart for the operation performed when the candidate value DLY_0 is set as the initial value. Timing chart TB-1 is the operation that follows the operation corresponding to timing chart TA, when the candidate value DLY_1 is set and ΔV HOLD1 ΔV HOLD2 This is the timing chart for when it is determined to be greater than . Timing chart TB-2 sets the candidate value DLY_1 and ΔV after the operation corresponding to timing chart TA. HOLD2 ΔV HOLD1 This is the timing chart for when the value is judged to be greater than [a certain value]. Therefore, after timing chart TA, the next step is to proceed to either timing chart TB-1 or TB-2. Timing charts TA, TB-1, and TB-2 are explained in relation to the flowchart in Figure 12.

[0066] [Timing Chart TA] The control circuit 70 sets the candidate value DLY_0 in the phase adjustment circuit 40 (S101), and the DC voltage signal V is output from the demodulation unit 50_2. P6 , V N6 The signal V is input to the sample-and-hold circuit 61. The sample-and-hold circuit 61 receives the signal SMPL1 from the control circuit 70 and receives the DC voltage signal V P6 , V N6 The voltage difference ΔV HOLD1 It holds (S102).

[0067] [Timing Chart TB-1] The control circuit 70 sets the candidate value DLY_1 in the phase adjustment circuit 40 (S103, S104), and the DC voltage signal V is output from the demodulation unit 50_2. P6 , V N6 This is input to the sample-and-hold circuit 62. The sample-and-hold circuit 62 receives the signal SMPL2 from the control circuit 70 and receives the DC voltage signal V P6 , V N6 The voltage difference ΔV HOLD2 It retains (S105).

[0068] In comparator 63, ΔV HOLD1 and ΔV HOLD2 These are compared (S106). As can be understood from Figure 12, ΔV HOLD1 ΔV HOLD2 Because it is larger, the comparator 63 outputs the signal V indicating the comparison result. CMP A low-level signal is output. The control circuit 70 inputs a LATCH signal to the latch circuit 64, which latches the low level and outputs the signal AMPDET. The signal AMPDET is the signal V CMP It is the same low-level signal.

[0069] The control circuit 70 controls ΔV based on the signal AMPDET. HOLD1 ΔV HOLD2 Recognizing the larger value (No. S106), the control circuit 70 uses the difference in the voltage held by the sample-and-hold circuit 61 as the current ΔV. HOLD1 While maintaining this, the phase adjustment amount in the phase adjustment circuit 40 is changed to the next candidate value DLY_2 (S103, 104). The DC voltage signal V output from the demodulation unit 50_2 P6 , V N6 V HOLD1_P2 , V HOLD1_N2 This is then input to the sample-and-hold circuit 62.

[0070] [Timing Chart TB-2] The control circuit 70 sets the candidate value DLY_1 in the phase adjustment circuit 40 (S103, S104), and the DC voltage signal V is output from the demodulation unit 50_2. P6 , V N6 This is input to the sample-and-hold circuit 62. The sample-and-hold circuit 62 receives the signal SMPL2 from the control circuit 70 and receives the DC voltage signal V P6 , V N6 The voltage difference ΔV HOLD2 It retains (S105).

[0071] In comparator 63, ΔV HOLD1 and ΔV HOLD2 These are compared (S106). As can be understood from Figure 12, ΔVHOLD2 ΔV HOLD1 Because it is larger, the comparator 63 outputs the signal V indicating the comparison result. CMP A high-level signal is output as follows. The LATCH signal from the control circuit 70 is input to the latch circuit 64, the latch circuit 64 latches the high level and outputs the signal AMPDET. The signal AMPDET is the signal V CMP It is the same high-level signal.

[0072] The control circuit 70 controls ΔV based on the signal AMPDET. HOLD2 ΔV HOLD1 Recognizes that it is greater (Yes in S106). The control circuit 70 controls the difference ΔV of the voltage held by the sample-and-hold circuit 62. HOLD2 And ΔV in the sample-and-hold circuit 61 HOLD1 Maintain this state (S107). Specifically, the control circuit 70 maintains the state in which DLY_1 is set in the phase adjustment circuit 40, and the DC voltage signal V output from the demodulation unit 50_1 is maintained. P6 , V N6 These are input to the sample-and-hold circuit 61. The control circuit 70 outputs the signal SMPL1 to the sample-and-hold circuit 61, thereby generating the DC voltage signal V P6 , V N6 The voltage difference is held in the sample-and-hold circuit 61. As can be seen from Figure 12, ΔV is held in accordance with the sampling timing of the signal SMPL1. HOLD1 The value of is increasing. Therefore, the control circuit 70 changes the phase adjustment amount in the phase adjustment circuit 40 to the next candidate value DLY_2, and the DC voltage signal V output from the demodulation unit 50_2 is changed. P6 , V N6 This is input to the sample-and-hold circuit 62 (S103, 104).

[0073] As described above, according to this embodiment, by maximizing the difference in DC voltage output from demodulation unit 50_2, the phase of the clock signals input to demodulation units 50_1 and 50_2 can be optimized. This maximizes or increases the amplitude of the analog signal (restored signal) output from demodulation unit 50_1, and maximizes or increases the signal-to-noise ratio of the restored signal.

[0074] Furthermore, according to this embodiment, the phase adjustment amount to be set in the phase adjustment circuit 40 is determined using the DC voltage output from the demodulation unit 50_2, rather than the output signal from the demodulation unit 50_1. This makes it possible to optimize the phase adjustment amount to be set in the phase adjustment circuit 40 even when no analog signal is input to the primary side or when no device for inputting an analog signal is connected to the primary side.

[0075] (Fourth Embodiment) Figure 13 shows an example configuration of the isolation amplifier 400 as an electronic circuit according to the fourth embodiment. The configuration for modulating the input signal into a high-frequency signal and demodulating the high-frequency signal into an analog signal, and the configuration for adjusting the phase of the clock signal using the result of demodulating the clock signal, are the same as in the third embodiment. Furthermore, the configurations of the electromagnetic field coupling unit 1 and the electromagnetic field coupling unit 2 are assumed to be the same or substantially the same.

[0076] In this fourth embodiment, a reference voltage generation circuit 420 and a modulation unit 410 (fourth conversion circuit) are provided on the primary side. The reference voltage generation circuit 420 generates a reference voltage signal V REF1A , V REF1B Generates a reference voltage signal V. REF1A , V REF1B These have different DC voltages (reference voltages), and as an example, the reference voltage signal V REF1A The voltage is the reference voltage signal V REF1B The voltage is greater than the reference voltage signal V. REF1A , V REF1B The voltage it possesses is used as the reference voltage signal V REF1A , V REF1B Using the same reference sign, the reference voltage V REF1A , V REF1B It is written as follows: Reference voltage signal V REF1A , V REF1B This corresponds to the first reference voltage signal generated by the reference voltage generation circuit 420.

[0077] The modulation unit 410 (fourth conversion circuit) uses the clock signals CLKA and CLKB generated by the clock generation circuit 20 to generate the reference voltage signal V REF1A , V REF1BThis signal is converted to a pulsed signal (or clock signal) and a high-frequency reference voltage signal V A1 , V B1 The following is output. Here, the pulsed signal (or clock signal) refers to a periodic rectangular wave signal having a pulse width and amplitude similar to that of the clock signals CLKA and CLKB mentioned above. High-frequency reference voltage signal V A1 , V B1 This corresponds to the third signal obtained by converting the first reference voltage signal based on the first clock signal (clock signals CLKA, CLKB). The third signal is a pulsed signal having a frequency (period) corresponding to the first clock signal.

[0078] The configuration of the modulation unit 410 is the same as that of the modulation unit 10 (see Figure 4). In Figure 4(A) or Figure 4(B), the reference voltage signal V REF1A The reference voltage signal V is input to terminal INA. REF1B The following is input to terminal INB: Reference voltage signal V REF1A , V REF1B However, by sampling in opposite directions according to the clock signals CLKA and CLKB, a high-frequency reference voltage signal V is transmitted from terminal OUTA. A1 The output is generated, and a high-frequency reference voltage signal V is output from terminal OUTB. B1 The output is a high-frequency reference voltage signal V. A1 , V B1 Each of these contains information about the clock signals CLKA and CLKB, and the reference voltage signal V. REF1A , V REF1B It includes voltage information.

[0079] In the first to third embodiments, clock signals CLKA and CLKB were input to the electromagnetic field coupling unit 2, but in the fourth embodiment, a high-frequency reference voltage signal V from the modulation unit 410 was input to the electromagnetic field coupling unit 2. A1 , V B1 The following is input: High-frequency reference voltage signal V A1 , V B1 This is transmitted to the secondary side via the electromagnetic field coupling unit 2.

[0080] On the secondary side, the transmitted high-frequency reference voltage signal V A1 , V B1The high-frequency reference voltage signal V is input to the waveform shaping circuit 30. A1 , V B1 The waveform is shaped by the waveform shaping circuit 30, and its phase is further adjusted by the phase adjustment circuit 40. The high-frequency reference voltage signal V has been waveform shaped and phase adjusted. A1 , V B1 These are supplied to the demodulation units 50_1 and 50_2 as clock signals CLKA1 and CLKB1.

[0081] Furthermore, the high-frequency reference voltage signal V transmitted via the electromagnetic field coupling unit 2 A1 , V B1 This is also input to the demodulation unit 50_2 (5th conversion circuit). High-frequency reference voltage signal V A1 , V B1 In the demodulation unit 50_2, based on the clock signals CLKA1 and CLKB1 from the phase adjustment circuit 40, the high-frequency reference voltage signal V A1 , V B1 DC voltage signal V corresponding to the amplitude P7 , V N7 It is converted into a (second DC voltage signal). That is, the high-frequency reference voltage signal V A1 , V B1 The signal is demodulated (reduced to a lower frequency) based on the clock signals CLKA1 and CLKB1. The operation of the demodulation unit 50_2 is the same as in the third embodiment, except that the input signal is different.

[0082] More specifically, the frequency converter 51_2 in the demodulation unit 50_2 receives the input high-frequency reference voltage signal V A1 , V B1These signals are sampled in opposite directions based on the clock signals CLKA1 and CLKB1 input from the phase adjustment circuit 40 to obtain non-pulsed signals DA1 and DB1 (fourth signals). A non-pulsed signal (or non-clock signal) here refers to a signal in which at least one of the pulse width and amplitude of the above-mentioned pulsed signal is reduced, resulting in a signal where the DC component is dominant, and a high-frequency component corresponding to at least one of the reduced pulse width and amplitude may remain. Signals DA1 and DB1 are amplified by amplifier 52_2, and the amplified signals are input to low-pass filter 53_2. The low-pass filter 53_2 filters the amplified signal to remove the high-frequency component (clock signals CLKA1 and CLKB1 and high-frequency reference voltage signal V A1 , V B1 The high-frequency components contained in the signal are attenuated or reduced, and the attenuated or reduced signal becomes a DC voltage signal V P7 , V N7 It is output as (second DC voltage signal). DC voltage signal V P7 , V N7 This is input to the comparison circuit 60. The comparison circuit 60 operates in the same manner as in the third embodiment to produce a signal (comparison result signal) V indicating the comparison result. CMP The signal is generated and sent to the control circuit 70. The control circuit 70, similar to the third embodiment, obtains multiple comparison results by setting multiple candidate phase adjustment amounts in the phase adjustment circuit 40, and determines the phase adjustment amount to be set in the phase adjustment circuit 40.

[0083] Furthermore, the DC voltage signal V output from the demodulation unit 50_2 P7 , V N7 This is input to the comparison circuit 440. The reference voltage generation circuit 430 generates the reference voltage signal V REF2A , V REF2B It generates and outputs to the comparison circuit 440. Reference voltage signal V REF2A , V REF2B These have different DC voltages. Reference voltage signal V REF2A , V REF2B The DC voltage it possesses is used as the reference voltage signal V REF2A , V REF2B Using the same reference sign, the reference voltage V REF2A , V REF2BIt should be written as follows: Reference voltage V REF2A , V REF2B The difference (ΔREF) is the reference voltage V generated by the reference voltage generation circuit 420. REF1A , V REF1B This is the same value as the difference. Reference voltage V REF2A The reference voltage V REF1A The same value is also acceptable. Reference voltage V REF2B The reference voltage V REF1B The same value is also acceptable. Reference voltage V REF2A , V REF2B This corresponds to the second reference voltage.

[0084] The comparison circuit 440, in response to the trigger signal from the control circuit 70, sets the reference voltage V REF2A , V REF2B The difference (denoted as difference ΔREF) and the DC voltage signal V P7 , V N7 The difference (denoted as difference ΔDC) is compared with the signal (comparison result signal) V, which shows the comparison result. CMP1 Obtain the comparison result signal V. CMP1 This is a signal that indicates, for example, whether the difference ΔDC is greater than the difference ΔREF. Comparison result signal V CMP1 This is input to the control circuit 70. Comparing the difference ΔDC and the difference ΔREF is performed to obtain the second DC voltage signal (DC voltage signal V P7 , V N7 This corresponds to an example of comparing the voltage of ( ) with the second reference voltage.

[0085] The control circuit 70 receives the comparison result signal V CMP1 Accordingly, the amplification amount (gain) of amplifier 52_1 of demodulation unit 50_1 and amplifier 52_2 of demodulation unit 50_2 are adjusted. More specifically, the control circuit 70 adjusts the gain adjustment signals output to amplifier 52_1 and amplifier 52_2, respectively.

[0086] The control circuit 70 receives the comparison result signal V CMP1Based on this, if the difference ΔDC is greater than the difference ΔREF, the gain adjustment signals output to amplifiers 52_1 and 52_2 are modified so that the gains of amplifiers 52_1 and 52_2 decrease. The amount of decrease may be a fixed amount, a fixed percentage, or a value determined by other methods. The amount of change in the gains of amplifiers 52_1 and 52_2 may be the same or different.

[0087] If the difference ΔDC is less than the difference ΔREF, the control circuit 70 modifies the gain adjustment signals output to amplifiers 52_1 and 52_2 so that the gains of amplifiers 52_1 and 52_2 increase. The amount of gain increase may be a fixed amount, a fixed percentage, or a value determined by other methods. The amount of gain change for amplifiers 52_1 and 52_2 may be the same or different.

[0088] Since the configurations of electromagnetic field coupling section 1 and electromagnetic field coupling section 2 are identical or substantially identical, the attenuation amounts in electromagnetic field coupling section 1 and electromagnetic field coupling section 2 are also identical or substantially identical. Therefore, the DC voltage signal V P7 , V N7 The difference in voltage is the reference voltage V REF2A , V REF2B By changing the gains of amplifiers 52_1 and 52_2 to match the difference, the attenuation generated in electromagnetic field coupling sections 1 and 2 can be canceled on the secondary side. This makes it possible to calibrate the gain from input to output of this electronic circuit.

[0089] Figure 14 shows an example of the operation flow for adjusting the gain of amplifiers 52_1 and 52_2 by the comparator circuit 440 and the control circuit 70. The gain adjustment operation may be performed once after power-on and after the phase adjustment of the clock signal is completed, or it may be performed continuously while the circuit is operating after the phase adjustment is completed. Alternatively, the gain adjustment operation may be performed when a signal to execute gain adjustment is input from an external device, or it may be performed periodically at arbitrary intervals using a timer or the like.

[0090] The comparison circuit 440 compares the voltage difference ΔDC of the DC voltage signal from the demodulation unit 50_2 with the reference voltage V REF2A , V REF2BA comparison is made with the difference ΔREF (S201).

[0091] If the difference ΔDC is greater than the difference ΔREF, the control circuit 70 modifies the gain adjustment signals output to amplifiers 52_1 and 52_2 so that the gain of amplifiers 52_1 and 52_2 decreases (S202). If the difference ΔDC is less than the difference ΔREF, the control circuit 70 modifies the gain adjustment signals output to amplifiers 52_1 and 52_2 so that the gain of amplifiers 52_1 and 52_2 increases (S203).

[0092] As described above, according to this embodiment, the phase difference between the high-frequency signal and the clock signal can be reduced, the analog signal can be restored with the maximum amplitude, and the signal-to-noise ratio can be maximized or increased.

[0093] (Fifth embodiment) Figure 15 shows an example configuration of a power converter 500 using an isolation amplifier 100 according to the first embodiment. Instead of the isolation amplifier 100 according to the first embodiment, an isolation amplifier according to any of the second to fourth embodiments may be used.

[0094] The power converter 500 has terminal T D It is connected to the load device 600 via [a certain method]. The power converter 500 is provided with a high-voltage circuit and a low-voltage circuit. On the high-voltage side, a switching element M 11 M 12 These are connected in series. Switching element M 11 One end is terminal T D It is connected to the load device 600 via and the other end is connected to a switching element M 12 It is connected to one end of the switching element M. 12 The other end is connected to the reference potential. Terminal T D The voltage is V D Switching element M 11 M 12 Examples of such elements include switching elements such as GaN elements, LVMOS elements, or SiC elements. Switching element M 11For example, a normally-on type, a switching element M 12 For example, it is a normally-off type. The power converter 500 has a switching element M 11 M 12 By turning it on and off, terminal T D It supplies power to the connected load device 600.

[0095] A drive circuit 510 (gate driver) is provided on the high-voltage side. The drive circuit 510 (gate driver) is a switching element M 11 M 12 A gate signal (control signal) is supplied to the gate terminal (control terminal) of the switching element M. The gate signal controls the switching element M. 11 M 12 The on and off states of each are switched, and the current I flowing through the load device 600 D This is controlled. In order to reduce losses due to switching elements and improve the overall conversion efficiency of the power converter, the current I D It is necessary to detect this with high precision and speed and feed it back to the low-voltage control circuit 540.

[0096] Switching element M 12 One end is connected to the positive input terminal of amplifier 520, and the switching element M 12 The other end is connected to the negative input terminal of amplifier 520. Amplifier 520 includes a detection circuit that detects the voltage V1 between these two terminals. Voltage V1 is transmitted through the switching element M 12 The on-resistance (R ON (as stated) and the current I D Based on this, it is calculated using the following formula (1). V1=R ON ×I D (1)

[0097] Amplifier 520 amplifies the detected voltage V1 with amplification factor A and inputs the analog signal (voltage signal) representing the amplified voltage V2 to isolation amplifier 100 via the positive and negative output terminals. The analog signal input from the positive output terminal of amplifier 520 to isolation amplifier 100 corresponds to the analog signal input to the input terminal INP of isolation amplifier 100 in Figure 1. The analog signal input from the negative output terminal of amplifier 520 to isolation amplifier 100 corresponds to the analog signal input to the input terminal INN of isolation amplifier 100 in Figure 1. The amplified voltage V2 in amplifier 520 is equal to the on-resistance R ON And, current I D Based on the amplification factor A, it can be expressed by the following equation (2). V2 = A × V1 = A × R ON ×I D (2)

[0098] The isolation amplifier 100 transmits an analog signal representing the input voltage V2 from the high-voltage side (primary side) to the low-voltage side (secondary side), and outputs the voltage V3 represented by the transmitted analog signal to the control circuit 540 on the low-voltage side. The voltage difference between the analog signal output from the output terminal OUTP (see Figure 1) of the isolation amplifier 100 and the analog signal output from the output terminal OUTN (see Figure 1) corresponds to the voltage V3. If the amplification factor of the isolation amplifier 100 is 1 (0 dB), the voltage V3 is expressed by the following equation (3). V3 = V2 = A × R ON ×I D (3)

[0099] On the low-voltage side (secondary side), the control circuit 540 switches the switching element M based on the voltage V3 indicated by the signal input from the isolation amplifier 100. 11 M 12 The control circuit 540 determines the on / off timing and generates a timing signal that indicates the determined timing. More specifically, based on equation (3), the control circuit 540 determines the amplification factor A of the amplifier 520 and the switching element M 12 On-resistance R ON From voltage V3 and current ID Calculate the value of the calculated current I D Depending on the value, the switching element M 11 M 12 This determines the on / off timing of the switching element M. 11 M 12 It performs gate control. The control circuit 540 has a switching element M 11 M 12 A timing signal indicating the on / off timing of the switching element M is transmitted to the drive circuit 510 via the isolator 550. The isolator 550 is an insulating part that insulates the primary side and the secondary side. A capacitor or a transformer can be used as the configuration of the isolator 550 (see Figure 4). A photocoupler or a digital isolator may also be used for the isolator 550. Based on the timing signal received from the low-voltage control circuit 540 via the isolator 550, the drive circuit 510 generates a gate signal and switches the switching element M 11 M 12 To supply.

[0100] As described above, according to this embodiment, terminal T on the high-voltage side D The current I that flows in D It detects the current I D A signal indicating the corresponding voltage can be fed back to the low-voltage control circuit with a high signal-to-noise ratio. Therefore, the control circuit uses a switching element M 11 M 12 This improves the accuracy of the feedback control of the switching element M. 11 M 12 This reduces losses due to switching and improves the overall conversion efficiency of the power converter.

[0101] In this embodiment, examples of measurement and signal transmission via isolation are shown as application examples, but the applications of the present invention are not limited to this example and can be applied to analog signal processing in general. For example, a circuit similar to that in Figure 15 can be used for applications such as canceling DC offset.

[0102] It should be noted that the present invention is not limited to the embodiments described above, and the components can be modified and implemented in practice without departing from the spirit of the invention. Furthermore, various inventions can be formed by appropriately combining the multiple components disclosed in the above embodiments. For example, some components may be deleted from all the components shown in the embodiments. Moreover, components from different embodiments may be appropriately combined.

[0103] Furthermore, this embodiment can also be configured as follows. [Item 1] A clock generation circuit that generates the first clock signal, A first conversion circuit that converts an input signal into a first signal having a frequency corresponding to the first clock signal based on the first clock signal, A first electromagnetic field coupling unit that transmits the first signal by electromagnetic field coupling, A second electromagnetic field coupling unit that transmits the first clock signal by electromagnetic field coupling, A second conversion circuit that converts the first signal transmitted by the first electromagnetic field coupling unit into a second signal having a frequency corresponding to the input signal, based on the first clock signal transmitted by the second electromagnetic field coupling unit, An electronic circuit equipped with [a specific feature / feature]. [Item 2] The system includes a phase adjustment circuit that adjusts the phase of the first clock signal transmitted by the second electromagnetic field coupling unit to generate a second clock signal, The second conversion circuit converts the frequency of the first signal based on the second clock signal. The electronic circuit described in item 1. [Item 3] The system includes a waveform shaping circuit that shapes the waveform of the first clock signal transmitted by the second electromagnetic field coupling unit, The phase adjustment circuit adjusts the phase of the first clock signal based on the waveform of the first clock signal, The amount of phase adjustment of the first clock signal in the phase adjustment circuit is based on the amount of phase delay of the first clock signal generated in the waveform shaping circuit. The electronic circuit described in item 2. [Item 4] The waveform shaping circuit shapes the waveform of the first clock signal by amplifying the first clock signal. The electronic circuit described in item 3. [Item 5] The waveform shaping circuit shapes the waveform of the first clock signal by clipping the first clock signal. The electronic circuit described in item 3. [Item 6] A third conversion circuit converts the first clock signal transmitted by the second electromagnetic field coupling unit into a first DC voltage signal corresponding to the amplitude of the first clock signal, based on the second clock signal. The system comprises a control circuit that determines the amount of phase adjustment to be adjusted by the phase adjustment circuit based on the voltage of the first DC voltage signal, The phase adjustment circuit adjusts the phase of the first clock signal by the phase adjustment amount determined by the control circuit. An electronic circuit as described in any one of items 2 through 5. [Item 7] The control circuit causes the phase adjustment circuit to perform phase adjustment using a plurality of candidate phase adjustment amounts. For each candidate, it acquires the voltage of the first DC voltage signal and, based on the voltage acquired for each candidate, determines the phase adjustment amount to be adjusted by the phase adjustment circuit from the plurality of candidate phase adjustment amounts. The electronic circuit described in item 6. [Item 8] The control circuit determines the phase adjustment amount for which the maximum voltage is obtained as the phase adjustment amount to be adjusted by the phase adjustment circuit. The electronic circuit described in item 7. [Item 9] The system further comprises a fourth conversion circuit that converts a first reference voltage signal having a first reference voltage, based on the first clock signal generated by the clock generation circuit, into a pulsed third signal having a frequency corresponding to the first clock signal. The second electromagnetic field coupling unit transmits the third signal via the electromagnetic field coupling, A fifth conversion circuit that converts the third signal transmitted by the second electromagnetic field coupling unit based on the second clock signal into a second DC voltage signal according to the amplitude of the third signal, The system further comprises a control circuit that determines the amount of phase adjustment to be adjusted by the phase adjustment circuit based on the voltage of the second DC voltage signal, The phase adjustment circuit adjusts the phase of the first clock signal by the phase adjustment amount determined by the control circuit. The electronic circuit according to any one of claims 2 to 8. [Item 10] The second conversion circuit includes a frequency converter that converts the first signal transmitted by the first electromagnetic field coupling unit into a fifth signal having a frequency corresponding to the input signal based on a second clock, and a first amplifier that amplifies the fifth signal, wherein the second signal is a signal based on the fifth signal amplified by the first amplifier. The fifth conversion circuit includes a frequency converter that converts the third signal into a non-pulsed fourth signal based on the second clock signal, a second amplifier that amplifies the fourth signal, and a low-pass filter that reduces high-frequency components from the amplified fourth signal to obtain the second DC voltage signal. The system further includes a control circuit that controls the gains of the first and second amplifiers based on a comparison between the voltage of the second DC voltage signal and a second reference voltage. The electronic circuit according to claim 9. [Item 11] The second conversion circuit further includes a low-pass filter that reduces high-frequency components from the fifth signal amplified by the first amplifier to obtain the second DC voltage signal. The electronic circuit described in item 10. [Item 12] A fourth conversion circuit converts a first reference voltage signal having a first reference voltage, based on the first clock signal generated by the clock generation circuit, into a pulsed third signal having a frequency corresponding to the first clock signal. The second electromagnetic field coupling unit transmits the third signal via the electromagnetic field coupling, A fifth conversion circuit that converts the third signal transmitted by the second electromagnetic field coupling unit based on the second clock signal into a second DC voltage signal corresponding to the amplitude of the third signal, Furthermore, The second conversion circuit includes a frequency converter that converts the first signal transmitted by the first electromagnetic field coupling unit into a fifth signal having a frequency corresponding to the input signal based on a second clock signal, and a first amplifier that amplifies the fifth signal, wherein the second signal is a signal based on the fifth signal amplified by the first amplifier. The fifth conversion circuit includes a frequency converter that converts the third signal into a non-pulsed fourth signal based on the second clock signal, a second amplifier that amplifies the fourth signal, and a low-pass filter that reduces high-frequency components from the amplified fourth signal to obtain the second DC voltage signal. The system further includes a control circuit that controls the gains of the first and second amplifiers based on a comparison between the voltage of the second DC voltage signal and a second reference voltage. The electronic circuit according to any one of claims 2 to 11. [Item 13] The second conversion circuit includes a low-pass filter that reduces high-frequency components from the fifth signal amplified by the first amplifier to obtain the second DC voltage signal. The electronic circuit described in item 12. [Item 14] The system includes a second phase adjustment circuit that adjusts the phase of the first signal transmitted by the first electromagnetic field coupling unit to generate a sixth signal, The second conversion circuit generates the second signal by converting the frequency of the sixth signal based on the first clock signal. An electronic circuit as described in any one of items 1 through 13. [Item 15] The phase delay amount in the first electromagnetic field coupling section is approximately the same as the phase delay amount in the second electromagnetic field coupling section. An electronic circuit as described in any one of items 3 through 14. [Item 16] The first electromagnetic field coupling unit includes at least one capacitor. The second electromagnetic field coupling unit includes at least one capacitor. An electronic circuit described in any one of items 1 through 15. [Item 17] The first electromagnetic field coupling unit includes at least one transformer. The second electromagnetic field coupling unit includes at least one transformer. An electronic circuit as described in any one of items 1 through 16. [Item 18] A power converter for supplying power to a load device, A first switching element, one end of which is connected to the load device, A second switching element, one end of which is connected to the other end of the first switching element, A detection circuit for detecting an input signal including the voltage at one end of the second switching element and the voltage at the other end of the second switching element, A clock generation circuit that generates the first clock signal, A first conversion circuit that converts the input signal into a first signal having a frequency corresponding to the first clock signal based on the first clock signal, A first electromagnetic field coupling unit that transmits the first signal by electromagnetic field coupling, A second electromagnetic field coupling unit that transmits the first clock signal by electromagnetic field coupling, A second conversion circuit that converts the first signal transmitted by the first electromagnetic field coupling unit into a second signal having a frequency corresponding to the input signal, based on the first clock signal transmitted by the second electromagnetic field coupling unit, A power converter equipped with [a specific feature / equipment]. [Item 19] A control circuit that controls the on and off timing of the first switching element and the second switching element based on the second signal. A power converter as described in item 18, further comprising the features described therein. [Item 20] The control circuit generates timing signals indicating the on and off timings of the first switching element and the second switching element. Based on the timing signal, further comprising a drive circuit that supplies drive signals for driving the first switching element and the second switching element to control terminals of the first switching element and the second switching element. The power converter according to item 19.

Explanation of symbols

[0104] 1, 2 Electromagnetic field coupling part 10 Modulation part 11 Frequency converter 20 Clock generation circuit 30 Waveform shaping circuit 40 Phase adjustment circuit 50, 50_1, 50_2 Demodulation part 51, 51_1, 51_2 Frequency converter 52, 52_1, 52_2 Amplifier 53, 53_1, 53_2 Low-pass filter 60 Comparison circuit 61, 62 Sample-and-hold circuit 63 Comparator 64 Latch circuit 70 Control circuit 90 Insulation barrier 100, 200, 300, 400 Isolation amplifier 240 Phase adjustment circuit 410 Modulation part 420, 430 Reference voltage generation circuit 440 Comparison circuit 500 Power converter 510 Drive circuit 520 Amplifier 540 Control circuit 550 Isolator 600 Load device A1, A2 Terminals B1, B2 Terminals C11~C22 Capacitors CLKA, CLKB Clock signals (first clock signals) CLKA1, CLKB1 Clock signals (second clock signals) DA, DB Signals DA1 and DB1 signals (the 4th signal) GND_T1 and GND_T2 terminals GND1 and GND2 reference potentials I D Current INA and INB terminals INN and INP input terminals Coils L11 to L14 LATCH signal M1 to M4 NMOS transistors M 11 and M 12 Switching element M n1 to M n4 NMOS transistor M p1 to M p4 PMOS transistor OUTA and OUTB terminals OUTN and OUTP output terminals SMPL1 and SMPL2 sampling command signals Transformers T11 and T12 Timing charts TA, TB-1, and TB-2 T D Terminal Voltages V1, V2, and V3 V A1 and V B1 High-frequency reference voltage signal (the 3rd signal) V CMP and V CMP1 Comparison result signal VDD_T1 and VDD_T2 terminals Power supplies VDD1 and VDD2 V P1 and V N1 Input signals V P2 and V N2 High-frequency signal (the 1st signal) V P3 and V N3 Analog signal (the 3rd signal) V P4 and V N4 Output signal (the 2nd signal) V P5 and V N5 High-frequency signal V P6 , V N6 DC voltage signal (first DC voltage signal) V P7 , V N7 DC voltage signal (second DC voltage signal) V REF1A , V REF1B Reference voltage signal (first reference voltage, first reference voltage signal) V REF2A , V REF2B Reference voltage signal (second reference voltage, second reference voltage signal)

Claims

1. A clock generation circuit that generates the first clock signal, A first conversion circuit that modulates an input signal to a first signal having a frequency corresponding to the first clock signal using the first clock signal, A first electromagnetic field coupling unit that transmits the first signal by electromagnetic field coupling, A second electromagnetic field coupling unit that transmits the first clock signal by electromagnetic field coupling, A second conversion circuit that demodulates the first signal transmitted by the first electromagnetic field coupling unit into a second signal having a frequency corresponding to the input signal, using the first clock signal transmitted by the second electromagnetic field coupling unit. An electronic circuit equipped with [a specific feature / feature].

2. The system includes a phase adjustment circuit that adjusts the phase of the first clock signal transmitted by the second electromagnetic field coupling unit to generate a second clock signal, The second conversion circuit demodulates the first signal using the second clock signal. The electronic circuit according to claim 1.

3. The system includes a waveform shaping circuit for shaping the waveform of the first clock signal transmitted by the second electromagnetic field coupling unit, The phase adjustment circuit adjusts the phase of the first clock signal based on the waveform of the first clock signal, The amount of phase adjustment of the first clock signal in the phase adjustment circuit is based on the amount of phase delay of the first clock signal generated in the waveform shaping circuit. The electronic circuit according to claim 2.

4. The waveform shaping circuit shapes the waveform of the first clock signal by amplifying the first clock signal. The electronic circuit according to claim 3.

5. The waveform shaping circuit shapes the waveform of the first clock signal by clipping the first clock signal. The electronic circuit according to claim 3.

6. A third conversion circuit demodulates the first clock signal transmitted by the second electromagnetic field coupling unit using the second clock signal and converts it into a first DC voltage signal corresponding to the amplitude of the first clock signal, The system comprises a control circuit that determines the amount of phase adjustment to be performed by the phase adjustment circuit based on the voltage of the first DC voltage signal, The phase adjustment circuit adjusts the phase of the first clock signal by the phase adjustment amount determined by the control circuit. The electronic circuit according to claim 2.

7. The control circuit causes the phase adjustment circuit to perform phase adjustment using a plurality of candidate phase adjustment amounts, acquires the voltage of the first DC voltage signal for each candidate, and determines the phase adjustment amount to be adjusted by the phase adjustment circuit from the plurality of candidate phase adjustment amounts based on the voltage acquired for each candidate. The electronic circuit according to claim 6.

8. The control circuit determines the phase adjustment amount for which the maximum voltage is obtained as the phase adjustment amount to be adjusted by the phase adjustment circuit. The electronic circuit according to claim 7.

9. The system further includes a fourth conversion circuit that modulates a first reference voltage signal having a first reference voltage, based on the first clock signal generated by the clock generation circuit, into a pulse-like third signal having a frequency corresponding to the first clock signal. The second electromagnetic field coupling unit transmits the third signal via the electromagnetic field coupling. A fifth conversion circuit that demodulates the third signal transmitted by the second electromagnetic field coupling unit using the second clock signal and converts it into a second DC voltage signal according to the amplitude of the third signal, The system further comprises a control circuit that determines the amount of phase adjustment to be adjusted by the phase adjustment circuit based on the voltage of the second DC voltage signal, The phase adjustment circuit adjusts the phase of the first clock signal by the phase adjustment amount determined by the control circuit. The electronic circuit according to claim 2.

10. The second conversion circuit includes a frequency converter that demodulates the first signal transmitted by the first electromagnetic field coupling unit into a fifth signal having a frequency corresponding to the input signal using the second clock signal, and a first amplifier that amplifies the fifth signal, wherein the second signal is a signal based on the fifth signal amplified by the first amplifier. The fifth conversion circuit includes a frequency converter that demodulates the third signal into a non-pulsed fourth signal using the second clock signal, a second amplifier that amplifies the fourth signal, and a low-pass filter that reduces high-frequency components from the amplified fourth signal to obtain the second DC voltage signal. The system further includes a control circuit that controls the gains of the first and second amplifiers based on a comparison between the voltage of the second DC voltage signal and a second reference voltage. The electronic circuit according to claim 9.

11. The second conversion circuit further includes a low-pass filter that reduces high-frequency components from the fifth signal amplified by the first amplifier to obtain the second signal. The electronic circuit according to claim 10.

12. A fourth conversion circuit modulates a first reference voltage signal having a first reference voltage, based on the first clock signal generated by the clock generation circuit, into a pulse-like third signal having a frequency corresponding to the first clock signal. The second electromagnetic field coupling unit transmits the third signal via the electromagnetic field coupling. A fifth conversion circuit that demodulates the third signal transmitted by the second electromagnetic field coupling unit using the second clock signal and converts it into a second DC voltage signal corresponding to the amplitude of the third signal, Furthermore, The second conversion circuit includes a frequency converter that demodulates the first signal transmitted by the first electromagnetic field coupling unit into a fifth signal having a frequency corresponding to the input signal using a second clock signal, and a first amplifier that amplifies the fifth signal, wherein the second signal is a signal based on the fifth signal amplified by the first amplifier. The fifth conversion circuit includes a frequency converter that demodulates the third signal into a non-pulsed fourth signal using the second clock signal, a second amplifier that amplifies the fourth signal, and a low-pass filter that reduces high-frequency components from the amplified fourth signal to obtain the second DC voltage signal. The system further includes a control circuit that controls the gains of the first and second amplifiers based on a comparison between the voltage of the second DC voltage signal and a second reference voltage. The electronic circuit according to claim 2.

13. The second conversion circuit includes a low-pass filter that reduces high-frequency components from the fifth signal amplified by the first amplifier to obtain the second signal. The electronic circuit according to claim 12.

14. The system includes a second phase adjustment circuit that adjusts the phase of the first signal transmitted by the first electromagnetic field coupling unit to generate a sixth signal, The second conversion circuit demodulates the sixth signal using the first clock signal to generate the second signal. The electronic circuit according to claim 1.

15. The phase delay amount in the first electromagnetic field coupling section is approximately the same as the phase delay amount in the second electromagnetic field coupling section. The electronic circuit according to claim 3.

16. The first electromagnetic field coupling unit includes at least one capacitor. The second electromagnetic field coupling unit includes at least one capacitor. The electronic circuit according to claim 1.

17. The first electromagnetic field coupling unit includes at least one transformer. The second electromagnetic field coupling unit includes at least one transformer. The electronic circuit according to claim 1.

18. A power converter for supplying power to a load device, A first switching element, one end of which is connected to the load device, A second switching element, one end of which is connected to the other end of the first switching element, A detection circuit for detecting an input signal including the voltage at one end of the second switching element and the voltage at the other end of the second switching element, A clock generation circuit that generates the first clock signal, A first conversion circuit that converts the input signal into a first signal having a frequency corresponding to the first clock signal based on the first clock signal, A first electromagnetic field coupling unit that transmits the first signal by electromagnetic field coupling, A second electromagnetic field coupling unit that transmits the first clock signal by electromagnetic field coupling, A second conversion circuit that converts the first signal transmitted by the first electromagnetic field coupling unit into a second signal having a frequency corresponding to the input signal, based on the first clock signal transmitted by the second electromagnetic field coupling unit, A power converter equipped with [a specific feature / equipment].

19. A control circuit that controls the on and off timing of the first switching element and the second switching element based on the second signal. The power converter according to claim 18, further comprising:

20. The control circuit generates timing signals indicating the on and off timings of the first switching element and the second switching element. The system further includes a drive circuit that supplies drive signals to the control terminals of the first and second switching elements, based on the timing signal, to drive the first and second switching elements. The power converter according to claim 19.

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