Nanosynaptic integrated device and method for manufacturing the same

Abstract

The present invention discloses a nanosynapse integrated device and a method for manufacturing the same. The nanosynapse integrated device includes a substrate, an insulating layer disposed on the substrate, and a plurality of nanosynapse units disposed on the insulating layer. Each nanosynapse unit includes a first microelectrode and a second microelectrode disposed opposite each other, and a GaN-based nanowire disposed between the first and second microelectrodes. The GaN-based nanowire has a first end connected to the first microelectrode and a second end connected to the second microelectrode. The present invention uses GaN-based nanowires as synaptic elements in the device, and the GaN-based nanowires have controllable direct transitions and stable physicochemical properties. In the nanosynapse integrated device, the plurality of nanosynapse units are integrated on the same substrate, allowing for large-scale fabrication, a small volume, and high integration. The plurality of nanosynapse units can be controlled independently or can be subject to overall array control according to an array pattern.

Description

Technical Field

[0001] The present invention relates to the technical field of artificial nerves, and specifically to a nano-synapse integrated device and a manufacturing method thereof.

Background Art

[0002] In the nervous system of the human brain, a synapse is defined as the junction point between two neurons and serves as an important pathway for transmitting nerve impulses from the presynaptic neuron to the postsynaptic neuron. When an electrical signal is sent to the presynaptic neuron, an electrical spike called an action potential occurs, and then a chemical substance (so-called neurotransmitter) is released through the synaptic cleft to trigger an impulse in the postsynaptic neuron. An artificial synapse mimics a biological synapse in a neuromorphic computing system and is applied to various detection devices and bioionic structures based on such a synapse structure.

[0003] In recent years, with the rapid development of big data, the Internet, and artificial intelligence, a conventional computing system based on the von Neumann architecture (an independent memory and storage unit) has difficulty meeting future application needs. In contrast, the human brain has remarkable capabilities when processing a large amount of data, and can simultaneously store, integrate, and process information through a dense cooperative network of synapses and neurons. When processing an analog signal detected by a sensory organ, such as visual information received by the retina, the human brain can significantly reduce energy consumption and improve the efficiency of data management. The interconnected neural network performs distributed processing to achieve high-speed computing capabilities. Inspired by the human brain, artificial synapse devices have already emerged and are widely noted for their ability to process and store data simultaneously. Therefore, artificial synapses are expected to become an essential core component of the next-generation computing system.

[0004] Nanowires possess outstanding characteristics such as a high surface-to-volume ratio and small volume, making them suitable for effectively simulating the learning and cognition processes of artificial synapses. Currently, the manufacturing difficulty of nanosynaptic devices is high, resulting in extremely low integration densities. Therefore, high-density integrated systems based on nanosynaptic devices are difficult to manufacture, severely limiting their application in fields such as neuromorphic computing systems. [Overview of the project] [Problems that the invention aims to solve]

[0005] In view of this, the present invention provides a nanosynaptic integrated device with a simple manufacturing process and high integration density, and a method for manufacturing the same. [Means for solving the problem]

[0006] To achieve the above objective, the present invention employs the following technical solutions.

[0007] Nanosynaptic integration devices are circuit board and An insulating layer installed on the substrate, The insulating layer includes a plurality of nanosynaptic units, The nanosynaptic unit includes a first microelectrode and a second microelectrode positioned opposite each other, and a GaN-based nanowire positioned between the first and second microelectrodes, wherein the first end of the GaN-based nanowire is coupled to the first microelectrode and the second end is coupled to the second microelectrode.

[0008] In a preferred solution, the GaN-based nanowire is a GaN nanowire, an AlGaN nanowire, or an InGaN nanowire.

[0009] In a preferred solution, the thickness of the first microelectrode and the second microelectrode is 50 nm to 500 nm, and the pitch between the first microelectrode and the second microelectrode is 0.8 μm to 5 μm.

[0010] In a preferred solution, the multiple nanosynaptic units are arranged in an M x N array on the insulating layer, where M and N are positive integers.

[0011] In a preferred solution, in the nanosynapse unit, the first microelectrode is electrically connected to a first external electrode, the second microelectrode is electrically connected to a second external electrode, the first microelectrodes of all the nanosynapse units are each connected in a one-to-one correspondence to one first external electrode, and the second microelectrodes of all the nanosynapse units are commonly connected to the same second external electrode, or the first microelectrodes of all the nanosynapse units are commonly connected to the same first external electrode, and the second microelectrodes of all the nanosynapse units are commonly connected to the same second external electrode.

[0012] In a preferred solution, a first coating electrode is formed on the first microelectrode so as to cover the first end of the GaN-based nanowire, and a second coating electrode is formed on the second microelectrode so as to cover the second end of the GaN-based nanowire.

[0013] In a preferred solution, the thicknesses of the first coated electrode and the second coated electrode are 80 nm to 200 nm, respectively.

[0014] In a preferred solution, the first microelectrode and the first coated electrode both constitute a source electrode, the second microelectrode and the second coated electrode both constitute a drain electrode, and a gate layer is formed on the surface of the substrate opposite to the insulating layer.

[0015] A method for manufacturing a nanosynaptic integrated device as described above, according to another aspect of the present invention, The steps include providing a substrate and depositing an insulating layer onto the substrate, A step of manufacturing multiple pairs of opposing first and second microelectrodes on an insulating layer by applying a photolithography process, The steps include growing GaN-based nanowires on an epitaxial substrate, The steps include: peeling the GaN-based nanowire from the epitaxial substrate and transferring it between the first microelectrode and the second microelectrode; The procedure includes the step of coupling both ends of a GaN-based nanowire to a first microelectrode and a second microelectrode, respectively.

[0016] In a preferred solution, after transferring the GaN-based nanowire between the first and second microelectrodes, a dielectrophoresis process is applied to connect both ends of the GaN-based nanowire to the surfaces of the first and second microelectrodes, respectively. The process parameters for the dielectrophoresis process are an AC voltage of 3V to 15V, a frequency of 1kHz to 1MHz, an energizing time of 10min to 20min, and the dielectrophoresis solution is acetone, isopropyl alcohol, or ethanol. [Effects of the Invention]

[0017] In the nanosynaptic integrated device and its manufacturing method according to embodiments of the present invention, GaN-based nanowires are used as synaptic elements in the device. The GaN-based nanowires have controllable direct transitions, stable physicochemical properties, compatibility with conventional semiconductor technology, a mature and stable manufacturing process, and a simple process. They allow for the integration of optoelectronic neuromorphic devices on a chip together with a light source, and can simultaneously provide optical pulse stimulation and electrical pulse stimulation capabilities. In the nanosynaptic integrated device, multiple nanosynaptic units are arranged to be integrated on the same substrate, enabling large-scale manufacturing, resulting in a small volume and high integration density. The integrated multiple nanosynaptic units may be arranged to be independently controllable, or they may be arranged to be subject to overall array control according to an arranged array pattern. [Brief explanation of the drawing]

[0018] [Figure 1] This is a cross-sectional view of the nanosynaptic integration device in Example 1. [Figure 2]It is a schematic configuration diagram when the nanosynapse units in Example 1 are distributed in the insulating layer. [Figure 3] It is a SEM photograph when the GaN-based nanowire in Example 1 is connected between the microelectrodes. [Figure 4] It is a diagram showing the results of the optical pulse stimulation response test with different pulse times in Example 1. [Figure 5] It is a diagram showing the results of the continuous optical pulse stimulation response test in Example 1. [Figure 6] It is a schematic configuration diagram when the nanosynapse units in another preferred embodiment are distributed in the insulating layer. [Figure 7] It is a schematic configuration diagram when the nanosynapse units in a further preferred embodiment are distributed in the insulating layer. [Figure 8] It is a cross-sectional view of the nanosynapse integrated device in Example 2. [Figure 9] It is a diagram showing the results of the test simulating the synaptic learning behavior in Example 2. [Figure 10] It is a cross-sectional view of the nanosynapse integrated device in Example 3.

Mode for Carrying Out the Invention

[0019] To make the object, technical solution and advantages of the present invention more clear, the specific embodiments of the present invention will be described in detail below with reference to the drawings. Examples of these preferred embodiments are illustratively shown in the drawings. The embodiments of the present invention shown in the drawings and described based on the drawings are merely exemplary, and the present invention is not limited to these embodiments.

[0020] Here, in order to avoid obscuring the present invention with unnecessary details, only the structures and / or processing steps closely related to the solution means according to the present invention are shown in the drawings, and other details less related to the present invention are omitted. (Example 1)

[0021] This embodiment provides a nanosynaptic integration device, where Figure 1 is a cross-sectional view at a position corresponding to one nanosynaptic unit of the nanosynaptic integration device in this embodiment, and Figure 2 is a schematic configuration diagram when the nanosynaptic units in this embodiment are distributed in an insulating layer.

[0022] Referring to Figures 1 and 2, the nanosynaptic integration device includes a substrate 1 and an insulating layer 2 placed on the substrate 1. Multiple nanosynaptic units 3 are placed on the insulating layer 2, and the multiple nanosynaptic units 3 are arranged in an array to form a nanosynaptic unit array 4.

[0023] The nanosynaptic unit 3 includes a first microelectrode 31 and a second microelectrode 32 positioned opposite each other, and a GaN-based nanowire 33 positioned between the first microelectrode 31 and the second microelectrode 32. The GaN-based nanowire 33 has its first end coupled to the first microelectrode 31 and its second end coupled to the second microelectrode 32. In this embodiment, the substrate 1 is a silicon substrate, and the material of the insulating layer 2 is SiO2.

[0024] As a preferred solution, in this embodiment, the GaN-based nanowire is a GaN nanowire. In some other embodiments, the GaN-based nanowire may be an AlGaN nanowire or an InGaN nanowire.

[0025] As a preferred solution, in this embodiment, the thickness of the first microelectrode 31 and the second microelectrode 32 is 80 nm each, and specifically includes a stacked Ti metal layer with a thickness of 20 nm and an Au metal layer with a thickness of 60 nm, and the pitch between the first microelectrode 31 and the second microelectrode 32 is 1 μm. In some other embodiments, the thickness of the first microelectrode 31 and the second microelectrode 32 is preferably set within the range of 50 nm to 500 nm each, and the pitch between the first microelectrode 31 and the second microelectrode 32 is preferably set within the range of 0.8 μm to 5 μm.

[0026] In a preferred solution, the multiple nanosynapse units 3 are arranged in an M x N array on the insulating layer 2, where M and N are positive integers. As shown in Figure 2, in this embodiment, the multiple nanosynapse units 3 are arranged in a 4 x 2 array on the insulating layer 2. In some other embodiments, as shown in Figures 6 and 7, the multiple nanosynapse units 3 are arranged in a 6 x 1 array on the insulating layer 2.

[0027] In a preferred solution, referring to Figure 2, in the nanosynapse unit 3, the first microelectrode 31 is electrically connected to the first external electrode 51, and the second microelectrode 32 is electrically connected to the second external electrode 52. In some embodiments, as shown in Figures 2 and 7, each first microelectrode 31 of all the nanosynapse units 3 is connected to one first external electrode 51 in a one-to-one correspondence, and each second microelectrode 32 of all the nanosynapse units 3 is commonly connected to the same second external electrode 52, so that each nanosynapse unit 3 can be controlled independently.

[0028] In some other embodiments, as shown in Figure 6, the first microelectrodes 31 of all the nanosynapse units 3 are commonly connected to the same first external electrode 51, and the second microelectrodes 32 of all the nanosynapse units 3 are commonly connected to the same second external electrode 52. In this case, all the nanosynapse units 3 need to be controlled simultaneously, that is, all the nanosynapse units 3 may be subjected to overall array control according to the arranged array pattern.

[0029] The method for manufacturing a nanosynaptic integrated device according to this embodiment includes the following steps 1 to 5.

[0030] In step 1, a substrate 1 is provided, and an insulating layer 2 is deposited on the substrate 1.

[0031] In step 2, a photolithography process is applied to fabricate multiple pairs of opposing first microelectrodes 31 and second microelectrodes 32 placed on the insulating layer 2.

[0032] In step 3, molecular beam epitaxial irradiation is applied to grow GaN nanowires on an epitaxial substrate, and these are then transferred to an isopropyl alcohol solution using a physical exfoliation method and dispersed with ultrasound to thoroughly fuse the GaN nanowires with the isopropyl alcohol solution.

[0033] In step 4, the device obtained in step 2 is placed on the probe platform, 5 μL of the solution obtained in step 3 is extracted using a microsyringe and dropped between the first microelectrode 31 and the second microelectrode 32, and one end of the GaN nanowire in the solution is connected to the first microelectrode 31 using dielectrophoresis, and the other end of the GaN nanowire is connected to the second microelectrode 32. For the process parameters of the above dielectrophoresis process, an AC voltage of 3V to 15V may be selected, the frequency may be set to 1kHz to 1MHz, the energizing time may be within the range of 10min to 20min, which is sufficient for the solution to completely evaporate, and acetone, isopropyl alcohol, or ethanol may be selected as the dielectrophoresis solution.

[0034] In step 5, the device obtained in step 4 is placed in an annealing furnace and subjected to high-temperature annealing to bond both ends of the GaN nanowire to the first microelectrode 31 and the second microelectrode 32, respectively, thereby fabricating a nanosynaptic integrated device.

[0035] When the surface of the obtained nanosynaptic integrated device was observed with an electron scanning electron microscope (SEM), it was found that a single GaN nanowire was connected between two microelectrodes, as shown in Figure 3.

[0036] In this embodiment, the nanosynaptic integrated device obtained was subjected to an optical pulse stimulation test. Specifically, the first external electrode 51 and the second external electrode 52 were connected to both ends of a DC power supply, and a DC voltage of 5V was applied to the first microelectrode 31 and the second microelectrode 32 via the first external electrode 51 and the second external electrode 52, and optical pulse stimulation was performed by irradiating the GaN nanowire with ultraviolet light. (1) Multiple sets of tests were performed with the output power of the ultraviolet lamp set to 2W and the pulse times set to 100ms, 250ms, 500ms, 1000ms, and 1500ms, respectively. As shown in the test results in Figure 4, in each set of tests, if there are two optical pulse stimuli, the device has a memory function for the photon signals detected. (2) A continuous optical pulse stimulation test was performed on the GaN nanowire with the output power of the ultraviolet lamp set to 2W and the pulse time set to 1s. As shown in the test results in Figure 5, when there is continuous stimulation from the signal source, the device continues to respond, and after the signal source stops, the device's response gradually returns to its initial state. As the test results show, by changing the light power, pulse duration, and pulse frequency of ultraviolet light, performance similar to that of a nerve synapse can be obtained, providing the capabilities of light pulse stimulation.

[0037] An electrical pulse stimulation test was performed on the nanosynaptic integration device obtained in this embodiment. Specifically, the first external electrode 51 and the second external electrode 52 were connected to both ends of a pulse power supply, and a pulse voltage was applied to the first microelectrode 31 and the second microelectrode 32 via the first external electrode 51 and the second external electrode 52, with a voltage amplitude of 3V and a voltage pulse duration of 100ms. As can be seen from the test results, by changing the duration, number, and voltage of the voltage pulses, performance similar to that of a nerve synapse can be obtained, and the device possesses the performance of electrical pulse stimulation. (Example 2)

[0038] The nanosynaptic integration device according to this embodiment is installed with the following additional structure based on the structure of the device according to Embodiment 1. Referring to Figure 8, a first covering electrode 61 is formed on the first microelectrode 31 so as to cover the first end of the GaN-based nanowire 33, and a second covering electrode 62 is formed on the second microelectrode 32 so as to cover the second end of the GaN-based nanowire 33.

[0039] In this embodiment, the first microelectrode 31 and the first coated electrode 61 both constitute a source electrode, and the second microelectrode 32 and the second coated electrode 62 both constitute a drain electrode.

[0040] In this embodiment, the thickness of the first coated electrode 61 and the second coated electrode 62 is 80 nm each. In some other embodiments, the thickness of the first coated electrode 61 and the second coated electrode 62 may be set within the range of 80 nm to 200 nm.

[0041] The differences between this embodiment and Embodiment 1 regarding the manufacturing process of the nanosynaptic integrated device are as follows. Referring to the steps of the manufacturing process of Embodiment 1, in step 4, after connecting the two microelectrodes by wrapping a GaN nanowire between them, first, the first coated electrode 61 is manufactured and formed on the first microelectrode 31 using the overlay method, and the second coated electrode 62 is manufactured and formed on the second microelectrode 32, and then the annealing bonding process in step 5 is performed.

[0042] An electrical pulse stimulation test is performed on the nanosynaptic integrated device obtained in this embodiment. Specifically, the first external electrode 51 and the second external electrode 52 are connected to both ends of a pulse power supply, and a pulse voltage is applied to the source electrode and the drain electrode via the first external electrode 51 and the second external electrode 52. The voltage amplitude is set to 5V and the voltage pulse time to 1s. The source electrode simulates a presynaptic neuron, the drain electrode simulates a postsynaptic neuron, the pulse power supply simulates presynaptic stimulation, and the GaN nanowire simulates the synaptic effect.

[0043] Figure 9 shows the results of a test simulating synaptic learning behavior. A total of four tests were performed sequentially. As shown in Figure 9, from left to right, after completing 20 pulse stimuli for the first group, the electrical stimulation was stopped for a certain period of time before performing 20 pulse stimuli for the second group. After completing 20 pulse stimuli for the second group, the electrical stimulation was stopped for a certain period of time before performing 20 pulse stimuli for the third group. After completing 20 pulse stimuli for the third group, the electrical stimulation was stopped for a certain period of time before performing 20 pulse stimuli for the fourth group. This simulated the learning-forgetting-relearning process of synapses. The first 20 consecutive pulse stimuli served as the training process for the artificial neural synapse, which is similar to the learning process of the human brain. After the pulse stimuli were removed, the weight of the device gradually decreased, which is similar to the forgetting process of the human brain. After a certain period of time, when pulses were applied again, a small number of pulses were sufficient for the synaptic device to reach the amount of memory it had before forgetting, which is similar to the relearning process of the human brain. As can be seen from Figure 9, the nanosynaptic integration device of this embodiment has the capability to simulate the learning-forgetting-relearning process of synapses. Such a learning-forgetting-relearning process can be used for the learning and discrimination functions of future artificial neural networks.

[0044] Long-term testing and comparison of the nanosynaptic integration device of this embodiment with the device of Example 1 revealed that in this embodiment, applying a coated electrode to the microelectrode effectively protects the contact point between the GaN nanowire and the electrode, thereby improving the reliability of the device. (Example 3)

[0045] The nanosynaptic integrated device according to this embodiment is installed by adding the following structure to the device structure according to Embodiment 2. Referring to Figure 10, a gate layer 7 is formed on the surface of the substrate 1 opposite to the insulating layer 2. In a specific solution, a single PCB circuit board is added below the substrate 1, and the two are connected with silver paste, thereby forming a gate on the PCB circuit board.

[0046] In this embodiment, an electrical pulse stimulation test was performed on the nanosynaptic integrated device obtained. Specifically, a source electrode consisting of a first microelectrode 31 and a first coated electrode 61 was connected to one end of a pulse power supply, the other end of the pulse power supply was connected to the lead port of the gate layer 7, the source electrode was simultaneously connected to one end of a DC power supply, and the other end of the DC power supply was connected to a drain electrode consisting of a second microelectrode 32 and a second coated electrode 62. The voltage of the DC power supply was set to 10V, the voltage of the pulse power supply was set to 5V, and the pulse time was set to 1s. The gate simulates a presynaptic neuron, the drain electrode simulates a postsynaptic neuron, the pulse power supply simulates presynaptic stimulation, the DC power supply supplies energy to the source electrode, and the GaN nanowire simulates a pulse-induced facilitation. In this embodiment, the device can be controlled more easily by adding a gate.

[0047] Based on the above, the nanosynaptic integrated device and its manufacturing method according to the embodiment of the present invention use GaN-based nanowires as synaptic elements in the device, and the GaN-based nanowires have controllable direct transitions, stable physicochemical properties, are compatible with conventional semiconductor technology, have a mature and stable manufacturing process, are simple processes, and can integrate optoelectronic neuromorphic devices on a chip together with a light source, and can simultaneously possess the performance of optical pulse stimulation and electrical pulse stimulation. In the nanosynaptic integrated device, multiple nanosynaptic units are arranged to be integrated on the same substrate, can be manufactured on a large scale, have a small volume and high integration density. In some specific embodiments, multiple nanosynaptic units arranged to be integrated can each be controlled independently, and in some other specific embodiments, the nanosynaptic units arranged to be integrated may be subjected to overall array control according to an arranged array pattern.

[0048] The above embodiments are merely intended to illustrate the technical idea and features of the present invention so that those skilled in the art can understand and implement the invention, and do not limit the scope of protection of the present invention. Any equivalent modifications or alterations made based on the gist of the present invention should be included within the scope of protection of the present invention.

Claims

1. circuit board and An insulating layer installed on the substrate, The insulating layer includes a plurality of nanosynaptic units, The nanosynaptic unit includes a first microelectrode and a second microelectrode positioned opposite each other, and a GaN-based nanowire positioned between the first microelectrode and the second microelectrode, wherein the first end of the GaN-based nanowire is coupled to the first microelectrode and the second end is coupled to the second microelectrode. A nanosynaptic integrated device in which the GaN-based nanowire is stretched across the first microelectrode and the second microelectrode so as to be irradiated with stimulating light, and the stimulating light is irradiated onto the GaN-based nanowire while an operating voltage is applied to the first microelectrode and the second microelectrode.

2. The nanosynaptic integration device according to claim 1, wherein no coated electrodes are formed on the first microelectrode and the second microelectrode.

3. The nanosynaptic integration device according to claim 1, wherein the first microelectrode and the second microelectrode each contain a Ti metal layer.

4. The nanosynaptic integration device according to claim 1, wherein the GaN-based nanowire is a GaN nanowire, an AlGaN nanowire, or an InGaN nanowire.

5. The nanosynaptic integration device according to claim 1, wherein the thickness of the first microelectrode and the second microelectrode is 50 nm to 500 nm, and the pitch between the first microelectrode and the second microelectrode is 0.8 μm to 5 μm.

6. The nanosynaptic integration device according to claim 1, wherein a plurality of the nanosynaptic units are arranged in an M x N array on the insulating layer, where M and N are each positive integers.

7. In the nanosynaptic unit, the first microelectrode is electrically connected to the first external electrode, and the second microelectrode is electrically connected to the second external electrode. The nanosynaptic integration device according to claim 6, wherein each first microelectrode of all the nanosynaptic units is connected in a one-to-one correspondence to one first external electrode, and all the second microelectrodes of all the nanosynaptic units are commonly connected to the same second external electrode, or, all the first microelectrodes of all the nanosynaptic units are commonly connected to the same first external electrode, and all the second microelectrodes of all the nanosynaptic units are commonly connected to the same second external electrode.

8. The steps include providing a substrate and depositing an insulating layer onto the substrate, A step of manufacturing multiple pairs of opposing first and second microelectrodes on an insulating layer by applying a photolithography process, The steps include growing GaN-based nanowires on an epitaxial substrate, The steps include: peeling the GaN-based nanowire from the epitaxial substrate and transferring it between the first microelectrode and the second microelectrode; A method for manufacturing a nanosynaptic integrated device according to claim 1, comprising the step of coupling and connecting both ends of a GaN-based nanowire to a first microelectrode and a second microelectrode, respectively.

9. A method for manufacturing a nanosynaptic integrated device according to claim 8, wherein a GaN-based nanowire is transferred between a first microelectrode and a second microelectrode, and then a dielectrophoresis process is applied to connect both ends of the GaN-based nanowire to the surfaces of the first microelectrode and the second microelectrode, respectively, and the process parameters of the dielectrophoresis process are an AC voltage of 3V to 15V, a frequency of 1kHz to 1MHz, an energizing time of 10min to 20min, and the dielectrophoresis solution is acetone, isopropyl alcohol, or ethanol.

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