Continuity testing device, Kelvin measuring probe, and static elimination device

Abstract

To automatically and easily inspect presence or absence of continuity between two chuck lead wires of a force wire and a sense wire.SOLUTION: A wafer inspection system includes a wafer chuck 16 having a support surface for holding a wafer to be measured with a Kelvin measurement prober, a probe that contacts a front surface electrode of a semiconductor chip formed on the surface of the wafer, a force line 40F and a sense line 40S that contact a back surface electrode of the semiconductor chip formed on a back surface of the wafer, first connection wiring 64 connected to any one of the force line and the sense line, second connection wiring 66 connected to the other of the force line and the sense line, a first relay 46 and a first resistor 48 provided on the first connection wiring side, and a power source 58 provided on the second connection wiring 66 side. A current loop is formed by electrically coupling the first connection wiring and the second connection wiring via a first relay, a first resistor, and the power source, and a general controller 62 for determining whether the current flows through the current loop is provided.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a conduction inspection device, a Kelvin measurement probe, and a charge removal device used in a wafer test system for inspecting the electrical characteristics of semiconductor chips formed on a wafer.

Background Art

[0002] A plurality of semiconductor chips are formed on a wafer (also referred to as a semiconductor wafer). The electrical characteristics of the formed semiconductor chips are inspected by a wafer test system composed of a probe and a tester. Depending on the type of semiconductor chip to be formed, electrodes (front electrodes) are formed on the surface, and electrodes (back electrodes) are also formed on the back surface. On the wafer chuck of a wafer test system corresponding to the inspection of such semiconductor chips, there is a support surface that supports the wafer in contact with the back surface of the wafer, and a conductive support surface (wafer mounting surface) that acts as a measurement electrode of the tester is provided. This support surface is electrically connected to the tester via a chuck lead wire drawn out from the wafer chuck.

[0003] Here, in the measurement of semiconductor chips of power devices, a Kelvin connection is made by connecting two chuck lead wires (force wire and sense wire) to the wafer chuck for measurement (see Patent Document 1). In addition, in order to apply a large current or a high voltage to the wafer chuck, the chuck lead wires are designed to have a thick diameter or a hard material is used for the chuck lead wire material. During measurement, the wafer chuck rotates and the temperature also becomes high, so the chuck lead wires are prone to breakage due to being exposed to severe mechanical and thermal conditions.

[0004] Therefore, conventionally, the fixing method of the chuck lead wires has been devised so that the chuck lead wires do not break, or the operator checks the conduction of the chuck lead wires using a handy tester or the like during regular maintenance.

[0005] Furthermore, Patent Document 2 proposes a continuity testing device that can automatically perform continuity testing on chuck lead wires. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2012-58225 [Patent Document 2] Japanese Patent Publication No. 2019-176080 [Overview of the project] [Problems that the invention aims to solve]

[0007] However, even if a method is devised to secure the chuck lead wires to prevent breakage, breakage can still occur. Furthermore, before regular maintenance is performed, it may not be possible to detect breakage in the chuck lead wires, resulting in inaccurate wafer inspections during that time. In addition, the continuity testing apparatus described in Patent Document 2, when testing the continuity of a single chuck lead wire, connects an additional wire to the wafer chuck, forms a current loop including the chuck lead wire and the additional wire, and performs the continuity test of the chuck lead wire by checking whether or not current flows through the current loop. Therefore, it is not applicable to wafer test systems that have two chuck lead wires consisting of a force wire and a sense wire and perform Kelvin measurement.

[0008] Furthermore, the wafer chuck becomes charged (static electricity), and consequently the wafer on the wafer chuck also becomes charged, so during wafer inspection, the surface electrodes of the semiconductor chip and the probe... When the probe makes contact with the semiconductor chip, an arc may be generated due to a discharge between the semiconductor chip and the probe, potentially damaging the semiconductor chip. Therefore, it is necessary to discharge static electricity from the wafer chuck.

[0009] The present invention has been made in view of these circumstances, and its first objective is to provide a continuity testing device and a Kelvin measuring probe that can automatically and easily check for the continuity of two chuck lead wires, a force wire and a sense wire. Its second objective is to provide a static elimination device that can minimize the generation of leakage current. [Means for solving the problem]

[0010] A continuity testing apparatus for achieving the first object of the present invention comprises a wafer chuck having a support surface for holding a wafer to be measured with a Kelvin measuring prober, a probe that contacts the surface electrodes of a semiconductor chip formed on the surface of the wafer, a force line and a sense line that contact the back surface electrodes of a semiconductor chip formed on the back surface of the wafer, a first connection wiring connected to either the force line or the sense line, a second connection wiring connected to the other of the force line or the sense line, a first relay and a first resistor provided on the side of the first connection wiring, and a power supply provided on the side of the second connection wiring, and a determination unit that electrically couples the first connection wiring and the second connection wiring via the first relay, the first resistor and the power supply to form a current loop and determines whether or not current flows in the current loop.

[0011] According to this embodiment, the first and second connection wirings can form a current loop including force lines and sense lines provided in the wafer chuck, and by determining whether or not current flows through this current loop, it is possible to determine whether or not the force lines and sense lines are conductive.

[0012] In another aspect of the present invention, a continuity test device includes a second relay and a second resistor included in a current loop and provided on the side of the second connecting wiring, and a voltage detection unit for detecting the voltage of the second resistor, wherein a determination unit makes a determination based on the detection result of the voltage detection unit. This makes it possible to determine whether or not current flows in the current loop based on the voltage detection result of the voltage detection unit for the second resistor.

[0013] In another aspect of the present invention, a continuity test device is provided, which includes a relay control unit that individually switches between the closed and open states of both the first relay and the second relay, and a determination unit makes a determination based on the detection result of the voltage detection unit when both the first relay and the second relay are switched to the closed state by the relay control unit. As a result, it is possible to determine whether or not current flows in the current loop based on the voltage detection result of the voltage detection unit of the second resistor.

[0014] In another aspect of the present invention, the continuity test device is connected in the order of first relay, first resistor, between the other end of the first connecting wiring opposite to the end to which either the force wire or the sense wire is connected, and ground. This allows the first resistor to be isolated from the support surface by turning off the first relay, thereby minimizing leakage current.

[0015] In another aspect of the present invention, in a continuity testing apparatus, one of the first or second connection wirings is connected to the force connector of a tester for testing the electrical characteristics of a semiconductor chip, to which the other end opposite to one end of a force wire connected to a support surface is connected, and the other of the first or second connection wirings is connected to the sense connector of the tester, to which the other end opposite to one end of a sense wire connected to a support surface is connected.

[0016] A Kelvin measuring probe for achieving the first object of the present invention is a wafer chuck that holds a wafer on which a plurality of semiconductor chips are formed, and which has a semiconductor formed on the back surface of the wafer. The system comprises a wafer chuck having a conductive support surface that contacts the back electrode of a conductor chip, a probe that contacts the surface electrode of a semiconductor chip formed on the surface of the wafer, and the continuity testing device described above.

[0017] The static eliminator for achieving the second object of the present invention includes a wafer chuck for holding a wafer on which a plurality of semiconductor chips are formed, and a probe that contacts a surface electrode of the semiconductor chip formed on the surface of the wafer. A conductive support surface provided on the support surface of the wafer provided on the wafer chuck of the Kelvin measurement probe and contacting the back electrode of the semiconductor chip formed on the back surface of the wafer, and either a force line or a sense line that is electrically connected to the conductive support surface; a first connection wiring connected to either the force line or the sense line; a first relay connected to the first connection wiring; and a first resistor connected to the first relay and grounded.

[0018] According to this static eliminator, by turning off the first relay, the first resistor can be separated from the support surface in the shortest possible way, so that the leakage current can be minimized.

Advantages of the Invention

[0019] According to the continuity inspection device and the Kelvin measurement probe of the present invention, the first connection wiring and the second connection wiring can form a current loop including the force line and the sense line provided on the wafer chuck, and by determining whether a current flows through this current loop, the continuity of the force line and the sense line can be determined. Further, the static eliminator of the present invention can minimize the generation of leakage current.

Brief Description of the Drawings

[0020] [Figure 1] FIG. 1 is a schematic diagram of a wafer test system. [Figure 2] FIG. 2 is a diagram for explaining the wiring in the tester main body, the probe, and the wafer chuck. [Figure 3] FIG. 3 is an explanatory diagram for explaining the force line, the sense line, and the additional circuit. [Figure 4] FIG. 4 is a schematic diagram of a static elimination circuit of a comparative example. [Figure 5] FIG. 5 is an explanatory diagram for explaining the current loop and the power supply. [Figure 6]FIG. 6 is a functional block diagram of the overall control unit of the prober. [Figure 7] FIG. 7 is a flowchart showing the flow of the processes of discharging the wafer chuck by the additional circuit, conducting a continuity check of the chuck lead wire, and self-diagnosing each relay.

Embodiments for Carrying Out the Invention

[0021] [Configuration of Wafer Test System] FIG. 1 is a schematic diagram of a wafer test system 9. Hereinafter, the upper side and the upper surface in the Z-axis direction, which is the vertical direction in the drawing, are appropriately referred to as the "upper side" and the "upper surface", and the lower side and the lower surface in the Z-axis direction are appropriately referred to as the "lower side" and the "lower surface".

[0022] The wafer test system 9 inspects the electrical characteristics of each of a plurality of semiconductor chips (not shown) formed on a wafer W, each having electrodes (not shown) formed on both sides. This wafer test system 9 includes a prober 10 and a tester 30. In particular, the wafer test system 9 has a configuration for inspecting a wafer W on which a plurality of power devices are formed as semiconductor chips. Therefore, the prober 10 is a Kelvin measurement prober having force lines and sense lines connected by Kelvin connection as will be described later (see FIG. 2).

[0023] The prober 10 brings the probe 25 into contact with a surface electrode (not shown) formed on the surface of an individual semiconductor chip (not shown) on the wafer W, and brings the conductive support surface 16a of the wafer chuck 16 described later into contact with a back surface electrode (not shown) formed on the back surface of the individual semiconductor chip. The tester 30 is electrically connected to the probe 25 and the support surface 16a, and inspects the electrical characteristics of the individual semiconductor chips. formed on the back surface of the individual semiconductor chip. The tester 30 is electrically connected to the probe 25 and the support surface 16a, and inspects the electrical characteristics of the individual semiconductor chips.

[0024] The prober 10 comprises a base 11, a base 12, a Y stage 13, an X stage 14, a Zθ stage 15, a wafer chuck 16, a probe position detection camera 18, a probe height detector 20, height adjustment mechanisms 21 and 27, a wafer alignment camera 19, a head stage 22, a card holder 23, a probe card 24, and a probe 25.

[0025] A roughly flat base plate 12 is fixed to the upper surface of the base plate 11. Alternatively, leg members may be used instead of the base plate 11, or the base plate 11 may be omitted altogether.

[0026] A substantially flat Y-stage 13 is supported on the upper surface of the base 12 via a Y-movement part (not shown) so as to be movable in the Y-axis direction. The Y-movement part includes a guide rail provided on the upper surface of the base 12 and parallel to the Y-axis, a slider provided on the lower surface of the Y-stage 13 and engaging with the guide rail, and a drive mechanism such as a motor for moving the Y-stage 13 in the Y-axis direction. By driving this Y-movement part, the Y-stage 13 and the X-stage 14 and Zθ-stage 15, etc., described later, are moved together in the Y-axis direction on the base 12.

[0027] A substantially flat X-stage 14 is supported on the upper surface of the Y-stage 13 via an X-movement part (not shown) so as to be movable in the X-axis direction. The X-movement part comprises a guide rail provided on the upper surface of the Y-stage 13 and parallel to the X-axis, a slider provided on the lower surface of the X-stage 14 and engaging with the guide rail, and a drive mechanism such as a motor for moving the X-stage 14 in the X-axis direction. By driving this X-movement part, the X-stage 14 and the Zθ stage 15 (described later) are moved together in the X-axis direction on the Y-stage 13.

[0028] The upper surface of the X-stage 14 is provided with a Zθ stage 15 and height adjustment mechanisms 21 and 27. Inside the Zθ stage 15 is a Zθ moving part (not shown). A wafer chuck 16 is held on the upper surface of the Zθ stage 15 via the Zθ moving part (not shown). This Zθ moving part has, for example, a lifting mechanism that allows the upper surface of the Zθ stage 15 to move in the Z-axis direction, and a rotation mechanism that rotates this upper surface around the Z-axis. Therefore, the Zθ moving part moves the wafer chuck 16 held on the upper surface of the Zθ stage 15 in the Z-axis direction and rotates it around the Z-axis.

[0029] The wafer chuck 16 holds the wafer W from its back side. The wafer chuck 16 is supported by the Y stage 13, X stage 14, and Zθ stage 15 described above so as to be movable in the XYZ directions relative to the base 12, and is also supported so as to be rotatable around the Z axis. This allows the wafer W held by the wafer chuck 16 and the probe 25 described later to move relative to each other.

[0030] The support surface 16a of the wafer W, which is the upper surface of the wafer chuck 16, is plated with various metals, such as nickel plating or gold plating, and is electrically conductive. This support surface 16a contacts the back electrodes (not shown) of each semiconductor chip on the wafer W. This support surface 16a is connected to the tester body 31 via chuck lead wires (force wire 40F and sense wire 40S) (see Figure 2), and acts as a measuring electrode for the tester body 31. As a result, depending on the various measurement conditions during inspection of each semiconductor chip (not shown) on the wafer W, the back electrodes of each semiconductor chip are subjected to voltage and current from the tester body 31 via the support surface 16a, or are grounded.

[0031] The height adjustment mechanism 21 raises and lowers the probe position detection camera 18 (described later) in the Z-axis direction. The height adjustment mechanism 27 raises and lowers the probe height detector 20 (described later) in the Z-axis direction. The height adjustment mechanisms 21 and 27 can be any known linear movement mechanism, such as a linear guide mechanism and a ball screw mechanism.

[0032] The headstage 22, for example, constitutes the top plate of the housing (not shown) of the prober 10 and is supported above the wafer chuck 16 (wafer W) by pillars (not shown). The headstage 22 is formed in a substantially annular shape, and a substantially annular card holder 23 for holding the probe card 24 is provided in its central part. That is, the headstage 22 holds the probe card 24 via the card holder 23.

[0033] The probe card 24 has multiple probes 25. These probes 25 are arranged on the probe card 24 in a pattern corresponding to the arrangement pattern of the surface electrodes of each semiconductor chip (not shown) on the wafer W to be inspected.

[0034] The probe position detection camera 18 is attached to the height adjustment mechanism 21. The probe position detection camera 18 is, for example, a camera equipped with a needle alignment microscope, and it photographs the probe 25 of the probe card 24 from below. Based on the image of the probe 25 taken by this probe position detection camera 18, the position of the probe 25 can be detected. Specifically, the XY coordinates of the tip position of the probe 25 are detected from the position coordinates of the probe position detection camera 18, and the Z coordinate of the tip position of the probe 25 is detected from the focal point position of the probe position detection camera 18.

[0035] The wafer alignment camera 19 is supported by a support column (not shown) on the base 12 and photographs the semiconductor chip (not shown) on the wafer W held in the wafer chuck 16 from above. Based on the image of the semiconductor chip captured by this wafer alignment camera 19, the position of the electrodes on the semiconductor chip can be detected. As a result, based on the information obtained by the wafer alignment camera 19 and the position information of the tip of the probe 25 obtained by the probe position detection camera 18, two-dimensional alignment of the probe 25 and the electrodes of the semiconductor chip on the wafer W in the XY plane can be performed.

[0036] The probe height detector 20 is attached to the height adjustment mechanism 27 described above on the X-stage 14. This probe height detector 20 detects the height of the tip of the probe 25 from a reference plane that serves as the height reference for the probe position detection camera 18. The probe height detector 20 is a contact-type detector and detects the height of the tip of the probe 25 by physically contacting the tip of the probe 25. Here, the reference plane is the plane that serves as the height reference for the probe 10 as a whole, and can be set arbitrarily (for example, the top surface of the X-stage 14).

[0037] The aforementioned height adjustment mechanism 21 adjusts the probe position detection camera 18 to a height that is a working distance away from the tip of the probe 25, based on the detection result of the height of the tip of the probe 25. This prevents the probe position detection camera 18 from being raised too high and colliding with the tip of the probe 25.

[0038] The tester 30 has a tester body 31, which is connected to probes 25 installed on a probe card 24 by force lines 33F and sense lines 33S (see Figure 2). The probe card 24 is provided with terminals that are connected to each probe 25.

[0039] The tester unit 31 is electrically connected to the surface electrodes of a semiconductor chip (not shown) via force wire 33F, sense wire 33S, probe card 24, and probe 25, and also via force wire 35F, 40F, sense wire 35S, 40S, force connector 68F, sense connector The tester unit 31 is electrically connected to the back electrode of a semiconductor chip (not shown) via the 68S and the support surface 16a, etc. The tester unit 31 then tests the electrical characteristics of the semiconductor chip by applying current or voltage to the semiconductor chip.

[0040] [Kelvin Connection] Figure 2 illustrates the wiring in the tester body 31, probe 25, and wafer chuck 16.

[0041] A wafer W is placed on a wafer chuck 16, and a probe card 24 is positioned opposite the wafer W by a headstage 22 (not shown in Figure 2) and a card holder 23 (not shown in Figure 2). The probe card 24 has a pair of probes 25A and 25B that can simultaneously contact the surface electrodes of a semiconductor chip. In the following description, probe 25 will be referred to as probes 25A and 25B.

[0042] Probe 25A is connected to force line 33F, and probe 25B is connected to sense line 33S. Force line 33F connects probe 25A to the tester body 31, and sense line 33S connects probe 25B to the tester body 31. Inside the tester body 31, force line 33F is connected to current source 31B, and sense line 33S is connected to voltmeter 31A. Force line 35F connects current source 31B to force connector 68F, and sense line 35S connects voltmeter 31A to sense connector 68S. Force line 40F is connected to force connector 68F to wafer chuck 16, and sense line 40S is connected to sense connector 68S to wafer chuck 16. Force line 40F is connected to one end of wafer chuck 16 (right end in Figure 2), and sense line 40S is connected to the other end (left end in Figure 2).

[0043] In this way, the tester body 31, probes 25A and 25B, and wafer chuck 16 are connected in Kelvin via force lines 33F, 35F, and 40F and sense lines 33S, 35S, and 40S.

[0044] [Chuck lead wires and additional circuits] Figure 3 is an explanatory diagram illustrating the force line 40F, the sense line 40S, and the additional circuit 52.

[0045] The force wire 40F and the sense wire 40S constitute the chuck lead wires. Therefore, the wafer chuck 16 is electrically connected to two chuck lead wires. The force wire 40F has one end 40Fa that is electrically connected to the support surface 16a, and the other end 40Fb, which is opposite to the one end 40Fa, and is electrically connected to the force connector 68F. The sense wire 40S has one end 40Sa that is electrically connected to the support surface 16a, and the other end 40Sb, which is opposite to the one end 40Sa, and is electrically connected to the sense connector 68S. The types of force wire 40F and sense wire 40S are not particularly limited. In this embodiment, a portion of both the force wire 40F and the sense wire 40S is housed in the cable carrier (registered trademark) 78.

[0046] The additional circuit 52 functions as a continuity testing device of the present invention, with a part of it functioning as a static elimination device of the present invention. The additional circuit 52 performs continuity testing (open circuit testing) of the force line 40F and the sense line 40S, and also performs static elimination (discharge) of the wafer chuck 16.

[0047] The additional circuit 52 includes a force connector 68F, a sense connector 68S, a first connection wire 64, a second connection wire 66, a static elimination circuit 50 (first relay 46 and first resistor 48), and a second relay 5 The additional circuit 52 comprises a second resistor 56, a power supply 58, and a detection circuit 60. The additional circuit 52 is electrically connected to the force wire 40F and the sense wire 40S in the force connector 68F and the sense connector 68S. Specifically, in the force connector 68F, the force wire 40F is electrically connected to the first connection wiring 64. Also, in the sense connector 68S, the sense wire 40S is electrically connected to the second connection wiring 66.

[0048] The other end of the first connecting wiring 64, opposite to the end connected to the force connector 68F, is electrically connected to the first relay 46, which constitutes the static elimination circuit 50. As a result, the support surface 16a and the tester 30 are electrically connected via the force wire 40F and the force connector 68F, and the support surface 16a, the first connecting wiring 64, and the static elimination circuit 50 (first relay 46) are also electrically connected.

[0049] The static elimination circuit 50 corresponds to the static elimination device of the present invention. The static elimination circuit 50 includes a first relay 46 electrically connected to the force line 40F via a force connector 68F and a first connecting wire 64, and a first resistor 48 connected to the first relay 46 and grounded. As described above, the wafer chuck 16 becomes charged with electric charge (static electricity), and as a result, the wafer W on the wafer chuck 16 also becomes charged with electric charge. Therefore, the static elimination circuit 50 eliminates the electric charge (static electricity) accumulated on the wafer chuck 16.

[0050] The first relay 46 can be switched between a closed state (connected state), in which the first connecting wiring 64, force wire 40F, and support surface 16a (hereinafter abbreviated as support surface 16a, etc.) and the first resistor 48 are electrically connected, and an open state (disconnected state), in which the electrical connection between the two is released. There are no particular limitations on the type of first relay 46. In this specification, switching the first relay 46 to the closed state is defined as "on," and conversely, switching it to the open state is defined as "off." The on / off switching of the first relay 46 is controlled by the control unit 62 described later.

[0051] The first relay 46 is turned on when static electricity is removed from the wafer chuck 16 and when the continuity of the force line 40F and sense line 40S described later is tested, electrically connecting the support surface 16a etc. to the first resistor 48. The first relay 46 is also turned off when the electrical characteristics of each semiconductor chip (not shown) are tested, releasing the electrical connection between the support surface 16a etc. and the first resistor 48.

[0052] The first resistor 48 is a current-limiting resistor that prevents the charge (static electricity) accumulated on the wafer chuck 16 from flowing all at once toward the ground when the first relay 46 is turned on during static discharge of the wafer chuck 16, and a high-resistivity resistor is used. As a result, when the first relay 46 is turned on during static discharge of the wafer chuck 16, the charge accumulated on the wafer chuck 16 can be gradually discharged toward the ground via the first resistor 48, and as a result the wafer chuck 16 is discharged.

[0053] Next, the effects of the static elimination circuit 50 of this embodiment will be explained in more detail by comparing it with the static elimination circuit 200 of the comparative example (see Figure 4). However, the present invention is not limited to the following explanation of its effects.

[0054] Figure 4 is a schematic diagram of a comparative example static elimination circuit 200. In the comparative example shown in Figure 4, components that are functionally or structurally identical to those in this embodiment are denoted by the same reference numerals and their descriptions are omitted. As shown in Figure 4, in the comparative example static elimination circuit 200, for example, as disclosed in Japanese Patent Application Publication No. 2003-218175, a first resistor 48 is electrically connected to the force connector 68F first, and a grounded first relay 46 is connected to this first resistor 48.

[0055] In this comparative example static elimination circuit 200, by turning on the first relay 46, the charge accumulated on the wafer chuck 16 can be gradually discharged to the ground side via the first resistor 48, similar to the static elimination circuit 50 of this embodiment.

[0056] However, in the comparative example static elimination circuit 200, a first resistor 48 is placed between the wafer chuck 16 and the first relay 46, so even when the first relay 46 is switched off, the connection between the support surface 16a, etc. and the first resistor 48 is maintained. On the other hand, since the first resistor 48 is a high-resistivity element, leakage current may occur when the first relay 46 is off. If leakage current occurs from the first resistor 48, this leakage current may be mixed into the signal output from the back electrode (not shown) during the inspection of each semiconductor chip (not shown) of the wafer W, potentially affecting the inspection of each semiconductor chip or even adversely affecting each semiconductor chip. Therefore, in order to perform accurate inspection of each semiconductor chip, it is necessary for the wafer chuck 16 to be in a highly insulated state (a state that is not affected by external leakage current, etc.), and it is undesirable to connect extra components to the wafer chuck 16.

[0057] In contrast to the static elimination circuit 200 of the comparative example, in the static elimination circuit 50 of this embodiment, as shown in Figure 3, the first relay 46 is electrically connected to the force connector 68F first, and the grounded first resistor 48 is electrically connected to this first relay 46. As a result, by turning off the first relay 46 when inspecting each semiconductor chip, the first resistor 48 can be isolated from the support surface 16a, etc., in the shortest possible distance. Consequently, the leakage current caused by the static elimination circuit 50 added for static elimination can be minimized.

[0058] Returning to Figure 3, one end 40Sa of the sense wire 40S is electrically connected to the support surface 16a, and the other end 40Sb, opposite to the one end 40Sa, is electrically connected to the sense connector 68S. As a result, the sense wire 40S and the force wire 40F are electrically connected via the support surface 16a. In addition, the sense wire 40S is electrically connected to the second connection wiring 66 via the sense connector 68S.

[0059] The other end of the second connecting wiring 66, opposite to the end connected to the sense connector 68S, is electrically connected to the second relay 54. As a result, the support surface 16a and the tester 30 are electrically connected via the sense wire 40S, connector 44S, and sense connector 68S, and the support surface 16a, the second connecting wiring 66, and the second relay 54 are also electrically connected.

[0060] The second relay 54 can be switched between a closed state (connected state) where it is electrically connected to the power supply 58, the second resistor 56, the second connection wiring 66, and the sense wire 40S, and an open state (disconnected state) where it is electrically disconnected. There are no particular limitations on the type of second relay 54. In this specification, switching the second relay 54 to the closed state is defined as "on," and conversely, switching it to the open state is defined as "off." The on / off switching of the second relay 54 is controlled by the control unit 62 described later, similar to the first relay 46.

[0061] The second relay 54 is turned on during the continuity test of the force line 40F and the sense line 40S, electrically connecting the second resistor 56, the power supply 58, the second connection wiring 66, and the sense line 40S. The second relay 54 is also turned off during static discharge of the wafer chuck 16 and during the inspection of the electrical characteristics of each semiconductor chip (not shown), releasing the electrical connection between the second resistor 56, the power supply 58, the second connection wiring 66, and the sense line 40S.

[0062] The second resistor 56 is electrically connected to the second relay 54. This second resistor 56 is a current-limiting resistor similar to the first resistor 48, and a high-resistivity resistor is used. The voltage across this second resistor 56 (voltage across its terminals, potential difference) indicates whether or not there is continuity (openness) in the force wire 40F and sense wire 40S. It is used to make that determination.

[0063] Figure 5 is an explanatory diagram illustrating the current loop CR and the power supply 58. As shown in Figures 3 and 5, the power supply 58 is connected to and grounded to the second resistor 56. Since the power supply 58 and the previously described first resistor 48 are so-called frame grounded (connected to, for example, an earth electrode or a metal housing), the power supply 58 and the first resistor 48 are electrically connected. Therefore, the force wire 40F, sense wire 40S, first relay 46, first resistor 48, first connection wiring 64, second connection wiring 66, second relay 54, second resistor 56, and power supply 58 constitute an electrically coupled current loop CR.

[0064] The power supply 58 supplies current (applies voltage) to the current loop CR when the continuity test of the force line 40F and sense line 40S described later is performed, that is, when both the first relay 46 and the second relay 54 are turned on. As a result, if the force line 40F and sense line 40S are conducting (not broken), that is, if the current loop CR is formed, a current Is (small current) flows through this current loop CR.

[0065] The detection circuit 60 corresponds to the voltage detection unit of the present invention and is a voltmeter that detects the voltage (voltage across its terminals, potential difference) of the second resistor 56. When both the first relay 46 and the second relay 54 are ON and the force line 40F and sense line 40S are conducting, a current Is flows through the current loop CR described above. In this case, if the voltage applied to the current loop CR by the power supply 58 is V, the resistance value of the first resistor 48 is R1, and the resistance value of the second resistor 56 is R2, then the detected voltage of the second resistor 56 detected by the detection circuit 60 is "V × (R2 / (R1 + R2))". Therefore, for example, if R1 = R2, the detected voltage of the second resistor 56 is "V / 2". To avoid complicating the explanation below, we will assume "R1 = R2".

[0066] On the other hand, even when both the first relay 46 and the second relay 54 are turned on, if at least one of the force wire 40F and the sense wire 40S is broken, the current Is from the power supply 58 will not flow through the current loop CR. Therefore, in this case, the detected voltage by the detection circuit 60 will be "V".

[0067] By referring to the voltage detected by the detection circuit 60 in this way, it is possible to determine whether or not current Is is flowing through the current loop CR, that is, whether or not there is continuity in the force wire 40F and sense wire 40S (whether or not there is a break in the wire). The detection circuit 60 then outputs the voltage detection result of the second resistor 56 to the control unit 62.

[0068] Conversely, if continuity is confirmed in the force wire 40F and the sense wire 40S, the voltage detection result of the second resistor 56 by the detection circuit 60 can be used for self-diagnosis of the first relay 46 and the second relay 54.

[0069] For example, when both the first relay 46 and the second relay 54 are turned on, if the detection voltage by the detection circuit 60 is "V / 2", it can be determined that both the first relay 46 and the second relay 54 are functioning normally. On the other hand, when both the first relay 46 and the second relay 54 are turned on, if the detection voltage by the detection circuit 60 is "V", it can be determined that at least one of the first relay 46 and the second relay 54 is not actually turned on, i.e., at least one is malfunctioning. Also, when at least one of the first relay 46 and the second relay 54 is turned off, if the detection voltage by the detection circuit 60 is "V / 2", it can be determined that both the first relay 46 and the second relay 54 are actually turned on, and therefore at least one of the first relay 46 and the second relay 54 is malfunctioning.

[0070] Figure 6 shows the control unit 62 of the prober 10 (or wafer test system 9; the same applies hereafter). This is a functional block diagram. The central control unit 62 is composed of various arithmetic units, processing units, and memory, including, for example, a CPU (Central Processing Unit) or FPGA (field-programmable gate array), and controls the operation of each part of the prober 10. In Figure 6, among the multiple functions of the central control unit 62, only the functions related to static elimination of the wafer chuck 16 by the additional circuit 52, continuity testing of the force line 40F and sense line 40S, and self-diagnosis of each relay 46 and 54 are shown, and other functions related to the control of the prober 10, such as wafer W inspection, are known technology and are therefore not shown.

[0071] The control unit 62 is connected to the operation unit 70 which accepts various operation inputs, the display unit 72 which displays various information, the relays 46 and 54 described above, the power supply 58, and the detection circuit 60, as well as the various parts of the prober 10. The control unit 62 then functions as an additional circuit control unit 76, a determination unit 80, and a self-diagnosis unit 82 by executing a predetermined control program.

[0072] The additional circuit control unit 76 controls the on / off status of each relay 46 and 54 and the on / off status of the power supply 58 when the additional circuit 52 starts the static discharge of the wafer chuck 16, the continuity test of the force line 40F and sense line 40S, and the self-diagnosis of each relay 46 and 54. In other words, the additional circuit control unit 76 functions as a relay control unit of the present invention.

[0073] The static elimination, continuity test, and self-diagnosis performed by the additional circuit 52 are executed at any time when the inspection of each semiconductor chip (not shown) is not being performed, i.e., when the probe 25 is separated from the wafer W. Examples of such times include when the wafer chuck 16 is retracted downward by the Zθ stage 15, when the wafer W is loaded or unloaded onto the wafer chuck 16, and when the semiconductor chip index is fed. The static elimination, continuity test, and self-diagnosis may also be started in response to a start operation on the operation unit 70.

[0074] The additional circuit control unit 76 turns on only the first relay 46 at any timing to perform static elimination or upon receiving an input from the operation unit 70 for the start of static elimination. The additional circuit control unit 76 also turns on both relays 46 and 54 and the power supply 58 at any timing to perform a continuity test or upon receiving an input from the operation unit 70 for the start of a continuity test. Furthermore, the additional circuit control unit 76 turns each relay 46 and 54 on and off individually one or more times and the power supply 58 at the timing to perform a self-diagnosis or upon receiving an input from the operation unit 70 for the start of a self-diagnosis.

[0075] When the continuity test is started, that is, when both the first relay 46 and the second relay 54 are turned on and the power supply 58 is turned on, the determination unit 80 determines whether or not current Is is flowing through the current loop CR based on the voltage detection result of the second resistor 56 input from the detection circuit 60. As a result, the determination unit 80 can determine whether or not the force line 40F and the sense line 40S are conducting. As described above, when the voltage of the second resistor 56 is "V / 2", the determination unit 80 determines that current Is is flowing through the current loop CR and that the force line 40F and the sense line 40S are conducting. On the other hand, when the voltage of the second resistor 56 is "V", the determination unit 80 determines that current Is is not flowing through the current loop CR and that at least one of the force line 40F and the sense line 40S is broken.

[0076] The determination unit 80 then outputs whether or not the force line 40F and the sense line 40S are continuing to the display unit 72. As a result, the display unit 72 displays whether or not the force line 40F and the sense line 40S are continuing (whether or not they are broken). The display unit 72 includes not only a monitor for screen display (image display) but also a speaker for audio display (audio output).

[0077] When self-diagnosis is being performed, that is, when each relay 46 and 54 is turned on or off and the power supply 58 is on, the self-diagnosis unit 82 performs a self-diagnosis of each relay 46 and 54 based on the voltage detection result of the second resistor 56 input from the detection circuit 60. As described above, for example, when both relays 46 and 54 are turned on, the self-diagnosis unit 82 determines that both relays 46 and 54 are normal if the detected voltage by the detection circuit 60 is "V / 2", and determines that at least one of relays 46 and 54 is abnormal if the detected voltage is "V". Also, when at least one of relays 46 and 54 is turned off, the self-diagnosis unit 82 determines that at least one of relays 46 and 54 is abnormal if the detected voltage by the detection circuit 60 is "V / 2".

[0078] The self-diagnosis unit 82 then outputs the self-diagnosis results of each relay 46 and 54 to the display unit 72. As a result, the self-diagnosis results of each relay 46 and 54 are displayed on the display unit 72.

[0079] [Operation of the additional circuit in this embodiment] Figure 7 is a flowchart showing the process flow of static discharge of the wafer chuck 16 by the additional circuit 52 of the above configuration, continuity testing of the force line 40F and sense line 40S, and self-diagnosis of each relay 46 and 54.

[0080] <Continuity Test> As shown in Figure 7, the additional circuit control unit 76 turns on both relays 46 and 54 (step S2) and the power supply 58 (step S3) at any time when the continuity test is to be performed or when an input for starting the continuity test is received from the operation unit 70 (YES in step S1). Meanwhile, the detection circuit 60 starts detecting the voltage of the second resistor 56 in conjunction with the turning on of the power supply 58 and outputs the voltage detection result of the second resistor 56 to the determination unit 80 (step S4).

[0081] The determination unit 80 determines that if the voltage across the second resistor 56 is "V / 2", current Is is flowing through the current loop CR, that is, the force line 40F and the sense line 40S are conducting (step S5). On the other hand, if the voltage across the second resistor 56 is "V", the determination unit 80 determines that current Is is not flowing through the current loop CR, that is, at least one of the force line 40F and the sense line 40S is open (step S5). The determination unit 80 then outputs the determination result to the display unit 72. As a result, the determination result of whether or not the force line 40F and the sense line 40S are conducting is displayed on the display unit 72 (step S6).

[0082] <Static removal> The additional circuit control unit 76 turns on the first relay 46 (step S8) at any timing to execute the static discharge, or upon receiving an input from the operation unit 70 for the start of static discharge (NO in step S1, YES in step S7). As a result, the charge accumulated on the wafer chuck 16 is discharged to ground via the first resistor 48, thereby discharging static electricity from the wafer chuck 16.

[0083] <Self-diagnosis> The additional circuit control unit 76 turns on the power supply 58 (step S9) at any timing that executes the self-diagnosis of each relay 46, 54, or upon receiving an input from the operation unit 70 for starting the self-diagnosis (NO in both steps S1 and S7). In conjunction with turning on the power supply 58, the detection circuit 60 starts detecting the voltage of the second resistor 56 and outputs the voltage detection result to the self-diagnosis unit 82 (step S10).

[0084] Next, the additional circuit control unit 76 turns each relay 46 and 54 on and off individually at least once (step S11). Then, while each relay 46 and 54 is being turned on and off, the self-diagnosis unit 82, based on the voltage detection result of the second resistor 56 input from the detection circuit 60, performs the following: As described above, each relay 46 and 54 performs a self-diagnosis and outputs the diagnosis result to the display unit 72 (step S12). As a result, the self-diagnosis result of each relay 46 and 54 is displayed on the display unit 72 (step S13).

[0085] [Effects of this embodiment] As described above, with the additional circuit 52 of this embodiment, a current loop CR is formed by the two chuck lead wires (force wire 40F and sense wire 40S) and the additional circuit 52. By detecting whether or not current Is flows through this current loop CR, that is, whether or not the voltage detection result of the second resistor 56 by the detection circuit 60 is "V / 2", it is possible to determine whether or not the force wire 40F and sense wire 40S are conducting.

[0086] Furthermore, while the continuity testing device described in Patent Document 2 (Japanese Patent Application Publication No. 2019-176080) inspects the continuity of a single chuck lead wire by providing additional wiring, in this embodiment, an additional circuit 52 is electrically connected to each of the force wire 40F and sense wire 40S via the first connecting wiring 64 and the second connecting wiring 66, respectively, making it possible to determine whether or not the two chuck lead wires, the force wire 40F and the sense wire 40S, are continuing.

[0087] Furthermore, in the static elimination circuit 50 of this embodiment, the first relay 46 is electrically connected to the force connector 68F first, and the grounded first resistor 48 is electrically connected to this first relay 46. Therefore, by turning off the first relay 46 when inspecting each semiconductor chip, the first resistor 48 can be isolated from the chuck lead wire (e.g., force wire 40F) in the shortest possible distance. As a result, the leakage current caused by the static elimination circuit 50 can be minimized, preventing the leakage current from affecting the inspection of each semiconductor chip (not shown) on the wafer W, or from adversely affecting each semiconductor chip.

[0088] [others] In the above embodiment, the force wire 40F is electrically connected to the first connecting wire 64 and the sense wire 40S is electrically connected to the second connecting wire 66, but the present invention is not limited thereto. For example, even if the sense wire 40S is electrically connected to the first connecting wire 64 and the force wire 40F is electrically connected to the second connecting wire 66, the continuity test of the force wire 40F and the sense wire 40S can be performed as described above.

[0089] In the above embodiment, the second relay 54, the second resistor 56, and the power supply 58 are connected to the second connection wiring 66 in that order. However, the order is not particularly limited as long as the supply of current Is to the current loop CR can be switched on and off according to the on / off status of the second relay 54. Also, in the above embodiment, the first relay 46 and the first resistor 48 are connected to the first connection wiring 64 in that order in order to minimize the leakage current caused by the static elimination circuit 50. However, if there is no need to consider leakage current, the first resistor 48 and the first relay 46 may be connected to the first connection wiring 64 in that order.

[0090] In the above embodiment, the first resistor 48 and the second resistor 56 were described using individual resistors as examples, but the first resistor 48 and the second resistor 56 may be composed of multiple resistors (including electronic components equivalent to resistors, or electronic components other than resistors).

[0091] In the above embodiment, the detection circuit 60 detects the voltage of the second resistor 56. However, the detection circuit 60 may also detect the voltage of the first resistor 48, and the determination unit 80 may perform a determination and the self-diagnosis unit 82 perform a diagnosis based on this voltage detection result.

[0092] In the above embodiment, the power supply 58 is connected to the second connection wiring side, but the power supply 58 may also be connected to the static elimination circuit 50. Also, in the case where the purpose is solely to eliminate static electricity from the wafer chuck 16 Alternatively, only the static elimination circuit 50 may be connected to the force connector 68F.

[0093] Although examples of the present invention have been described above, it goes without saying that the present invention is not limited to the embodiments described above, and various modifications are possible without departing from the spirit of the invention. [Explanation of symbols]

[0094] 9…Wafer Test System 10…Prova 16… Wafer chuck 16a...support surface 30... Tester 40F... Force line 40S... Sense line 46…1st Relay 48...1st resistance 50…Static elimination circuit 54…2nd Relay 56…Second resistance 58…Power supply 60...Detection circuit 62...General Control Unit 80…Judgment section 82...Self-Diagnosis Department

Claims

1. A wafer chuck having a support surface for holding a wafer to be measured with a Kelvin measuring prober, A probe that contacts the surface electrode of a semiconductor chip formed on the surface of the wafer, Force lines and sense lines that contact the back electrode of the semiconductor chip formed on the back surface of the wafer, A first connecting wire connected to either the force wire or the sense wire, A second connecting wire connected to the other of either the force wire or the sense wire, A first relay and a first resistor are provided on the side of the first connection wiring, A power supply provided on the side of the second connecting wiring, Prepare, The first connecting wire and the second connecting wire are electrically coupled via the first relay, the first resistor, and the power supply to form a current loop. The system includes a determination unit that determines whether or not current flows through the current loop. Continuity testing device.

2. The current loop includes a second relay and a second resistor provided on the side of the second connecting wiring, The system includes a voltage detection unit that detects the voltage across the second resistor, The continuity test apparatus according to claim 1, wherein the determination unit performs the determination based on the detection result of the voltage detection unit.

3. The system includes a relay control unit that individually switches between the closed state and the open state of both the first relay and the second relay, The continuity testing apparatus according to claim 2, wherein the determination unit makes the determination based on the detection result of the voltage detection unit when both the first relay and the second relay are switched to the closed state by the relay control unit.

4. The continuity testing device according to any one of claims 1 to 3, wherein the first relay and the first resistor are connected in the order of the first relay and the first resistor between the other end of the first connecting wiring opposite to the end to which either the force wire or the sense wire is connected and ground.

5. The other end of the force wire, opposite to one end connected to the support surface, is connected to the force connector of a tester for inspecting the electrical characteristics of the semiconductor chip, to which one of the first or second connection wires is connected. The continuity testing device according to any one of claims 1 to 4, wherein the other of the first connecting wiring or the second connecting wiring is connected to the sense connector of the tester, to which the other end of the sense wire opposite to the one end connected to the support surface is connected.

6. A wafer chuck for holding a wafer on which multiple semiconductor chips are formed, and having a conductive support surface that contacts the back surface electrodes of the semiconductor chips formed on the back surface of the wafer, A probe that contacts the surface electrode of the semiconductor chip formed on the surface of the wafer, A continuity test device according to any one of claims 1 to 5, A Kelvin measuring probe equipped with [a specific feature].

7. A Kelvin measuring probe comprising a wafer chuck for holding a wafer on which multiple semiconductor chips are formed, and a probe that contacts the surface electrodes of the semiconductor chips formed on the surface of the wafer, wherein the wafer support surface provided on the wafer chuck and the A force line or a sense line is electrically connected to a conductive support surface that contacts the back electrode of the semiconductor chip formed on the back surface of the EHA, A first connecting wire connected to one of the force wire or the sense wire, A first relay connected to the first connection wiring, A first resistor connected to the first relay and grounded, A static elimination device equipped with the following features.

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