Semiconductor equipment

Abstract

To provide a semiconductor device which can suppress increase of the leakage current and deterioration of the voltage-withstanding or suppress a current collapse phenomenon by suppressing the electric field concentration of an AlGaN layer.SOLUTION: A semiconductor device according to the present invention comprises: an n-type GaN layer 12; a first n-type AlGaN layer 13 which is arranged on the n-type GaN layer 12; a second n-type AlGaN layer 21 which is arranged on the first n-type AlGaN layer 13; a source electrode 15 which is arranged on the first n-type AlGaN layer 13 and located on one side of the second n-type AlGaN layer 21; a drain electrode 16 which is arranged on the first n-type AlGaN layer 13 and located on the other side of the second n-type AlGaN layer 21; a p-type AlGaN layer 22 which is arranged on the second n-type AlGaN layer 21 and located on the source electrode 15 side relative to the center on the second n-type AlGaN layer 21; and a gate electrode 18 which is arranged on the p-type AlGaN layer 22.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This invention relates to a semiconductor device. [Background technology]

[0002] Conventional semiconductor devices are polarized junction GaN-based FETs (HEMTs) with high electron mobility. This polarized junction GaN-based FET has a buffer layer formed on a Si substrate, a first n-type GaN layer formed on the buffer layer, an n-type AlGaN layer formed on the first n-type GaN layer, and a second n-type GaN layer formed on the n-type AlGaN layer. A source electrode located on one side of the second n-type GaN layer and a drain electrode located on the other side of the second n-type GaN layer are formed on the n-type AlGaN layer. A p-type GaN layer is formed on the second n-type GaN layer, and a gate electrode is formed on this p-type GaN layer. Related technology is disclosed in Patent Document 1.

[0003] In the conventional polarization junction GaN-based FET described above, a first GaN layer, an AlGaN layer, and a second GaN layer are sequentially formed on a buffer layer by epitaxial growth. During this epitaxial growth, impurities such as Si and C are introduced into the first GaN layer, the AlGaN layer, and the second GaN layer, causing these layers to become n-type. This can lead to electric field concentration in the n-type AlGaN layer and the n-type GaN layer, resulting in increased leakage current and degradation of breakdown voltage. Furthermore, the n-type transformation of these layers can hinder the suppression of current collapse.

[0004] Therefore, in the semiconductor device described above, there is a need to suppress electric field concentration between the n-type AlGaN layer and the n-type GaN layer, thereby suppressing the increase in leakage current and the deterioration of breakdown voltage, as well as suppressing the current collapse phenomenon. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2015-106627 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] Various aspects of the present invention aim to provide a semiconductor device that can suppress the increase in leakage current and the deterioration of breakdown voltage, as well as the current collapse phenomenon, by suppressing electric field concentration in the AlGaN layer. [Means for solving the problem]

[0007] Various aspects of the present invention will be described below.

[0008] [1] n-type GaN layer and A first n-type AlGaN layer disposed on the aforementioned n-type GaN layer, A second n-type AlGaN layer disposed on the first n-type AlGaN layer, A source electrode is disposed on the first n-type AlGaN layer and located on one side of the second n-type AlGaN layer, A drain electrode is disposed on the first n-type AlGaN layer and located on the other side of the second n-type AlGaN layer, A p-type AlGaN layer is disposed on the second n-type AlGaN layer and is located on the source electrode side from the center of the second n-type AlGaN layer, A gate electrode disposed on the aforementioned p-type AlGaN layer, A semiconductor device characterized by having the following features.

[0009] [2] n-type GaN layer and An n-type AlGaN layer disposed on the aforementioned n-type GaN layer, A first p-type AlGaN layer disposed on the n-type AlGaN layer, A source electrode is disposed on the n-type AlGaN layer and located on one side of the first p-type AlGaN layer, A drain electrode is disposed on the n-type AlGaN layer and located on the other side of the first p-type AlGaN layer, A second p-type AlGaN layer disposed on the first p-type AlGaN layer and located on the source electrode side from the center on the first p-type AlGaN layer, A gate electrode disposed on the second p-type AlGaN layer, A semiconductor device, characterized by comprising the above.

[0010] [3] In the above [1], The composition of the second n-type AlGaN layer is Al Ga 1-X N, where x is 0.01 or more and 0.25 or less, a semiconductor device characterized by this.

[0011] [4] In the above [1] or [3], The Al concentration of the second n-type AlGaN layer is 5 atomic% or less, a semiconductor device characterized by this.

[0012] [5] In the above [2], The composition of the first p-type AlGaN layer is Al x Ga 1-x N, where x is 0.01 or more and 0.25 or less, a semiconductor device characterized by this.

[0013] [6] In the above [2] or [5], The Al concentration of the first p-type AlGaN layer is 5 atomic% or less, a semiconductor device characterized by this.

[0014] [7] In any one of the above [1], [2], [3] and [5], The n-type GaN layer is disposed on a buffer layer, The buffer layer is disposed on a substrate, a semiconductor device characterized by this.

[0015] [8] In the above [7], The substrate is a Si substrate, a sapphire substrate, a SiC substrate, a GaN substrate, an AlN substrate or a Ga2O3 substrate, a semiconductor device characterized by this.

[0016] [9] In the above [1], A semiconductor device characterized in that each of the first n-type AlGaN layer, the second n-type AlGaN layer, and the p-type AlGaN layer has a thickness in the range of 1 nm to 60 nm.

[0017]

[10] In the above [2] or [5], A semiconductor device characterized in that each of the n-type AlGaN layer, the first p-type AlGaN layer, and the second p-type AlGaN layer has a thickness in the range of 1 nm to 60 nm. [Effects of the Invention]

[0018] According to the semiconductor device described in [1] above, when a first n-type AlGaN layer 13 is stacked on an n-type GaN layer 12, lattice matching occurs. That is, the atomic arrangement of the upper layer matches the atomic arrangement of the lower layer. Furthermore, since the second n-type AlGaN layer 21 is made of the same material as the first n-type AlGaN layer 13 below it in terms of being AlGaN, lattice matching occurs when the second n-type AlGaN layer 21 is epitaxially grown. In other words, when epitaxial growth occurs, the lattice constants match well and strain is less likely to occur, so surface defects and lattice defects are less likely to occur in the second n-type AlGaN layer 21. As a result, it is thought that the leakage current when the transistor is off will decrease. Along with this, even if electrons from a two-dimensional electron gas (2DEG), which is a current collapse phenomenon, move across the potential barrier to the first n-type AlGaN layer, it is possible to suppress their capture in the surface defect levels of the second n-type AlGaN layer.

[0019] According to the semiconductor device described in [2] above, since the first p-type AlGaN layer has p-type carriers, the balance when the transistor is off is improved, and thus degradation of the breakdown voltage can be suppressed. Furthermore, since the first p-type AlGaN layer is made of the same material as the underlying n-type AlGaN layer in terms of being AlGaN, lattice matching occurs when the first p-type AlGaN layer is epitaxially grown. In other words, when epitaxial growth occurs, the lattice constants are well matched and distortion is less likely to occur, so surface defects and lattice defects are less likely to occur in the first p-type AlGaN layer. As a result, leakage current when the transistor is off is expected to decrease. Along with this, even if electrons from the two-dimensional electron gas (2DEG), which is a current collapse phenomenon, move across the potential barrier to the n-type AlGaN layer, it is possible to suppress them from being trapped in defect levels inherent in the first p-type AlGaN layer a, and as a result, the current collapse phenomenon can be suppressed.

[0020] According to the semiconductor device described in [4] above, by setting the Al concentration of the second n-type AlGaN layer to 5 atomic percent or less, drain source leak during the off state can be reduced.

[0021] According to the semiconductor device described in [6] above, by setting the Al concentration of the first p-type AlGaN layer to 5 atomic percent or less, drain source leak during the off state can be reduced.

[0022] Furthermore, according to various aspects of the present invention, it is possible to provide a semiconductor device that can suppress the increase in leakage current and the deterioration of breakdown voltage, as well as the current collapse phenomenon, by suppressing electric field concentration in the AlGaN layer. [Brief explanation of the drawing]

[0023] [Figure 1] This is a schematic cross-sectional view showing a semiconductor device according to one aspect of the present invention. [Figure 2] This is a schematic cross-sectional view showing a semiconductor device according to one aspect of the present invention. [Modes for carrying out the invention]

[0024] Embodiments of the present invention will be described in detail below with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the present invention. Accordingly, the present invention shall not be interpreted as being limited to the descriptions of the embodiments shown below.

[0025] (First Embodiment) Figure 1 is a schematic cross-sectional view showing a semiconductor device according to one aspect of the present invention.

[0026] This semiconductor device includes an n-type GaN layer 12, a first n-type AlGaN layer 13 disposed on the n-type GaN layer 12, a second n-type AlGaN layer 21 disposed on the first n-type AlGaN layer 13, a source electrode 15 disposed on the first n-type AlGaN layer 13 and located on one side of the second n-type AlGaN layer 21, a drain electrode 16 disposed on the first n-type AlGaN layer 13 and located on the other side of the second n-type AlGaN layer 21, a p-type AlGaN layer 22 disposed on the second n-type AlGaN layer 21 and located on the source electrode 15 side from the center of the second n-type AlGaN layer 21, and a gate electrode 18 disposed on the p-type AlGaN layer 22.

[0027] The details are explained below. The semiconductor device shown in Figure 1 is a polarized junction GaN-based FET (Field Effect Transistor) used as a HEMT (High Electron Mobility Transistor). A polarization junction GaN-based FET has a substrate 10, which may be a Si substrate, sapphire substrate, SiC substrate, GaN substrate, AlN substrate, or Ga2O3 substrate. A buffer layer 11 is formed on the substrate 10. This buffer layer 11 is called a superlattice structure (SLS) and may be formed from, for example, a GaN mixed crystal, so-called AlGaN, InGaN, AlInGaN, or a combination thereof. An n-type GaN layer 12 is arranged on the buffer layer 11.

[0028] A first n-type AlGaN layer (n-AlGaN1) 13 is arranged on an n-type GaN layer (n-GaN) 12. The thickness of the first n-type AlGaN layer 13 is preferably 1 nm or more and 20 nm or less.

[0029] A second n-type AlGaN layer (n-AlGaN2) 21 is arranged on the first n-type AlGaN layer 13. The thickness of the second n-type AlGaN layer 21 is preferably 1 nm or more and 15 nm or less.

[0030] The first and second n-type AlGaN layers 13 and 21 are formed by introducing TMG (trimethylgallium: Ga(CH3)3) along with TMA (trimethylaluminum: (CH3)-Al), a mixed gas containing Al atoms, into the chamber, which causes Ga atoms to be substituted for Al atoms that would otherwise form GaN. If only TMG is introduced into the chamber, n-GaN will grow.

[0031] Polarization by the piezoelectric effect of the first n-type AlGaN layer 13 induces a positive fixed charge in the first n-type AlGaN layer 13 near the interface between the n-type GaN layer 12 and the first n-type AlGaN layer 13, and a negative fixed charge is induced in the first n-type AlGaN layer 13 near the interface between the first n-type AlGaN layer 13 and the second n-type AlGaN layer 21. As a result, a two-dimensional hole gas (2DHG) 30 is formed in the second n-type AlGaN layer 21 near the interface between the first n-type AlGaN layer 13 and the second n-type AlGaN layer 21, and a two-dimensional electron gas (2DEG) 31 is formed in the n-type GaN layer 12 near the interface between the n-type GaN layer 12 and the first n-type AlGaN layer 13. This two-dimensional electron gas (2DEG) 31 becomes the channel of the transistor.

[0032] A source electrode (S) 15 is placed on the first n-type AlGaN layer 13, and this source electrode 15 is located on one side of the second n-type AlGaN layer 21.

[0033] Furthermore, a drain electrode (D) 16 is placed on the first n-type AlGaN layer 13, and this drain electrode 16 is located on the other side of the second n-type AlGaN layer 21. The source electrode 15 and the drain electrode 16 may be made of a multilayer film, for example, a Ti film with a Ni film, Au film, Al film, etc., stacked on top.

[0034] A p-type AlGaN layer (p-AlGaN2) 22 is arranged on the second n-type AlGaN layer 21, and the p-type AlGaN layer 22 is located on the source electrode 15 side from the center of the second n-type AlGaN layer 21. The thickness of the p-type AlGaN layer 22 is preferably 1 nm or more and 20 nm or less.

[0035] The p-type AlGaN layer 22 contains a mixed gas containing Al atoms, TMA (trimethylaluminum: (CH₃)₃Al), along with TMG (trimethylgallium: Ga(CH₃)₃) and Cp₂Mg gas (cyclopentadienylmagnesium gas: C₂₂Mg). 10 H 10 Mg 10 It is formed by introducing ) into the chamber.

[0036] A gate electrode (G) 18 is placed on the p-type AlGaN layer 22, and this gate electrode 18 may be made of a multilayer film in which other metal films are stacked on top of a Ni film, for example.

[0037] According to this embodiment, when the first n-type AlGaN layer 13 is stacked on the n-type GaN layer 12, lattice matching occurs. That is, the upper atomic arrangement matches the lower atomic arrangement. Also, since the second n-type AlGaN layer 21 is made of the same material as the first n-type AlGaN layer 13 below it in terms of AlGaN, lattice matching occurs when the second n-type AlGaN layer 21 grows epitaxially. That is, when growing epitaxially, the lattice constant has good consistency and strain is less likely to occur, so surface defects and lattice defects are less likely to occur in the second n-type AlGaN layer 21. Thereby, it is considered that the leakage current when the transistor is off decreases. At the same time, even if electrons in the two-dimensional electron gas (2DEG) 31, which is a current collapse phenomenon, move over the potential barrier to the first n-type AlGaN layer 13, it can be suppressed from being captured by the surface defect levels of the second n-type AlGaN layer 21.

[0038] The composition of the second n-type AlGaN layer 21 shown in FIG. 1 is Al x Ga 1-x N, and x is preferably 0.01 or more and 0.25 or less. The reason for setting the Al composition in the range of 1 to 25% is that when the Al composition is small, the threshold voltage Vth shifts in the positive direction, which is one of the factors for a normally-off N-off device. As a method for making it N-off, there are two main methods: reducing the Al composition as much as possible or reducing the film thickness of the first p-type AlGaN film 21. In the case of making a normally-off N-off device, it is not the case that both should be made small, and it is preferable to take a balance. If both are made small, the amount of 2DEG decreases, making it difficult to make contact with the first n-type AlGaN layer 13, and it is considered that it becomes difficult to form the film thickness (crystal) of the first p-type AlGaN film 21. "It becomes difficult to form the film thickness (crystal)" means that the film thickness and crystal do not have the necessary physical properties to function.

[0039] The Al concentration of the second n-type AlGaN layer 21 shown in FIG. 1 is preferably 5 atomic % or less. For example, the composition of the second n-type AlGaN layer 21 is Al 0.05 Ga 0.95Setting it to N reduces drain source leak when the device is off. The IDSS value for normally off devices becomes smaller.

[0040] The first n-type AlGaN layer 13, the second n-type AlGaN layer 21, and the p-type AlGaN layer 22 each preferably have a thickness in the range of 1 nm to 60 nm. The reasons for setting the thickness of the p-type AlGaN layer 22 within this range are: (1) it is the thickness necessary to have a sufficient amount of holes or electrons to form the p-type; (2) it is the thickness necessary to prevent fracture due to electric field concentration; (3) it is the thickness necessary to maintain a correlation with the substrate that can suppress the occurrence of warping and cracking; for example, if the substrate is thin and the top layer is thick, warping and cracking will occur, so it is necessary to maintain a correlation with the substrate that can suppress the occurrence of such warping and cracking; and (4) it is the thickness necessary to maintain the required crystallinity.

[0041] A more preferable thickness for the first n-type AlGaN layer 13 is in the range of 1 nm to 25 nm. As the thickness of the first n-type AlGaN layer 13 decreases, the 2DEG amount decreases and the threshold voltage Vth shifts to a positive value, so the range of 1 nm to 25 nm is preferable.

[0042] A more preferable thickness for the second n-type AlGaN layer 21 is within the range of 1 nm to 30 nm. The reason for this is that the second n-type AlGaN layer 21 only needs to be thick enough to withstand electric field concentration without being damaged, and simulation results show that a lower limit of 1 nm provides the necessary functionality and is also a thickness that can be manufactured using the manufacturing process.

[0043] (Second embodiment) Figure 2 is a schematic cross-sectional view showing a semiconductor device according to one aspect of the present invention, and the same parts as in Figure 1 are denoted by the same reference numerals.

[0044] This semiconductor device includes an n-type GaN layer 12a, an n-type AlGaN layer 13 disposed on the n-type GaN layer 12a, a first p-type AlGaN layer 21a disposed on the n-type AlGaN layer 13, a source electrode 15 disposed on the n-type AlGaN layer 13 and located on one side of the first p-type AlGaN layer 21a, a drain electrode 16 disposed on the n-type AlGaN layer 13 and located on the other side of the first p-type AlGaN layer 21a, a second p-type AlGaN layer 22 disposed on the first p-type AlGaN layer 21a and located on the source electrode 15 side from the center of the first p-type AlGaN layer 21a, and a gate electrode 18 disposed on the second p-type AlGaN layer 22.

[0045] The details are explained below. The semiconductor device shown in Figure 2 is a polarized junction GaN-based FET (High Electron Mobility Transistor) used as a HEMT (High Electron Mobility Transistor). The polarization junction GaN-based FET has a substrate 10 and a buffer layer 11 similar to those in the first embodiment. An n-type GaN layer 12a is disposed on the buffer layer 11.

[0046] An n-type AlGaN layer (n-AlGaN1) 13 is arranged on an n-type GaN layer (n-GaN) 12a. The thickness of the n-type AlGaN layer 13 is preferably 1 nm or more and 20 nm or less. The method for forming the n-type AlGaN layer 13 and the n-type GaN layer 12a is the same as in the first embodiment.

[0047] A first p-type AlGaN layer (p-AlGaN1) 21a is arranged on the n-type AlGaN layer 13. The thickness of the first p-type AlGaN layer 21a is preferably 1 nm or more and 15 nm or less.

[0048] Polarization due to the piezoelectric effect of the n-type AlGaN layer 13 induces a positive fixed charge in the n-type AlGaN layer 13 near the interface between the n-type GaN layer 12a and the n-type AlGaN layer 13, and a negative fixed charge is induced in the n-type AlGaN layer 13 near the interface between the n-type AlGaN layer 13 and the first p-type AlGaN layer 21a. As a result, a two-dimensional hole gas (2DHG) 30 is formed in the first p-type AlGaN layer 21a near the interface between the n-type AlGaN layer 13 and the first p-type AlGaN layer 21a, and a two-dimensional electron gas (2DEG) 31 is formed in the n-type GaN layer 12a near the interface between the n-type GaN layer 12a and the n-type AlGaN layer 13. This two-dimensional electron gas (2DEG) 31 becomes the channel of the transistor.

[0049] A source electrode (S) 15 is placed on the n-type AlGaN layer 13, and this source electrode 15 is located on one side of the first p-type AlGaN layer 21a.

[0050] Furthermore, a drain electrode (D) 16 is placed on the n-type AlGaN layer 13, and this drain electrode 16 is located on the other side of the first p-type AlGaN layer 21a. The source electrode 15 and the drain electrode 16 may, for example, be made of a multilayer film in which a Ni film, Au film, Al film, etc., are stacked on a Ti film.

[0051] A second p-type AlGaN layer (p-AlGa2) 22 is arranged on the first p-type AlGaN layer 21a, and the second p-type AlGaN layer 22 is located on the source electrode 15 side from the center of the first p-type AlGaN layer 21a. The thickness of the second p-type AlGaN layer 22 is preferably 1 nm or more and 20 nm or less. The methods for forming the first p-type AlGaN layer 21a and the second p-type AlGaN layer 22 are the same as those for the p-type AlGaN layer 22 in the first embodiment.

[0052] A gate electrode (G) 18 is placed on the second p-type AlGaN layer 22, and this gate electrode 18 may be made of a multilayer film in which other metal films are stacked on top of a Ni film, for example.

[0053] According to this embodiment, since the first p-type AlGaN layer 21a has p-type carriers, the balance when the transistor is off is improved, and thus the degradation of the breakdown voltage can be suppressed. In other words, a high breakdown voltage is achieved.

[0054] Furthermore, since the first p-type AlGaN layer 21a is made of the same material as the underlying n-type AlGaN layer 13 in terms of being AlGaN, lattice matching occurs during epitaxial growth of the first p-type AlGaN layer 21a. In other words, during epitaxial growth, the lattice constants match well and strain is less likely to occur, so surface defects and lattice defects are less likely to occur in the first p-type AlGaN layer 21a. As a result, leakage current when the transistor is off is expected to decrease. Along with this, even if electrons from the two-dimensional electron gas (2DEG) 31, which is a current collapse phenomenon, move across the potential barrier to the n-type AlGaN layer 13, it is possible to suppress their capture by defect levels inherent in the first p-type AlGaN layer 21a.

[0055] Furthermore, in this embodiment, the second n-type GaN layer in the conventional polarization junction GaN-based FET is replaced with a first p-type AlGaN layer 21a having p-type carriers. This means that even when electrons from the two-dimensional electron gas (2DEG) 31, accelerated by a high voltage, move across the potential barrier to the n-type AlGaN layer 13 when the transistor is ON, these electrons are neutralized with holes in the first p-type AlGaN layer 21a. Therefore, it is believed that the negative charging of the lower part of the n-type AlGaN layer 13 can be suppressed. Consequently, the depletion of electrons in the channel of the two-dimensional electron gas (2DEG) 31 directly beneath the n-type AlGaN layer 13 can be suppressed. As a result, the increase in channel resistance can be suppressed, the decrease in drain current can be suppressed, and the increase in on-resistance can be suppressed. Thus, it becomes possible to suppress the current collapse phenomenon. In other words, the first p-type AlGaN layer 21a can also be considered to have the function of balancing the polarization of the n-type AlGaN layer 13 by the piezoelectric effect. Based on the above explanation, a low-loss GaN-based FET can be realized.

[0056] The composition of the first p-type AlGaN layer 21a shown in Figure 2 is Alx Ga 1-x The value is N, and x should be between 0.01 and 0.25. The reason for setting the Al composition to the range of 1-25% is that a smaller Al composition causes the threshold voltage Vth to shift to the positive side, which is one factor in becoming a normally reoff N-off device. There are two main ways to make it N-off: either make the Al composition as small as possible, or reduce the thickness of the first p-type AlGaN film 21a. When making it a normally reoff N-off device, it is not simply a matter of making both small; it is preferable to strike a balance. If both are reduced, the amount of 2DEG decreases, making it difficult to make contact with the n-type AlGaN layer 13, and making it difficult to form the thickness (crystal) of the first p-type AlGaN film 21a. "Difficulty in forming the thickness (crystal)" means that the thickness or crystal does not have the necessary physical properties to function.

[0057] The Al concentration of the first p-type AlGaN layer 21a shown in Figure 2 is preferably 5 atomic percent or less. For example, the composition of the first n-type AlGaN layer 21a is Al 0.05 Ga 0.95 Setting it to N reduces drain source leak when the device is off. The IDSS value for normally off devices becomes smaller.

[0058] The n-type AlGaN layer 13, the first p-type AlGaN layer 21a, and the second p-type AlGaN layer 22 each preferably have a thickness in the range of 1 nm to 60 nm. The reasons for setting the thickness of the first p-type AlGaN layer 21a and the second p-type AlGaN layer 22 in this range are: (1) it is the thickness necessary to have a sufficient amount of holes or electrons to form the p-type; (2) it is the thickness necessary to prevent fracture due to electric field concentration; (3) it is the thickness necessary to maintain a correlation with the substrate that can suppress the occurrence of warping and cracking; for example, if the substrate is thin and the top layer is thick, warping and cracking will occur, so it is necessary to maintain a correlation with the substrate that can suppress the occurrence of such warping and cracking; and (4) it is the thickness necessary to maintain the required crystallinity.

[0059] A more preferable thickness for the n-type AlGaN layer 13 is 1 nm to 25 nm. As the thickness of the n-type AlGaN layer 13 decreases, the 2DEG amount decreases and the threshold voltage Vth shifts to a positive value, so the range of 1 nm to 25 nm is preferable. A more preferable thickness for the first p-type AlGaN layer 21a is 1 nm to 30 nm. [Explanation of symbols]

[0060] 10 circuit boards 11 Buffer Layer 12 n-type GaN layer (n-GaN) 12a n-type GaN layer 12a 13. First n-type AlGaN layer, n-type AlGaN layer (n-AlGaN1) 15 Source electrode (S) 16 Drain electrode (D) 18 Gate Tube (G) 21. Second n-type AlGaN layer (n-AlGaN2) 21a First p-type AlGaN layer (p-AlGaN1) 22 p-type AlGaN layer, second p-type AlGaN layer (p-AlGaN2)

Claims

1. n-type GaN layer, A first n-type AlGaN layer is disposed on the aforementioned n-type GaN layer, A second n-type AlGaN layer is disposed on the first n-type AlGaN layer, A source electrode is disposed on the first n-type AlGaN layer and located on one side of the second n-type AlGaN layer, A drain electrode is disposed on the first n-type AlGaN layer and located on the other side of the second n-type AlGaN layer, A p-type AlGaN layer is disposed on the second n-type AlGaN layer and is located on the source electrode side from the center of the second n-type AlGaN layer, A gate electrode disposed on the p-type AlGaN layer, It has, A semiconductor device characterized in that the Al concentration of the second n-type AlGaN layer is 5 atomic percent or less.

2. n-type GaN layer, An n-type AlGaN layer disposed on the aforementioned n-type GaN layer, A first p-type AlGaN layer is disposed on the n-type AlGaN layer, A source electrode is disposed on the n-type AlGaN layer and located on one side of the first p-type AlGaN layer, A drain electrode is disposed on the n-type AlGaN layer and located on the other side of the first p-type AlGaN layer, A second p-type AlGaN layer is disposed on the first p-type AlGaN layer and is located on the source electrode side from the center of the first p-type AlGaN layer, A gate electrode disposed on the second p-type AlGaN layer, A semiconductor device characterized by having the following features.

3. In claim 2, The composition of the first p-type AlGaN layer is Al ｘ Ga １－ｘ A semiconductor device characterized by being N and x being between 0.01 and 0.

25.

4. In claim 2 or 3, A semiconductor device characterized in that the Al concentration of the first p-type AlGaN layer is 5 atomic percent or less.

5. In any one of claims 1 to 3, The n-type GaN layer is placed on a buffer layer, The semiconductor device is characterized in that the buffer layer is arranged on a substrate.

6. In claim 5, The substrate is a Si substrate, a sapphire substrate, a SiC substrate, a GaN substrate, an AlN substrate, or Ga ２ O ３ A semiconductor device characterized by being a substrate.

7. In claim 1, A semiconductor device characterized in that each of the first n-type AlGaN layer, the second n-type AlGaN layer, and the p-type AlGaN layer has a thickness in the range of 1 nm to 60 nm.

8. In claim 2 or 3, A semiconductor device characterized in that each of the n-type AlGaN layer, the first p-type AlGaN layer, and the second p-type AlGaN layer has a thickness in the range of 1 nm to 60 nm.

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