Semiconductor device and method for manufacturing a semiconductor device

Abstract

To provide a semiconductor device capable of suppressing an increase of a contact resistance, and a method for manufacturing the semiconductor device.SOLUTION: A semiconductor device includes a semiconductor layer, first and second electrodes, a control electrode, and a connection region. The semiconductor layer includes first to third semiconductor regions. The control electrode faces the first to third semiconductor regions via an insulating film. The connection region is positioned between the first electrode and the first semiconductor region and electrically connects the first electrode to the first semiconductor region. The connection region includes a compound of a first metallic element and Si, and a compound of Pt and Si. The first metallic element is at least one selected from the group consisting of Ti, V, Cr, Zr, Mo, Hf, Ta, and W. The connection region includes a first part adjacent to an n-type region of the semiconductor layer in a first direction. A peak position of a concentration distribution of the first metallic element in the first direction of the first part is between the n-type region and a peak position of a concentration distribution of Pt in the first direction of the first part.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices and methods for manufacturing semiconductor devices. [Background technology]

[0002] In semiconductor devices, a connection region is formed in the semiconductor layer, for example, containing silicide, to which electrodes are connected. It is desirable to suppress the increase in electrical resistance (contact resistance) through the connection region between the electrodes and the semiconductor layer. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Patent No. 3803631 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] The problem that this invention aims to solve is to provide a semiconductor device and a method for manufacturing a semiconductor device that can suppress the increase in contact resistance. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a semiconductor layer, a first electrode, a second electrode, a control electrode, and a connection region. The semiconductor layer includes a first semiconductor region, a second semiconductor region, and a third semiconductor region. The first semiconductor region is of a first conductivity type. The second semiconductor region is in contact with the first semiconductor region and is of a second conductivity type. The third semiconductor region is provided such that a part of the second semiconductor region is located between it and the first semiconductor region and is of a first conductivity type. The first electrode is electrically connected to the first semiconductor region. The second electrode is electrically connected to the third semiconductor region. The control electrode faces each of the first semiconductor region, the second semiconductor region, and the third semiconductor region via an insulating film. The connection region is located between the first electrode and the first semiconductor region and electrically connects the first electrode and the first semiconductor region. The connection region includes a compound of Si with at least one first metal element selected from the group consisting of Ti, V, Cr, Zr, Mo, Hf, Ta, and W, and a compound of Pt and Si. The connection region includes a first portion adjacent to the n-type region of the semiconductor layer in a first direction. The peak position of the concentration distribution of the first metal element in the first portion in the first direction is between the peak position of the concentration distribution of Pt in the first portion in the first direction and the n-type region. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment. [Figure 2] Figure 2 is a schematic cross-sectional view illustrating a semiconductor device according to a modified embodiment. [Figure 3] Figure 3 is a schematic cross-sectional view illustrating a semiconductor device according to a modified embodiment. [Figure 4] Figure 4 is a schematic cross-sectional view illustrating a semiconductor device according to a modified embodiment. [Figure 5] Figure 5 is a schematic cross-sectional view illustrating a semiconductor device according to a modified embodiment. [Figure 6]Figures 6(a) to 6(e) are schematic cross-sectional views illustrating the manufacturing process of a semiconductor device according to an embodiment. [Modes for carrying out the invention]

[0007] Each embodiment of the present invention will be described below with reference to the drawings. Drawings are schematic or conceptual, and the relationships between the thickness and width of each part, as well as the ratios of the sizes of different parts, are not necessarily identical to those of reality. Even when representing the same part, the dimensions and ratios may be depicted differently in different drawings. In this specification and in each figure, elements similar to those already described are denoted by the same reference numerals, and detailed explanations are omitted as appropriate. In the following description and drawings, n + , n, n - and p + The notation "p" indicates the relative level of each impurity concentration. That is, a notation with "+" indicates a relatively higher impurity concentration than a notation without either "+" or "-", and a notation with "-" indicates a relatively lower impurity concentration than a notation without either. When both p-type and n-type impurities are present in each region, these notations represent the relative level of the net impurity concentration after the impurities have compensated for each other.

[0008] Figure 1 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment. In Figure 1, a vertical n-channel MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) is shown as an example of a semiconductor device 101 according to the embodiment. The semiconductor device 101 includes a semiconductor layer 10, a first electrode 21, a second electrode 22, and a plurality of control electrodes 23. In the n-channel MOSFET, the semiconductor layer 10 includes a plurality of source regions 11 (first semiconductor region), a plurality of contact regions 12 (fourth semiconductor region), a plurality of body regions 13 (second semiconductor region), a drift region 14 (third semiconductor region), and a drain region 15 (fifth semiconductor region).

[0009] In describing the embodiments, the XYZ Cartesian coordinate system is used. The direction from the second electrode 22 toward the first electrode 21 is defined as the Z direction. The two directions perpendicular to the Z direction and mutually orthogonal are defined as the X and Y directions. For the sake of explanation, the direction from the second electrode 22 toward the first electrode 21 is referred to as "up," and the opposite direction is referred to as "down." These directions are based on the relative positional relationship between the first electrode 21 and the second electrode 22 and are independent of the direction of gravity.

[0010] The second electrode 22 is provided on the lower surface 10s of the semiconductor layer 10. The second electrode 22 is, for example, a drain electrode. The second electrode 22 contains a metal such as aluminum.

[0011] The drain region 15 is in contact with the upper surface of the second electrode 22 and is electrically connected to the second electrode 22. In this example, the drain region 15 is n-type (an example of the first conductivity type). The drain region 15 is, for example, n + This is the drain region.

[0012] The drift region 14 is located above the drain region 15 and is in contact with the drain region 15. The drift region 14 is electrically connected to the second electrode 22 via the drain region 15. In this example, the drift region 14 is n-type. The concentration of n-type impurities in the drift region 14 is lower than the concentration of n-type impurities in the drain region 15. The drift region 14 is, for example, n - This is a region of shape drift.

[0013] The body region 13 is located above a portion of the drift region 14 and is in contact with the drift region 14. A portion 13a of the body region 13 is located between the source region 11 and the drift region 14. In this example, the body region 13 is p-type (an example of a second conductivity type). The concentration of p-type impurities in the body region 13 is lower than the concentration of p-type impurities in the contact region 12. The body region 13 is, for example, a p-type body region.

[0014] The source region 11 is provided on a part of the body region 13 and is in contact with the body region 13. The source region 11 is away from the drift region 14. The source region 11 forms a part of the upper surface 10u (the surface opposite to the lower surface 10s) of the semiconductor layer 10. Two source regions 11 arranged in the X direction are provided on one body region 13. The source region 11 is n-type in this example. The source region 11 is, for example, an n + -type source region.

[0015] The contact region 12 is provided on a part of the body region 13 and is in contact with the body region 13. In this example, the contact region 12 is arranged in the X direction parallel to the source region 11 and is in contact with the source region 11. The contact region 12 is located between the two source regions 11 on one body region 13. The contact region 12 is p-type in this example. The contact region 12 is, for example, a p + -type region.

[0016] Each semiconductor region (source region 11 to drain region 15) of the semiconductor layer 10 contains silicon as a semiconductor material. As an n-type impurity, arsenic, phosphorus, or antimony can be used. As a p-type impurity, boron can be used.

[0017] The control electrode 23 faces the source region 11, the body region 13 (part 13a), and the drift region 14 respectively through the insulating film 31. In this example, the insulating film 31 is provided on the upper surface 10u of the semiconductor layer 10, and the control electrode 23 is provided on the insulating film 31. The upper surface and side surfaces of the control electrode 23 are covered by the insulating film 32. For example, the control electrode 23 is a gate electrode, and the insulating film 31 is a gate insulating film. The control electrode 23 contains a conductive material such as polysilicon. The insulating film 31 and the insulating film 32 contain an insulating material such as silicon oxide or silicon nitride.

[0018] The first electrode 21 is provided on the semiconductor layer 10 and the insulating film 32. The first electrode 21 is electrically connected to the source region 11 and the contact region 12. The first electrode 21 is insulated from the control electrode 23 by the insulating film 32. The first electrode 21 is, for example, a source electrode. The first electrode 21 contains a metal such as titanium or aluminum. The first electrode 21 may have a multilayer structure. For example, the first electrode 21 may have a multilayer structure containing, from bottom to top, a titanium film, a titanium nitride film, a tungsten film, and an aluminum film.

[0019] Specifically, the first electrode 21 includes a plurality of contact portions 21c. The contact portions 21c are located between two control electrodes 23 (insulating film 32) aligned in the X direction. On the upper surface 10u side of the semiconductor layer 10, a connection region 50 (e.g., a conductive region) to which the contact portions 21c are connected is provided. The connection region 50 is located between the first electrode 21 and the source region 11, electrically connecting the first electrode 21 and the source region 11. The connection region 50 is also located between the first electrode 21 and the contact region 12, electrically connecting the first electrode 21 and the contact region 12. The connection region 50 is in contact with the source region 11, the contact region 12, and the first electrode 21, respectively.

[0020] The connecting region 50 includes a first metallic element, a second metallic element, and silicon. The first metallic element is at least one selected from the group consisting of, for example, titanium (Ti), vanadium (V), chromium (Cr), zirconium (Zr), molybdenum (Mo), hafnium (Hf), tantalum (Ta), and tungsten (W). The second metallic element is platinum (Pt).

[0021] For example, the connecting region 50 includes a compound of a first metal element and silicon (Si) (first silicide) and a compound of a second metal element and Si (second silicide). The connecting region 50 may have a first region 51 containing the first silicide and a second region 52 containing the second silicide. For convenience, the boundary between the first region 51 and the second region 52 is shown as a dashed line in the cross-sectional view.

[0022] As shown in Figure 1, the connection region 50 has a first portion 50a adjacent to the n-type region of the semiconductor layer 10 in a first direction (e.g., the Z direction). The first portion 50a is adjacent in the first direction to, for example, one of the n-type regions of the source region 11 and the contact region 12 (in this example, the source region 11). That is, in this example, the first portion 50a is the portion of the connection region 50 between the source region 11 and the first electrode 21. The first portion 50a is located directly above the source region 11 and is in contact with the source region 11. The first portion 50a may include, for example, a part of the first region 51 and a part of the second region 52.

[0023] The concentration distribution of the first metal element in the first direction (e.g., the Z direction) in the first part 50a peaks (maximum) at the first position P1. The concentration distribution of the second metal element in the first direction (e.g., the Z direction) in the first part 50a peaks (maximum) at the second position P2. The position of the first position P1 in the first direction is between the position of the second position P2 in the first direction and the position of at least a part of the source region 11 (the n-type region) in the first direction.

[0024] The first region 51 is, for example, a silicide layer of the first metal element. For example, in the first region 51, the concentration of the first metal element is higher than the concentration of the second metal element. For example, the concentration of the first metal element in the first region 51 is higher than the concentration of the first metal element in the second region 52.

[0025] The second region 52 is, for example, a silicide layer of the second metal element. For example, in the second region 52, the concentration of the second metal element is higher than the concentration of the first metal element. For example, the concentration of the second metal element in the second region 52 is higher than the concentration of the second metal element in the first region 51.

[0026] Furthermore, the first region 51 does not necessarily have to contain a second metallic element or a second silicide. The second region 52 does not necessarily have to contain a first metallic element or a first silicide. The range of not containing metallic elements includes cases where they are substantially absent, such as when they are below the detection limit.

[0027] At least a portion of the first region 51 is located between the source region 11 and the first electrode 21 and is in contact with the source region 11. For example, the first region 51 (first silicide) is in Schottky contact with the source region 11. At least a portion of the second region 52 is located between the first region 51 and the first electrode 21 and is in contact with both the first region 51 and the first electrode 21.

[0028] For example, the first region 51 is located directly beneath a part of the second region 52. The first region 51 is formed only on the n-type semiconductor region (source region 11 in this example) and does not have to be formed on the p-type semiconductor region (contact region 12 in this example). However, the first region 51 may be in contact with the contact region 12. Also, in this example, the second region 52 is positioned between the first region 51 and the first electrode 21, and the first region 51 is not in contact with the first electrode 21. However, the first region 51 may be in contact with the first electrode 21.

[0029] Each of the multiple source regions 11 has a plurality of first regions 51. The second region 52 is provided continuously on two first regions 51 aligned in the X direction, and on a contact region 12 located between those two first regions 51. One contact portion 21c is in contact with the upper surface of one of the second regions 52. In this way, a part of the second region 52 is located between the contact region 12 and the first electrode 21, and is in contact with both the contact region 12 and the first electrode 21. For example, the second region 52 (second silicide) is in Schottky contact with the contact region 12. The second region 52 may or may not be in contact with the n-type semiconductor region (source region 11 in this example).

[0030] The aforementioned first portion 50a is the portion where the first region 51 and the second region 52 overlap in the first direction. The first position P1 where the concentration of the first metal element peaks in the first portion 50a is within the first region 51. The second position P2 where the concentration of the second metal element peaks in the first portion 50a is within the second region 52.

[0031] The concentrations of the first and second metal elements in the connection region 50 can be, for example, concentrations (atomic percent) obtained by elemental analysis using energy-dispersive X-ray spectroscopy (TEM-EDX) with a transmission electron microscope.

[0032] The contact portion 21c, the source region 11, and the contact region 12 each extend in the Y direction. The connection region 50 extends in the Y direction along the contact portion 21c, the source region 11, and the contact region 12.

[0033] Furthermore, the state in which one region touches another does not necessarily require a clearly observable boundary between the regions; the regions may be continuous or directly connected (joined).

[0034] The operation of the semiconductor device 101 will be described. For example, a positive voltage is applied to the second electrode 22 and the control electrode 23, respectively, with the voltage of the first electrode 21 as the reference (0V). When a voltage greater than the threshold voltage is applied to the control electrode 23, an inversion layer (channel) is formed near the interface between the body region 13 and the insulating film 31. This results in an ON state where current flows from the second electrode 22 to the first electrode 21 through the drain region 15, drift region 14, body region 13, and source region 11. When the voltage of the control electrode 23 is below the threshold voltage (e.g., 0V), the channel disappears, and an OFF state is obtained where virtually no current flows from the second electrode 22 to the first electrode 21. The contact region 12, body region 13, drift region 14, and drain region 15 also function as body diodes. In other words, when a negative voltage is applied to the second electrode 22 with the voltage of the first electrode 21 as a reference, current flows from the first electrode 21 to the second electrode 22 via the contact region 12, body region 13, drift region 14, and drain region 15. The semiconductor device according to this embodiment may be an IGBT (Insulated Gate Bipolar Transistor) or a reverse-conducting IGBT. That is, for example, a semiconductor region of a second conductivity type may be provided on at least a portion of the second electrode 22. The drift region 14 is electrically connected to the second electrode 22 via this semiconductor region of the second conductivity type. As described above, the connection region 50 contains Pt. For example, Pt can be diffused from the surface side of the semiconductor layer 10 into each semiconductor region by heat treatment. This makes it possible to control the lifetime of carriers in the semiconductor layer 10 and suppress power loss during switching.

[0035] The effects of this embodiment will be described. When a compound of Pt and Si (second silicide) comes into contact with an n-type semiconductor region, a high energy barrier is formed between the second silicide and the n-type semiconductor region. Therefore, the electrical resistance between the electrode connected to the second silicide and the n-type semiconductor region may increase through the second silicide. In other words, the contact resistance may increase.

[0036] In contrast, in this embodiment, for example, the peak position (first position P1) of the concentration distribution of the first metal element in the first direction in the first portion 50a of the connection region 50 is between the peak position (second position P2) of the concentration distribution of Pt in the first direction in the first portion 50a and the n-type source region 11. In this case, contact between the source region 11 and the second silicide is suppressed, and the formation of a high energy barrier between the source region 11 and the second silicide is suppressed. This suppresses an increase in contact resistance.

[0037] Furthermore, in this embodiment, the source region 11 is in contact with, for example, the first region 51. That is, the source region 11 is in contact with a compound of a first metal element and Si (first silicide). Even when the first silicide is in contact with the n-type semiconductor region, an energy barrier is formed between the first silicide and the n-type semiconductor region. However, the energy barrier between the first silicide and the n-type semiconductor region is lower than the energy barrier between the second silicide and the n-type semiconductor region. When the source region 11 is in contact with the first region 51, the energy barrier between the source region 11 and the first silicide is relatively low, so the increase in electrical resistance between the source region 11 and the first region 51 is suppressed. In other words, the increase in contact resistance can be suppressed.

[0038] Furthermore, the energy barrier formed between the second silicide and the p-type semiconductor region, which are in contact with each other, is lower than the energy barrier formed between the first silicide and the p-type semiconductor region, which are in contact with each other. Therefore, when the contact region 12 is in contact with the second region 52, the electrical resistance between the connection region 50 and the contact region 12 can be reduced compared to when the p-type contact region 12 is in contact with the first region 51.

[0039] For example, the work function of the first silicide is smaller than the work function of the second silicide. Therefore, the Schottky barrier formed by the Schottky contact between the first silicide and the n-type semiconductor region is lower than the Schottky barrier formed by the Schottky contact between the second silicide and the n-type semiconductor region. Also, the Schottky barrier formed by the Schottky contact between the second silicide and the p-type semiconductor region is lower than the Schottky barrier formed by the Schottky contact between the first silicide and the p-type semiconductor region. For example, the work function of the first silicide can be between 4.05 eV and 4.85 eV, more preferably between 4.40 eV and 4.80 eV.

[0040] Figure 2 is a schematic cross-sectional view illustrating a semiconductor device according to a modified embodiment. The semiconductor device 102 according to the embodiment shown in Figure 2 differs from the semiconductor device 101 described with respect to Figure 1 in the arrangement of the first region 51 of the connection region 50.

[0041] In the semiconductor device 102, the first region 51 is located directly beneath the entire area of ​​the second region 52. The first region 51 is formed on an n-type semiconductor region (source region 11 in this example) and on a p-type semiconductor region (contact region 12 in this example). More specifically, the first region 51 is continuously provided on two source regions 11 aligned in the X direction and on the contact region 12 between the two source regions 11. The first region 51 is in contact with the source region 11 and the contact region 12. For example, one second region 52 is provided on one first region 51. A part of the first region 51 is located between the second region 52 and the contact region 12, and the second region 52 does not necessarily have to be in contact with the contact region 12.

[0042] Figure 3 is a schematic cross-sectional view illustrating a semiconductor device according to a modified embodiment. The semiconductor device 103 according to the embodiment shown in Figure 3 differs from the semiconductor device 101 described with respect to Figure 1 in the arrangement of the control electrodes 23.

[0043] In the semiconductor device 103, a plurality of trenches T1 are provided on the upper surface 10u of the semiconductor layer 10. The insulating film 31 is provided on the inner surface (side and bottom surface) of the trenches T1. The control electrode 23 is provided inside the insulating film 31 of the trenches T1. In the X direction, the control electrode 23 is aligned with the source region 11, the body region 13, and the drift region 14, respectively. The insulating film 31 is positioned between the control electrode 23 and the source region 11, between the control electrode 23 and the body region 13, and between the control electrode 23 and the drift region 14. Thus, the control electrode 23 may be provided, for example, as a trench gate.

[0044] Figure 4 is a schematic cross-sectional view illustrating a semiconductor device according to a modified embodiment. The semiconductor device 104 according to the embodiment shown in Figure 4 differs from the semiconductor device 103 described with respect to Figure 3 in the arrangement of the contact portion 21c, connection area 50, and contact area 12.

[0045] In the semiconductor device 104, a plurality of trenches T2 are provided on the upper surface 10u of the semiconductor layer 10. For example, trenches T1 and T2 are arranged alternately in the X direction. The lower part 21cd of the contact portion 21c is located within the trenches T2. Therefore, the lower part 21cd of the contact portion 21c is located below the upper surface 10u of the semiconductor layer 10 and is aligned in the X direction with the control electrode 23, the source region 11, and the body region 13, respectively. The contact region 12 is located at the bottom of the trench T2, above a part of the body region 13. Therefore, in this example, the contact region 12 is located below the source region 11 and does not necessarily have to be in contact with the source region 11. The lower part 21cd of the contact portion 21c is located above the contact region 12 via a second region 52. The first region 51 and the second region 52 each have portions 51z and 52z that extend in the Z direction along the side surface of the lower part 21cd of the contact portion 21c. Thus, the contact portion 21c may be provided as, for example, a trench contact.

[0046] Figure 5 is a schematic cross-sectional view illustrating a semiconductor device according to a modified embodiment. The semiconductor device 105 shown in Figure 5 is an embodiment in which the p-type and n-type semiconductor regions are reversed compared to the semiconductor device 101 described with respect to Figure 1. That is, in semiconductor devices 101 to 104, the first conductivity type was n-type and the second conductivity type was p-type. In contrast, in semiconductor device 105, the first conductivity type is p-type and the second conductivity type is n-type. The semiconductor device 105 is, for example, a p-channel MOSFET. In semiconductor device 105, the arrangement of the first region 51 differs from that of semiconductor device 101, corresponding to the arrangement of the n-type and p-type semiconductor regions. In a p-channel MOSFET, the semiconductor layer 10 includes a plurality of source regions 11 (first semiconductor regions), a plurality of contact regions 12 (fourth semiconductor regions), a plurality of body regions 13 (second semiconductor regions), a drift region 14 (third semiconductor region), and a drain region 15 (fifth semiconductor region).

[0047] The source region 11 is p-type (e.g., a p-type source region). The contact region 12 is n-type (e.g., an n-type region). The body region 13 is n-type (e.g., an n-type body region). The drift region 14 is p-type (e.g., a p-type drift region). The drain region 15 is p-type (e.g., a p-type drain region). + The contact region 12 is n-type (e.g., an n-type region). The body region 13 is n-type (e.g., an n-type body region). The drift region 14 is p-type (e.g., a p-type drift region). The drain region 15 is p-type (e.g., a p-type drain region). + The body region 13 is n-type (e.g., an n-type body region). The drift region 14 is p-type (e.g., a p-type drift region). The drain region 15 is p-type (e.g., a p-type drain region). - The drift region 14 is p-type (e.g., a p-type drift region). The drain region 15 is p-type (e.g., a p-type drain region). + The drain region 15 is p-type (e.g., a p-type drain region).

[0048] As shown in FIG. 5, the connection region 50 has a first portion 50a that is adjacent in the first direction (e.g., the Z direction) to an n-type region of the semiconductor layer 10. The first portion 50a is adjacent in the first direction to, for example, one of the source region 11 and the contact region 12 that is n-type (the contact region 12 in this example). That is, in this example, the first portion 50a is the portion between the contact region 12 and the first electrode 21 in the connection region 50. The first portion 50a is located directly above the contact region 12 in the connection region 50 and is in contact with the contact region 12.

[0049] At least a part of the first region 51 is located between the contact region 12 and the first electrode 21 and is in contact with the contact region 12. For example, the first region 51 (first silicide) is in Schottky contact with the contact region 12. A part of the second region 52 is located between the first region 51 and the first electrode 21 and is in contact with the first region 51 and the first electrode 21.

[0050] For example, the first region 51 may be formed only on an n-type semiconductor region (the contact region 12 in this example) and not necessarily on a p-type semiconductor region (the source region 11 in this example). However, the first region 51 may be in contact with the source region 11.

[0051] Each of the multiple contact regions 12 has a plurality of first regions 51. The second region 52 is provided continuously on two source regions 11 aligned in the X direction, and on the first region 51 located between the two source regions 11. One contact portion 21c is in contact with the upper surface of one of the second regions 52. In this way, a part of the second region 52 is located between the source region 11 and the first electrode 21, and is in contact with both the source region 11 and the first electrode 21. For example, the second region 52 (second silicide) is in Schottky contact with the source region 11. The second region 52 may or may not be in contact with the n-type semiconductor region (contact region 12 in this example).

[0052] For example, the peak position (first position P1) of the concentration distribution of the first metal element in the first direction in the first part 50a of the connection region 50 is between the peak position (second position P2) of the concentration distribution of Pt in the first direction in the first part 50a and the n-type contact region 12. In this case, contact between the contact region 12 and the second silicide is suppressed, and the formation of a high energy barrier between the contact region 12 and the second silicide is suppressed. This suppresses an increase in contact resistance.

[0053] Furthermore, when the n-type contact region 12 is in contact with the first region 51 (for example, the first silicide), the energy barrier between the n-type semiconductor region and the first silicide is relatively low, so the increase in electrical resistance between the contact region 12 and the first region 51 can be suppressed. In other words, the increase in contact resistance can be suppressed. Also, when the p-type source region 11 is in contact with the second region 52 (for example, the second silicide), the energy barrier between the p-type semiconductor region and the second silicide is relatively low, so the increase in electrical resistance between the source region 11 and the second region 52 can be suppressed.

[0054] Thus, in each semiconductor device according to this embodiment, the p-type and n-type of each semiconductor region may be reversed. In this case, the first region 51 is arranged to be adjacent to the n-type semiconductor region.

[0055] Figures 6(a) to 6(e) are schematic cross-sectional views illustrating the manufacturing process of a semiconductor device according to an embodiment. Figures 6(a) to 6(e) show the manufacturing process of the semiconductor device 101 as explained in Figure 1. As shown in Figure 6(a), a semiconductor layer 10 is prepared. The semiconductor layer 10 is provided with a source region 11, a contact region 12, a body region 13, a drift region 14, and a drain region 15. An insulating film 31, a control electrode 23, and an insulating film 32 are provided on the upper surface 10u of the semiconductor layer 10. An opening OP is formed in the insulating film 32 and insulating film 31, located above the source region 11 and the contact region 12. In other words, the insulating film 32 and insulating film 31 are not formed on the surface region 10a of the semiconductor layer 10, which includes a part of the source region 11 and a part of the contact region 12. The upper surface 10u of the semiconductor layer 10 (the upper surface of the surface region 10a) may be exposed upward through the opening OP.

[0056] Subsequently, the first metal element is implanted into at least a portion of the surface region 10a of the semiconductor layer 10. For example, as shown in Figure 6(b), the first metal element M1 is ion-implanted through an aperture OP into the n-type semiconductor region (source region 11) of the surface region 10a. For example, by forming a mask on the p-type semiconductor region (contact region 12) of the surface region 10a using photolithography or the like, the first metal element M1 is not implanted into the p-type semiconductor region. However, the first metal element M1 may be implanted over the entire area of ​​the aperture OP without forming a mask.

[0057] Subsequently, a second metal element is deposited on the surface region 10a of the semiconductor layer 10. For example, as shown in Figure 6(c), a film M2f containing the second metal element is formed on the surface region 10a and the insulating film 32 by sputtering. This introduces the second metal element to the region of the surface region 10a above the location where the first metal element M1 is implanted.

[0058] Subsequently, as shown in Figure 6(d), the film M2f is removed and the surface is cleaned using, for example, aqua regia or dilute hydrofluoric acid. Then, the second metal element introduced into the surface region 10a is diffused into the semiconductor layer 10 by heat treatment.

[0059] In the surface region 10a, heat causes the semiconductor layer 10 to react with the first metal element, and then the semiconductor layer 10 to react with the second metal element, forming a connection region 50. In this example, the heat from the sputtering process in Figure 6(c) (and the heat from the diffusion process in Figure 6(d)) forms the first region 51 (first silicide) and the second region 52 (second silicide). A heat treatment process for forming the silicide may be provided as needed.

[0060] Subsequently, as shown in Figure 6(e), a first electrode 21 is formed on the connection region 50 using, for example, a sputtering method. A second electrode 22 is also formed on the lower surface of the semiconductor layer 10 using, for example, a sputtering method.

[0061] Furthermore, the method for introducing the second metal element into the surface region 10a is not limited to depositing a film M2f containing the second metal element. For example, a method may be used in which the second metal element is implanted in a region above the location where at least a portion of the first metal element M1 is implanted in the surface region 10a. For example, instead of the steps of depositing and removing the film M2f, the second metal element may be ion-implanted through an opening OP at a position shallower than at least a portion of the first metal element M1 in the surface region 10a.

[0062] The embodiment may include the following configurations. (Composition 1) The first semiconductor region of the first conductivity type, A second semiconductor region of a second conductivity type in contact with the first semiconductor region, A third semiconductor region of a first conductivity type is provided such that a portion of the second semiconductor region is located between it and the first semiconductor region, A semiconductor layer including, A first electrode electrically connected to the first semiconductor region, A second electrode electrically connected to the third semiconductor region, Control electrodes facing the first semiconductor region, the second semiconductor region, and the third semiconductor region, respectively, via an insulating film, A connection region is located between the first electrode and the first semiconductor region, electrically connecting the first electrode and the first semiconductor region, and includes a compound of Si and at least one first metal element selected from the group consisting of Ti, V, Cr, Zr, Mo, Hf, Ta, and W, and a compound of Pt and Si, and includes a first portion of the semiconductor layer adjacent to the n-type region in a first direction, wherein the peak position of the concentration distribution of the first metal element in the first portion in the first direction is between the peak position of the concentration distribution of Pt in the first portion in the first direction and the n-type region, A semiconductor device equipped with [the necessary components]. (Configuration 2) The first conductive type mentioned above is n-type, The aforementioned second conductivity type is p-type, The semiconductor device according to configuration 1, wherein the first portion is between the first semiconductor region and the first electrode. (Composition 3) The aforementioned connection area is The compound comprising the first metal element and Si, at least a portion of which is a first region located between the first semiconductor region and the first electrode and in contact with the first semiconductor region, The compound comprises Pt and Si, and at least a portion of it comprises a second region located between the first region and the first electrode and in contact with the first electrode, A semiconductor device as described in configuration 2, including the above. (Composition 4) Further comprising a fourth semiconductor region of the second conductivity type, The second semiconductor region is in contact with the fourth semiconductor region and has a lower impurity concentration of the second conductivity type than the fourth semiconductor region. The semiconductor device according to any one of configurations 1 to 3, wherein the connection region is located between the first electrode and the fourth semiconductor region and electrically connects the first electrode and the fourth semiconductor region. (Composition 5) Further comprising a fourth semiconductor region of the second conductivity type, The second semiconductor region is in contact with the fourth semiconductor region and has a lower impurity concentration of the second conductivity type than the fourth semiconductor region. The connection region is located between the first electrode and the fourth semiconductor region and electrically connects the first electrode and the fourth semiconductor region. The fourth semiconductor region is in contact with the second region, and is the semiconductor device according to configuration 3. (Composition 6) Further comprising a fourth semiconductor region of the second conductivity type, The second semiconductor region is in contact with the fourth semiconductor region and has a lower impurity concentration of the second conductivity type than the fourth semiconductor region. The connection region is located between the first electrode and the fourth semiconductor region and electrically connects the first electrode and the fourth semiconductor region. The first conductive type is p-type, The second conductive type is n-type, The semiconductor device according to configuration 1, wherein the first portion is between the fourth semiconductor region and the first electrode. (Composition 7) The aforementioned connection area is The compound comprising the first metal element and Si, at least a portion of which is a first region located between the fourth semiconductor region and the first electrode and in contact with the fourth semiconductor region, The compound comprises Pt and Si, and at least a portion of it comprises a second region located between the first region and the first electrode and in contact with the first electrode, A semiconductor device as described in configuration 6, including the above. (Composition 8) The semiconductor device according to configuration 7, wherein the first semiconductor region is in contact with the second region. (Composition 9) The first semiconductor region of the first conductivity type, A second semiconductor region of a second conductivity type in contact with the first semiconductor region, A third semiconductor region of a first conductivity type is provided such that a portion of the second semiconductor region is located between it and the first semiconductor region, A semiconductor layer including, A first electrode electrically connected to the first semiconductor region, A second electrode electrically connected to the third semiconductor region, Control electrodes facing the first semiconductor region, the second semiconductor region, and the third semiconductor region, respectively, via an insulating film, A connecting region is located between the first electrode and the first semiconductor region, electrically connecting the first electrode and the first semiconductor region, and includes a first region containing the first metal element, in contact with the n-type region of the semiconductor layer, and containing a compound of Si and at least one first metal element selected from the group consisting of Ti, V, Cr, Zr, Mo, Hf, Ta, and W, and a compound of Pt and Si, and a second region in contact with the first electrode, containing Pt, having a lower concentration of the first metal element than the first region, or not containing the first metal element. A semiconductor device equipped with [the necessary components]. (Composition 10) The first semiconductor region of the first conductivity type, A second semiconductor region of a second conductivity type in contact with the first semiconductor region, A third semiconductor region of a first conductivity type is provided such that a portion of the second semiconductor region is located between it and the first semiconductor region, The process includes preparing a semiconductor layer in which the control electrode faces the second semiconductor region and the third semiconductor region, respectively, via an insulating film, A step of implanting at least one first metal element selected from the group consisting of Ti, V, Cr, Zr, Mo, Hf, Ta, and W into at least a portion of the surface region of the semiconductor layer, which includes a portion of the first semiconductor region; A step of depositing Pt on the surface region, or injecting Pt into a region of the surface region above the location where at least a portion of the first metal element is injected, A step of forming a connection region on which the semiconductor layer and the first metal element react in the surface region and the semiconductor layer and Pt react to form a first electrode that is electrically connected to the first semiconductor region, A step of forming a second electrode that is electrically connected to the aforementioned third semiconductor region, A method for manufacturing a semiconductor device, comprising the features described above.

[0063] According to the embodiment, a semiconductor device and a method for manufacturing a semiconductor device that can suppress an increase in contact resistance can be provided.

[0064] The relative levels of impurity concentrations between semiconductor regions in each embodiment described above can be confirmed, for example, using an SCM (Scanning Capacitive Microscope). The carrier concentration in each semiconductor region can be considered equal to the concentration of activated impurities in that region. Therefore, the relative levels of carrier concentrations between semiconductor regions can also be confirmed using an SCM. The relative levels of impurity concentrations between semiconductor regions can be considered equivalent to the relative levels of carrier concentrations between those regions. Furthermore, the impurity concentration in each semiconductor region can be measured, for example, by SIMS (Secondary Ion Mass Spectrometry). "Impurity concentration" may refer to the net impurity concentration after the cancellation of both donor and acceptor impurities in each region.

[0065] In this specification, "electrically connected" includes not only cases where the connection is made by direct contact, but also cases where the connection is made via other conductive members or the like. The phrase "placed on top of" one element may include not only cases where the two elements are touching (or continuous) with each other, but also cases where another element is placed between the two elements. For example, the phrase "placed on top of" one element may include cases where one element is located above another element, regardless of whether the two elements are touching each other or not.

[0066] Although several embodiments of the present invention have been illustrated above, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. Furthermore, the embodiments described above can be implemented in combination with each other. [Explanation of Symbols]

[0067] 10: Semiconductor layer 10a: Surface area 10s: Bottom side 10u:Top surface 11: Source Area 12: Contact area 13: Body area 13a: Some 14: Drift Region 15: Drain area 21: 1st electrode 21c: Contact area 21cd: bottom 22:Second electrode 23: Control electrode 31: Insulating Film 32: Insulating film 50: Connection area 50a: 1st part 51:First area 51z:part 52:Second area 52z:part 101-105: Semiconductor Equipment M1: First metal element M2f: Membrane OP: Opening P1: 1st position P2: 2nd position T1: Trench T2: Trench

Claims

1. The first semiconductor region of the first conductivity type, A second semiconductor region of a second conductivity type in contact with the first semiconductor region, A third semiconductor region of a first conductivity type is provided such that a part of the second semiconductor region is located between it and the first semiconductor region, A semiconductor layer including, A first electrode electrically connected to the first semiconductor region, A second electrode electrically connected to the third semiconductor region, Control electrodes facing each of the first semiconductor region, the second semiconductor region, and the third semiconductor region via an insulating film, A connection region is located between the first electrode and the first semiconductor region, electrically connecting the first electrode and the first semiconductor region, and includes a compound of Si and at least one first metal element selected from the group consisting of Ti, V, Cr, Zr, Mo, Hf, Ta, and W, and a compound of Pt and Si, and includes a first portion adjacent to the n-type region of the semiconductor layer in a first direction, wherein the peak position of the concentration distribution of the first metal element in the first portion in the first direction is between the peak position of the concentration distribution of Pt in the first portion in the first direction and the n-type region, A semiconductor device equipped with [the necessary components].

2. The first conductive type is n-type, The aforementioned second conductivity type is p-type, The semiconductor device according to claim 1, wherein the first portion is between the first semiconductor region and the first electrode.

3. The aforementioned connection area is The compound comprising the first metal element and Si, at least a portion of which is a first region located between the first semiconductor region and the first electrode and in contact with the first semiconductor region, The compound comprising Pt and Si, at least a portion of which is a second region located between the first region and the first electrode and in contact with the first electrode, The semiconductor device according to claim 2, including the above.

4. Further comprising a fourth semiconductor region of the second conductivity type, The second semiconductor region is in contact with the fourth semiconductor region and has a lower impurity concentration of the second conductivity type than the fourth semiconductor region. The semiconductor device according to any one of claims 1 to 3, wherein the connection region is located between the first electrode and the fourth semiconductor region and electrically connects the first electrode and the fourth semiconductor region.

5. Further comprising a fourth semiconductor region of the second conductivity type, The second semiconductor region is in contact with the fourth semiconductor region and has a lower impurity concentration of the second conductivity type than the fourth semiconductor region. The connection region is located between the first electrode and the fourth semiconductor region and electrically connects the first electrode and the fourth semiconductor region. The semiconductor device according to claim 3, wherein the fourth semiconductor region is in contact with the second region.

6. Further comprising a fourth semiconductor region of the second conductivity type, The second semiconductor region is in contact with the fourth semiconductor region and has a lower impurity concentration of the second conductivity type than the fourth semiconductor region. The connection region is located between the first electrode and the fourth semiconductor region and electrically connects the first electrode and the fourth semiconductor region. The first conductivity type is p-type, The second conductive type is n-type, The semiconductor device according to claim 1, wherein the first portion is between the fourth semiconductor region and the first electrode.

7. The aforementioned connection area is The compound comprising the first metal element and Si, at least a portion of which is a first region located between the fourth semiconductor region and the first electrode and in contact with the fourth semiconductor region, The compound comprising Pt and Si, at least a portion of which is a second region located between the first region and the first electrode and in contact with the first electrode, The semiconductor device according to claim 6, including the above.

8. The semiconductor device according to claim 7, wherein the first semiconductor region is in contact with the second region.

9. The first semiconductor region of the first conductivity type, A second semiconductor region of a second conductivity type in contact with the first semiconductor region, A third semiconductor region of a first conductivity type is provided such that a part of the second semiconductor region is located between it and the first semiconductor region, A semiconductor layer including, A first electrode electrically connected to the first semiconductor region, A second electrode electrically connected to the third semiconductor region, Control electrodes facing each of the first semiconductor region, the second semiconductor region, and the third semiconductor region via an insulating film, A connecting region is located between the first electrode and the first semiconductor region, electrically connecting the first electrode and the first semiconductor region, and includes a first region containing the first metal element, in contact with the n-type region of the semiconductor layer, and containing a compound of at least one first metal element selected from the group consisting of Ti, V, Cr, Zr, Mo, Hf, Ta, and W and Si, and a compound of Pt and Si, and a second region in contact with the first electrode, containing Pt, having a lower concentration of the first metal element than the first region, or not containing the first metal element, A semiconductor device equipped with [the necessary components].

10. The first semiconductor region of the first conductivity type, A second semiconductor region of a second conductivity type in contact with the first semiconductor region, A third semiconductor region of a first conductivity type is provided such that a part of the second semiconductor region is located between it and the first semiconductor region, The process includes preparing a semiconductor layer in which the control electrode faces the second semiconductor region and the third semiconductor region, respectively, via an insulating film, A step of implanting at least one first metal element selected from the group consisting of Ti, V, Cr, Zr, Mo, Hf, Ta, and W into at least a portion of the surface region of the semiconductor layer, which includes a portion of the first semiconductor region; A step of depositing Pt on the surface region, or injecting Pt into a region of the surface region above the location where at least a portion of the first metal element is injected, A step of forming a connection region on which the semiconductor layer and the first metal element react in the surface region and the semiconductor layer and Pt react to form a first electrode that is electrically connected to the first semiconductor region, A step of forming a second electrode that is electrically connected to the aforementioned third semiconductor region, A method for manufacturing a semiconductor device, comprising the features described above.

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