Vertical Cavity Surface Emitting Laser Array

Abstract

To provide a device having a plurality of vertical cavity surface emitting lasers (VCSELs) that is addressable in groups.SOLUTION: The device has a bottom RDL that is able to electrically couple a first group of VCSELs to a first bond pad through a bond pad via. The device also has a top RDL that is able to electrically couple a second group of VCSELs to a second bond pad through a group of VCSEL vias. Each VCSEL of the second group of VCSELs is electrically coupled to a corresponding VCSEL via of the group of VCSEL vias. Furthermore, the plurality of VCSEL may be positioned in any manner including random positioning.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Cross - Reference to Related Applications

[0001] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 659,567, entitled "METHODS FOR AND SYSTEM OF VERTICAL CAVITY SURFACE EMITTING LASERS ARRAYS (Methods and Systems for Vertical Cavity Surface Emitting Laser Arrays)", filed on June 13, 2024, the disclosure of which is incorporated herein by reference in its entirety.

Background Art

[0002]

[0002] The limitations and drawbacks of conventional systems and methods for addressing vertical - cavity surface - emitting lasers (VCSELs) will become apparent to those skilled in the art by comparing such techniques with some aspects of the methods and systems described in the remainder of this disclosure, with reference to the drawings.

Summary of the Invention

[0003]

[0003] A system and method for addressing vertical - cavity surface - emitting lasers (VCSELs) are provided, substantially as shown in at least one of the figures and / or described in connection with this figure, and more fully described by the claims.

Brief Description of the Drawings

[0004] [Figure 1]

[0004] A figure showing an example of an ohmic RDL in a system with independently addressable VCSELs, according to various implementations of the present disclosure. [Figure 2]

[0005] A figure showing an example of an insulating layer in a system with independently addressable VCSELs, according to various implementations of the present disclosure. [Figure 3]

[0006] This figure shows an example of a first address layer in a system with independently addressable VCSELs, based on various implementations of the present disclosure. [Figure 4]

[0007] This figure shows an example of a top-level RDL in a system with independently addressable VCSELs, based on various implementations of this disclosure. [Figure 5]

[0008] This figure shows a cross-sectional example of a system with independently addressable VCSELs, based on various implementation examples of this disclosure. [Figure 6]

[0009] This figure shows another example of a system with independently addressable VCSELs, based on various implementations of this disclosure. [Modes for carrying out the invention]

[0005]

[0010] Vertical-cavity surface-emitting laser (VCSEL) arrays can be used in three-dimensional sensing applications. This disclosure describes a VCSEL array design having a number of independent channels (or subarrays). VCSEL emitters of different channels may be mixed and arranged in irregular (e.g., random or semi-random) locations.

[0006]

[0011] Multi-channel ordered arrays can be designed and processed relatively simply, and therefore can be single-channel disordered arrays. However, disordered arrays with a large number of independent mixed channels tend to be more complex to design and / or process.

[0007]

[0012] This disclosure provides a system and method for designing a multichannel array having mixed and irregularly arranged emitters while retaining the relative simplicity of layout, processing, and design rules enjoyed by a multichannel array having alternating row contacts.

[0008]

[0013] A multi-channel VCSEL array can have subarrays of emitters that are either physically separated from each other or mixed in the form of alternating row contacts. In these alternating row contact designs, the rows of emitters are generally placed within the center of the row contacts. As a result, these designs tend to have regular emitter locations and the emitters are not sufficiently mixed.

[0009]

[0014] An addressable VCSEL array may comprise an array of emitters arranged in a primary (i.e., row or column), secondary, or tertiary configuration. The emitters in the array may be arranged such that emitters belonging to different channels are spatially separated and / or interleaved within the array location.

[0010]

[0015] In an interleaved configuration, emitters belonging to different arrays are connected via multilayer redistribution layers (RDLs), with each RDL assigned to a single array channel. The RDLs are routed and overlaid to connect to the individual ohmic contacts of the VCSEL, thereby creating the desired interleaved pattern.

[0011]

[0016] This disclosure describes a method for a multi-channel interleaved VCSEL array, in which ohmic RDLs and multiple RDLs may be used in association to connect assigned emitters to one another. This minimizes the number of RDLs required and thus simplifies the design and fabrication of the apparatus.

[0012]

[0017] Multi-channel VCSEL arrays with mixed emitters and irregular emitter locations can utilize vertically stacked sheet contacts. While these solutions allow for significant mixing and irregularity of emitter locations, processing and layout requirements tend to become more complex to ensure effective isolation between different channels, raising concerns regarding capacitance between parallel sheet contacts (which can potentially limit the pulsing rate of these arrays), emitter output uniformity (when the lower sheet contacts may have significantly different series resistances for different emitters), and dielectric breakdown (when the lower sheet contacts introduce additional topology).

[0013]

[0018] This disclosure relates to the design of individual vertical-cavity surface-emitting lasers (VCSELs) and to a method for arranging VCSELs in an array and making electrical contact. Such VCSEL arrays may be used, for example, for three-dimensional sensing.

[0014]

[0019] Figure 1 shows an example of an ohmic RDL in a system with independently addressable VCSELs, based on various implementations of this disclosure.

[0020] The apparatus in Figure 1 comprises multiple VCSELs, with emitters 101 and 103 of each VCSEL shown. Each VCSEL in the multiple VCSELs comprises an emitter aperture which may have a diameter of, for example, 10 to 15 microns. Each VCSEL in the multiple VCSELs may be operable to emit light of a specific wavelength (e.g., less than 1000 nm) (e.g., infrared light).

[0015]

[0021] The lower / ohmic RDL in Figure 1 comprises a first continuous metal surface 102 and one or more discrete metal surfaces 104. Each of the multiple VCSELs is connected to the ohmic contact metal 102 or 104 in the lower RDL.

[0016]

[0022] The first continuous metal surface 102 can electrically couple the first VCSEL group (e.g., one VCSEL having emitter 103) to the first bond pad (see 115 in Figures 3 to 5) via the first bond pad via 107. As shown, the first VCSEL group (including emitter B103) forms channel B.

[0017]

[0023] Each discrete metal surface 104 can electrically couple one VCSEL in the second VCSEL group (e.g., one VCSEL having emitter 101) to a second bond pad (see 111 in Figures 4 and 5) via VCSEL via 105. As shown, the second VCSEL group (with emitter A 101) forms channel A. Each VCSEL in the second VCSEL group is connected to another discrete metal surface 104 in the lower RDL. Each other discrete metal surface 104 is coupled to another VCSEL via 105. Each discrete metal surface 104 in the lower RDL is physically separated from the first continuous metal surface 102 106. The physical separation can be 1.5 to 2 microns.

[0018]

[0024] In various implementations, the first VCSEL group and the second VCSEL group each contain one or more VCSELs from a set of multiple VCSELs. For illustrative purposes, Figures 1 to 5 show the first and second VCSEL groups as one VCSEL per group. Figure 6 shows the first and second VCSEL groups as two or more VCSELs per group.

[0019]

[0025] Figure 2 shows an example of an insulating layer 109 in a system comprising independently addressable VCSELs 101 and 103, according to various implementations of the present disclosure. The insulating layer 109 (including, for example, SiO2 and / or SiN) can electrically isolate the lower RDL (see 102 and 104 in Figure 1) from the upper RDL (see upper RDL 113 in Figures 4 and 5). A group of VCSEL vias 105 and a first bond pad via 107 extend through the insulating layer 109.

[0020]

[0026] FIG. 3 shows an example of a first address layer in a system with independently addressable VCSELs according to various implementation examples of the present disclosure. The first bond pad 115 is physically connected to (and on) the insulating layer 109 and is electrically coupled to a first group of VCSELs (including emitter B 103) via via 107 and the first continuous metal surface 102.

[0021]

[0027] FIG. 4 shows an example of an upper RDL 113 in a system with independently addressable VCSELs according to various implementation examples of the present disclosure.

[0028] A second bond pad (bond pad A 111) is physically connected to the upper RDL 113. The upper RDL 113 is operable to electrically couple a second group of VCSELs 101 to the second bond pad 111 via a group of VCSEL vias 105. The second group of VCSELs 101 includes one or more SCSELs of the plurality of VCSELs. The first group of VCSELs 103 includes VCSELs different from the second group of VCSELs 101. Each VCSEL of the second group 101 of VCSELs is electrically coupled to a corresponding VCSEL via 105 of the group of VCSEL vias.

[0022]

[0029] FIG. 5 shows a cross-sectional example of a system with independently addressable VCSELs according to various implementation examples of the present disclosure.

[0030] The lower RDL 123 includes dedicated or assigned ohmic contact metal to connect each emitter to the assigned channel of the emitter array. In that case, the RDL is connected to the bond pad 111 or 115 of the device. Optical paths 117 and 119 for each of the plurality of VCSELs 101 and 103 penetrate the aperture.

[0023]

[0031] Emitters A101 and B103 are connected to the lower RDL123. The lower RDL123 bypasses the upper RDL113 and is directly connected to the bond pad 115. The lower RDL123 has a continuous metal surface 102 and a discrete metal surface 104, as shown in Figure 1.

[0024]

[0032] This approach, in which the lower RDL123 is used for addressing capabilities, reduces the number of RDL layers to enable interleaved address VCSEL design, thereby simplifying the process flow.

[0025]

[0033] Figure 6 shows another example of a system with independently addressable VCSELs, based on various implementations of the present disclosure.

[0034] The multiple VCSELs in Figure 6 include three channel groups. Channel A addresses the group of devices A 601 with bond pad A607. Channel B addresses the group of devices B 603 with bond pad B609. Channel C addresses the group of devices C 605 with bond pad C611. All VCSELs within a specific channel (e.g., A, B, or C) are driven simultaneously.

[0026]

[0035] The group of apparatus B 603 and the group of apparatus C 605 are each coupled to different continuous metal surfaces in the lower RDL. As shown in the figure, multiple VCSELs are arranged randomly. Also, the number of VCSELs in each particular channel / group (e.g., A, B, or C) does not have to be the same. For example, in some embodiments, the number of VCSELs in one group may be more than 10 times the number of VCSELs in another group.

[0027]

[0036] As used herein, the terms “circuit” and “circuitry” mean physical electronic components (i.e., hardware) and any software and / or firmware ("code") that may constitute the hardware, may be executed by the hardware, and / or may otherwise be associated with the hardware. As used herein, for example, a particular processor and memory may comprise a first “circuit” when executing one or more first lines of code, and a second “circuit” when executing one or more second lines of code. As used herein, “and / or” means any one or more items in the list joined by “and / or”. For example, “x and / or y” means any element of the set of three elements {(x), (y), (x,y)}. For another example, “x, y, and / or z” means any element of the set of seven elements {(x), (y), (z), (x,y), (x,z), (y,z), (x,y,z)}. As used herein, the term “exemplary” means serving as an unrestricted example, instance, or illustration. As used herein, the terms “e.g.” and “for example” emphasize a list of one or more unrestricted examples, instances, or illustrations. As used herein, a network is “operable” to perform a function whenever the network has the necessary hardware and code (if any), regardless of whether the performance of that function is disabled or enabled (e.g., by user-configurable settings, factory trim, etc.). As used herein, the term “based on” means “at least partially based on.” For example, “x based on y” means that “x” is at least partially based on “y” (for example, it could also be based on z).

[0028]

[0037] While the Method and / or System has been described with reference to a specific implementation, it will be understood by those skilled in the art that various modifications can be made and equivalents can be substituted without departing from the scope of the Method and / or System. In addition, many modifications can be made without departing from the scope to adapt the teachings of this disclosure to specific circumstances or materials. Therefore, the Method and / or System is not limited to the specific implementation disclosed, and the Method and / or System includes all implementations within the scope of the appended claims.

Claims

1. Multiple vertical-cavity surface-emitting lasers (VCSELs), A lower redistribution layer (RDL) that can operate to electrically couple the electrodes of each VCSEL in the first VCSEL group to the first bond pad via the first bond pad via, An upper RDL that can operate to electrically couple the electrodes of each VCSEL in the second VCSEL group to the second bond pad via the VCSEL via group, An insulating layer that can operate to electrically isolate the lower RDL from the upper RDL, A device equipped with, The electrodes of each VCSEL in the first VCSEL group and the electrodes of each VCSEL in the second VCSEL group are either positive or negative electrodes. The first VCSEL group comprises one or more VCSELs from the plurality of VCSELs, The second VCSEL group comprises one or more VCSELs from the plurality of VCSELs, The first VCSEL group comprises VCSELs different from the second VCSEL group. Each VCSEL in the second VCSEL group is electrically coupled to the corresponding VCSEL via of the VCSEL via group. Each VCSEL in the first VCSEL group and each VCSEL in the second VCSEL group can be addressed independently. Device.

2. The apparatus according to claim 1, Each of the plurality of VCSELs is equipped with an emitter aperture having a diameter of less than 15 microns. Device.

3. The apparatus according to claim 1, Each of the plurality of VCSELs is capable of emitting light in the infrared spectrum. Device.

4. The apparatus according to claim 1, Each of the plurality of VCSELs is connected to the ohmic contact metal in the lower RDL. Device.

5. The apparatus according to claim 1, Each VCSEL in the first VCSEL group is connected to a first continuous metal surface in the lower RDL. Device.

6. The apparatus according to claim 5, The first continuous metal surface is electrically coupled to the first bond pad via. Device.

7. The apparatus according to claim 5, Each VCSEL in the second VCSEL group is connected to a discrete metal surface in the lower RDL. Device.

8. The apparatus according to claim 7, Each discrete metal surface connected to each VCSEL in the second VCSEL group is electrically coupled to the corresponding VCSEL via. Device.

9. The apparatus according to claim 7, Each discrete metal surface within the lower RDL is physically separated from the first continuous metal surface. Device.

10. The apparatus according to claim 9, The physical separation is 1.5 to 2 microns. Device.

11. The apparatus according to claim 1, The VCSEL via group and the first bond pad via extend through the insulating layer. Device.

12. The apparatus according to claim 1, The first bond pad is physically connected to the insulating layer. Device.

13. The apparatus according to claim 1, The second bond pad is physically connected to the upper RDL. Device.

14. The apparatus according to claim 1, The optical paths for each of the plurality of VCSELs penetrate the insulating layer and the upper RDL. Device.

15. The apparatus according to claim 1, The lower RDL is operable to electrically couple the third VCSEL group to the third bond pad via the second bond pad via. Device.

16. The apparatus according to claim 15, Each VCSEL in the third VCSEL group is connected to a second continuous metal surface in the lower RDL. Device.

17. The apparatus according to claim 16, The second continuous metal surface is electrically coupled to the second bond pad via. Device.

18. The apparatus according to claim 1, The aforementioned multiple VCSELs are arranged randomly. Device.

19. The apparatus according to claim 1, The second VCSEL group comprises more than 10 times the number of VCSELs in the first VCSEL group. Device.

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