Semiconductor equipment

Abstract

To provide a semiconductor device capable of improving operation characteristics.SOLUTION: A semiconductor device according to an embodiment includes: a first nitride semiconductor layer 12 provided on a substrate 10; a second nitride semiconductor layer 13 provided on the first nitride semiconductor layer 12 and having a band gap wider than that of the first nitride semiconductor layer 12; a source electrode 14 and a drain electrode 15, being provided on the second nitride semiconductor layer 13 separately from each other; a gate electrode 16 provided on the second nitride semiconductor layer 13 and disposed between the source electrode 14 and the drain electrode 15; a first field plate electrode SFP1 provided on the second nitride semiconductor layer 13, disposed between the gate electrode 16 and the drain electrode 15, and electrically connected to the source electrode 14; and a second field plate electrode SFP2 provided on the first field plate electrode SFP1 and formed to project toward the gate electrode 16.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices. [Background technology]

[0002] Semiconductor elements such as transistors and diodes are used in circuits such as switching power supply circuits and inverter circuits. These semiconductor elements require high voltage resistance and low on-resistance. There is a trade-off relationship between voltage resistance and on-resistance, which is determined by the element material.

[0003] Thanks to advances in technological development, semiconductor devices have achieved extremely low on-resistance, close to the limits of silicon, the primary device material. To further improve voltage resistance or reduce on-resistance, it is necessary to change the device material. By using nitride semiconductors such as gallium nitride and aluminum gallium nitride as the device material for semiconductor devices, the trade-off relationship determined by the device material can be improved. This makes it possible to dramatically increase the voltage resistance and lower the on-resistance of semiconductor devices.

[0004] To ensure low loss and high reliability in transistors using nitride semiconductors, it is necessary to reduce the gate-drain capacitance Cgd, which is a parasitic capacitance, and to mitigate localized electric field concentration that occurs internally during operation. Field plate electrodes are used to mitigate electric field concentration in transistors.

[0005] Furthermore, reducing the gate-drain capacitance Cgd improves switching speed and reduces switching losses. However, reducing the gate-drain capacitance Cgd increases noise during switching operation. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2020-150193 [Overview of the project] [Problems that the invention aims to solve]

[0007] The problem that this invention aims to solve is to provide a semiconductor device capable of improving its operating characteristics. [Means for solving the problem]

[0008] The semiconductor device according to the embodiment includes a first nitride semiconductor layer provided on a substrate, a second nitride semiconductor layer provided on the first nitride semiconductor layer and having a larger band gap than the first nitride semiconductor layer, a source electrode and a drain electrode provided spaced apart from each other on the second nitride semiconductor layer, a gate electrode provided on the second nitride semiconductor layer and positioned between the source electrode and the drain electrode, and on the second nitride semiconductor layer directly The device comprises a first field plate electrode provided and positioned between the gate electrode and the drain electrode and electrically connected to the source electrode, and a second field plate electrode provided on the first field plate electrode and configured to protrude toward the gate electrode. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a cross-sectional view of a semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a diagram illustrating the operation of a semiconductor device. [Figure 3] Figure 3 is a graph illustrating the relationship between drain-source voltage and capacitance. [Figure 4] Figure 4 is a cross-sectional view of a semiconductor device according to the second embodiment. [Figure 5] Figure 5 is a cross-sectional view of the semiconductor device according to the third embodiment. [Figure 6] Figure 6 is a cross-sectional view of a semiconductor device according to the fourth embodiment. [Figure 7] Figure 7 is a cross-sectional view of a semiconductor device according to the fifth embodiment. [Figure 8] Figure 8 is a cross-sectional view of a semiconductor device according to the sixth embodiment. [Modes for carrying out the invention]

[0010] Embodiments will be described below with reference to the drawings. The embodiments shown below are illustrative examples of devices and methods for realizing the technical concept of the present invention, and the technical concept of the present invention is not defined by the shape, structure, arrangement, etc. of the components. Each functional block can be realized as hardware, software, or a combination of both. It is not essential that each functional block is distinguished as in the following example. For example, some functions may be performed by functional blocks other than the illustrative functional blocks. Furthermore, the illustrative functional blocks may be further divided into finer functional subblocks. In the following description, elements having the same function and configuration are denoted by the same reference numerals, and redundant descriptions are omitted.

[0011] [1] First Embodiment [1-1] Configuration of semiconductor device 1 Figure 1 is a cross-sectional view of a semiconductor device 1 according to the first embodiment. The semiconductor device 1 is a nitride semiconductor device using a nitride semiconductor as a compound. Furthermore, the semiconductor device 1 is a field-effect transistor (FET), and more specifically, a high-electron-mobility transistor (HEMT).

[0012] The semiconductor device 1 comprises a substrate 10, a buffer layer 11, a channel layer 12, a barrier layer 13, a source electrode 14, a drain electrode 15, a gate electrode 16, and field plate electrodes SFP1 and SFP2.

[0013] The substrate 10 is composed of, for example, a silicon (Si) substrate. As the substrate 10, silicon carbide (SiC), gallium nitride (GaN), gallium phosphide (GaP), indium phosphide (InP), gallium arsenide (GaAs), or sapphire (Al2O3) may be used. Further, the substrate 10 may be composed of a SOI (Silicon On Insulator) substrate having a structure in which an insulating layer (SiO2) is inserted between the Si substrate and the surface Si layer.

[0014] A buffer layer 11 is provided on the substrate 10. The buffer layer 11 has a function of relaxing the strain caused by the difference between the lattice constant of the nitride semiconductor layer formed on itself and the lattice constant of the substrate 10, and controlling the crystallinity of the nitride semiconductor layer formed on itself. The buffer layer 11 is composed of, for example, Al W Ga 1-W N (0 < W ≦ 1). The buffer layer 11 may be formed by laminating a plurality of Al W Ga 1-W N. In this case, the composition ratios of the plurality of layers may be adjusted so that the lattice constant changes from the lowermost layer to the uppermost layer. The buffer layer 11 may be formed by alternately laminating a plurality of layers of aluminum nitride (AlN) layer and gallium nitride (GaN) layer.

[0015] A channel layer 12 is provided on the buffer layer 11. The channel layer 12 is a layer in which a channel (current path) of the transistor is formed. The channel layer 12 is also referred to as an electron traveling layer. The channel layer 12 is composed of a nitride semiconductor, for example, a nitride semiconductor having good crystallinity (high quality). The channel layer 12 is, for example, undoped aluminum gallium nitride (Al X Ga 1-X N (0 ≦ X < 1)). More specifically, the channel layer 12 is, for example, undoped gallium nitride (GaN). Undoped means that impurities are not intentionally doped. For example, the amount of impurities that enter during the manufacturing process or the like is within the category of undoped. In this specification, undoped means that the impurity concentration is 2 × 10 16 cm -3It means the following. The thickness of the channel layer 12 is, for example, 0.1 μm or more and 10 μm or less.

[0016] A barrier layer 13 is provided on the channel layer 12. The barrier layer 13 is composed of a nitride semiconductor. The barrier layer 13 is also referred to as an electron supply layer. The bandgap of the barrier layer 13 is larger than the bandgap of the channel layer 12. The barrier layer 13 is, for example, composed of undoped aluminum gallium nitride (Al Y Ga 1-Y N (0 < Y ≦ 1, X < Y)). More specifically, the barrier layer 13 is, for example, composed of undoped AlGaN. The composition ratio of Al in the AlGaN layer as the barrier layer 13 is, for example, about 0.2. The thickness of the barrier layer 13 is, for example, 2 nm or more and 100 nm or less.

[0017] Note that the plurality of semiconductor layers constituting the semiconductor device 1 are sequentially formed by epitaxial growth using, for example, the MOCVD (Metal Organic Chemical Vapor Deposition) method. That is, the plurality of semiconductor layers constituting the semiconductor device 1 are composed of epitaxial layers.

[0018] Source electrodes 14 and drain electrodes 15 spaced apart from each other are provided on the barrier layer 13. Further, a gate electrode 16 spaced apart from the source electrodes 14 and the drain electrodes 15 is provided on the barrier layer 13 and between the source electrodes 14 and the drain electrodes 15.

[0019] The gate electrode 16 and the barrier layer 13 are in a Schottky contact. That is, the gate electrode 16 is configured to include a material that forms a Schottky contact with the barrier layer 13. As the gate electrode 16, for example, titanium nitride (TiN) is used. The semiconductor device 1 shown in FIG. 1 is a Schottky barrier type HEMT. Note that the semiconductor device 1 is not limited to a Schottky barrier type HEMT, and may be a MIS (Metal Insulator Semiconductor) type HEMT in which a gate insulating film is interposed between the barrier layer 13 and the gate electrode 16.

[0020] The source electrode 14 and the barrier layer 13 are in ohmic contact. Similarly, the drain electrode 15 and the barrier layer 13 are in ohmic contact. That is, each of the source electrode 14 and the drain electrode 15 is configured to include a material that makes ohmic contact with the barrier layer 13. For example, a laminated structure in which titanium (Ti) and aluminum (Al) are stacked in that order can be used as the source electrode 14 and the drain electrode 15.

[0021] An insulating layer 17 is provided on the barrier layer 13, gate electrode 16, source electrode 14, and drain electrode 15. The insulating layer 17 is made of silicon oxide (SiO2), silicon nitride (SiN), or a high-dielectric constant (high-k) material. Examples of high-k materials include hafnium oxide (HfO2).

[0022] (Field plate electrode configuration) Next, the configuration of the field plate electrodes SFP1 and SFP2 will be described. The field plate electrodes have the function of mitigating the concentration of electric fields at predetermined locations such as the gate electrode terminal and improving the breakdown voltage. The field plate electrodes SFP1 and SFP2 are electrically connected to the source electrode 14. That is, the field plate electrodes SFP1 and SFP2 are set to the same potential (e.g., 0V) as the source electrode 14. For example, the field plate electrodes SFP1 and SFP2 are electrically connected to terminals (pads) for applying voltage to the source electrode 14.

[0023] The field plate electrode SFP1 is provided on the barrier layer 13 and between the gate electrode 16 and the drain electrode 15. The field plate electrode SFP1 has the function of mitigating localized electric field concentration in the barrier layer 13. The height of the field plate electrode SFP1 is set to be less than or equal to the height of the gate electrode 16, for example. The height of the field plate electrode SFP1 is set to be the same as the height of the gate electrode 16, for example. The field plate electrode SFP1 is made of the same conductive material as the gate electrode 16. Note that the configuration is not limited to the field plate electrode SFP1 being in contact with the barrier layer 13, and an insulating layer may be interposed between the field plate electrode SFP1 and the barrier layer 13.

[0024] The field plate electrode SFP2 is provided on the field plate electrode SFP1 and is configured to protrude toward the gate electrode 16. In other words, the field plate electrode SFP2 is configured in a stepped manner toward the gate electrode 16. The end of the field plate electrode SFP2 is located on the drain electrode 15 side of the end of the gate electrode 16. The height of the field plate electrode SFP2 from the barrier layer 13 is greater than the height of the gate electrode 16. The field plate electrode SFP2 is made of, for example, aluminum (Al).

[0025] Furthermore, the configuration is not limited to the field plate electrode SFP2 being in contact with the field plate electrode SFP1; an insulating layer may be interposed between the field plate electrode SFP2 and the field plate electrode SFP1. That is, the field plate electrode SFP1 and the field plate electrode SFP2 overlap or have contact in the projection plane in the direction in which each layer is stacked (up and down direction in Figure 1), and are positioned such that the field plate electrode SFP2 is above the field plate electrode SFP1.

[0026] In this specification, the types and concentrations of elements in semiconductor layers and semiconductor regions can be measured, for example, by SIMS (Secondary Ion Mass Spectrometry) and EDX (Energy Dispersive X-ray Spectroscopy). Furthermore, the relative levels of elemental concentrations can be determined, for example, from the carrier concentrations obtained by SCM (Scanning Capacitance Microscopy). Additionally, the depth, thickness, width, and spacing of impurity regions can be determined, for example, by SIMS. These distances can also be determined, for example, from comparative images of SCM images and atom probe images.

[0027] [1-2] Operation The operation of the semiconductor device 1 configured as described above will now be explained. Figure 2 is a diagram illustrating the operation of the semiconductor device 1. The drain-source capacitance is referred to as Cds, the gate-source capacitance as Cgs, and the gate-drain capacitance as Cgd.

[0028] In the heterojunction structure of the channel layer 12 and the barrier layer 13, the barrier layer 13 has a smaller lattice constant than the channel layer 12, causing strain in the barrier layer 13. Due to the piezoelectric effect caused by this strain, piezoelectric polarization occurs within the barrier layer 13, and a two-dimensional electron gas (2DEG) is generated near the interface between the channel layer 12 and the barrier layer 13. This two-dimensional electron gas forms a channel between the source electrode 14 and the drain electrode 15. Furthermore, the Schottky barrier formed by the junction between the gate electrode 16 and the barrier layer 13 enables control of the drain current. In addition, because the two-dimensional electron gas has high electron mobility, the semiconductor device 1 can perform very fast switching operations.

[0029] The semiconductor device 1 is, for example, a normally-on type. When the semiconductor device 1 is turned on, for example, 0V is applied to the gate electrode 16, 0V to the source electrode 14, and a high voltage (for example, 200V) is applied to the drain electrode 15. At this time, a channel CH is formed in the channel layer 12 between the drain electrode 15 and the source electrode 14. A drain current flows between the drain electrode 15 and the source electrode 14 through the channel CH formed in the channel layer 12.

[0030] When semiconductor device 1 is turned off, for example, a negative voltage (e.g., -15V) is applied to the gate electrode 16, 0V to the source electrode 14, and 200V to the drain electrode 15. At this time, the thickness of the depletion layer extending beneath the gate electrode 16 is controlled, and the drain current is interrupted.

[0031] Here, the field plate electrode SFP1 is set to the same potential as the source electrode 14. The field plate electrode SFP1 mitigates localized electric field concentration in the barrier layer 13. In particular, it can mitigate the concentration of the electric field at the edge of the gate electrode 16. This improves the breakdown voltage of the semiconductor device 1.

[0032] The field plate electrode SFP2 is set to the same potential as the source electrode 14. The channel CH is electrically connected to the drain electrode 15. Therefore, the field plate electrode SFP2 constitutes part of the drain-source capacitance Cds.

[0033] In this embodiment, the field plate electrodes SFP1 and SFP2 are configured in a stepped manner, decreasing in height from the gate electrode 16 towards the drain electrode 15 (to the right in the diagram). Therefore, the drain-source capacitance Cds can be changed in steps from the gate electrode 16 towards the drain electrode 15.

[0034] Figure 3 is a graph illustrating the relationship between drain-source voltage Vds and capacitance. In Figure 3, the horizontal axis represents the drain-source voltage Vds (V), and the vertical axis represents the capacitance (F). Figure 3 also shows graphs for drain-source capacitance Cds, gate-source capacitance Cgs, and gate-drain capacitance Cgd.

[0035] In this embodiment, the gate-drain capacitance Cgd can be reduced primarily by the function of the field plate electrode SFP1. This makes it possible to mitigate localized electric field concentration in the barrier layer 13.

[0036] Furthermore, primarily due to the function of the field plate electrode SFP2, the rapid decrease in the drain-source capacitance Cds can be suppressed. This effect is shown in Figure 3(1). In addition, as the drain-source voltage Vds increases, the drain-source capacitance Cds can be gradually reduced. This effect is shown in Figure 3(2). As a result, the rapid change in the drain-source voltage Vds can be suppressed. Therefore, noise during the switching operation of the semiconductor device 1 can be reduced.

[0037] [1-3] Effects of the first embodiment According to the first embodiment, by providing field plate electrodes SFP1 and SFP2 electrically connected to the source electrode 14, localized electric field concentration in the barrier layer 13 can be mitigated. This improves the breakdown voltage of the semiconductor device 1.

[0038] Furthermore, by configuring the field plate electrodes SFP1 and SFP2 in a stepped manner, the drain-source capacitance Cds can be gradually reduced as the drain-source voltage Vds increases. This suppresses rapid changes in the drain-source voltage Vds. As a result, noise during the switching operation of the semiconductor device 1 can be reduced. Ultimately, this makes it possible to realize a semiconductor device 1 with improved operating characteristics.

[0039] [2] Second embodiment In the second embodiment, the three field plate electrodes are configured in a stepped manner, decreasing in height from the gate electrode 16 towards the drain electrode 15.

[0040] Figure 4 is a cross-sectional view of the semiconductor device 1 according to the second embodiment. The semiconductor device 1 includes field plate electrodes SFP1 to SFP3. The configuration of field plate electrodes SFP1 and SFP2 is the same as in the first embodiment.

[0041] The field plate electrode SFP3 is mounted on the field plate electrode SFP2 and is configured to protrude toward the gate electrode 16. The end of the field plate electrode SFP3 is located on the drain electrode 15 side of the end of the gate electrode 16. The height of the field plate electrode SFP3 from the barrier layer 13 is greater than the height of the gate electrode 16. The field plate electrode SFP3 is made of, for example, aluminum (Al). The field plate electrode SFP3 is electrically connected to the source electrode 14.

[0042] The field plate electrodes SFP1 to SFP3 are arranged in a stepped pattern, decreasing in height from the gate electrode 16 towards the drain electrode 15 (to the right in the diagram).

[0043] In the semiconductor device 1 configured in this way, the drain-source capacitance Cds can be changed in steps from the gate electrode 16 to the drain electrode 15. Furthermore, as the drain-source voltage Vds increases, the drain-source capacitance Cds can be reduced more gradually. This reduces noise during the switching operation of the semiconductor device 1. Other effects are the same as in the first embodiment.

[0044] [3] Third embodiment The third embodiment, in addition to the field plate electrode configuration of the first embodiment, configures the field plate electrodes in a stepped manner so that they become higher from the gate electrode 16 towards the drain electrode 15.

[0045] Figure 5 is a cross-sectional view of the semiconductor device 1 according to the third embodiment. The semiconductor device 1 includes field plate electrodes SFP1 to SFP3. The configuration of field plate electrodes SFP1 and SFP2 is the same as in the first embodiment.

[0046] The field plate electrode SFP3 is mounted on the field plate electrode SFP1 and is configured to protrude toward the drain electrode 15. The end of the field plate electrode SFP3 is located closer to the drain electrode 15 than the end of the field plate electrode SFP1. The height of the field plate electrode SFP3 from the barrier layer 13 is greater than the height of the gate electrode 16. The field plate electrode SFP3 is made of, for example, aluminum (Al). The field plate electrode SFP3 is electrically connected to the source electrode 14.

[0047] The field plate electrodes SFP1 and SFP3 are configured in a stepped manner, increasing in height from the gate electrode 16 towards the drain electrode 15 (to the right in the diagram).

[0048] In the semiconductor device 1 configured in this way, localized electric field concentration in the barrier layer 13 can be mitigated. Furthermore, the gate-drain capacitance Cgd can be further reduced. In addition, as the drain-source voltage Vds increases, the drain-source capacitance Cds can be reduced more gradually. Other effects are the same as in the first embodiment.

[0049] As a modification, the field plate electrode SFP3 of the second embodiment may be applied to the third embodiment.

[0050] [4] Fourth Embodiment The fourth embodiment is a modification of the third embodiment, wherein the field plate electrode on the field plate electrode SFP1 is configured as a continuous layer.

[0051] Figure 6 is a cross-sectional view of the semiconductor device 1 according to the fourth embodiment. The semiconductor device 1 includes field plate electrodes SFP1 and SFP2. The configuration of the field plate electrode SFP1 is the same as in the first embodiment.

[0052] The field plate electrode SFP2 is provided on the field plate electrode SFP1 and is configured to protrude from both sides of the field plate electrode SFP1. In other words, the field plate electrode SFP2 includes a first electrode portion that protrudes from the field plate electrode SFP1 toward the gate electrode 16 and a second electrode portion that protrudes from the field plate electrode SFP1 toward the drain electrode 15. One end of the field plate electrode SFP2 is located on the drain electrode 15 side of the gate electrode 16, and the other end of the field plate electrode SFP2 is located on the gate electrode 16 side of the drain electrode 15. The height of the field plate electrode SFP2 from the barrier layer 13 is greater than the height of the gate electrode 16. The field plate electrode SFP2 is made of, for example, aluminum (Al). The field plate electrode SFP2 is electrically connected to the source electrode 14.

[0053] The fourth embodiment simplifies the manufacturing process compared to the third embodiment. Other effects are the same as those of the third embodiment.

[0054] As a modification, the field plate electrode SFP3 of the second embodiment may be applied to the fourth embodiment.

[0055] [5] Fifth embodiment The fifth embodiment includes, in addition to the field plate electrode configuration of the third embodiment, a field plate electrode having an upwardly convex shape from the gate electrode 16 toward the drain electrode 15.

[0056] Figure 7 is a cross-sectional view of the semiconductor device 1 according to the fifth embodiment. The semiconductor device 1 includes field plate electrodes SFP1 to SFP5. The configuration of field plate electrodes SFP1 to SFP3 is the same as in the third embodiment.

[0057] The field plate electrode SFP4 is provided on the field plate electrode SFP3 and is configured to protrude toward the drain electrode 15. The field plate electrodes SFP1, SFP3, and SFP4 are configured in a stepped manner, increasing in height from the gate electrode 16 toward the drain electrode 15.

[0058] The field plate electrode SFP5 is located below the field plate electrode SFP4 and is configured to protrude toward the drain electrode 15. The field plate electrode SFP5 consists of the same wiring layer as the field plate electrode SFP3. The field plate electrodes SFP4 and SFP5 are configured in a stepped manner, decreasing in height from the gate electrode 16 toward the drain electrode 15.

[0059] In other words, the field plate electrodes SFP1, SFP3 to SFP5 have an upward-convex shape.

[0060] The field plate electrodes SFP4 and SFP5 are made of, for example, aluminum (Al). The field plate electrodes SFP4 and SFP5 are electrically connected to the source electrode 14.

[0061] In the semiconductor device 1 configured in this way, localized electric field concentration in the barrier layer 13 can be mitigated. Furthermore, the gate-drain capacitance Cgd can be further reduced. In addition, as the drain-source voltage Vds increases, the drain-source capacitance Cds can be reduced more gradually. Other effects are the same as in the first embodiment.

[0062] As a variation, the semiconductor device 1 may be configured by omitting the field plate electrode SFP5. Furthermore, the fifth embodiment may be applied to the second embodiment.

[0063] [6] Sixth Embodiment The sixth embodiment further includes two field plate electrodes provided on the source electrode 14 and the drain electrode 15, respectively.

[0064] Figure 8 is a cross-sectional view of the semiconductor device 1 according to the sixth embodiment. The configuration of the field plate electrodes SFP1 and SFP2 is the same as in the first embodiment. The semiconductor device 1 further comprises a source field plate electrode 18 and a drain field plate electrode 19.

[0065] The source field plate electrode 18 is provided on the source electrode 14 and is configured to protrude toward the drain electrode 15. The source field plate electrode 18 is configured to include a first electrode portion extending upward from the source electrode 14 and a second electrode portion extending toward the drain electrode 15 from the first electrode portion. The source field plate electrode 18 is configured to cover the gate electrode 16 and the field plate electrodes SFP1 and SFP2. The source field plate electrode 18 is electrically connected to the source electrode 14. The source field plate electrode 18 is made of, for example, aluminum (Al).

[0066] The drain field plate electrode 19 is provided on the drain electrode 15 and is configured to protrude toward the source electrode 14. The drain field plate electrode 19 is configured to include a first electrode portion extending upward from the drain electrode 15 and a second electrode portion extending toward the source electrode 14 from the first electrode portion. The end of the drain field plate electrode 19 is located toward the drain electrode 15 than the end of the field plate electrode SFP1. The drain field plate electrode 19 is electrically connected to the drain electrode 15. The drain field plate electrode 19 is made of, for example, aluminum (Al).

[0067] In the semiconductor device 1 configured in this way, the source field plate electrode 18 mitigates localized electric field concentration in the barrier layer 13. Furthermore, since the source field plate electrode 18 can substantially increase the volume of the source electrode 14, the resistance of the source electrode 14 can be reduced.

[0068] The drain field plate electrode 19 mitigates localized electric field concentration in the barrier layer 13. Furthermore, the drain field plate electrode 19 can substantially increase the volume of the drain electrode 15, thereby reducing the resistance of the drain electrode 15.

[0069] Alternatively, only one of the source field plate electrode 18 and the drain field plate electrode 19 may be provided.

[0070] Furthermore, the sixth embodiment can also be applied to the second to fifth embodiments.

[0071] In the above embodiments, the two field plate electrodes, positioned vertically, are configured to be in contact with each other. However, the invention is not limited to this configuration, and an insulating layer may be interposed between the two field plate electrodes positioned vertically.

[0072] In this specification, "lamination" includes not only cases where layers are stacked in contact with each other, but also cases where other layers are interposed between them. Similarly, "placed on top" also includes cases where other layers are interposed between them. In contrast, "placed directly on top" means that there are no interposed layers.

[0073] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0074] 1...Semiconductor device, 10...Substrate, 11...Buffer layer, 12...Channel layer, 13...Barrier layer, 14...Source electrode, 15...Drain electrode, 16...Gate electrode, 17...Insulating layer, 18...Source field plate electrode, 19...Drain field plate electrode, SFP1~SFP5...Field plate electrodes.

Claims

1. A first nitride semiconductor layer provided on a substrate, A second nitride semiconductor layer is provided on the first nitride semiconductor layer and has a larger band gap than the first nitride semiconductor layer, Source electrode and drain electrode provided spaced apart from each other on the second nitride semiconductor layer, A gate electrode is provided on the second nitride semiconductor layer and is positioned between the source electrode and the drain electrode, A first field plate electrode is provided directly on the second nitride semiconductor layer, positioned between the gate electrode and the drain electrode, and electrically connected to the source electrode, A second field plate electrode is provided on the first field plate electrode and configured to protrude toward the gate electrode, A semiconductor device equipped with the following.

2. A first nitride semiconductor layer provided on a substrate, A second nitride semiconductor layer is provided on the first nitride semiconductor layer and has a larger band gap than the first nitride semiconductor layer, Source electrode and drain electrode provided spaced apart from each other on the second nitride semiconductor layer, A gate electrode is provided on the second nitride semiconductor layer and is positioned between the source electrode and the drain electrode, A first field plate electrode is provided on the second nitride semiconductor layer, positioned between the gate electrode and the drain electrode, and electrically connected to the source electrode, A second field plate electrode is provided on the first field plate electrode and configured to protrude toward the gate electrode, A third field plate electrode is provided on the first field plate electrode and configured to protrude toward the drain electrode, A fourth field plate electrode is provided on the third field plate electrode and configured to protrude toward the drain electrode, A fifth field plate electrode is provided below the fourth field plate electrode and configured to protrude toward the drain electrode, A semiconductor device equipped with the following.

3. The end of the second field plate electrode is located between the gate electrode and the first field plate electrode. The semiconductor device according to claim 1 or 2.

4. The height of the first field plate electrode is less than or equal to the height of the gate electrode. The semiconductor device according to claim 1 or 2.

5. The height of the second field plate electrode is higher than the height of the gate electrode. The semiconductor device according to claim 1 or 2.

6. The device further comprises a third field plate electrode provided on the second field plate electrode and configured to protrude toward the gate electrode. The semiconductor device according to claim 1.

7. The system further comprises a third field plate electrode provided on the first field plate electrode and configured to protrude toward the drain electrode. The semiconductor device according to claim 1.

8. The second field plate electrode is configured to protrude toward the gate electrode and the drain electrode, respectively. The semiconductor device according to claim 1.

9. The system further comprises a source field plate electrode provided on the source electrode and configured to protrude toward the drain electrode. The semiconductor device according to claim 1 or 2.

10. The system further comprises a drain field plate electrode provided on the drain electrode and configured to protrude toward the source electrode. The semiconductor device according to claim 1 or 2.

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