Clock generation circuits and semiconductor devices

Abstract

This provides a clock generation circuit that reduces the frequency of the clock signal when the power supply voltage increases. [Solution] The clock generation circuit 100 of the present invention includes a reference current setting unit 20, a bias voltage generation unit 110, and a ring oscillator 40. The bias voltage generation unit 110 generates a PBIAS voltage to be applied to each gate of the PMOS transistor MP3 of the ring oscillator 40, and an NBIAS voltage to be applied to each gate of the NMOS transistor MN3. In response to the power supply voltage Vcc reaching the target voltage, the bias voltage generation unit 110 increases the PBIAS voltage, thereby reducing the current supplied by the PMOS transistor MP3 and lowering the frequency of the clock signal OSC.

Description

Technical Field

[0001] The present invention relates to a clock generation circuit, and more particularly to a ring oscillator in which an odd number of inverters are connected.

Background Art

[0002] In semiconductor devices such as memories and logic, a ring oscillator that generates a clock signal without requiring an external clock is used (for example, Patent Document 1). The ring oscillator is configured by connecting an odd number of inverters in series and feeding back the output of the last stage to the input of the first stage. The frequency of the generated clock signal is determined by the delay time of the inverter and the number of inverters. The clock signal generated by the ring oscillator is used, for example, for generating a high voltage by a charge pump circuit.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] FIG. 1 is a diagram showing a configuration example of a conventional clock generation circuit. As shown in the figure, the clock generation circuit 10 includes a reference current setting unit 20, a bias voltage generation unit 30, and a ring oscillator 40. The reference current setting unit 20 includes resistors R, R1, R2, R3, R4 connected in series in a current path between the power supply voltage Vcc and GND, and an NMOS transistor MN1 connected in diode connection, and further includes transistors CP1, CP2, CP3, CP4 connected in parallel with the resistors. The transistors CP1, CP2, CP3, CP4 select a resistor between the power supply voltage Vcc and the node N1, and the transistor MN1 generates a reference current IREF according to the voltage of the node N1 generated by the selected resistor.

[0005] The bias voltage generation unit 30 includes a PMOS transistor MP2 and an MNOS transistor MN2 in the current path between the power supply voltage Vcc and GND. Transistor MP2 is diode-connected to node N2, and transistor MN2 forms a current mirror with transistor MN1. The gate voltage of transistor MN2, i.e., node N1, generates the NBIAS voltage, and node N2 generates the gate and drain voltages corresponding to the reference current IREF as the PBIAS voltage.

[0006] The ring oscillator 40 includes an odd number of inverter stages (five in the example shown), with the output of the final CMOS inverter connected to the input of the first CMOS inverter. Each inverter stage includes a PMOS transistor MP3 connected in series between the power supply voltage Vcc and the CMOS inverter, and an NMOS transistor MN3 connected in series between the CMOS inverter and GND. A common PBIAS voltage is applied to the gate of transistor MP3 in each inverter stage, so that transistor MP3 forms a current mirror with transistor MP2. A common NBIAS voltage is applied to the gate of transistor MN3, so that transistor MP3 forms a current mirror with transistor MN2.

[0007] The ring oscillator 40 controls the frequency of the clock signal OSC by current control. In other words, the frequency of the clock signal OSC output from the output buffer 42 is controlled by the current flowing through transistors MP3 and MN3, which are biased by the PBIAS voltage and NBIAS voltage, respectively. If the current supplied to the CMOS inverter via transistor MP3 increases, the delay time due to charging and discharging of the CMOS inverter decreases, and the frequency of the clock signal OSC increases.

[0008] While it is desirable for the power supply voltage Vcc to be constant, if it becomes higher than the intended voltage due to the influence of the operating environment, the current supplied from the power supply voltage Vcc increases, the voltage at node N1 increases, and the reference current IREF increases. When the reference current IREF increases, the PBIAS voltage decreases, the current flowing through transistor MP3 of ring oscillator 40 increases, and the frequency of the generated clock signal OSC increases. When the charge pump circuit is driven using the clock signal OSC, as the frequency of the clock signal OSC increases, the output current Iout of the charge pump circuit increases, which increases the current consumption and peak current Icc of the charge pump circuit. An increase in current consumption and peak current Icc is undesirable from the standpoint of saving power in semiconductor devices and protecting circuit elements.

[0009] The present invention aims to solve these conventional problems and provide a clock generation circuit and semiconductor device that reduce the frequency of the clock signal when the power supply voltage increases. [Means for solving the problem]

[0010] The clock generation circuit according to the present invention comprises a ring oscillator in which an odd number of inverter stages, each including a PMOS transistor connected between a power supply voltage and a CMOS inverter, are arranged in series, and a generation means for generating a first bias voltage that is commonly applied to the gates of each PMOS transistor in the ring oscillator, wherein the generation means increases the first bias voltage in response to the power supply voltage reaching a target voltage. [Effects of the Invention]

[0011] According to the present invention, since the first bias voltage is increased in response to the power supply voltage reaching the target voltage, the current supplied from the PMOS transistor to the CMOS inverter is reduced, and the frequency of the generated clock signal can be reduced. [Brief explanation of the drawing]

[0012] [Figure 1] This figure shows an example of a conventional clock generation circuit configuration. [Figure 2] This figure shows the configuration of a clock generation circuit according to the first embodiment of the present invention. [Figure 3] This figure shows an example of generating the target voltage VDIV. [Figure 4] This graph shows the relationship between PBIAS voltage, NBIAS voltage, and power supply voltage Vcc. [Figure 4A] This figure shows an example configuration of a charge pump circuit that operates using the clock signal generated by the clock generation circuit of this embodiment. [Figure 5] Figure 5(A) is a graph showing the relationship between the frequency of the clock signal and the output current Iout of the charge pump circuit in a conventional example, and Figure 5(B) is a graph showing the relationship between the frequency of the clock signal and the output current Iout of the charge pump circuit in the first embodiment. [Figure 6] Figure 6(A) is a graph showing the relationship between the frequency of the clock signal and the peak current Icc of the charge pump circuit in a conventional example, and Figure 6(B) is a graph showing the relationship between the frequency of the clock signal and the peak current Icc of the charge pump circuit in the first embodiment. [Figure 7] Figure 7(A) is a graph showing the relationship between the frequency of the clock signal and the efficiency Ifeff of the charge pump circuit in a conventional example, and Figure 7(B) is a graph showing the relationship between the frequency of the clock signal and the efficiency Ifeff of the charge pump circuit in the first embodiment. [Figure 8] Figure 8(A) shows the configuration of a clock generation circuit according to a second embodiment of the present invention, and Figure 8(B) is a graph showing the relationship between the PBIAS voltage, NBIAS voltage and power supply voltage Vcc. [Figure 9] Figure 9(A) is a graph showing the relationship between the frequency of the clock signal and the output current Iout of the charge pump circuit in the second embodiment, and Figure 9(B) is a graph showing the relationship between the frequency of the clock signal and the peak current Icc of the charge pump circuit in the second embodiment. [Figure 10]It is a graph showing the relationship between the frequency of the clock signal and the efficiency Ieff of the charge pump circuit in the second embodiment. [Figure 11] FIG. 11(A) is a diagram showing the configuration of a clock generation circuit according to a third embodiment of the present invention, and FIG. 11(B) is a graph showing the relationship between the PBIAS voltage and the NBIAS voltage and the power supply voltage Vcc.

Embodiment for Carrying Out the Invention

[0013] Embodiments of the present invention relate to a ring oscillator mounted on a semiconductor device such as a memory or logic. In one aspect, a clock signal generated by the ring oscillator is provided to a charge pump circuit, and the charge pump circuit generates a high voltage required for writing to a flash memory.

Examples

[0014] Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 2 is a diagram showing the configuration of a clock generation circuit according to a first embodiment of the present invention. The clock generation circuit 100 of this embodiment includes a reference current setting unit 20, a bias voltage generation unit 110 that generates a PBIAS voltage and an NBIAS voltage, and a ring oscillator 40. The reference current setting unit 20 and the ring oscillator 40 are the same as the configurations described in FIG. 1 of the conventional example, and the description thereof will be omitted here.

[0015] The bias voltage generation unit 110 of this embodiment includes a newly added current control unit 120, and other than that, it is configured in the same manner as the bias voltage generation unit 30 shown in FIG. 1. The bias voltage generation unit 110 includes a diode-connected PMOS transistor MP2 and an NMOS transistor MN2 in the current path between the power supply voltage Vcc and GND, and further includes a current control unit 120 connected to node N2. The node N2 that couples the transistor MP2 and the transistor MN2 generates the PBIAS voltage. As will be described later, when the power supply voltage Vcc increases beyond the target voltage, the current control unit 120 supplies a current i1 to node N2, thereby reducing the current i1 flowing through the diode-connected transistor MP2, and thereby increasing the PBIAS voltage.

[0016] The transistor MN2 forms a current mirror with the transistor MN1 of the reference current setting unit 20 and conducts the reference current IRER. The current i2 from the transistor MP2 and the current i1 from the current control unit 120 are supplied to node N2, and the following relational expression holds. Reference current IREF = i1 + i2 i2 = IREF - i1 From this relational expression, when the current control unit 120 supplies the current i1 to node N2, the current i1 flowing through the diode-connected transistor MP2 decreases, and thereby the PBIAS voltage of node N2 increases. When the PBIAS voltage increases, the current supplied from the PMOS transistor MP3 of the ring oscillator 40 to the CMOS inverter is restricted, and the frequency of the clock signal OSC decreases.

[0017] The current control unit 120 supplies the current i1 when the power supply voltage Vcc increases. This configuration is not particularly limited. For example, the current control unit 120 includes a differential amplifier 122 and a PMOS transistor MP1. The differential amplifier 122 has an inverting input terminal (+) that receives the reference voltage VREF, an inverting input terminal (-) that receives the target voltage VDIV, and an output connected to the gate of the transistor MP1.

[0018] The reference voltage VREF is not particularly limited. For example, it is generated using a BGR circuit and VREF = 1.1V. The target voltage VDIV sets the voltage at which the current narrowing by the transistor MP3 in the ring oscillator 40 starts. The target voltage VDIV is generated, for example, using the resistance voltage division of the resistor BR1 and the resistor BR2 connected in series between the power supply voltage Vcc and GND as shown in FIG. 3. For example, if the charge pump circuit is designed assuming that the power supply voltage Vcc is 1.6, the target voltage VDIV is set to a desired voltage when the power supply voltage Vcc is 1.6V.

[0019] When the power supply voltage Vcc is 1.6 V or less, the gate-source voltage Vgs of the transistor MP1 is greater than the threshold voltage Vtp (Vgs > Vtp), and the transistor MP1 is off. Therefore, i1 = 0 and i2 = IREF, and the PBIAS voltage at the node N2 is the gate and drain voltages of the transistor MP2 corresponding to the current i2, and the intended current as designed is supplied to the CMOS inverter of the ring oscillator 40.

[0020] When the power supply voltage Vcc exceeds 1.6V, a negative (minus) voltage corresponding to the difference between the reference voltage VREF and the target voltage VDIV is applied to the transistor MP1 by the differential amplifier 122, and the gate-source voltage Vgs of the transistor MP1 becomes Vgs < Vtp, the transistor MP1 turns on, and the current i1 flows. Since i2 = IREF - i1, when the current i1 is supplied to the node N2, the current i2 flowing through the transistor MP2 decreases, and accordingly the PBIAS voltage at the node N2 increases. As a result, the current flowing through the transistor MP3 in the ring oscillator 40 is narrowed so as to decrease, and the frequency of the generated clock signal OSC is reduced. The current i1 flowing through the transistor MP1 is proportional to the increase in the power supply voltage Vcc. That is, as the power supply voltage Vcc increases, the negative output voltage of the differential amplifier 122 increases, and the current i1 increases.

[0021] Figure 4 is a graph showing the relationship between the PBIAS voltage, NBIAS voltage, and power supply voltage Vcc. As described above, when the power supply voltage Vcc exceeds 1.6V, the current control unit 120 turns on transistor MP1 when Vgs > Vtp, supplying current i1 to node N2. This reduces the current i2 flowing through transistor MP2 by the amount of current i1, and the PBIAS voltage increases. On the other hand, as the power supply voltage Vcc increases, the voltage at node N1 of the reference current setting unit 20 increases, so the NBIAS voltage also has a somewhat positive slope.

[0022] When the power supply voltage Vcc exceeds 1.6V, the PBIAS voltage of the ring oscillator 40 increases, which reduces the current flowing through transistor MP3, increases the delay caused by the CMOS inverter, and consequently decreases the frequency of the output clock signal OSC.

[0023] The clock signal OSC output from the clock generation circuit 100 is supplied to the charge pump circuit 200, as shown in Figure 4A(A). The charge pump circuit 200 uses the clock signal OSC to generate a high voltage Vpp. This high voltage Vpp is used, for example, as the write voltage or erase voltage for flash memory.

[0024] Figure 4A(B) shows an example of a charge pump circuit. The charge pump circuit 200 includes, for example, multiple diode-connected MOS transistors, each MOS transistor connected in series. Capacitors are connected to the gates of the MOS transistors, and a clock signal OSC is applied to the capacitor of each odd-numbered MOS transistor, while a clock signal / OSC is applied to the capacitor of each even-numbered MOS transistor. The clock signal OSC and the clock signal / OSC are in phase with a difference of 180 degrees. The charge pump circuit 200 takes a power supply voltage Vcc as input and outputs a boosted high voltage Vpp.

[0025] Figure 5(A) is a graph showing the relationship between the frequency of the clock signal OSC and the output current Iout of the charge pump circuit in a conventional example, and Figure 5(B) is a graph showing the relationship between the frequency of the clock signal OSC and the output current Iout of the charge pump circuit in the first embodiment.

[0026] In a conventional example, when the power supply voltage Vcc is 1.6V, the clock signal frequency is 54MHz, and the output current (drive current) Iout of the charge pump circuit operating with that clock signal is 2.13mA. As the power supply voltage Vcc increases, the clock signal frequency increases, and the output current Iout of the charge pump circuit increases proportionally.

[0027] For example, if a charge pump circuit is designed assuming operation at a power supply voltage Vcc of 1.6V, it is sufficient to obtain an output current Iout = 2.13mA, and an output current Iout exceeding that is not necessary. In other words, when the power supply voltage Vcc rises from 1.6V to 2.0V, the output current Iout increases by almost double, from 2.13mA to 3.83mA, but an output current exceeding 2.13mA can be wasted.

[0028] In contrast, in this embodiment, when the power supply voltage Vcc increases from 1.6V to 2.0V, the frequency of the clock signal decreases from 54MHz to 44MHz, and the output current Iout of the charge pump circuit increases only from 2.13mA to 2.99mA. Because the frequency of the clock signal decreases even when the power supply voltage Vcc increases, the output current Iout can be reduced compared to the conventional example.

[0029] Figure 6(A) is a graph showing the relationship between the frequency of the clock signal and the peak current Icc of the charge pump circuit in a conventional example, and Figure 6(B) is a graph showing the relationship between the frequency of the clock signal and the peak current Icc of the charge pump circuit in the first embodiment. As is clear from these figures, in this embodiment, when the power supply voltage Vcc increases, the peak current Icc of the charge pump circuit can be reduced compared to the conventional example.

[0030] Figure 7(A) is a graph showing the relationship between the frequency of the clock signal and the efficiency Ieff of the charge pump circuit in a conventional example, and Figure 7(B) is a graph showing the relationship between the frequency of the clock signal and the efficiency Ieff of the charge pump circuit in the first embodiment. In the conventional example, when the power supply voltage Vcc increases from 1.6V to 2.0V, the efficiency Ieff of the charge pump circuit increases from 20.7% to 21.6%. In contrast, in this embodiment, when the power supply voltage Vcc increases from 1.6V to 2.0V, the frequency of the clock signal decreases, but the efficiency Ieff remains at 20.7% to 21.6%, maintaining the same efficiency as the conventional example. This is because even though the frequency of the clock signal decreases with increasing power supply voltage Vcc, the amplitude of the clock signal increases due to the increase in power supply voltage Vcc, thus maintaining the power supplied to the charge pump circuit overall, and the charge pump circuit can generate the required output current Iout.

[0031] Thus, according to this embodiment, even when the power supply voltage Vcc increases, the frequency of the ring oscillator's clock signal can be reduced while maintaining the efficiency of the charge pump circuit and generating the output current and high voltage required for the charge pump circuit.

[0032] Next, a second embodiment of the present invention will be described. Figure 8(A) shows the configuration of the clock generation circuit according to the second embodiment. In the second embodiment, the bias voltage generation unit 110A includes a current control unit 120, similar to the first embodiment. Instead of using the reference current setting unit 20 as in the first embodiment, a reference voltage VREF is applied to the gate of transistor MN2, and transistor MN2 generates a reference current IREF corresponding to the reference voltage VREF, generating a PBIAS voltage at node N2. The bias voltage generation unit 110A also includes a unity gain buffer 124, which generates a reference voltage VREF at node N3 and supplies this reference voltage VREF to the ring oscillator 40 as an NBIAS voltage. The method for generating the reference voltage VREF is not particularly limited, but it is desirable to generate a reference voltage that is not dependent on fluctuations in the power supply voltage or temperature by using a BGR circuit, for example.

[0033] Figure 8(B) is a graph showing the relationship between the PBIAS voltage, NBIAS voltage, and power supply voltage Vcc. In the second embodiment, unlike the first embodiment, the NBIAS voltage remains almost constant even when the power supply voltage Vcc increases. Also, since the reference current IREF flowing through transistor MN2 is constant and does not depend on the power supply voltage Vcc, the decrease in current i2 with increasing power supply voltage Vcc becomes larger. As a result, the slope of the PBIAS voltage becomes somewhat larger than in the first embodiment, and the current supplied to the CMOS inverter of the ring oscillator 40 is reduced accordingly. In other words, the frequency of the clock signal generated by the ring oscillator 40 is reduced compared to the first embodiment.

[0034] Figure 9(A) is a graph showing the relationship between the frequency of the clock signal OSC and the output current Iout of the charge pump circuit in the second embodiment, and Figure 9(B) is a graph showing the relationship between the frequency of the clock signal OSC and the peak current Icc of the charge pump circuit in the second embodiment. In the second embodiment, when the power supply voltage Vcc increases from 1.6V to 2.0V, the frequency of the clock signal decreases from 54MHz to 32MHz, and the output current Iout of the charge pump circuit is suppressed to an increase of 2.13mA to 2.19mA. In addition, the peak current Icc is also kept within the range of 10.1mA to 10.9mA.

[0035] Figure 10 is a graph showing the relationship between the frequency of the clock signal and the efficiency Ieff of the charge pump circuit in the second embodiment. The efficiency Ieff transitions from 20.7% to 21.7%, which is almost the same as in the conventional example shown in Figure 7(A) and the first embodiment shown in Figure 7(B).

[0036] Thus, according to the second embodiment, the frequency of the clock signal can be reduced even further than in the first embodiment, and the current consumption and peak current of the charge pump circuit can be suppressed while maintaining the efficiency of the charge pump circuit.

[0037] Next, a third embodiment of the present invention will be described. Figure 11(A) shows the configuration of a clock generation circuit according to the third embodiment. The clock generation circuit 100B according to the third embodiment has a PMOS transistor MP4 that constitutes a current mirror with transistor MP2, and an NMOS transistor MN4 that is diode-connected to transistor MP4. Transistor MN4 constitutes a current mirror with transistor MN3 of the ring oscillator 40.

[0038] In the third embodiment, when the power supply voltage Vcc exceeds 1.6V, the PBIAS voltage increases, as in the second embodiment, and the current supplied from transistor MP3 of the ring oscillator 40 is reduced. At the same time, the current i2 flowing through transistor MP4 decreases, so the drain and gate voltages of the diode-connected transistor MN4, i.e., the NBIAS voltage, decrease. This reduces the current that transistor MN3 of the ring oscillator 40 supplies to GND. Figure 11(B) is a graph showing the relationship between the PBIAS voltage, NBIAS voltage and the power supply voltage Vcc. In the third embodiment, when the power supply voltage Vcc exceeds 1.6V, the PBIAS voltage slopes positively and the NBIAS voltage slopes negatively. By appropriately setting the slopes of the PBIAS voltage and NBIAS voltage, the frequency of the ring oscillator clock signal can be optimized.

[0039] In the above embodiments, the frequency of the clock signal and the output current / peak current of the charge pump circuit were illustrated when the power supply voltage Vcc is 1.6V, but it goes without saying that the present invention is not limited to these examples. Furthermore, although an example in which the ring oscillator is composed of five inverter stages was shown, the present invention is not limited to this.

[0040] Although preferred embodiments of the present invention have been described in detail, the present invention is not limited to any particular embodiment, and various modifications and changes are possible within the scope of the gist of the invention as described in the claims. [Explanation of Symbols]

[0041] 20: Reference current setting section 30: Bias voltage generation section 40: Ring Oscillator 100, 100A, 100B: Clock generation circuit 110, 110A: Bias voltage generation unit 120: Current Control Unit 122: Differential Amplifier 124: Unity Gain Buffer

Claims

1. A ring oscillator is formed by connecting an odd number of inverter stages, each containing a PMOS transistor, between the power supply voltage and the CMOS inverter. A generation means for generating a first bias voltage that is commonly applied to the gates of each PMOS transistor of the ring oscillator, The detection means includes an operational amplifier for detecting an increase in the power supply voltage and a first transistor with its gate connected to the output of the operational amplifier. The generation means is a clock generation circuit that increases the first bias voltage in accordance with the first current flowing through the first transistor.

2. The clock generation circuit according to claim 1, wherein the operational amplifier is a differential amplifier that takes a reference voltage and a voltage obtained by resistively dividing the power supply voltage as input.

3. The generating means further includes a second transistor diode-connected between the power supply voltage and the node, the node being connected to the second transistor and the first transistor, and the node generating the first bias voltage. The clock generation circuit according to claim 1, wherein the second current flowing through the second transistor is controlled by the first current, and the first bias voltage is controlled by the second current.

4. The generating means further includes a third transistor connected between the node and the reference potential, the third transistor passing a reference current through the reference potential, The clock generation circuit according to claim 3, wherein the relationship is second current = reference current - first current.

5. The inverter stage further includes an NMOS transistor between the CMOS inverter and the reference potential. The clock generation circuit according to claim 1, wherein the generation means generates a second bias voltage that is commonly applied to the gates of each NMOS transistor of the ring oscillator.

6. The clock generation circuit according to claim 5, wherein the generation means includes a unity-gain buffer, and generates the second bias voltage at the output of the unity-gain buffer.

7. The clock generation circuit according to claim 5, further comprising a second transistor diode-connected between a power supply voltage and a node, the node being connected to the second transistor and the first transistor, and generating the second bias voltage based on a third current flowing through a fourth transistor that replicates the second current generated by the second transistor.

8. The clock generation circuit according to claim 7, further comprising a fifth diode-connected transistor connected to the fourth transistor, wherein the drain and gate voltages of the fifth transistor generate the second bias voltage.

9. The clock generation circuit according to claim 8, wherein the second bias voltage has a negative slope when the power supply voltage increases.

10. A clock generation circuit according to any one of claims 1 to 9, A charge pump circuit that operates using the clock signal generated by the clock generation circuit, Semiconductor devices including [this].

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