Semiconductor device and its manufacturing method

Abstract

To suppress a surge voltage while reducing recovery loss in RC-IGBT.SOLUTION: A semiconductor device includes an n-type field stop region distributed across an IGBT region and a diode region, a p-type collector region disposed on a lower side of the field stop region in the IGBT region, a plurality of n-type cathode regions disposed on the lower side of the field stop region in the diode region, and a plurality of p-type surge suppression regions disposed on the lower side of the field stop region in the diode region. Each cathode region includes a first cathode region being in contact with the lower electrode and having n-type impurity concentration of 1×1019 cm-3 or more, and a second cathode region disposed between the first cathode region and the field stop region and having an n-type impurity activation ratio of 85% or less.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The technologies disclosed herein relate to semiconductor devices and methods for manufacturing the same.

[0002] Patent Document 1 discloses a method for manufacturing a semiconductor device having an insulated-gate bipolar transistor and a diode. Hereafter, the insulated-gate bipolar transistor may be referred to as an IGBT (i.e., Insulated Gate Bipolar Transistor). Also, hereafter, the semiconductor device having an IGBT and a diode may be referred to as an RC-IGBT. In the manufacturing method of Patent Document 1, an n-type cathode region is formed by ion implantation of n-type impurities. Next, crystal defects are formed in the cathode region by irradiating the semiconductor substrate with helium ions. By forming crystal defects in the cathode region, snapback can be suppressed when the IGBT is turned on. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2015-211149 [Overview of the project] [Problems that the invention aims to solve]

[0004] When the voltage applied to the diode switches from a forward voltage to a reverse voltage, holes present inside the diode are discharged to the anode electrode. This causes a recovery current to flow in the reverse direction through the diode. In the RC-IGBT described in Patent Document 1, crystal defects in the cathode region function as recombination centers. Therefore, during the recovery operation, holes disappear through recombination at the crystal defects, and the recovery current decays quickly. This reduces the recovery loss of the diode.

[0005] The voltage applied to a diode can change rapidly. When the voltage applied to a diode switches rapidly from forward to reverse, the rate of decay of the recovery current can become excessively fast, which can generate a surge voltage. If crystal defects are present in the cathode region, the recovery current decays easily, making surge voltages more likely to occur.

[0006] As explained above, while the presence of crystal defects in the cathode region can reduce recovery losses, it also makes surge voltages more likely to occur when the applied voltage changes rapidly. This specification proposes a technique for suppressing surge voltages while reducing recovery losses in RC-IGBTs. [Means for solving the problem]

[0007] A semiconductor device disclosed herein includes a semiconductor substrate having an IGBT region and a diode region, an upper electrode in contact with the upper surface of the semiconductor substrate within the IGBT region and the diode region, a lower electrode in contact with the lower surface of the semiconductor substrate within the IGBT region and the diode region, and a gate electrode. The semiconductor substrate has an emitter region, an upper p-type region, a drift region, a field stop region, a collector region, a plurality of cathode regions, and a plurality of surge suppression regions. The emitter region is an n-type region in contact with the upper electrode within the IGBT region. The upper p-type region is distributed across the IGBT region and the diode region and is in contact with the upper electrode within the IGBT region and the diode region. The drift region is an n-type region located below the upper p-type region, distributed across the IGBT region and the diode region, and separated from the emitter region by the upper p-type region. The field stop region is located below the drift region, has a higher n-type impurity concentration than the drift region, has a bell-shaped distribution in the n-type impurity concentration distribution along the thickness direction of the semiconductor substrate, and is an n-type region distributed across the IGBT region and the diode region. The collector region is located within the IGBT region, below the field stop region, and is a p-type region in contact with the lower electrode. The plurality of cathode regions are located within the diode region, below the field stop region, and are n-type regions in contact with the lower electrode. The plurality of surge suppression regions are located within the diode region, below the field stop region, and are p-type regions in contact with the lower electrode. The gate electrode faces the upper p-type region between the emitter region and the drift region via a gate insulating film. Within the diode region, the plurality of cathode regions and the plurality of surge suppression regions are alternately arranged along a specific direction on the lower surface of the semiconductor substrate. Each of the cathode regions is in contact with the lower electrode and 1 × 10 19 cm -3The device has a first cathode region having the above-mentioned n-type impurity concentration, and a second cathode region located between the first cathode region and the field stop region, wherein the activation rate of the n-type impurity is 85% or less.

[0008] In this specification, the upper p-type region can be any p-type region that is distributed across the IGBT region and the diode region and is in contact with the upper electrode within both the IGBT region and the diode region. For example, the concentration profiles of p-type impurities in the upper p-type region within the IGBT region and the upper p-type region within the diode region may be the same, or they may be different.

[0009] In this semiconductor device, the upper electrode functions as both the emitter electrode of the IGBT and the anode electrode of the diode. The lower electrode functions as both the collector electrode of the IGBT and the cathode electrode of the diode. The cathode region has a first cathode region and a second cathode region. The first cathode region is 1 × 10⁻⁶ 19 cm -3Because of the above n-type impurity concentration, the first cathode region is in contact with the lower electrode with low contact resistance. Therefore, losses are less likely to occur when the diode is turned on. Also, since the activation rate of n-type impurities in the second cathode region is 85% or less, there are many unactivated n-type impurities in the second cathode region. These unactivated n-type impurities in the second cathode region constitute crystal defects and function as hole recombination centers. In addition, a p-type surge suppression region is located next to the cathode region within the diode region. When the applied voltage to the diode switches rapidly from forward voltage to reverse voltage, a recovery current flows through the diode. The crystal defects in the second cathode region (i.e., unactivated n-type impurities) act to attenuate the recovery current. On the other hand, when the applied voltage to the diode switches rapidly from forward voltage to reverse voltage, holes are injected from the surge suppression region into the drift region. When holes are injected into the drift region in this way, the recovery current becomes less likely to attenuate. Therefore, when the applied voltage to the diode switches rapidly from forward to reverse voltage, the rapid decay of the recovery current is suppressed, and the generation of surge voltage is suppressed. Also, when the applied voltage to the diode switches from forward to reverse voltage at a normal speed, almost no hole injection occurs from the surge suppression region to the drift region. Therefore, in this case, crystal defects in the second cathode region cause the recovery current to decay early. Thus, recovery loss can be reduced. In this way, with this semiconductor device, recovery loss can be reduced in normal recovery operation, and surge voltage can be suppressed when the applied voltage switches rapidly. [Brief explanation of the drawing]

[0010] [Figure 1] Cross-sectional view of the semiconductor device of Example 1. [Figure 2] A graph showing the impurity concentration distribution at the location of line AA in Figure 1. [Figure 3] A graph showing the impurity concentration distribution at the positions of the BB and CC lines in Figure 1. [Figure 4] A graph showing the recovery characteristics when the voltage Vak switching speed is slow. [Figure 5] Graph showing the recovery characteristics when the switching speed of the voltage Vak is high. [Figure 6] Explanatory drawing of the manufacturing process of the semiconductor device of Example 1. [Figure 7] Explanatory drawing of the manufacturing process of the semiconductor device of Example 1. [Figure 8] Explanatory drawing of the manufacturing process of the semiconductor device of Example 1. [Figure 9] Explanatory drawing of the manufacturing process of the semiconductor device of Example 1. [Figure 10] Graph showing the impurity concentration distribution at the position of the A - A line of the semiconductor device of Example 2. [Figure 11] Graph showing the impurity concentration distribution at the positions of the B - B line and the C - C line of the semiconductor device of Example 3.

Mode for Carrying Out the Invention

[0011] In one form disclosed in this specification, a mountain - type distribution may be provided in the n - type impurity concentration distribution along the thickness direction of the semiconductor substrate within the second cathode region.

[0012] Thus, when the n - type impurity concentration in the second cathode region is increased, the activation rate in the second cathode region can be made lower. Therefore, the recovery loss can be more effectively suppressed.

[0013] The mountain - type distribution provided in the second cathode region may have a peak value higher than 1×10 18 cm -3 and lower than 1×10 19 cm -3

[0014] ​Any of the semiconductor devices described above may be manufactured by the following manufacturing method. This manufacturing method may include an ion implantation step and a laser irradiation step. In the ion implantation step, the collector region, the cathode region, and the surge suppression region may be formed by ion implanting p-type impurities and n-type impurities into the lower surface of the semiconductor substrate. In the laser irradiation step, the lower surface of the semiconductor substrate may be irradiated with a laser after the formation of the collector region, the cathode region, and the surge suppression region. In the step of irradiating with a laser, a heating range of 950°C or higher may be formed in the surface layer near the lower surface of the semiconductor substrate. The thickness of the heating range may be thinner than the thickness of the cathode region.

[0015] This manufacturing method makes it possible to lower the activation rate of n-type impurities in the second cathode region. [Examples]

[0016] The semiconductor device 10 of Embodiment 1 shown in Figure 1 has a semiconductor substrate 12. The semiconductor substrate 12 is made of silicon. However, the semiconductor substrate 12 may be made of a semiconductor material other than silicon. The semiconductor substrate 12 has an IGBT region 30 and a diode region 40. An IGBT is provided in the IGBT region 30, and a diode is provided in the diode region 40. In other words, the semiconductor device 10 is an RC-IGBT.

[0017] Multiple trenches 14 are provided on the upper surface 12a of the semiconductor substrate 12. Each trench 14 extends parallel to the others on the upper surface 12a. Multiple trenches 14 are provided in both the IGBT region 30 and the diode region 40. The inner surface of each trench 14 is covered with a gate insulating film 18. Electrodes 16 are placed within each trench 14. Each electrode 16 is insulated from the semiconductor substrate 12 by the gate insulating film 18. The electrodes 16 in the IGBT region 30 are gate electrodes 16a. Each gate electrode 16a is connected to a gate pad (not shown). An external circuit is connected to the gate pad. The potential of each gate electrode 16a is controlled by the external circuit. The electrodes 16 in the diode region 40 are dummy electrodes 16b. Each dummy electrode 16b may be connected to a gate pad, or it may not be connected to a gate pad but to another electrode (e.g., an upper electrode 22). When each dummy electrode 16b is connected to a gate pad, each dummy electrode 16b has the same potential as the gate electrode 16a. When each dummy electrode 16b is not connected to a gate pad, the potential of each dummy electrode 16b is independent of the gate electrode 16a.

[0018] An interlayer insulating film 20 and an upper electrode 22 are provided on the upper part of the semiconductor substrate 12. The interlayer insulating film 20 covers the upper surfaces of the gate electrode 16a and the dummy electrode 16b. Multiple contact holes 20a are provided in the interlayer insulating film 20. Each contact hole 20a is located in a position where there are no trenches 14. Multiple contact holes 20a are provided in both the IGBT region 30 and the diode region 40. The upper electrode 22 covers the interlayer insulating film 20 and the upper surface 12a of the semiconductor substrate 12. The upper electrode 22 is in contact with the upper surface 12a of the semiconductor substrate 12 within each contact hole 20a. Therefore, the upper electrode 22 is in contact with the upper surface 12a in both the IGBT region 30 and the diode region 40.

[0019] A lower electrode 24 is provided at the bottom of the semiconductor substrate 12. The lower electrode 24 covers the entire bottom surface 12b of the semiconductor substrate 12. Therefore, the lower electrode 24 is in contact with the bottom surface 12b in both the IGBT region 30 and the diode region 40.

[0020] Multiple n-type emitter regions 52 are provided within the IGBT region 30. Each emitter region 52 has a high n-type impurity concentration. Each emitter region 52 is located in the region between the trenches 14 (hereinafter referred to as the inter-trench region). Each emitter region 52 is located in a range that includes the upper surface 12a of the semiconductor substrate 12. Each emitter region 52 is in ohmic contact with the upper electrode 22 at the corresponding contact hole 20a. Each emitter region 52 is in contact with the gate insulating film 18 at the upper end of the side surface of the corresponding trench 14.

[0021] An upper p-type region is provided spanning the IGBT region 30 and the diode region 40. Hereinafter, the upper p-type region within the IGBT region 30 will be referred to as the body region 54, and the upper p-type region within the diode region 40 will be referred to as the anode region 56. The upper p-type region is in contact with the upper electrode 22 at each contact hole 20a within the IGBT region 30 and the diode region 40.

[0022] The body region 54 has a low-concentration region 54b and multiple contact regions 54a. Each contact region 54a has a higher p-type impurity concentration than the low-concentration region 54b. Each contact region 54a is located in the corresponding inter-trench region. Each contact region 54a is located in the area including the upper surface 12a of the semiconductor substrate 12. Each contact region 54a is in ohmic contact with the upper electrode 22 in the corresponding contact hole 20a. The low-concentration region 54b is distributed across multiple inter-trench regions. The low-concentration region 54b is located below the contact regions 54a and the emitter region 52. The low-concentration region 54b separates each emitter region 52 from the drift region 58, which will be described later. The low-concentration region 54b is in contact with the gate insulating film 18 below each emitter region 52. Each gate electrode 16a faces the low-concentration region 54b between the emitter region 52 and the drift region 58 via the gate insulating film 18.

[0023] The anode region 56 has a low-concentration region 56b and multiple contact regions 56a. Each contact region 56a has a higher p-type impurity concentration than the low-concentration region 56b. Each contact region 56a is located in the corresponding inter-trench region. Each contact region 56a is located in the area including the upper surface 12a of the semiconductor substrate 12. Each contact region 56a is in ohmic contact with the upper electrode 22 in the corresponding contact hole 20a. The low-concentration region 56b is distributed across multiple inter-trench regions. The low-concentration region 56b is located below the contact region 54a.

[0024] An n-type drift region 58 is provided below the upper p-type region (i.e., the body region 54 and the anode region 56). The n-type impurity concentration in the drift region 58 is low. The drift region 58 is distributed across the IGBT region 30 and the diode region 40. The drift region 58 is in contact with the body region 54 and the anode region 56 from below. The drift region 58 is in contact with the gate insulating film 18 below the body region 54 and the anode region 56.

[0025] A field stop region 60 is provided below the drift region 58. The field stop region 60 is an n-type region having a higher n-type impurity concentration than the drift region 58. The field stop region 60 is distributed across the IGBT region 30 and the diode region 40. The field stop region 60 is in contact with the drift region 58 from below.

[0026] Within the IGBT region 30, an intermediate n-type region 62 and a collector region 64 are located below the field stop region 60. The collector region 64 is a p-type region with a high p-type impurity concentration. The collector region 64 is located in an area that includes the lower surface 12b of the semiconductor substrate 12 and is in ohmic contact with the lower electrode 24. The intermediate n-type region 62 is an n-type region with an n-type impurity concentration similar to that of the drift region 58. Within the IGBT region 30, the intermediate n-type region 62 is located between the field stop region 60 and the collector region 64.

[0027] Within the diode region 40, multiple intermediate n-type regions 62, multiple cathode regions 66, and multiple surge suppression regions 70 are arranged below the field stop region 60. Each cathode region 66 is an n-type region having a higher n-type impurity concentration than the drift region 58. Each cathode region 66 is located in a range that includes the lower surface 12b of the semiconductor substrate 12. Each surge suppression region 70 is a p-type region having a high p-type impurity concentration. The p-type impurity concentration of each surge suppression region 70 is approximately equal to the p-type impurity concentration of the collector region 64. Each surge suppression region 70 is located in a range that includes the lower surface 12b of the semiconductor substrate 12. Within the diode region 40, on the lower surface 12b of the semiconductor substrate 12, multiple cathode regions 66 and multiple surge suppression regions 70 are alternately arranged along a specific direction (in Figure 1, the direction perpendicular to each trench 14). Each cathode region 66 and each surge suppression region 70 are in ohmic contact with the lower electrode 24. Within the diode region 40, the intermediate n-type region 62 is located between the field stop region 60 and the surge suppression region 70.

[0028] Each cathode region 66 has a first cathode region 66a having an n-type impurity concentration of 1×10 19 cm -3 or more, and a second cathode region 66b having an n-type impurity concentration of less than 1×10 19 cm -3 The first cathode region 66a is disposed in a range including the lower surface 12b of the semiconductor substrate 12. The first cathode region 66a makes an ohmic contact with the lower electrode 24. The second cathode region 66b is disposed between the first cathode region 66a and the field stop region 60. The second cathode region 66b contacts the field stop region 60 from below and contacts the first cathode region 66a from above.

[0029] Next, the impurity concentration distributions in the drift region 58, the field stop region 60, the intermediate n-type region 62, the collector region 64, the cathode region 66, and the surge suppression region 70 will be described. FIG. 2 shows the impurity concentration distribution along the line A-A in FIG. 1, and FIG. 3 shows the impurity concentration distributions along the lines B-B and C-C in FIG. 1. Note that the impurity concentration distributions are substantially equal for the B-B line and the C-C line. In FIGS. 2 and 3, the horizontal axis indicates the position in the thickness direction of the semiconductor substrate, and the origin corresponds to the position of the lower surface 12b. Also, in FIGS. 2 and 3, the graph N shows the n-type impurity concentration distribution, and the graph P shows the p-type impurity concentration distribution.

[0030] As shown in FIGS. 2 and 3, in the drift region 58, the n-type impurity concentration is distributed substantially uniformly at a low value.

[0031] As shown in FIGS. 2 and 3, in the field stop region 60, an n-type impurity concentration forms a mountain-shaped distribution M1 in the thickness direction of the semiconductor substrate 12. That is, the field stop region 60 is a region where the mountain-shaped distribution M1 continuously exists from the IGBT region 30 to the diode region 40 in the thickness direction. The peak value of the n-type impurity concentration in the field stop region 60 is less than 1×10 19 cm -3 .

[0032] As shown in Figure 2, within the first cathode region 66a, the n-type impurity concentration is 1 × 10⁻⁶. 19 cm -3 That concludes the explanation. Within the first cathode region 66a, the n-type impurity concentration is high (for example, 1 × 10 in Figure 2). 20 cm -3 It is distributed at approximately a constant level. In other words, n-type impurities are distributed in a box profile within the first cathode region 66a. The second cathode region 66b is the n-type region between the field stop region 60 and the first cathode region 66a. The n-type impurity concentration in the second cathode region 66b is higher than the n-type impurity concentration at the lower end 60L of the field stop region 60, and is 1 × 10⁻⁶ 19 cm -3 It is less than [value]. In Figure 2, the n-type impurity concentration continuously increases from the top to the bottom within the second cathode region 66b.

[0033] As shown in Figure 3, in the intermediate n-type region 62, the collector region 64, and the surge suppression region 70, the n-type impurity concentration is uniformly distributed at a similar value to that in the drift region 58. In the collector region 64 and the surge suppression region 70, the p-type impurity concentration is higher than the n-type impurity concentration. In the collector region 64 and the surge suppression region 70, the p-type impurity is distributed in a box profile.

[0034] Graph X in Figure 2 shows the concentration distribution of activated n-type impurities. That is, while graph N shows the concentration distribution of n-type impurities, including both activated and inactivated n-type impurities, graph X shows the concentration distribution of activated n-type impurities. The values ​​shown in graph X (i.e., the concentration of activated n-type impurities) are calculated from the measurement results of the resistance distribution in the semiconductor substrate 12 measured along the thickness direction. The difference between graph N and graph X corresponds to the concentration of inactivated n-type impurities. As shown in Figure 2, the difference between graph N and graph X is large within the second cathode region 66b. The activation rate of n-type impurities within the second cathode region 66b is 85% or less. In this specification, the activation rate means the value obtained by dividing the total amount of activated n-type impurities in the target region by the total amount of n-type impurities present in the target region. For example, the activation rate in the second cathode region 66b can be calculated by dividing the value obtained by integrating graph X within the second cathode region 66b by the value obtained by integrating graph N within the second cathode region 66b. Since the activation rate of n-type impurities is low in the second cathode region 66b, unactivated n-type impurities exist in high concentration within the second cathode region 66b. Unactivated impurities in the semiconductor substrate 12 are a type of crystal defect and act as carrier recombination centers. Therefore, the carrier lifetime is short in the second cathode region 66b. As shown in Figure 2, the activation rate of n-type impurities is higher in the first cathode region 66a than in the second cathode region 66b. For example, the activation rate of n-type impurities in the first cathode region 66a may be higher than 85%.

[0035] Next, the operation of the semiconductor device 10 will be described. The upper electrode 22 functions as the emitter electrode of the IGBT and also as the anode electrode of the diode. The lower electrode 24 functions as the collector electrode of the IGBT and also as the cathode electrode of the diode.

[0036] When the semiconductor device 10 operates as an IGBT, a higher potential is applied to the lower electrode 24 than to the upper electrode 22. When a potential above the gate threshold is applied to the gate electrode 16a, a channel is formed in the low-concentration region 54b adjacent to the gate insulating film 18, and the emitter region 52 and the drift region 58 are connected by this channel. As a result, the IGBT turns on, and electrons flow from the emitter region 52 to the drift region 58 through the channel. Also, when the IGBT turns on, holes flow from the collector region 64 to the drift region 58. This reduces the resistance of the drift region 58, allowing electrons to flow through the drift region 58 with low resistance. After passing through the drift region 58, the electrons flow to the collector region 64.

[0037] In an RC-IGBT, electrons flow from the drift region 58 to the cathode region 66 at the start of IGBT turn-on (i.e., when the channel resistance is high). In this state, the IGBT's on-voltage is high. Subsequently, as the channel resistance decreases, electrons begin to flow from the drift region 58 to the collector region 64, and the IGBT's on-voltage decreases. This phenomenon, where the on-voltage temporarily increases at the start of turn-on, is called snapback. In the semiconductor device of Example 1, the cathode region 66 and surge suppression region 70 are alternately provided within the diode region 40, and the area ratio of the cathode region 66 on the lower surface 12b is low. Therefore, electrons do not easily flow from the drift region 58 to the cathode region 66 when the IGBT is turned on. This suppresses snapback.

[0038] When the semiconductor device 10 operates as a diode, a higher potential is applied to the upper electrode 22 than to the lower electrode 24. In this state, electrons flow from the cathode region 66 into the drift region 58. Also, holes flow from the anode region 56 into the drift region 58. As a result, the resistance of the drift region 58 decreases, and electrons flow through the drift region 58 with low resistance. After passing through the drift region 58, electrons flow to the anode region 56. After passing through the drift region 58, holes flow to the cathode region 66.

[0039] When the semiconductor device 10 is operating as a diode, the voltage Vak between the upper electrode 22 and the lower electrode 24 may switch from a forward voltage (i.e., a voltage at which the potential of the upper electrode 22 is higher than the potential of the lower electrode 24) to a reverse voltage (i.e., a voltage at which the potential of the lower electrode 24 is higher than the potential of the upper electrode 22). When the voltage Vak switches in this way, the diode performs a recovery operation. In the diode's recovery operation, holes present in the drift region 58, the field stop region 60, and the cathode region 66 are discharged to the upper electrode 22 via the anode region 56. As these holes flow, a reverse current (so-called recovery current) flows instantaneously through the diode. By quickly attenuating the recovery current, recovery losses can be suppressed. On the other hand, if the attenuation rate of the recovery current is too fast, a surge voltage will be generated due to the rapid change in the recovery current. In the semiconductor device of Embodiment 1, the operation of the diode changes depending on whether the voltage Vak switches quickly or slowly, thereby achieving both a reduction in recovery losses and a suppression of surges. The operation of the semiconductor device in Example 1 will be described below for both the case where the voltage Vak switches slowly and the case where it switches quickly.

[0040] (If the voltage Vak switching speed is slow) Figure 4 shows a comparison of the recovery characteristics of the diode in Example 1 and the diode in Comparative Example 1 when the voltage Vak switching speed is slow. The diode in Comparative Example 1 differs from the diode in Example 1 in that it has a higher activation rate of n-type impurities in the second cathode region 66b. In Figure 4, the voltage Vak is shown with the higher potential of the cathode (i.e., the lower electrode 24) as positive. In Figure 4, the graphs of voltage Vak for Example 1 and Comparative Example 1 overlap. In Figure 4, the current I F The value indicates the current flowing through the diode. A positive value indicates current flowing in the forward direction, and a negative value indicates current flowing in the reverse direction.

[0041] In Figure 4, current I FThe recovery state occurs when the value is negative. In the recovery state, holes located in the drift region 58, the field stop region 60, and the cathode region 66 are discharged to the upper electrode 22 via the anode region 56. Holes located closer to the anode region 56 are more easily discharged to the upper electrode 22. Therefore, holes located in the cathode region 66 take time to be discharged to the upper electrode 22. In the diode of Comparative Example 1, the recovery current flows until the holes located in the cathode region 66 are discharged to the upper electrode 22, so the recovery current does not decay easily. In contrast, in the diode of Example 1, the activation rate of the n-type impurities in the second cathode region 66b is low, so the carrier lifetime in the second cathode region 66b is short. Therefore, many holes in the second cathode region 66b disappear through recombination with electrons. For this reason, the recovery current decays faster in the diode of Example 1 than in the diode of Comparative Example 1. Therefore, recovery losses are less likely to occur in the diode of Example 1. Furthermore, the surge suppression region 70 has almost no effect on the diode characteristics when the voltage Vak switching speed is slow.

[0042] (When the voltage Vak switching speed is fast) Figure 5 shows a comparison of the recovery characteristics of the diode in Example 1 and the diode in Comparative Example 2 when the voltage Vak switching speed is fast. In the diode in Comparative Example 2, the activation rate of n-type impurities in the second cathode region 66b is low, similar to the diode in Example 1. The diode in Comparative Example 2 differs from the diode in Example 1 in that it does not have a surge suppression region 70.

[0043] In the diode of Comparative Example 2, the activation rate of n-type impurities in the second cathode region 66b is low, so the recovery current is easily attenuated. Therefore, when the voltage Vak switching speed is fast, the rate of attenuation of the recovery current becomes extremely fast, as shown in Figure 5. As a result, a surge voltage Vs is generated during recovery operation due to the effect of parasitic inductance in the electrical circuit. On the other hand, in the diode of Example 1, when the voltage Vak switching speed is fast, holes flow from the surge suppression region 70 to the drift region 58. The inflow of holes into the drift region 58 slows down the rate of attenuation of the recovery current. This prevents the rate of attenuation of the recovery current from becoming excessively fast, as shown in Figure 5, and suppresses the surge voltage.

[0044] As described above, in the semiconductor device of Example 1, when the voltage Vak switching speed is slow, the second cathode region 66b accelerates the decay of the recovery current, thereby reducing recovery losses. Furthermore, in the semiconductor device of Example 1, when the voltage Vak switching speed is fast, the surge suppression region 70 prevents the decay speed of the recovery current from becoming excessively fast, thereby suppressing surge voltage.

[0045] Next, the manufacturing method of the semiconductor device 10 will be described. First, as shown in Figure 6, the structure of the upper surface of the semiconductor device 10 and the field stop region 60 are formed. Next, as shown in Figure 7, a p-type region 72 is formed in the surface layer near the lower surface 12b by injecting p-type impurities into the entire lower surface 12b of the semiconductor substrate 12. The p-type region 72 is a p-type region corresponding to the collector region 64 and the surge suppression region 70. Next, as shown in Figure 8, a cathode region 66 is formed by injecting n-type impurities into a part of the lower surface 12b (i.e., the area corresponding to the cathode region 66) at a higher concentration than the p-type impurity concentration of the p-type region 72. Here, the cathode region 66 is made thicker than the p-type region 72. The remaining p-type region 72 after the formation of the cathode region 66 becomes the collector region 64 and the surge suppression region 70.

[0046] Next, as shown in Figure 9, the lower surface 12b of the semiconductor substrate 12 is heated by irradiating it with a laser L so as to scan the entire lower surface 12b of the semiconductor substrate 12. In this embodiment, a green laser with a wavelength of 532 nm is used as the laser L. By irradiating with the laser L, the surface layer of the semiconductor substrate 12 near the lower surface 12b is heated to a temperature of 950°C or higher. Hereinafter, the area heated to a temperature of 950°C or higher by irradiation with the laser L will be referred to as the heated area 94. Within the heated area 94, the semiconductor substrate 12 temporarily melts. When the semiconductor substrate 12 temporarily melts, impurities diffuse uniformly within the heated area 94. As a result, as shown in Figures 1 to 3, a first cathode region 66a, a surge suppression region 70, and a collector region 64 having a box profile are formed within the heated area 94. Here, the heated area 94 is controlled so that its thickness is thinner than the thickness of the cathode region 66. Therefore, the portion of the cathode region 66 above the heating range 94 becomes the second cathode region 66b, which has a lower n-type impurity concentration than the first cathode region 66a. Since the second cathode region 66b is not included within the heating range 94, the n-type impurities in the second cathode region 66b are less likely to be activated. Consequently, the second cathode region 66b with a low activation rate is formed.

[0047] After the laser irradiation process, the semiconductor device shown in Figure 1 is completed by forming the lower electrode 24. Since the first cathode region 66a, surge suppression region 70, and collector region 64 have high impurity concentrations, these regions make contact with the lower electrode 24 with low contact resistance.

[0048] In Figure 2, the activation rate of n-type impurities is not very high in the first cathode region 66a because the concentration of n-type impurities in the first cathode region 66a is close to the solid solubility limit. In contrast, in the second cathode region 66b, the activation rate of n-type impurities is low despite the n-type impurity concentration not being very high. This is because the second cathode region 66b is not included within the heating range 94 during the laser irradiation process. [Examples]

[0049] Figure 10 shows the impurity concentration distribution at the AA line position of the semiconductor device of Example 2. In Example 2, a bell-shaped distribution M2 of n-type impurity concentration is formed within the second cathode region 66b. The peak value of the n-type impurity concentration in the bell-shaped distribution M2 is 1 × 10⁻⁶. 18 cm -3 Higher, 1 x 10 19 cm -3 It is lower than that. The other configurations of Example 2 are the same as those of Example 1. In the step of injecting n-type impurities into the cathode region 66, a bell-shaped distribution M2 can be formed by locally injecting n-type impurities at a high concentration within the depth range of the second cathode region 66b.

[0050] As in Example 2, forming a bell-shaped distribution M2 increases the concentration of n-type impurities in the second cathode region 66b, thereby lowering the activation rate of n-type impurities within the second cathode region 66b. This shortens the carrier lifetime within the second cathode region 66b, which in turn allows for more effective suppression of the diode's recovery loss. [Examples]

[0051] Figure 11 shows the impurity concentration distribution at the BB line and CC line positions of the semiconductor device of Example 3. In Example 3, the collector region 64 and the surge suppression region 70 have a bell-shaped distribution M3 above the box profile. The other configurations of Example 3 are the same as those of Example 1. In the p-type impurity injection process for the collector region 64 and the surge suppression region 70, the bell-shaped distribution M3 can be formed by injecting p-type impurities such that the peak is above the heating range 94. By forming this bell-shaped distribution M3, the collector region 64 and the surge suppression region 70 can be made thicker than in Example 1. In Example 1, the thickness of the collector region 64 and the surge suppression region 70 was about the same as or thinner than the first cathode region 66a. However, according to Example 3, it is possible to make the thickness of the collector region 64 and the surge suppression region 70 thicker than the first cathode region 66a.

[0052] In the above-described examples 1 to 3, the gate electrode of the IGBT was of the trench type, but the gate electrode of the IGBT may also be of the planar type.

[0053] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness. [Explanation of symbols]

[0054] 10: Semiconductor device, 12: Semiconductor substrate, 16a: Guard electrode, 18: Gate insulating film, 22: Upper electrode, 24: Lower electrode, 30: IGBT region, 40: Diode region, 52: Emitter region, 54: Body region, 56: Anode region, 58: Drift region, 60: Field stop region, 64: Collector region, 66: Cathode region, 66a: First cathode region, 66b: Second cathode region, 70: Surge suppression region

Claims

1. A semiconductor device, A semiconductor substrate (12) having an IGBT region (30) and a diode region (40), An upper electrode (22) that is in contact with the upper surface of the semiconductor substrate within the IGBT region and the diode region, A lower electrode (24) that is in contact with the lower surface of the semiconductor substrate within the IGBT region and the diode region, gate electrode (16a), It has, The aforementioned semiconductor substrate Within the IGBT region, an n-type emitter region (52) in contact with the upper electrode, The upper p-type regions (54, 56) are distributed across the IGBT region and the diode region, and are in contact with the upper electrode within the IGBT region and the diode region. An n-type drift region (58) is located below the upper p-type region, is distributed across the IGBT region and the diode region, and is separated from the emitter region by the upper p-type region. An n-type field stop region (60) is located below the drift region, has a higher n-type impurity concentration than the drift region, has a bell-shaped distribution (M1) in the n-type impurity concentration distribution along the thickness direction of the semiconductor substrate, and is distributed across the IGBT region and the diode region. A p-type collector region (64) is located within the IGBT region, below the field stop region, and in contact with the lower electrode, A plurality of n-type cathode regions (66) are arranged within the diode region, positioned below the field stop region, and in contact with the lower electrode, A plurality of p-type surge suppression regions (70) are arranged within the diode region, located below the field stop region, and in contact with the lower electrode. It has, The gate electrode faces the upper p-type region between the emitter region and the drift region via a gate insulating film (18). Within the diode region, on the lower surface of the semiconductor substrate, a plurality of cathode regions and a plurality of surge suppression regions are alternately arranged along a specific direction. Each of the aforementioned cathode regions is It is in contact with the lower electrode, 1 × 10 １９ cm －３ A first cathode region (66a) having the above n-type impurity concentrations, A second cathode region (66b) is located between the first cathode region and the field stop region, and the activation rate of n-type impurities is 85% or less. Having, Semiconductor equipment.

2. The semiconductor device according to claim 1, wherein a bell-shaped distribution (M2) is provided in the n-type impurity concentration distribution along the thickness direction of the semiconductor substrate within the second cathode region.

3. The bell-shaped distribution provided within the second cathode region is 1 × 10 １８ cm －３ Higher 1 x 10 １９ cm －３ The semiconductor device according to claim 2, having a lower peak value.

4. A method for manufacturing a semiconductor device according to any one of claims 1 to 3, The process involves forming the collector region, the cathode region, and the surge suppression region by ion implanting p-type and n-type impurities into the lower surface of the semiconductor substrate. A step of irradiating the lower surface of the semiconductor substrate with a laser after the formation of the collector region, the cathode region, and the surge suppression region. It has, In the step of irradiating with the laser, a heating area (94) of 950°C or higher is formed in the surface layer near the lower surface of the semiconductor substrate. The thickness of the heating region is thinner than the thickness of the cathode region. Manufacturing method.

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