Power amplifier

Abstract

To provide a power amplifier that meets various requirements for preventing damage to power amplification transistors.SOLUTION: In a power amplifier circuit, a voltage detection circuit 10 outputs a first detection signal det1 giving notice of whether a power supply voltage Vcc applied to a power amplifier transistor is equal to or higher than a first threshold Vth and a second detection signal det2 giving notice of whether the power supply voltage Vcc is equal to or higher than a second threshold, which is larger than the first threshold; a bias circuit 30 supplies a bias current Ibb to the power amplifier transistor; a bias power supply circuit 50 generates a bias power supply current IeC to be supplied to the bias circuit; and a bias control circuit 70 controls the bias circuit. Under the control by the bias control circuit, the bias circuit operates in one of an on-mode in which the bias power supply current is supplied to the power amplifier transistor as a bias current, and an off-mode in which the bias current is supplied at the level lower than that in the on-mode or the supply is stopped.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a power amplification device.

Background Art

[0002] A high-frequency signal power amplification circuit having an overcurrent or overvoltage protection function is disclosed in Patent Document 1. In the power amplification circuit disclosed in Patent Document 1, the level of the power supply current supplied to the collector of the power amplification transistor is limited so as to avoid destruction of the power amplification transistor when an overcurrent or overvoltage occurs. Also, when an overcurrent or overvoltage occurs, the operation of the power amplification transistor is stopped by blocking the current supplied to the base of the bias transistor for supplying a bias current to the power amplification transistor. Thereby, destruction of the amplification transistor is avoided.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Due to various factors from inside and outside and the characteristics of the power amplification circuit, it is necessary to limit the level of the power supply current for preventing destruction of the power amplification transistor and to change the conditions for stopping the operation. An object of the present invention is to provide a power amplification device capable of meeting various requirements for preventing destruction of the power amplification transistor.

Means for Solving the Problems

[0005] According to one aspect of the present invention, a power amplification transistor that amplifies the power of a high-frequency signal, A voltage detection circuit that outputs a first detection signal indicating whether the power supply voltage applied to the power amplification transistor is greater than or equal to a first threshold, and a second detection signal indicating whether it is greater than or equal to a second threshold which is greater than the first threshold, A bias circuit that supplies bias current to the power amplifier transistor, A bias power supply circuit that generates a bias power supply current to be supplied to the bias circuit, A bias control circuit that controls the bias circuit and Equipped with, The bias power supply circuit operates in one of a plurality of current generation modes that generate bias power supply currents of different levels, The plurality of current generation modes include a weak limiting mode in which, when notified by the first detection signal that the power supply voltage is greater than or equal to the first threshold, the bias power supply current is reduced compared to when notified that the power supply voltage is less than the first threshold. The bias circuit operates in either an on-mode, which, under control from the bias control circuit, supplies the bias power supply current generated by the bias power supply circuit to the power amplifier transistor as the bias current, or an off-mode, which supplies the bias current at a lower level than in the on-mode or stops supplying it altogether. The bias control circuit is provided in a power amplifier that can operate the bias circuit in the off mode when notified by the second detection signal that the power supply voltage is equal to or greater than the second threshold. [Effects of the Invention]

[0006] By selecting one of several current generation modes, the level of the bias power supply current can be changed. Lowering the bias power supply current level reduces the bias current of the power amplifier transistor, resulting in a decrease in the power supply current flowing into the collector. Reducing the power supply current can suppress the breakdown of the power amplifier transistor. Selecting one of several current generation modes allows for flexible responses to various requirements for suppressing the breakdown of the power amplifier transistor. Operating the bias circuit in off mode stops the amplification operation of the power amplifier transistor, thereby suppressing its breakdown. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 is a block diagram of a power amplifier circuit according to the first embodiment. [Figure 2] Figure 2 is the equivalent circuit diagram of the voltage selection circuit. [Figure 3] Figure 3 is an equivalent circuit diagram of the first voltage-to-current conversion circuit of the bias power supply circuit. [Figure 4] Figure 4 is a diagram showing the relationship between the first detection signal det1, the first mode selection signals p3 and p4, and the current generation mode. [Figure 5] Figure 5 is an equivalent circuit diagram of the second voltage-to-current conversion circuit of the bias control circuit. [Figure 6] Figure 6 is a diagram showing the relationship between the second detection signal det2, the second mode selection signals p1 and p2, and the operating mode of the bias circuit. [Figure 7] Figure 7 is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signal p3 is set to H level and p4 is set to L level, operating the bias power supply circuit in limit mode, and when the second mode selection signal p1 is set to H level and p2 is set to L level, operating the bias circuit in strong off mode. [Figure 8]Figure 8 is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signal p3 is set to H level and p4 is set to L level, operating the bias power supply circuit in limit mode, and when the second mode selection signal p1 is set to L level and p2 is set to H level, operating the bias circuit in weak off mode. [Figure 9] Figure 9 is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signals p3 and p4 are both set to L level, the bias power supply circuit operates in unrestricted mode, and the second mode selection signal p1 is set to H level and p2 is set to L level, the bias circuit operates in strong off mode. [Figure 10] Figure 10 is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signals p3 and p4 are both set to L level, the bias power supply circuit operates in unrestricted mode, and the second mode selection signal p1 is set to L level and p2 is set to H level, the bias circuit operates in weak off mode. [Figure 11] Figure 11 is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signal p3 is set to L level and p4 is set to H level, operating the bias power supply circuit in strong limit mode, and when the second mode selection signals p1 and p2 are both set to L level, operating the bias circuit in ON mode. [Figure 12] Figure 12 is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signals p3 and p4 are both set to L level, the bias power supply circuit operates in unrestricted mode, and the second mode selection signals p1 and p2 are both set to L level, the bias circuit operates in ON mode. [Figure 13] Figure 13 is an equivalent circuit diagram of the bias power supply circuit of the power amplifier circuit according to a modified example of the first embodiment. [Figure 14] Figure 14 is a block diagram of a power amplifier according to the second embodiment. [Figure 15] Figure 15 is an equivalent circuit diagram of the first voltage-to-current conversion circuit of the power amplifier according to the second embodiment. [Figure 16]FIG. 16 is a chart showing the relationship between the first mode selection signals p3, p4, p5, the bias power supply current IeC, and the current generation mode of the bias power supply circuit in the power amplification circuit according to the second embodiment. [Figure 17] FIG. 17 is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signals p3 and p4 are both set to the L level, p5 is set to the H level, the bias power supply circuit operates in the variable limit mode, the second mode selection signal p1 is set to the H level, and p2 is set to the L level, and the bias circuit operates in the strong off mode (FIG. 6). [Figure 18] FIG. 18 is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signals p3 and p4 are both set to the L level, p5 is set to the H level, the bias power supply circuit operates in the variable limit mode, the second mode selection signal p1 is set to the L level, and p2 is set to the H level, and the bias circuit operates in the weak off mode (FIG. 6).

BEST MODE FOR CARRYING OUT THE INVENTION

[0008] [First Embodiment] Referring to the drawings from FIG. 1 to FIG. 12, a power amplification device according to the first embodiment will be described. FIG. 1 is a block diagram of a power amplification circuit according to the first embodiment. The power amplification circuit according to the first embodiment includes a power amplification transistor 90, a voltage detection circuit 10, a bias circuit 30, a bias power supply circuit 50, and a bias control circuit 70.

[0009] As the power amplification transistor 90, for example, a heterojunction bipolar transistor is used. A high-frequency signal RFin is input to the base of the power amplification transistor 90 via a DC cut capacitor 92. A power supply voltage Vcc is applied to the collector of the power amplification transistor 90 via a choke coil 91. As a result, a DC power supply current Icc is supplied to the collector of the power amplification transistor 90. An amplified high-frequency signal RFout is output from the collector of the power amplification transistor 90. In the following embodiments, a field effect transistor may be used for each of the transistors including the power amplification transistor 90. In this case, the configuration of each embodiment may be understood by reading the base and gate of each transistor as the drain, and the emitter as the source, with the collector.

[0010] Next, the configuration and function of the voltage detection circuit 10 will be described. The voltage detection circuit 10 includes a first comparator 11, a second comparator 12, a voltage dividing circuit 13, and a voltage selection circuit 14. A reference voltage Vref3, selection signals sel1, sel2 are input to the voltage selection circuit 14. The voltage selection circuit 14 divides the reference voltage Vref3 according to each of the selection signals sel1, sel2 to generate a first voltage Vd1 and a second voltage Vd2. The second voltage Vd2 is higher than the first voltage Vd1.

[0011] The voltage dividing circuit 13 divides the power supply voltage Vcc to generate a divided voltage value Vccd. The first comparator 11 compares the divided voltage value Vccd with the first voltage Vd1 and outputs the comparison result as a first detection signal det1. The second comparator 12 compares the divided voltage value Vccd with the second voltage Vd2 and outputs the comparison result as a second detection signal det2. The first comparator 11 is substantially the same as comparing the power supply voltage Vcc (denoted with parentheses in FIG. 1) before dividing the divided voltage value Vccd with a first threshold value Vth1 (denoted with parentheses in FIG. 1) corresponding to the first voltage Vd1, and the second comparator 12 is substantially the same as comparing the power supply voltage Vcc with a second threshold value Vth2 (denoted with parentheses in FIG. 1) corresponding to the second voltage Vd2. The second threshold value Vth2 is higher than the first threshold value Vth1.

[0012] In other words, the voltage detection circuit 10 detects whether the power supply voltage Vcc is equal to or greater than the first threshold Vth1 and outputs the detection result as the first detection signal det1, and detects whether the power supply voltage Vcc is equal to or greater than the second threshold Vth2 and outputs the detection result as the second detection signal det2. For example, the first comparator 11 sets the first detection signal det1 to an L level when the power supply voltage Vcc is less than the first threshold Vth1, and sets the first detection signal det1 to an H level when the power supply voltage Vcc is equal to or greater than the first threshold Vth1. The second comparator 12 sets the second detection signal det2 to an L level when the power supply voltage Vcc is less than the second threshold Vth2, and sets the second detection signal det2 to an H level when the power supply voltage Vcc is equal to or greater than the second threshold Vth2. It is preferable that the first comparator 11 and the second comparator 12 have hysteresis characteristics.

[0013] Next, the detailed configuration of the voltage selection circuit 14 will be described with reference to Figure 2. Figure 2 is an equivalent circuit diagram of the voltage selection circuit 14. The voltage selection circuit 14 includes a multi-stage voltage divider circuit 15 in which multiple resistors are connected in multiple stages, and multiple switches 16 connected to multiple voltage extraction nodes of the multi-stage voltage divider circuit 15. One of the multiple switches 16 is selected and becomes conductive by the selection signal sel1. As a result, the voltage of the voltage extraction node to which the conductive switch 16 is connected (corresponding to the first voltage Vd1) is input to one input node of the first comparator 11. The other input node of the first comparator 11 is input to the divided voltage value Vccd of the power supply voltage Vcc generated by the voltage divider circuit 13. The circuit that generates the second voltage Vd2 (Figure 1) input to the second comparator 12 is the same as the circuit that generates the first voltage Vd1, and one of the multiple switches is selected by the selection signal sel2.

[0014] Next, we will explain the bias circuit 30. As shown in Figure 1, the bias circuit 30 includes a bias transistor 31, a resistor 32, and a diode circuit 33. For example, a heterojunction bipolar transistor is used as the bias transistor 31. The diode circuit 33 includes two diode-connected heterojunction bipolar transistors, and the two heterojunction bipolar transistors are connected in series. The bias power supply current IeC input from the bias power supply circuit 50 is supplied to the collector of the bias transistor 31. The emitter current of the bias transistor 31 is supplied to the base of the power amplifier transistor 90 as a bias current Ibb.

[0015] The bias control current IB, input from the bias control circuit 70, is supplied to the base of the bias transistor 31 via the resistor 32. A portion of the bias control current IB flows to ground via the diode circuit 33. The base current (control current) of the bias transistor 31 is controlled by the bias control current IB.

[0016] The bias circuit 30 receives a bias control current IB from the bias control circuit 70 and can operate in either "on mode" or "off mode". In on mode, it supplies a bias power supply current IeC to the power amplifier transistor 90 as a bias current Ibb. In off mode, it either supplies the power amplifier transistor 90 with a lower level of bias current Ibb than in on mode, or stops supplying it altogether. The mode in which the level of bias current Ibb is supplied to the power amplifier transistor 90 at a lower level than in on mode is called "weak off mode", and the mode in which the supply of bias current Ibb is stopped is called "strong off mode". In weak off mode, because the level of bias current Ibb is low, the power amplifier transistor 90 does not perform any amplification operation. In other words, in weak off mode, the power amplifier transistor 90 does not perform amplification operation with a positive gain.

[0017] Next, the bias power supply circuit 50 will be described. The bias power supply circuit 50 includes a first voltage-current conversion circuit 51 and a first decoder 52. The first voltage-current conversion circuit 51 generates a bias power supply current IeC by converting a reference voltage Vref1 into a current in response to a command from the first decoder 52. The generated bias power supply current IeC is supplied to the bias circuit 30. The first decoder 52 gives a command to the first voltage-current conversion circuit 51 based on first mode selection signals p3, p4, a first control signal cnt1, and a first detection signal det1.

[0018] The level of the bias power supply current IeC changes in response to the first detection signal det1 from the voltage detection circuit 10, as will be explained later. The detailed configuration and operation of the bias power supply circuit 50 will be explained later with reference to Figures 3 and 4.

[0019] Next, we will explain the bias control circuit 70. The bias control circuit 70 includes a second voltage-to-current conversion circuit 71 and a second decoder 72. The second voltage-to-current conversion circuit 71 generates a bias control current IB by converting a reference voltage Vref2 into a current in response to a command from the second decoder 72. The generated bias control current IB is supplied to the bias circuit 30. The second decoder 72 gives a command to the second voltage-to-current conversion circuit 71 based on second mode selection signals p1, p2, second control signal cnt2, and second detection signal det2.

[0020] The level of the bias control current IB changes in response to the second detection signal det2 from the voltage detection circuit 10, as will be explained later. The detailed configuration and operation of the bias control circuit 70 will be explained later with reference to Figures 5 and 6.

[0021] Next, the configuration and operation of the bias power supply circuit 50 will be described with reference to Figures 3 and 4.

[0022] Figure 3 is an equivalent circuit diagram of the first voltage-to-current conversion circuit 51 of the bias power supply circuit 50. The first constant current source 57 is composed of an operational amplifier 53, an n-channel MOSFET 54, three resistors 55, and three switches 56. A reference voltage Vref1 is applied to the non-inverting input node of the operational amplifier 53. The resistance values ​​of the three resistors 55 are all different. A switch 56 is connected in series to each of the three resistors 55. Three series circuits consisting of resistors 55 and switches 56 are connected in parallel. The switches 56 are turned on and off by commands from the first decoder 52. When one of the three switches 56 is selected and made conductive, the first constant current source 57 generates a current of a constant level corresponding to the resistance value of the resistor 55 connected to the conductive switch 56.

[0023] In Figure 3, a configuration is shown in which the resistance value is switched using three resistor elements 55 and three switches 56, but the method of switching the resistance value is not limited to this. For example, instead of providing multiple resistor elements with different resistance values ​​for the number of resistance values ​​to be achieved, as shown in Figure 3, a configuration may be used in which a group of resistor elements is provided that includes multiple resistor elements with the same resistance value and multiple switches that switch the connections between these resistor elements, and the combined resistance value of this group of resistor elements is switched.

[0024] Two p-channel MOSFETs constitute the first current mirror 58. The battery voltage VBAT is applied to the sources of the two p-channel MOSFETs. The drain current of the n-channel MOSFET 54 (the current generated by the first constant current source 57) is multiplied by K by the first current mirror 58 consisting of the two p-channel MOSFETs to generate a bias power supply current IeC. The bias power supply current IeC is supplied to the bias circuit 30.

[0025] The first decoder 52 receives the first control signal cnt1, the first detection signal det1, and the first mode selection signals p3 and p4. The first control signal cnt1 stops the operation of the first voltage-to-current conversion circuit 51 and adjusts the amount of current based on switching the resistance values ​​of the circuit including the three resistors 55.

[0026] The bias power supply circuit 50 can operate in any of several current generation modes that generate bias power supply currents IeC at different levels. For example, if a table like the one shown in Figure 4, which will be described later, is stored in the first decoder 52, the bias power supply circuit 50 can operate in any of several current generation modes that generate bias power supply currents IeC at different levels. Next, with reference to Figure 4, the relationship between the first detection signal det1, the first mode selection signals p3 and p4, and the current generation modes will be explained.

[0027] Figure 4 is a diagram showing the relationship between the first detection signal det1, the first mode selection signals p3 and p4, and the current generation mode. When the first detection signal det1 is at an L level, that is, when the power supply voltage Vcc is less than the first threshold Vth1, the bias power supply circuit 50 sets the level of the bias power supply current IeC to IeC1, regardless of the values ​​of the first mode selection signals p3 and p4.

[0028] When the first detection signal det1 is at a high level, that is, when the power supply voltage Vcc is equal to or greater than the first threshold Vth1, the bias power supply circuit 50 sets the level of the bias power supply current IeC according to the values ​​of the first mode selection signals p3 and p4. When both the first mode selection signals p3 and p4 are at a low level, the level of the bias power supply current IeC is set to IeC1. When the bias current Ibb at level IeC1 is supplied to the power amplifier transistor 90 (Figure 1), the power amplifier transistor 90 performs normal amplification operation. The current generation mode in which the level of the bias power supply current IeC is set to IeC1 is called the "unrestricted mode".

[0029] When the first mode selection signal p3 is at a low level and p4 is at a high level, the level of the bias power supply current IeC is set to IeCL. Level IeCL is a low level such that even if a bias current Ibb of this level is supplied to the power amplifier transistor 90 (Figure 1), the power amplifier transistor 90 will not substantially perform amplification operation. The current generation mode that sets the level of the bias power supply current IeC to IeCL is called the "strong limiting mode".

[0030] When the first mode selection signal p3 is at a high level and p4 is at a low level, the level of the bias power supply current IeC is set to a constant level IeC2, which is lower than IeC1. In this state, the bias current Ibb supplied to the power amplifier transistor 90 decreases compared to the unrestricted mode. The power amplifier transistor 90 performs amplification with its operating point changed. The current generation mode in which the level of the bias power supply current IeC is set to IeC2 is called the "weakly restricted mode". It is also sometimes called the "constantly restricted mode" because the restricted level IeC2 is a constant value.

[0031] Next, the configuration and operation of the bias control circuit 70 will be described with reference to Figures 5 and 6.

[0032] Figure 5 is an equivalent circuit diagram of the second voltage-current conversion circuit 71 of the bias control circuit 70. The basic circuit configuration of the second voltage-current conversion circuit 71 is the same as that of the first voltage-current conversion circuit 51, and includes a second constant current source 77 and a second current mirror 78.

[0033] The second constant current source 77 includes an operational amplifier 73, an n-channel MOSFET 74, two resistors 75, and two switches 76. A reference voltage Vref2 is applied to the non-inverting input node of the operational amplifier 73. The resistance values ​​of the two resistors 75 are different from each other. The switches 76 are turned on and off by commands from the second decoder 72. When one of the two switches 56 is selected to conduct, the second constant current source 77 generates a constant level of current corresponding to the resistance value of the resistor 75 connected to the conducted switch 76.

[0034] The drain current of the n-channel MOSFET 74 (the current generated by the second constant current source 77) is multiplied by K by the second current mirror 78 to generate the bias control current IB. Note that the current multiplier of the second current mirror 78 is usually different from that of the first current mirror 58 (Figure 3). The bias control current IB is supplied to the bias circuit 30.

[0035] The second decoder 72 receives the second control signal cnt2, the second detection signal det2, and the second mode selection signals p1 and p2. The second control signal cnt2 stops the operation of the second voltage-current conversion circuit 71 and adjusts the amount of current. The bias control circuit 70 switches the operating mode of the bias circuit 30 between on mode and off mode by generating bias control currents IB of different levels. Next, with reference to Figure 6, the relationship between the second detection signal det2, the second mode selection signals p1 and p2, and the operating mode of the bias circuit 30 will be explained.

[0036] Figure 6 is a diagram showing the relationship between the second detection signal det2, the second mode selection signals p1 and p2, and the operating modes of the bias circuit 30. For example, if a table like the one shown in Figure 6 is stored in the second decoder 72, it can be said that the bias circuit 30 can operate in any of the multiple operating modes, or that the bias control circuit 70 can make the bias circuit 30 operate in any of the multiple operating modes. When the second detection signal det2 is at the L level, that is, when the power supply voltage Vcc is less than the second threshold Vth2, the bias control circuit 70 sets the level of the bias control current IB to the normal level L, regardless of the values ​​of the second mode selection signals p1 and p2.

[0037] When the second detection signal det2 is at a high level, that is, when the power supply voltage Vcc is equal to or greater than the second threshold Vth2, the bias control circuit 70 sets the level of the bias control current IB according to the values ​​of the second mode selection signals p1 and p2.

[0038] When both the second mode selection signals p1 and p2 are at the L level, the level of the bias control current IB is set to the normal level L. When the bias control current IB at the normal level L is supplied to the bias circuit 30 (Figure 1), the bias current Ibb supplied to the power amplifier transistor 90 becomes approximately the same level as the bias power supply current IeC. The operating mode of the bias circuit 30 when the level of the bias control current IB is set to the normal level L is referred to as "on mode".

[0039] When the second mode selection signal p1 is at a low level and p2 is at a high level, the level of the bias control current IB is set to a low level (Llow). When the low-level bias control current IB is supplied to the bias circuit 30 (Figure 1), the bias current Ibb supplied to the power amplifier transistor 90 decreases compared to the bias current Ibb in the on-mode. In this state, the power amplifier transistor 90 does not perform any amplification operation. The operating mode of the bias circuit 30 when the level of the bias control current IB is set to a low level (Llow) is referred to as the "weak off mode".

[0040] When the second mode selection signal p1 is at a high level and p2 is at a low level, the level of the bias control current IB is set to the off level Loff. Specifically, the supply of the bias control current IB is stopped. At this time, the bias current Ibb is no longer supplied to the power amplifier transistor 90, and the amplification operation of the power amplifier transistor 90 stops. The operating mode of the bias circuit 30 when the level of the bias control current IB is set to the off level Loff is referred to as the "strong off mode".

[0041] Next, the relationship between the power supply voltage Vcc and power supply current Icc of the power amplifier transistor 90 will be explained with reference to Figures 7 to 12. Figures 7 to 12 are graphs showing the relationship between the power supply voltage Vcc and power supply current Icc of the power amplifier transistor 90. The horizontal axis represents the power supply voltage Vcc, and the vertical axis represents the power supply current Icc. The approximate failure region 60 of the power amplifier transistor 90 is represented by a hatched figure.

[0042] Figure 7 is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signal p3 is set to H level and p4 is set to L level, causing the bias power supply circuit 50 to operate in limit mode, and when the second mode selection signal p1 is set to H level and p2 is set to L level, causing the bias circuit 30 to operate in strong off mode.

[0043] When the power supply voltage Vcc is less than the first threshold Vth1 (the first detection signal det1 is at a low level), the level of the bias power supply current IeC becomes IeC1. When the power supply voltage Vcc is greater than or equal to the first threshold Vth1 (the first detection signal det1 is at a high level), the level of the bias power supply current IeC becomes IeC2, which is lower than IeC1. When the power supply voltage Vcc is less than the second threshold Vth2 (the second detection signal det2 is at a low level), the bias control current IB becomes the normal level Lon, and the bias circuit 30 (Figure 1) operates in ON mode.

[0044] When the bias circuit 30 is operating in ON mode, the power supply current Icc is proportional to the bias power supply current IeC. Specifically, the level of the power supply current Icc is approximately equal to the value obtained by multiplying the bias power supply current IeC by the current amplification factor hfe of the power amplification transistor 90. For example, when the level of the bias power supply current IeC is IeC1, the level of the power supply current Icc Icc1 is equal to hfe × IeC1. When the level of the bias power supply current IeC is IeC2, the level of the power supply current Icc Icc2 is equal to hfe × IeC2.

[0045] When the power supply voltage Vcc exceeds the second threshold Vth2 (the second detection signal det2 is at the off level Loff), the bias control current IB also becomes the off level Loff, and the bias circuit 30 operates in strong off mode. As a result, the power supply current Icc becomes almost zero. In other words, the power supply current Icc decreases in a two-step manner as the power supply voltage Vcc increases.

[0046] When an excessive voltage (a voltage above the second threshold Vth2) is applied to the power amplifier transistor 90, the amplification operation of the power amplifier transistor 90 is stopped, thereby suppressing the destruction of the power amplifier transistor 90. As the power supply voltage Vcc increases, the power supply current Icc decreases in a two-stage stepwise manner, allowing the safe operating region of the power amplifier transistor 90 to be effectively utilized.

[0047] Figure 8 is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signal p3 is set to H level and p4 is set to L level, causing the bias power supply circuit 50 to operate in limit mode, and when the second mode selection signal p1 is set to L level and p2 is set to H level, causing the bias circuit 30 to operate in weak off mode.

[0048] The relationship between the power supply voltage Vcc and the power supply current Icc when the power supply voltage Vcc is less than the second threshold Vth2 is the same as the relationship shown in Figure 7. When the power supply voltage Vcc becomes equal to or greater than the second threshold Vth2 (the second detection signal det2 is at a high level), the bias control circuit 70 sets the bias control current IB to a low level Llow. As a result, the operating mode of the bias circuit 30 becomes a weak off mode, and the level of the power supply current Icc drops to IccL. At this level IccL, the power amplifier transistor 90 does not perform any amplification operation.

[0049] Even when the power supply voltage Vcc exceeds the second threshold Vth2, the supply of bias power supply current IeC is not completely stopped (i.e., the supply of bias current Ibb is not completely stopped), resulting in a shorter recovery time compared to the case where the supply of bias power supply current IeC is completely stopped.

[0050] Figure 9 is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signals p3 and p4 are both set to L level, the bias power supply circuit 50 operates in unrestricted mode, and the second mode selection signal p1 is set to H level and p2 is set to L level, the bias circuit 30 operates in strong off mode.

[0051] Since the bias power supply circuit 50 operates in unrestricted mode, the level of the bias power supply current IeC is set to IeC1 regardless of whether the power supply voltage Vcc is greater than or equal to the first threshold Vth1. When the power supply voltage Vcc is less than the second threshold Vth2 (the second detection signal det2 is at the L level), the bias control current IB is set to the normal level Lon, so the level of the power supply current Icc becomes Icc1 (hfe × IeC1).

[0052] When the power supply voltage Vcc exceeds the second threshold Vth2 (the second detection signal det2 is at a high level), the bias control current IB is set to the off level Loff. As a result, similar to the case in Figure 7, the power supply current Icc becomes almost zero. In other words, as the power supply voltage Vcc increases, the power supply current Icc decreases in a stepwise manner.

[0053] Figure 10 is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signals p3 and p4 are both set to L level, the bias power supply circuit 50 operates in unrestricted mode, and the second mode selection signal p1 is set to L level and p2 is set to H level, the bias circuit 30 operates in weak off mode.

[0054] When the power supply voltage Vcc is less than the second threshold Vth2 (the second detection signal det2 is at the L level), the level of the power supply current Icc is the same as in Figure 9. When the power supply voltage Vcc is equal to or greater than the second threshold Vth2 (the second detection signal det2 is at the H level), the level of the power supply current Icc decreases to IccL, similar to the case in Figure 8. In other words, as the power supply voltage Vcc increases, the power supply current Icc decreases in a stepwise manner.

[0055] Figure 11 is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signal p3 is set to L level and p4 is set to H level, the bias power supply circuit 50 operates in strong limit mode, and the second mode selection signals p1 and p2 are both set to L level, the bias circuit 30 operates in ON mode. The level of the bias control current IB is normally set to level Lon, regardless of the power supply voltage Vcc.

[0056] When the power supply voltage Vcc is less than the first threshold Vth1 (the first detection signal det1 is at a low level), the level of the bias power supply current IeC is set to IeC1, causing the level of the power supply current Icc to become Icc1 (hfe × IeC1). When the power supply voltage Vcc becomes equal to or greater than the first threshold Vth1 (the first detection signal det1 is at a high level), the level of the bias power supply current IeC is set to IeCL, causing the level of the power supply current Icc to decrease to IccL (hfe × IeCL). In other words, as the power supply voltage Vcc increases, the power supply current Icc decreases in a stepwise manner.

[0057] Figure 12 is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signals p3 and p4 are both set to L level, the bias power supply circuit 50 operates in unrestricted mode, and the second mode selection signals p1 and p2 are both set to L level, the bias circuit 30 operates in ON mode. Regardless of the power supply voltage Vcc, the level of the bias control current IB is normally set to L level, and the level of the bias power supply current IeC is set to IeC1.

[0058] Therefore, the level of the power supply current Icc is a fixed value Icc1 (hfe × IeC1) regardless of the power supply voltage Vcc.

[0059] Next, we will describe the excellent effects of the first embodiment. In the first embodiment, as shown in Figures 4 and 6, the level of the bias power supply current IeC and the operating mode of the bias circuit 30 can be changed by setting the second mode selection signals p1 and p2 and the first mode selection signals p3 and p4. For example, as shown in Figures 7 and 8, the power supply current Icc of the power amplifier transistor 90 can be reduced in a two-step step as the power supply voltage Vcc increases. Furthermore, as shown in Figures 9, 10, and 11, the power supply current Icc of the power amplifier transistor 90 can be reduced in a single-step step. In addition, as shown in Figure 12, the power supply current Icc of the power amplifier transistor 90 can be kept almost constant regardless of the power supply voltage Vcc.

[0060] In this way, the power supply current Icc can be flexibly reduced according to the characteristics of the power amplifier transistor 90, and the amplification operation can be effectively stopped.

[0061] Next, with reference to Figure 13, the bias power supply circuit of the power amplifier circuit according to a modified example of the first embodiment will be described.

[0062] Figure 13 is an equivalent circuit diagram of the bias power supply circuit 50 of the power amplifier circuit according to a modification of the first embodiment. In the first embodiment (Figure 3), the level of the bias power supply current IeC is changed by changing the level of the current generated by the first constant current source 57. In contrast, in the modification shown in Figure 13, the level of the current generated by the first constant current source 57 is constant. In this modification, the level of the bias power supply current IeC is changed by changing the current multiplier of the first current mirror 58 according to the output of the first decoder 52.

[0063] Specifically, the output circuit of the first current mirror 58 is composed of a parallel circuit of multiple transistors. The gate of at least one of the multiple transistors constituting the parallel circuit is connected to the gate of the input transistor via a switch 59. The conduction and non-conductivity of the switch 59 is switched by the output of the first decoder 52. By switching the conduction and non-conductivity of the switch 59, the current multiplier of the first current mirror 58 can be changed.

[0064] Similarly to the first voltage-current conversion circuit 51 shown in Figure 13, the second voltage-current conversion circuit 71 (Figure 5) of the bias control circuit 70 may also be configured to have a fixed value for the resistor element 75 (Figure 5) without connecting the switch 76, and the current multiplier of the second current mirror 78 (Figure 5) may be made variable.

[0065] Next, other modifications of the first embodiment will be described. In the first embodiment, a bipolar transistor is used as the bias transistor 31, but a MOSFET may also be used. In this case, the bias power supply current IeC is supplied to the drain of the MOSFET. The bias control circuit 70 switches between the on mode, weak off mode, and strong off mode of the bias circuit 30 shown in Figure 6 by controlling the gate bias of the MOSFET.

[0066] [Second Example] Next, a power amplifier according to the second embodiment will be described with reference to Figures 14 to 18. The following description will omit explanations of components common to the power amplifier according to the first embodiment, which was described with reference to Figures 1 to 12.

[0067] Figure 14 is a block diagram of a power amplifier according to the second embodiment. In the first embodiment (Figure 1), the output of the first decoder 52 and the reference voltage Vref1 are input to the first voltage-current conversion circuit 51. In the second embodiment, the first voltage-current conversion circuit 51 is further input to the first voltage-current conversion circuit 51, which is the divided voltage value Vccd of the power supply voltage Vcc generated by the voltage divider circuit 13, and the first voltage Vd1 generated by the voltage selection circuit 14. Furthermore, in addition to the first mode selection signals p3 and p4, a third first mode selection signal p5 is input to the first decoder 52.

[0068] The first voltage-current conversion circuit 51 changes the level of the bias power supply current IeC based on the difference between the voltage divider value Vccd of the power supply voltage Vcc and the first voltage Vd1 (corresponding to the first threshold Vth1).

[0069] Figure 15 is an equivalent circuit diagram of the first voltage-current conversion circuit 51. The first voltage-current conversion circuit 51 of the power amplifier according to this modified example includes a differential current generation circuit 80 in addition to the first constant current source 57 and the first current mirror 58. The differential current generation circuit 80 generates a differential current Idif whose level corresponds to the difference between the power supply voltage Vcc and the first threshold Vth1.

[0070] Next, the configuration and operation of the differential current generation circuit 80 will be described. The current source is comprised of a third operational amplifier 81, a transistor 83, two resistors 84 connected in parallel, a switch 85 connected in series with each of the resistors 84, and a fourth operational amplifier 82. The switches 85 are controlled on and off by the output of the first decoder 52.

[0071] A voltage equivalent to the difference between the divided voltage Vccd of the power supply voltage Vcc and the first voltage Vd1 (corresponding to the first threshold voltage Vth1) is applied across each terminal of the resistor element 84. A current of magnitude determined by the difference between the divided voltage Vccd of the power supply voltage Vcc and the first voltage Vd1 (corresponding to the first threshold voltage Vth1) (hereinafter referred to as the differential voltage) and the resistance value of the resistor element 84 flows through the transistor 83.

[0072] Transistors 83 and 87 constitute a current mirror. When switch 86 is turned on, this current mirror operates, and current flows through transistor 87. Switch 86 is controlled on and off by the output of the first decoder 52. The current flowing through transistor 87 is output externally as differential current Idif. The level of differential current Idif increases linearly with respect to the differential voltage. Also, the rate of change of differential current Idif with respect to the differential voltage decreases as the resistance value of resistor 84 increases.

[0073] The differential current Idif acts to reduce the current generated by the first constant current source 57. As a result, the level of the bias power supply current IeC decreases in proportion to the differential voltage. That is, as the differential voltage increases, the decrease in the bias power supply current IeC increases.

[0074] Figure 16 is a diagram showing the relationship between the first mode selection signals p3, p4, and p5, the bias power supply current IeC, and the current generation mode of the bias power supply circuit 50. When the first mode selection signal p5 is at the L level, the switch 86 becomes non-conductive, and the differential current Idif does not flow. Therefore, the operation of the bias power supply circuit 50 is the same as in the first embodiment (Figure 4).

[0075] When the first mode selection signal p5 is at a high level, and both the first mode selection signals p3 and p4 are at low levels, the first detection signal det1 becomes high, causing the first decoder 52 to conduct at least one switch 85 and switch 86. As a result, the level IeC2 of the bias power supply current IeC decreases in accordance with the differential voltage. This current generation mode is called the "weak limiting mode." It is also sometimes called the variable limiting mode to distinguish it from the constant limiting mode (Figure 4).

[0076] Figure 17 is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signals p3 and p4 are both set to L level and p5 is set to H level, causing the bias power supply circuit 50 to operate in variable limit mode, and when the second mode selection signal p1 is set to H level and p2 is set to L level, causing the bias circuit 30 to operate in strong off mode (Figure 6).

[0077] In the example shown in Figure 7 of the first embodiment, when the power supply voltage Vcc is equal to or greater than the first threshold Vth1, the level of the bias power supply current IeC decreases to a constant value IeC2. In contrast, in the example shown in Figure 17, when the power supply voltage Vcc is equal to or greater than the first threshold Vth1 (the first detection signal det1 is at the H level), the level of the bias power supply current IeC IeC2 gradually and continuously decreases as the power supply voltage Vcc increases. Similarly, the level of the power supply current Icc Icc2 (hfe × IeC2) also gradually and continuously decreases, for example, linearly.

[0078] When the power supply voltage Vcc rises further and exceeds the second threshold Vth2 (the second detection signal det2 is at a high level), the bias control current IB becomes the off level Loff, and the supply of the bias power supply current IeC is stopped. As a result, the amplification operation of the power amplifier transistor 90 (Figure 1) stops.

[0079] Figure 18 is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signals p3 and p4 are both set to L level and p5 is set to H level, causing the bias power supply circuit 50 to operate in variable limit mode, and when the second mode selection signal p1 is set to L level and p2 is set to H level, causing the bias circuit 30 to operate in weak off mode (Figure 6).

[0080] The relationship between the power supply voltage Vcc and the power supply current Icc when the power supply voltage Vcc is less than the second threshold Vth2 is the same as in Figure 17. When the power supply voltage Vcc becomes equal to or greater than the second threshold Vth2 (the second detection signal det2 is at a high level), the bias control current IB becomes low, and the level of the bias power supply current IeC drops to IccL.

[0081] Next, the superior effects of the second embodiment will be described. In the second embodiment, as in the first embodiment, the power supply current Icc can be flexibly reduced and the amplification operation can be substantially stopped depending on the characteristics of the power amplifier transistor 90. Furthermore, in the second embodiment, since the bias power supply current IeC is gradually reduced as the power supply voltage Vcc increases, it becomes possible to use the safe operating region of the power amplifier transistor 90 more effectively.

[0082] The embodiments described above are illustrative, and it goes without saying that partial substitution or combination of the configurations shown in different embodiments is possible. Similar effects and benefits from similar configurations in multiple embodiments will not be mentioned sequentially for each embodiment. Furthermore, the present invention is not limited to the embodiments described above. For example, it will be obvious to those skilled in the art that various modifications, improvements, and combinations are possible.

[0083] Based on the embodiments described herein, the following inventions are disclosed. <1> A power amplifier transistor that amplifies the power of high-frequency signals, A voltage detection circuit that outputs a first detection signal indicating whether the power supply voltage applied to the power amplification transistor is greater than or equal to a first threshold, and a second detection signal indicating whether it is greater than or equal to a second threshold which is greater than the first threshold, A bias circuit that supplies bias current to the power amplifier transistor, A bias power supply circuit that generates a bias power supply current to be supplied to the bias circuit, A bias control circuit that controls the bias circuit and Equipped with, The bias power supply circuit operates in one of a plurality of current generation modes that generate bias power supply currents of different levels, The plurality of current generation modes include a weak limiting mode in which, when notified by the first detection signal that the power supply voltage is greater than or equal to the first threshold, the bias power supply current is reduced compared to when notified that the power supply voltage is less than the first threshold. The bias circuit operates in either an on-mode, which, under control from the bias control circuit, supplies the bias power supply current generated by the bias power supply circuit to the power amplifier transistor as the bias current, or an off-mode, which supplies the bias current at a lower level than in the on-mode or stops supplying it altogether. The bias control circuit is a power amplifier that can operate the bias circuit in the off mode when it is notified by the second detection signal that the power supply voltage is equal to or greater than the second threshold.

[0084] <2> The weak limiting mode includes a constant limiting mode that reduces the bias power supply current to a constant level lower than the level when the power supply voltage is notified to be below the first threshold. <1> The power amplifier described above.

[0085] <3> The weak limiting mode includes a variable limiting mode that increases the amount by which the level of the bias power supply current decreases relative to the level of the bias power supply current when the power supply voltage is indicated to be below the first threshold, as the power supply voltage increases. <1> or <2> The power amplifier described above.

[0086] <4> The aforementioned bias power supply circuit is A first mode selection signal for selecting the current generation mode, and a first decoder for decoding the first detection signal, A first constant current source that changes the level of current generated in accordance with the output from the first decoder, A first current mirror outputs the current generated by the first constant current source as the bias power supply current. including <2> The power amplifier described above.

[0087] <5> The aforementioned bias power supply circuit is A first mode selection signal for selecting the current generation mode, and a first decoder for decoding the first detection signal, First constant current source, A first current mirror outputs the current generated by the first constant current source as the bias power supply current by changing the magnification according to the output from the first decoder. including <2> The power amplifier described above.

[0088] <6> The aforementioned bias power supply circuit is A first mode selection signal for selecting the current generation mode, and a first decoder for decoding the first detection signal, First constant current source, A first current mirror outputs the current generated by the first constant current source as the bias power supply current by changing the magnification according to the output from the first decoder. including <2> The power amplifier described above.

[0089] <7> The aforementioned bias power supply circuit is A first mode selection signal for selecting the current generation mode, and a first decoder for decoding the first detection signal, A current source that changes the level of current generated according to the output from the first decoder and the difference between the power supply voltage and the first threshold, A first current mirror outputs the current generated by the current source as the bias power supply current. including <3> The power amplifier described above.

[0090] <8> The plurality of current generation modes further include an unrestricted mode that maintains the bias power supply current at a fixed value regardless of the state of the first detection signal. <1> ~ <7> A power amplifier as described in any one of the following.

[0091] <9> The plurality of current generation modes further include a strong limiting mode in which, when notified by the first detection signal that the power supply voltage is above the first threshold, the level of the bias power supply current is reduced to a level in which the power amplification transistor does not perform amplification operation. <1> ~ <8> A power amplifier as described in any one of the following.

[0092] <10> The bias control circuit can be operated in a strong off mode, which stops the supply of the bias current to the power amplifier transistor when the bias circuit is operated in the off mode. <1> ~ <9> A power amplifier as described in any one of the following.

[0093] <11> The bias control circuit can be operated in a weak off mode, where, when the bias circuit is operated in the off mode, the bias current, with a reduced level of the bias power supply current, is supplied from the bias circuit to the power amplification transistor. <1> ~ <10> A power amplifier as described in any one of the following.

[0094] <12> The voltage detection circuit is A first comparator compares the power supply voltage with the first threshold and outputs the comparison result as the first detection signal, A second comparator compares the power supply voltage with the second threshold and outputs the comparison result as the second detection signal. Claims including <1> ~ <11> A power amplifier as described in any one of the following.

[0095] <13> The bias circuit includes a bias transistor that supplies the bias current to the power amplifier transistor. The emitter or source of the bias transistor is connected to the base or gate of the power amplifier transistor, the bias power supply current is supplied to the collector or drain of the bias transistor, and the control current of the bias transistor is controlled by the bias control circuit. <1> ~ <12> A power amplifier as described in any one of the following.

[0096] <14> The bias control circuit is, A second mode selection signal for selecting the operating mode of the bias circuit, and a second decoder for decoding the second detection signal, A second constant current source that changes the level of the current it generates in accordance with the output from the second decoder, A second current mirror that supplies the current generated by the second constant current source to the bias circuit, including <1> ~ <13> A power amplifier as described in any one of the following.

[0097] <15> The bias control circuit is, A second mode selection signal for selecting the operating mode of the bias circuit, and a second decoder for decoding the second detection signal, Second constant current source, A second current mirror provides the bias circuit with the current generated by the second constant current source, with the magnification changed according to the output from the second decoder. including <1> ~ <13> A power amplifier as described in any one of the following. [Explanation of Symbols]

[0098] 10 Voltage detection circuit 11. First comparator 12. Second Comparator 13. Voltage divider circuit 14 Voltage Selection Circuit 15. Multi-stage voltage divider circuit 16 switches 30 Bias Circuit 31 Bias Transistors 32 Resistor elements 33 Diode Circuits 50 Bias power supply circuit 51. First Voltage-Current Conversion Circuit 52 First Decoder 53 Op-amps 54 n-channel MOSFET 55 Resistors 56 switches 57 1st constant current source 58. First Current Mirror 60 Destruction Zone 70 Bias control circuit 71 Second Voltage-Current Conversion Circuit 72 Second Decoder 73 Op-amps 75 Resistors 76 switches 77 Second constant current source 78. Second Current Mirror 80 Differential current generation circuit 81 Third operational amplifier 82. Fourth operational amplifier 83 Transistors 84 Resistors 85, 86 Switch 87 Transistors 90 Power Amplifier Transistors 91 Choke coil 92 DC Cut Capacitor

Claims

1. A power amplifier transistor that amplifies the power of high-frequency signals, A voltage detection circuit that outputs a first detection signal indicating whether the power supply voltage applied to the power amplification transistor is greater than or equal to a first threshold, and a second detection signal indicating whether it is greater than or equal to a second threshold which is greater than the first threshold, A bias circuit that supplies bias current to the power amplifier transistor, A bias power supply circuit that generates a bias power supply current to be supplied to the bias circuit, A bias control circuit that controls the bias circuit and Equipped with, The bias power supply circuit operates in one of a plurality of current generation modes that generate bias power supply currents of different levels, The plurality of current generation modes include a weak limiting mode in which, when notified by the first detection signal that the power supply voltage is equal to or greater than the first threshold, the bias power supply current is reduced compared to when notified that the power supply voltage is less than the first threshold. The bias circuit operates in either an on-mode, which, under control from the bias control circuit, supplies the bias power supply current generated by the bias power supply circuit to the power amplifier transistor as the bias current, or an off-mode, which supplies the bias current at a lower level than in the on-mode or stops supplying it altogether. The bias control circuit is a power amplifier that can operate the bias circuit in the off mode when notified by the second detection signal that the power supply voltage is equal to or greater than the second threshold.

2. The power amplifier according to claim 1, wherein the weak limiting mode includes a constant limiting mode that reduces the bias power supply current to a constant level lower than the level when the power supply voltage is notified to be less than the first threshold.

3. The power amplifier according to claim 1 or 2, wherein the weak limiting mode includes a variable limiting mode that increases the amount of decrease in the level of the bias power supply current relative to the level of the bias power supply current when the power supply voltage is notified to be below the first threshold as the power supply voltage increases.

4. The aforementioned bias power supply circuit is A first mode selection signal for selecting the current generation mode, and a first decoder for decoding the first detection signal, A first constant current source that changes the level of current generated in accordance with the output from the first decoder, A first current mirror outputs the current generated by the first constant current source as the bias power supply current. The power amplifier according to claim 2, including the following:

5. The aforementioned bias power supply circuit is A first mode selection signal for selecting the current generation mode, and a first decoder for decoding the first detection signal, First constant current source, A first current mirror outputs the current generated by the first constant current source as the bias power supply current, with the magnification changed according to the output from the first decoder. The power amplifier according to claim 2, including the following:

6. The aforementioned bias power supply circuit is A first mode selection signal for selecting the current generation mode, and a first decoder for decoding the first detection signal, First constant current source, A first current mirror outputs the current generated by the first constant current source as the bias power supply current, with the magnification changed according to the output from the first decoder. The power amplifier according to claim 2, including the following:

7. The aforementioned bias power supply circuit is A first mode selection signal for selecting the current generation mode, and a first decoder for decoding the first detection signal, A current source that changes the level of current generated according to the output from the first decoder and the difference between the power supply voltage and the first threshold, A first current mirror outputs the current generated by the current source as the bias power supply current. The power amplifier according to claim 3, including the following:

8. The power amplifier according to claim 1 or 2, further comprising an unrestricted mode in which the plurality of current generation modes maintain the bias power supply current at a fixed value regardless of the state of the first detection signal.

9. The power amplifier according to claim 1 or 2, further comprising a strong limiting mode in which, when notified by the first detection signal that the power supply voltage is above the first threshold, the level of the bias power supply current is reduced to a level such that the power amplifier transistor does not perform amplification operation.

10. The power amplifier according to claim 1 or 2, wherein the bias control circuit can be operated in a strong off mode that stops supplying the bias current to the power amplifier transistor when the bias circuit is operated in the off mode.

11. The power amplifier according to claim 1 or 2, wherein the bias control circuit can be operated in a weak off mode, in which the bias current, with the level of the bias power supply current reduced, is supplied from the bias circuit to the power amplifier transistor when the bias circuit is operated in the off mode.

12. The voltage detection circuit is A first comparator compares the power supply voltage with the first threshold and outputs the comparison result as the first detection signal, A second comparator compares the power supply voltage with the second threshold and outputs the comparison result as the second detection signal. A power amplifier according to claim 1 or 2, including the following:

13. The bias circuit includes a bias transistor that supplies the bias current to the power amplifier transistor. The power amplifier according to claim 1 or 2, wherein the emitter or source of the bias transistor is connected to the base of the power amplifier transistor, the bias power supply current is supplied to the collector or drain of the bias transistor, and the control current of the bias transistor is controlled by the bias control circuit.

14. The bias control circuit is, A second mode selection signal for selecting the operating mode of the bias circuit, and a second decoder for decoding the second detection signal, A second constant current source that changes the level of the current it generates according to the output from the second decoder, A second current mirror that supplies the current generated by the second constant current source to the bias circuit, A power amplifier according to claim 1 or 2, including the following:

15. The bias control circuit is, A second mode selection signal for selecting the operating mode of the bias circuit, and a second decoder for decoding the second detection signal, Second constant current source, A second current mirror provides the current generated by the second constant current source to the bias circuit, changing the magnification according to the output from the second decoder. A power amplifier according to claim 1 or 2, comprising:

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