Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device capable of suppressing a conduct of a heat generated in a transistor to an element.SOLUTION: A semiconductor device comprises: a silicon carbide substrate 10a; a nitride semiconductor layer 10b that is provided onto an upper surface of the silicon carbide substrate; a transistor 20 that is provided onto the nitride semiconductor layer; and an element that is provided onto the silicon carbide substrate. At least one part of the silicon carbide substrate is removed from a lower surface of the silicon carbide substrate, and the silicon carbide substrate is provided between the transistor and the element, and includes a hole 42 whose heat transfer coefficient in an inner part is smaller than that of the heat transfer coefficient of the silicon carbide substrate.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] In a HEMT (High Electron Mobility Transistor) having a nitride semiconductor layer, a silicon carbide (SiC) substrate with good thermal conductivity is used. In a MMIC (Monolithic Microwave Integrated Circuit), transistors and passive elements such as capacitors are provided on a substrate (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By using a silicon carbide substrate, heat generated in a transistor provided on a nitride semiconductor layer can be efficiently released to the back surface of the silicon carbide substrate. However, in an integrated circuit such as a MMIC, passive elements or active elements are provided in a region adjacent to the transistor. Therefore, heat generated in the transistor is conducted to the passive elements or active elements through the silicon carbide substrate. As a result, the temperature of the passive elements or active elements may rise, and desired characteristics may not be obtained.

[0005] The present disclosure has been made in view of the above problems, and an object thereof is to suppress heat generated in a transistor from being conducted to elements.

Means for Solving the Problems

[0006] One embodiment of the present disclosure is a semiconductor device comprising a silicon carbide substrate, a nitride semiconductor layer provided on the upper surface of the silicon carbide substrate, a transistor provided on the nitride semiconductor layer, and an element provided on the silicon carbide substrate, wherein the silicon carbide substrate is provided between the transistor and the element, and at least a portion of the silicon carbide substrate is removed from the lower surface of the silicon carbide substrate, and the internal thermal conductivity is smaller than that of the silicon carbide substrate.

[0007] One embodiment of the present disclosure is a method for manufacturing a semiconductor device, comprising the steps of: forming a transistor on a nitride semiconductor layer provided on the upper surface of a silicon carbide substrate; forming a device on the silicon carbide substrate; forming a mask layer on the lower surface of the silicon carbide substrate having a first opening and a second opening having an area smaller than the area of ​​the first opening; etching the silicon carbide substrate with the mask layer as a mask to simultaneously form a via hole defined by the first opening that penetrates the silicon carbide substrate and the nitride semiconductor layer, and a hole defined by the second opening that removes a portion of the silicon carbide substrate and does not penetrate the silicon carbide substrate and the nitride semiconductor layer, and whose internal thermal conductivity is smaller than that of the silicon carbide substrate; and forming a metal layer on the lower surface of the silicon carbide substrate that is electrically connected to the transistor via the via hole. [Effects of the Invention]

[0008] According to this disclosure, it is possible to suppress the conduction of heat generated in the transistor to the element. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a plan view of the semiconductor device according to Example 1. [Figure 2] Figure 2 is a cross-sectional view of AA in Figure 1. [Figure 3A] Figure 3A is a cross-sectional view showing a method for manufacturing a semiconductor device according to Example 1. [Figure 3B]Figure 3B is a cross-sectional view showing a method for manufacturing a semiconductor device according to Example 1. [Figure 3C] Figure 3C is a cross-sectional view showing a method for manufacturing a semiconductor device according to Example 1. [Figure 4A] Figure 4A is a cross-sectional view showing a method for manufacturing a semiconductor device according to Example 1. [Figure 4B] Figure 4B is a cross-sectional view showing a method for manufacturing a semiconductor device according to Example 1. [Figure 4C] Figure 4C is a cross-sectional view showing a method for manufacturing a semiconductor device according to Example 1. [Figure 5] Figure 5 is a cross-sectional view of the semiconductor device according to Comparative Example 1. [Figure 6] Figure 6 is a cross-sectional view of the semiconductor device according to Example 1. [Figure 7] Figure 7 is a cross-sectional view showing an example in which a semiconductor chip is mounted on a substrate in Example 1. [Figure 8] Figure 8 is a cross-sectional view showing another example in which a semiconductor chip is mounted on a substrate in Example 1. [Figure 9] Figure 9 is a cross-sectional view showing another example of the inside of the hole in Example 1. [Figure 10] Figure 10 is an enlarged plan view of the area near the heat conduction suppression region in Example 1. [Figure 11] Figure 11 is a plan view of the semiconductor device according to Example 2. [Figure 12] Figure 12 is a cross-sectional view of AA in Figure 11. [Figure 13] Figure 13 is a plan view of a semiconductor device according to a modified example 1 of Example 2. [Figure 14] Figure 14 is a plan view of the semiconductor device according to Example 3. [Modes for carrying out the invention]

[0010] [Details of the embodiments of this disclosure] First, the contents of the embodiments of this disclosure will be listed and explained. (1) One embodiment of the present disclosure includes a silicon carbide substrate, a nitride semiconductor layer provided on the upper surface of the silicon carbide substrate, a transistor provided on the nitride semiconductor layer, and an element provided on the silicon carbide substrate. The silicon carbide substrate is provided between the transistor and the element, and at least a part of the silicon carbide substrate is removed from the lower surface of the silicon carbide substrate, and the semiconductor device has a hole with an internal thermal conductivity smaller than that of the silicon carbide substrate. Thereby, heat generated in the transistor can be suppressed from being conducted to the element. (2) In the above (1), a metal layer is provided on the back surface of the silicon carbide substrate and is electrically connected to the transistor through a via hole penetrating the silicon carbide substrate and the nitride semiconductor layer. (3) In the above (1), the hole is provided from the lower surface of the silicon carbide substrate to the middle of the silicon carbide substrate and does not penetrate the silicon carbide substrate and the nitride semiconductor layer. (4) In the above (3), a metal layer is provided that is electrically connected to the transistor through a via hole penetrating the silicon carbide substrate and the nitride semiconductor layer, and the planar area of the hole on the back surface of the silicon carbide substrate is smaller than the planar area of the via hole on the back surface of the silicon carbide substrate. (5) In the above (2), the hole penetrates the silicon carbide substrate and the nitride semiconductor layer, and the semiconductor device includes a pad provided on the silicon carbide substrate, overlapping the hole and contacting the hole when viewed from the thickness direction of the silicon carbide substrate. (6) In the above (5), the pad is electrically separated from the metal layer. (7) In any of the above (1) to (6), at least a part of the inside of the hole is a cavity. (8) In any of the above (1) to (7), on the surface of the nitride semiconductor layer, all straight lines of the shortest distance from each point of the transistor to the element pass through the range projected by the hole onto the surface. (9) In any of the above (1) to (8), the element is a passive element. (10) In any of (1) to (8) above, the element is an active element. (11) One embodiment of the present disclosure is a method for manufacturing a semiconductor device, comprising the steps of: forming a transistor on a nitride semiconductor layer provided on the upper surface of a silicon carbide substrate; forming a mask layer on the lower surface of the silicon carbide substrate having a first opening and a second opening having an area smaller than the area of ​​the first opening; etching the silicon carbide substrate with the mask layer as a mask to simultaneously form a via hole defined by the first opening and penetrating the silicon carbide substrate and the nitride semiconductor layer, and a hole defined by the second opening that removes a portion of the silicon carbide substrate and does not penetrate the silicon carbide substrate and the nitride semiconductor layer, and whose internal thermal conductivity is smaller than that of the silicon carbide substrate; and forming a metal layer on the lower surface of the silicon carbide substrate that is electrically connected to the transistor via the via hole.

[0011] Specific examples of semiconductor devices and methods for manufacturing the same according to embodiments of this disclosure will be described below with reference to the drawings. However, this disclosure is not limited to these examples, and all modifications within the meaning and scope of the claims are intended to be included.

[0012] [Example 1] Figure 1 is a plan view of a semiconductor device according to Embodiment 1. Figure 2 is a cross-sectional view AA of Figure 1. The normal direction to the surface of the substrate 10 is the Z direction, the arrangement direction of the source electrode 12, gate electrode 14, and drain electrode is the X direction, and the extension direction of the source electrode, gate electrode, and drain electrode is the Y direction. In plan views such as Figure 1, the source electrode 12, drain electrode 16, source pad 22, drain busbar 26, and drain wiring 27 are shown with cross-hatching.

[0013] As shown in Figures 1 and 2, in the semiconductor device 100 of Example 1, an FET (Field Effect Transistor) 20 and a capacitor 30 are provided on the substrate 10.

[0014] The substrate 10 comprises a substrate 10a and a semiconductor layer 10b provided on the substrate 10a. 10a The substrate is a single-crystal silicon carbide substrate, and the semiconductor layer is a single-crystal nitride semiconductor layer. 10b The substrate 10 has an active region 11. The region other than the active region 11 is an inactive region 13 in which the semiconductor layer 10b has been deactivated by ion implantation or the like. In other words, the active region 11 is the region in the substrate 10 in which the semiconductor layer 10b has been activated, and the inactive region 13 This is a region where the semiconductor layer 10b is deactivated. The FET 20 is located in the active region 11. The capacitor 30 is located in the inactive region 13.

[0015] In the FET 20, a source electrode 12 (source finger), a gate electrode 14 (gate finger), and a drain electrode 16 (drain finger) are provided extending in the Y direction on the active region 11 on the surface 60 of the substrate 10. The planar shape of the source electrode 12, gate electrode 14, and drain electrode 16 is approximately rectangular, with the longer side of the rectangle extending in the Y direction. The source electrode 12, gate electrode 14, and drain electrode 16 are arranged in the X direction.

[0016] Source electrodes 12 and drain electrodes 16 are arranged alternately in the X direction. A gate electrode 14 is sandwiched between one source electrode 12 and one drain electrode 16. The source electrode 12 and drain electrode 16 sandwiching the gate electrode 14 form a single unit FET. Adjacent unit FETs share either a source electrode 12 or a drain electrode 16. Multiple unit FETs are arranged in the X direction. In Figure 1, there are three unit FETs, but the number of unit FETs can be set as appropriate.

[0017] A source pad 22, a gate busbar 24, and a drain busbar 26 are provided on the inactive region 13 of the substrate 10. The gate busbar 24 and drain busbar 26 extend in the X direction. The +Y ends of the multiple gate electrodes 14 in the Y direction are connected to the gate busbar 24. The gate busbar 24 and the source electrodes 12 intersect at a distance from each other and are electrically isolated. The -Y ends of the multiple drain electrodes 16 in the Y direction are connected to the drain busbar 26. Gate wiring 25 is connected to the gate busbar 24. Drain wiring 27 is connected to the drain busbar 26.

[0018] The source electrode 12, drain electrode 16, source pad 22, and drain busbar 26 each comprise an ohmic metal layer 18a and a low-resistance layer 18b provided on the semiconductor layer 10b. The ohmic metal layer 18a makes ohmic contact with the semiconductor layer 10b. The material of the low-resistance layer 18b has a lower resistivity than the material of the ohmic metal layer 18a. The low-resistance layer 18b is thicker than the ohmic metal layer 18a. As a result, the sheet resistance of the low-resistance layer 18b is lower than the sheet resistance of the ohmic metal layer 18a.

[0019] An insulating layer 38 is provided on the inactive region 13 of the substrate 10, and a capacitor 30 is provided on the insulating layer 38. The capacitor 30 is a MIM (Metal Insulator Metal) capacitor and comprises a lower electrode 32 provided on the insulating layer 38, a dielectric layer 34 provided on the lower electrode 32, and an upper electrode 36 provided on the dielectric layer 34.

[0020] Sourcepad 22A via hole 23 is provided below the substrate 10, penetrating from the back surface 62 to the front surface 60. A heat conduction suppression region 40 is provided in the inactive region 13 between the transistor 20 and the capacitor 30. The heat conduction suppression region 40 is provided with a hole 42 that reaches from the back surface 62 of the substrate 10 to at least a part of the substrate 10. The hole 42 does not penetrate the substrate 10. A metal layer 28 is provided on the back surface 62 of the substrate 10. A reference potential, such as ground potential, is supplied to the metal layer 28. A metal layer 28a is provided on the side and top (i.e., bottom) surfaces of the via hole 23 and hole 42. The metal layer 28a is the same metal layer as the metal layer 28 and is formed at the same time. A cavity 43 is provided in the metal layer 28a within the via hole 23 and hole 42. The cavity 43 is filled with a gas such as air. The area of ​​the region where hole 42 is projected onto the surface 60 of the substrate 10 is smaller than the area where via hole 23 is projected onto the surface 60 of the substrate 10. The planar shape of the via hole 23 and hole 42 may be, for example, circular, elliptical, oblong, rounded rectangle, track shape or Polygon It is the shape.

[0021] The substrate 10a is a single-crystal silicon carbide substrate having a hexagonal crystal structure such as 4H or 6H. The semiconductor layer 10b includes one or more nitride semiconductor layers such as gallium nitride (GaN), aluminum gallium nitride (AlGaN), or indium gallium nitride (InGaN). If the transistor 20 is a GaN HEMT, the semiconductor layer 10b includes a GaN electron transport layer and an AlGaN barrier layer provided on the GaN electron transport layer. The ohmic metal layer 18a is, for example, an adhesion film (e.g., a titanium film) provided on the substrate 10 and an aluminum film provided on the adhesion film. The low-resistance layer 18b is, for example, a gold layer. The gate electrode 14 is, for example, an adhesion film (e.g., a nickel film) provided on the substrate 10 and a gold film provided on the adhesion film. The lower electrode 32 and upper electrode 36 are, for example, metal films such as gold films, and the dielectric layer 34 and insulating layer 38 are, for example, silicon nitride films or silicon oxide films. The metal layers 28 and 28a are, for example, gold layers.

[0022] The length of the gate electrode 14 in the X direction is the gate length, for example, from 0.05 μm to 5 μm. The width of the active region 11 in the Y direction is the gate width of the unit FET, for example, from 50 μm to 1000 μm. The width of the via hole 23 is for example, 50 μm, and the width of the hole 42 is for example, 25 μm. The width of the transistor 20 and the capacitor 30 in the X direction is for example, 100 μm. The thickness T1 of the substrate 10a is for example, from 10 μm to 200 μm, and is 50 μm as an example. The thickness T2 of the semiconductor layer 10b is smaller than the thickness T1 of the substrate 10a, for example, from 1 μm to 10 μm. The thickness T2 of the semiconductor layer 10b is for example, 1 / 5 or less of the thickness T1 of the substrate 10a.

[0023] [Manufacturing method of Example 1] Figures 3A to 4C are cross-sectional views showing a method for manufacturing a semiconductor device according to Embodiment 1. Figures 3B to 4C are inverted. A transistor 20 and a capacitor 30 are formed on a substrate 10. As shown in Figure 3B, the substrate 10a is thinned by grinding or polishing the lower surface (upper surface in Figures 3B to 4C). As shown in Figure 3C, a mask layer 44 having openings 45a and 45b is formed on the substrate 10a. The mask layer 44 is a metal layer, such as a nickel layer or a nickel-chromium alloy layer. The opening area of ​​opening 45b is smaller than the opening area of ​​opening 45a.

[0024] As shown in Figure 4A, the substrate 10 is etched using the mask layer 44 as a mask. By appropriately selecting the etching conditions for the substrate 10, the etching rate of the substrate 10 at the smaller opening 45b can be made smaller than the etching rate of the substrate 10 at the opening 45a. As a result, a via hole 23 that penetrates the substrate 10 can be formed at the opening 45a as shown by arrow 50a, and a hole 42 that does not penetrate the substrate 10 can be formed at the opening 45b as shown by arrow 50b.

[0025] For etching the substrate 10, for example, reactive ion etching (RIE), inductively coupled plasma (ICP) etching, or electron cyclotron resonance (ECR) etching can be used. As the etching gas, fluorine-based gases such as SF6 or CF4 can be used. When using the ICP etching method, the vacuum level is, for example, 0.1 Pa to 10 Pa. The power for plasma formation is, for example, 100 W to 3000 W, and the bias power is, for example, 10 W to 1000 W. As an example, when the diameters of apertures 45a and 45b are 50 μm and 25 μm, respectively, the etching rate of the silicon carbide substrate 10a at aperture 45b can be made approximately 80% of the etching rate of the silicon carbide substrate at aperture 45a.

[0026] As shown in Figure 4B, the mask layer 44 is removed. If the mask layer 44 is, for example, a nickel layer or a nickel-chromium layer, the mask layer 44 is removed using a hydrochloric acid solution. As shown in Figure 4C, a metal layer 28 is formed on the back surface 62 of the substrate 10, and a metal layer 28a is formed on the side and bottom surfaces of the via hole 23 and the side and bottom surfaces of the hole 42. For the formation of the metal layers 28 and 28a, for example, a plating method is used. The semiconductor device according to Example 1 is manufactured as described above.

[0027] [Comparative Example 1] Figure 5 is a cross-sectional view of a semiconductor device according to Comparative Example 1. As shown in Figure 5, in Comparative Example 1, a heat conduction suppression region 40 is not provided between the transistor 20 and the capacitor 30. The thermal conductivity of the substrate 10a, which is a hexagonal single-crystal silicon carbide such as 4H and 6H, is 490 W / (m·K). The thermal conductivity of the semiconductor layer 10b, which is a single-crystal GaN, is 130 W / (m·K). Thus, when the substrate 10a is made of silicon carbide with high thermal conductivity, the heat generated in the transistor 20 is efficiently conducted to the back surface 62 of the substrate 10 and dissipated from the metal layer 28. For example, when the substrate 10a is made of silicon, the thermal conductivity of silicon is 150 W / (m·K). By making the substrate 10a a silicon carbide substrate, heat dissipation can be improved compared to when the substrate 10a is made of silicon.

[0028] When substrate 10a is a silicon carbide substrate and semiconductor layer 10b is a nitride semiconductor, the thermal conductivity of substrate 10a is approximately three times that of semiconductor layer 10b. In this case, as shown by arrow 52, ​​little of the heat generated in transistor 20 reaches capacitor 30 via semiconductor layer 10b. However, as shown by arrow 53, heat reaches capacitor 30 from transistor 20 via substrate 10a. This causes the temperature of capacitor 30 to rise. Capacitor 30 is designed to achieve desired performance and lifespan at a desired temperature. When capacitor 30 is affected by the heat generated in transistor 20, the characteristics of capacitor 30 deviate from the designed characteristics.

[0029] [Example 1] Figure 6 is a cross-sectional view of a semiconductor device according to Embodiment 1. As shown in Figure 6, in Embodiment 1, a semiconductor layer 10b (nitride semiconductor layer) is provided on a substrate 10a (silicon carbide substrate). A transistor 20 is provided on an activated region 11 of the semiconductor layer 10b. A capacitor 30 (element) is provided on the substrate 10. The substrate 10a has a hole 42 in an inactive region 13 between the transistor 20 and the capacitor 30. At least a portion of the substrate 10a is removed from the back surface 62 of the substrate 10a at the hole 42. The thermal conductivity inside the hole 42 (e.g., cavity 43) is smaller than the thermal conductivity of the substrate 10a. By providing a hole 42 with an internal thermal conductivity smaller than the thermal conductivity of the substrate 10a, heat conduction from the transistor 20 to the capacitor 30 via the substrate 10a, as shown by the dotted arrow 53a, can be suppressed. Therefore, the capacitor 30 is less affected by the heat generated in the transistor 20, and the characteristics of the capacitor 30 are less likely to deviate from the designed characteristics.

[0030] Figure 7 is a cross-sectional view showing an example of a semiconductor chip mounted on a mounting substrate in Example 1. As shown in Figure 7, the semiconductor device 100 of Example 1 is mounted on the mounting substrate 37a using solder 37. The via holes 23 and holes 42 are cavities 43. The thermal conductivity of air is 0.026 W / (m·K), which is less than 1 / 1000 of the thermal conductivity of silicon carbide. In this way, by making at least a part of the inside of the holes 42 a cavity 43, heat conduction from the transistor 20 to the capacitor 30 can be suppressed.

[0031] Figure 8 is a cross-sectional view showing another example in which a semiconductor chip is mounted on a substrate in Example 1. As shown in Figure 8, the via holes 23 and 42 are filled with solder 37. The thermal conductivity of solder 37 is lower than that of silicon carbide. For example, the thermal conductivity of tin-silver-copper solder is 55 W / (m·K). Therefore, even when the cavity 43 in the hole 42 is filled with solder 37, the hole 42 can suppress heat conduction from the transistor 20 to the capacitor 30.

[0032] Figure 9 is a cross-sectional view showing another example of the inside of a hole in Example 1. As shown in Figure 9, the filler material 39 is filled into the hole 42 so as not to form any voids. Even with this structure of hole 42, if the thermal conductivity of the filler material 39 is lower than the thermal conductivity of the substrate 10a, the hole 42 can suppress heat conduction from the transistor 20 to the capacitor 30. The filler material 39 is, for example, a resin. Resins generally have low thermal conductivity; for example, the thermal conductivity of epoxy resin is 0.3 W / (m·K). The thermal conductivity of the filler material 39 is made lower than the thermal conductivity of the solder 37 in Figure 7. This prevents the solder 37 from entering the hole 42 when the semiconductor device 100 is mounted on the mounting substrate 37a, thereby suppressing heat conduction from the transistor 20 to the capacitor 30. The thermal conductivity of the filler material 39 is, for example, 1 / 100 or less, and 1 / 1000 or less, of the thermal conductivity of the substrate.

[0033] Figure 10 is an enlarged plan view of the area near the heat conduction suppression region in Example 1. As shown in Figure 10, the region that generates heat in the transistor 20 is the active region 11, and the active region 11 corresponds to the region where the transistor 20 is located. On the surface 60, the range from the transistor 20 to the capacitor 30 is range 54. As shown by arrow 56, on the surface 60, the shortest straight line (arrow 56) from each point of the transistor 20 to the capacitor 30 all pass through the area where the hole 42 is projected onto the surface 60. As a result, for example, when heat tries to conduct from the active region 11 to the capacitor 30, as shown by arrow 56a, it will bypass the hole 42, as shown by arrow 57. Therefore, the distance over which heat is conducted from the transistor 20 to the capacitor 30 is substantially increased. Thus, heat conduction from the transistor 20 to the capacitor 30 can be suppressed.

[0034] If the hole 42 penetrates the substrate 10, the metal layer 28a will be exposed to the surface 60 of the semiconductor layer 10b. The potential of the metal layer 28a may affect the transistor 20 or capacitor 30 (for example, by electromagnetic field coupling). In Embodiment 1, the hole 42 is provided from the back surface 62 of the substrate 10a to partway across the substrate 10a, and does not penetrate the substrate 10a or the semiconductor layer 10b. This suppresses the influence of the potential of the metal layer 28a, etc., on the surface 60 of the semiconductor layer 10b.

[0035] From the viewpoint of suppressing heat conduction through the substrate 10a, the depth D1 of the hole 42 is at least 0.5 times and at least 0.8 times the thickness T1 of the substrate 10a. When the distance L1 between the transistor 20 and the capacitor 30 is long, heat conduction from the transistor 20 to the capacitor 30 is small. When the distance L1 is short, heat conduction from the transistor 20 to the capacitor 30 tends to become a problem. From this viewpoint, the distance L1 is, for example, 5 times or less the thickness T1 of the substrate 10a.

[0036] The metal layer 28 is provided on the back surface 62 of the substrate 10a and is electrically connected to the source electrode 12 (electrode) of the transistor 20 via a via hole 23 that penetrates the substrate 10a and the semiconductor layer 10b. As a result, by supplying a reference potential such as ground potential to the metal layer 28, a reference potential can be supplied to the source electrode 12 and source inductance can be suppressed.

[0037] If the via holes 23 and holes 42 are formed using separate processes, the manufacturing process will increase. Therefore, as shown in Figure 3C, a mask layer 44 is formed on the substrate 10, having a first opening 45a and a second opening 45b having a smaller area than the first opening 45a. As shown in Figure 4A, the substrate 10a is etched using the mask layer 44 as a mask. This simultaneously forms the via holes 23 defined by the first opening 45a that penetrate the substrate 10a and the semiconductor layer 10b, and the holes 42 defined by the second opening 45b that remove a portion of the substrate 10a and do not penetrate the substrate 10a and the semiconductor layer 10b. This makes it possible to simultaneously form via holes 23 and holes 42 that do not penetrate the substrate 10.

[0038] As in Example 1, when via holes 23 and holes 42 are formed, the planar area of ​​the holes 42 on the back surface 62 of the substrate 10a is smaller than the planar area of ​​the via holes 23 on the back surface 62. The planar area of ​​the holes 42 on the back surface 62 is less than or equal to half the planar area of ​​the via holes 23 on the back surface 62, and less than or equal to quarter the planar area of ​​the via holes 23 on the back surface 62. If the planar area of ​​the holes 42 is too small, the depth D1 of the holes 42 will become small. Therefore, the planar area of ​​the holes 42 on the back surface 62 is 1 / 50 or more the planar area of ​​the via holes 23 on the back surface 62.

[0039] [Example 2] Figure 11 is a plan view of the semiconductor device according to Embodiment 2. Figure 12 is a cross-sectional view AA of Figure 11. As shown in Figures 11 and 12, in the semiconductor device 102 of Embodiment 2, the hole 42 penetrates the substrate 10a and the semiconductor layer 10b. A pad 41 that contacts the hole 42 is provided on the surface 60 of the semiconductor layer 10b. The pad 41 is, for example, an ohmic metal layer 18a, a low-resistance layer 18b, or a laminated film of an ohmic metal layer 18a and a low-resistance layer 18b. A metal layer 28b is provided on the side and top surfaces of the hole 42. The metal layer 28 and the metal layer 28b provided on the back surface 62 of the substrate 10a are electrically separated by a separation portion 47.

[0040] The etching selectivity ratio between silicon carbide and nitride semiconductor is small. Therefore, in Figure 4A, when forming the hole 42, it is difficult to make the nitride semiconductor layer 10b function as an etching stopper layer for the substrate 10a. To address this, a pad 41 is provided that overlaps with the hole 42 when viewed from the Z direction (thickness direction of the substrate 10a). The material of the pad 41 is a material with a high etching selectivity ratio to both silicon carbide and nitride semiconductor layers (for example, a metal such as gold). This allows for over-etching when forming the hole 42, enabling the hole 42 to penetrate the substrate 10. The hole 42 is in contact with the pad 41. The other configurations are the same as in Example 1 and are therefore omitted from the description.

[0041] If the pad 41 is electrically connected to the metal layer 28, the pad 41 will, for example, become a reference potential and electromagnetically couple with the transistor 20 and capacitor 30. This causes the pad 41 to affect the transistor 20 and capacitor 30. For example, the parasitic capacitance of the transistor 20 and capacitor will increase. Therefore, the pad 41 is electrically isolated from the metal layer 28. The potential of the pad 41 is floating and it is not electrically connected to any electrode of the transistor 20 or capacitor 30. This suppresses interference between the pad 41 and the transistor 20 and capacitor 30.

[0042] [Modification 1 of Example 2] Figure 13 is a plan view of a semiconductor device according to Modification 1 of Example 2. As shown in Figure 13, in the semiconductor device 104 of Modification 1 of Example 2, the planar area of ​​the hole 42 is larger than the planar area of ​​the via hole 23. When the planar area of ​​the hole 42 is larger than the planar area of ​​the via hole 23, in Figure 4A, the hole 42 penetrates the substrate 10a and the semiconductor layer 10b. By providing the pad 41, etching is stopped by the pad 41. In addition, by providing the spacing portion 47 (see Figure 12), interference of the pad 41 with the transistor 20 and capacitor 30 can be suppressed. On the surface 60, the hole 42 crosses the range viewed from the active region 11 to the capacitor 30. This further suppresses heat conduction from the transistor 20 to the capacitor 30. The other configurations are the same as in Example 2 and will not be described.

[0043] [Example 3] Figure 14 is a plan view of the semiconductor device according to Embodiment 3. As shown in Figure 14, the semiconductor device 106 of Embodiment 3 is provided with a transistor 20a instead of a capacitor 30. A heat conduction suppression region 40 is provided between the transistor 20 and 20a. The other configurations are the same as in Embodiment 1 and will not be described further.

[0044] As in Examples 1 and 2 and their variations, the element sandwiching the thermal conduction suppression region 40 with the transistor 20 may be a passive element such as a capacitor 30, a resistor, or an inductor. As in Example 3, the element sandwiching the thermal conduction suppression region 40 with the transistor 20 may be an active element such as a transistor 20a or a diode.

[0045] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of this disclosure is indicated by the claims, not in the sense described above, and all modifications are intended to be in the sense and scope equivalent to the claims. [Explanation of symbols]

[0046] 10, 10a substrate 10b Semiconductor layer 11 Active area 12 Source electrodes 13 Inactive region 14 Guard gate 16 Drain electrode 18a Ohmic metal layer 18b Low resistance layer 20, 20a transistor 22 Sourcepad 23 Viaholes 24 Gate Bus Bar 25 Gate Wiring 26 Drain Busbar 27 Drain wiring 28, 28a, 28b metal layer 30 Capacitors 32 Lower electrode 34 Dielectric layer 36 Upper electrode 37 Handa 37a Mounted board 38 Insulating layer 39 Filler 40 Heat conduction suppression region 41 pads 42 holes 43 Cavity 44 mask layers 45a, 45b opening 47 Separation part 52, 53, 53a, 56, 56a, 57 Arrows 54 range 60 surface 62 Back side 100, 102, 104, 106 Semiconductor equipment

Claims

1. silicon carbide substrate and A nitride semiconductor layer having an activation region is provided on the upper surface of the silicon carbide substrate, A transistor provided on the nitride semiconductor layer and located within the activation region, The element provided on the silicon carbide substrate, A metal layer electrically connected to the transistor via a via hole penetrating the silicon carbide substrate and the nitride semiconductor layer, Equipped with, The silicon carbide substrate is provided between the transistor and the element, and at least a portion of the silicon carbide substrate is removed from the lower surface of the silicon carbide substrate, and has holes in which the internal thermal conductivity is less than that of the silicon carbide substrate. The aforementioned hole penetrates the silicon carbide substrate and the nitride semiconductor layer, The silicon carbide substrate has a pad that is provided on the silicon carbide substrate, and which overlaps with the hole and contacts the hole when viewed from the thickness direction of the silicon carbide substrate, A semiconductor device in which the pad is electrically isolated from the metal layer.

2. A silicon carbide substrate and A nitride semiconductor layer having an activation region is provided on the upper surface of the silicon carbide substrate, A transistor provided on the nitride semiconductor layer and located within the activation region, The element provided on the silicon carbide substrate, Equipped with, The silicon carbide substrate is provided between the transistor and the element, and at least a portion of the silicon carbide substrate is removed from the lower surface of the silicon carbide substrate, and has holes in which the internal thermal conductivity is less than that of the silicon carbide substrate. The aforementioned hole is provided from the lower surface of the silicon carbide substrate to partway through the silicon carbide substrate, and does not penetrate the silicon carbide substrate and the nitride semiconductor layer. The silicon carbide substrate and the nitride semiconductor layer are electrically connected to the transistor via a via hole that penetrates the silicon carbide substrate and the nitride semiconductor layer, A semiconductor device in which the planar area of ​​the holes on the lower surface of the silicon carbide substrate is smaller than the planar area of ​​the via holes on the lower surface of the silicon carbide substrate.

3. The semiconductor device according to claim 1 or claim 2, wherein at least a portion of the inside of the hole is hollow.

4. The semiconductor device according to claim 1 or claim 2, wherein, on the surface of the nitride semiconductor layer, the shortest straight line from each point of the transistor to the element all passes through the area obtained by projecting the hole onto the surface.

5. The semiconductor device according to claim 1 or claim 2, wherein the element is a passive element.

6. The semiconductor device according to claim 1 or claim 2, wherein the element is an active element.

7. A process of forming a transistor on a nitride semiconductor layer provided on the upper surface of a silicon carbide substrate, and forming an element on the silicon carbide substrate, A step of forming a mask layer on the lower surface of the silicon carbide substrate, having a first opening and a second opening having an area smaller than the area of ​​the first opening, The process involves etching the silicon carbide substrate with the mask layer as a mask, thereby simultaneously forming a via hole defined by the first opening and penetrating the silicon carbide substrate and the nitride semiconductor layer, and forming a hole defined by the second opening, where a portion of the silicon carbide substrate is removed and the hole does not penetrate the silicon carbide substrate and the nitride semiconductor layer, and the internal thermal conductivity is less than that of the silicon carbide substrate. A step of forming a metal layer on the lower surface of the silicon carbide substrate that is electrically connected to the transistor via the via hole, A method for manufacturing a semiconductor device containing [a specific component].

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