Solar cells and methods for manufacturing the same

Abstract

To provide a solar battery and a method for manufacturing the same.SOLUTION: A solar battery comprises: a silicon substrate including a first surface and a second surface which are opposite to each other; a first doping layer provided in the first surface; a second doping layer which is provided in the second surface, and which has a doping type opposite to that of the first doping layer; a first electrode connected to the first doping layer; a second electrode connected to the second doping layer; and a separation groove which penetrates through the first doping layer along a thickness direction of the silicon substrate, and surrounds the first electrode. The solar battery of the present invention avoids a power leakage due to a short circuit by separating each edge of an electrode and a battery by using the separation groove penetrating through the first doping layer.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] This application mainly relates to the technical field of photovoltaic power generation, and particularly relates to a solar cell and a manufacturing method thereof.

Background Art

[0002] Among many technologies that utilize solar energy, solar cells have attracted attention because they can convert solar energy into electrical energy. When a solar cell is irradiated with light, electron-hole pairs are generated. The electron-hole pairs are separated inside the cell and move to both electrodes of the cell respectively. With the development of solar cell technology, more and more types of solar cells have been developed. Currently, the types of solar cells mainly include Passivated Emitter and Rear Contact (PERC), Tunnel Oxide Passivated Contact (TOPCON), Hetero-Junction with Intrinsic Thin Film (HIT), and Interdigitated Back Contact (IBC) technology, etc. In the production process of solar cells, due to factors such as the manufacturing process and production environment, solar cells may generate a short-circuit current during operation, for example, a short-circuit current caused by an unwanted contact between an electrode and a partial functional layer of the solar cell. The short-circuit current leads to a decrease in the efficiency of the solar cell, and it should be avoided to generate a short-circuit current inside the solar cell.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The technical problem to be solved in this application is to provide a solar cell and a manufacturing method thereof that can avoid the leakage of the solar cell due to short circuit.

Means for Solving the Problems

[0004] The technology used in this application to solve the above-mentioned technical problems is a solar cell comprising: a silicon substrate having opposing first and second surfaces; a first doping layer provided on the first surface; a second doping layer provided on the second surface, the doping type of which is opposite to that of the first doping layer; a first electrode connected to the first doping layer; a second electrode connected to the second doping layer; and a separation groove that penetrates the first doping layer along the thickness direction of the silicon substrate and surrounds the first electrode.

[0005] In one embodiment of the present invention, the distance between the separation groove and the edge of the first doping layer is smaller than a preset distance, and the preset distance is 10 μm to 2000 μm.

[0006] In one embodiment of the present invention, a tunnel layer is further provided, the tunnel layer being provided on the second surface, and the second doping layer being provided on the surface of the tunnel layer that is separated from the silicon substrate.

[0007] In one embodiment of the present invention, the tunnel layer extends to the side surface of the silicon substrate and covers at least a portion of the side surface of the silicon substrate, the second doping layer covers the surface of the tunnel layer that is away from the silicon substrate, and the height of the tunnel layer located on the side surface of the silicon substrate is 0.1 μm or more and less than or equal to the thickness of the silicon substrate.

[0008] In one embodiment of the present invention, a first passivation layer is further provided, which is disposed on the surface of the first doping layer away from the silicon substrate.

[0009] In one embodiment of the present invention, the first passivation layer covers the bottom and side walls of the separation groove.

[0010] In one embodiment of the present application, a second passivation layer is further provided, which is disposed on the surface of the second doping layer away from the silicon substrate.

[0011] To solve the above-mentioned technical problems, this application further proposes a method for manufacturing a solar cell, comprising the steps of: providing a silicon substrate having opposing first and second surfaces; forming a first doping layer on the first surface of the silicon substrate; sequentially forming a tunnel layer and a second doping layer on the second surface of the silicon substrate, wherein the doping type of the first doping layer is opposite to that of the second doping layer; forming a first electrode connected to the first doping layer; forming a second electrode connected to the second doping layer; and forming a separation groove that penetrates the first doping layer along the thickness direction of the silicon substrate and surrounds the first electrode.

[0012] In one embodiment of the present application, a method for forming the tunnel layer and the second doping layer comprises forming an initial tunnel layer on the second surface, the side surface of the silicon substrate, and at least a portion of the surface of the first doping layer that is away from the silicon substrate; forming an initial second doping layer on the surface of the initial tunnel layer that is away from the silicon substrate; and removing the initial tunnel layer and the initial second doping layer on the first doping layer to form the tunnel layer and the second doping layer.

[0013] In one embodiment of the present invention, the separation groove is formed after the step of forming the initial tunnel layer and the initial second doping layer, and before the step of removing the initial tunnel layer and the initial second doping layer from the first doping layer.

[0014] In one embodiment of the present invention, a portion of the initial tunnel layer and the initial second doping layer on the side surface of the silicon substrate is further removed so that the height of the tunnel layer and the second doping layer located on the side surface of the silicon substrate is 0.1 μm or more and less than or equal to the thickness of the silicon substrate.

[0015] In one embodiment of the present invention, the distance between the separation groove and the edge of the first doping layer is smaller than a preset distance, and the preset distance is 10 μm to 2000 μm.

[0016] In one embodiment of the present invention, a first passivation layer is formed on the surface of the first doping layer that is separated from the silicon substrate.

[0017] In one embodiment of the present invention, the first passivation layer is formed after the step of forming the separation groove.

[0018] In one embodiment of the present invention, a second passivation layer is formed on the surface of the second doping layer that is separated from the silicon substrate.

[0019] In one embodiment of the present invention, the separation groove is formed after the step of forming the second passivation layer.

[0020] The solar cell and its manufacturing method of the present invention avoid leakage current from the solar cell due to short circuits by separating the electrode and the edge of the battery using a separation groove that penetrates the first doping layer.

[0021] To make the above-mentioned objectives, features, and advantages of this application clearer and easier to understand, specific embodiments of this application will be described in detail below with reference to the attached drawings. [Brief explanation of the drawing]

[0022] [Figure 1] This is a schematic plan view of a solar cell according to one embodiment of the present invention. [Figure 2] This is a schematic cross-sectional view of the solar cell along line AA in Figure 1 of one embodiment. [Figure 3] This is a schematic cross-sectional view of the solar cell along line AA in Figure 1 of another embodiment. [Figure 4] This is an illustrative flowchart of a method for manufacturing a solar cell according to one embodiment of the present invention. [Figure 5] This is a schematic cross-sectional view of an intermediate product in the manufacturing process of a solar cell in one embodiment. [Figure 6] This is a schematic cross-sectional view of an intermediate product in the manufacturing process of a solar cell in one embodiment. [Figure 7] It is a schematic cross-sectional view of an intermediate product in the manufacturing process of a solar cell in one embodiment. [Figure 8] It is a schematic cross-sectional view of an intermediate product in the manufacturing process of a solar cell in one embodiment. [Figure 9] It is a schematic cross-sectional view of an intermediate product in the manufacturing process of a solar cell in one embodiment. [Figure 10] It is a schematic cross-sectional view of an intermediate product in the manufacturing process of a solar cell in one embodiment. [Figure 11] It is a schematic cross-sectional view of an intermediate product in the manufacturing process of a solar cell in one embodiment. [Figure 12] It is a schematic cross-sectional view of an intermediate product in the manufacturing process of a solar cell in one embodiment. [Figure 13] It is a schematic cross-sectional view of an intermediate product in the manufacturing process of a solar cell in one embodiment. [Figure 14] It is an exemplary flowchart for forming a separation groove in different embodiments. [Figure 15] It is an exemplary flowchart for forming a separation groove in different embodiments.

Embodiments for Carrying Out the Invention

[0023] To make the above objects, features, and advantages of the present application clearer and easier to understand, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0024] In the following description, many specific details will be described in order to fully understand the present application. However, the present application can also be implemented in other ways different from those described in this specification, so the present application is not limited to the specific embodiments disclosed below.

[0025] As set forth in this application and claims, unless the context explicitly suggests an exception, terms such as “one,” “a kind,” and / or “it” do not specifically refer to a singular number and may include plurals. Generally, the terms “equipment” and “includes” only indicate the inclusion of clearly identified steps and elements, and these steps and elements do not constitute an exclusive list; the method or apparatus may include other steps or elements.

[0026] Furthermore, it is necessary to explain that the use of terms such as "first," "second," etc., to limit parts is simply to make it easier to distinguish corresponding parts, and unless otherwise stated, these terms have no special meaning and cannot be understood as limitations on the scope of protection of this application. In addition, while the terms used in this application are selected from publicly known terms, some terms in the specification of this application were selected by the applicant at their own discretion, and their detailed meanings are explained in the relevant parts of this specification. Moreover, it is required to understand this application not only in terms used, but also in the meanings contained within each term.

[0027] This application uses flowcharts to illustrate the operations performed by the system according to the embodiments of this application. It will be understood that the operations described above or below are not necessarily performed in exact order. In contrast, various steps can be performed in reverse order or simultaneously. Simultaneously, other operations can be added to these processes, or some steps or more operations can be removed from these processes.

[0028] Next, the solar cell of the present invention and its manufacturing method will be described with specific examples.

[0029] Figure 1 is a schematic plan view of a solar cell according to one embodiment, Figure 2 is a schematic cross-sectional view of the solar cell in Figure 1 according to one embodiment along line AA, and Figure 2 is a diagram in which a part of the first electrode is simply omitted. As shown in Figures 1 and 2, the solar cell comprises a silicon substrate 110, a first doping layer 120, a second doping layer 130, a first electrode 140, a second electrode 150, and a separation groove 160.

[0030] As shown in Figure 2, the silicon substrate 110 has a first surface 111 and a second surface 112 facing each other in its thickness direction D3, and two sides 113 facing each other in the first direction D1. It is understood that the silicon substrate 110 also has two opposing sides in the second direction D2. The first surface 111 and the second surface 112 may have a pyramidal pile morphology that helps reduce reflection of the solar cell to incident light rays.

[0031] The silicon substrate 110 may be a doped single-crystal silicon wafer or a doped polycrystalline silicon wafer, and the doping type may be N-type doping or P-type doping. If the silicon substrate 110 is N-type doped, one or more dopants can be selected from phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As). If the silicon substrate 110 is P-type doped, one or more dopants can be selected from boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0032] The first doping layer 120 is provided on the first surface 111. "Provided" means that the first doping layer 120 is in direct contact with the first surface 111, and other functional layers are provided between the first doping layer 120 and the first surface 111. This explanation also applies to subsequent documents, which will not elaborate further. In Figure 2, the first doping layer 120 is in direct contact with the first surface 111. A method for forming the first doping layer 120 includes doping the silicon substrate 110 to convert a portion of the silicon substrate 110 into the first doping layer 120. In addition to the above method, the first doping layer 120 can also be deposited on the first surface 111 by a deposition process. The first doping layer 120 may be doped single-crystal silicon or doped polycrystalline silicon.

[0033] The second doping layer 130 is provided on the second surface 112. The second doping layer 130 may be doped polycrystalline silicon. When the second doping layer 130 is doped polycrystalline silicon, the method for forming the second doping layer 130 comprises depositing amorphous silicon on the second surface 112, doping the amorphous silicon in this layer, and heat-treating the doped amorphous silicon to convert the amorphous silicon into polycrystalline silicon.

[0034] The doping type of the second doping layer 130 is the opposite of the doping type of the first doping layer 120, while the doping type of the other doping layer is the same as that of the silicon substrate 110. For example, the following cases may occur.

[0035] The silicon substrate 110 is N-type doped, the first doping layer 120 is P-type doped, and the second doping layer 130 is N-type doped. The first doping layer 120, together with the silicon substrate 110, forms a PN junction.

[0036] The silicon substrate 110 is N-type doped, the first doping layer 120 is N-type doped, and the second doping layer 130 is P-type doped. The second doping layer 130, together with the silicon substrate 110, forms a PN junction.

[0037] The silicon substrate 110 is P-type doped, the first doping layer 120 is N-type doped, and the second doping layer 130 is P-type doped. The first doping layer 120, together with the silicon substrate 110, forms a PN junction.

[0038] The silicon substrate 110 is P-type doped, the first doping layer 120 is P-type doped, and the second doping layer 130 is N-type doped. The second doping layer 130, together with the silicon substrate 110, forms a PN junction.

[0039] In the above case, the doping concentration of the first doping layer 120 may be greater than the doping concentration of the silicon substrate 110, and the doping concentration of the second doping layer 130 may be greater than the doping concentration of the silicon substrate 110.

[0040] For the sake of explanation, a solar cell will be described using an N-type doped silicon substrate 110, a P-type doped first doping layer 120, and an N-type doped second doping layer 130 as examples. Here, the doping concentration of the second doping layer 130 is greater than the doping concentration of the silicon substrate 110.

[0041] As shown in Figure 2, the first electrode 140 is connected in contact with the first doping layer 120, and the second electrode 150 is connected in contact with the second doping layer 130. The first electrode 140 and the second electrode 150 can be used to extract electrical energy generated by the solar cell. As shown in Figure 1, the first electrode 140 comprises a plurality of first gate lines 141 and a plurality of second gate lines 142. The plurality of first gate lines 141 are arranged at intervals along a first direction D1, and the plurality of second gate lines 142 are arranged at intervals along a second direction D2. Each second gate line 142 is connected to a plurality of first gate lines 141. The first gate lines 141 can be used to collect the current generated by the solar cell, and the second gate lines 142 can be used to collect the current collected by the plurality of second gate lines 141. The second electrode 150 may have an electrode structure similar to that of the first gate line 141 and the second gate line 142 in the first electrode 140, and further explanation is omitted.

[0042] As shown in Figure 2, the separation groove 160 penetrates the first doping layer 120 in the thickness direction D3. As shown in Figure 1, when viewed from a plan view of the solar cell, the separation groove 160 is a closed rectangle surrounding all of the first electrodes 140. As shown in Figures 1 and 2, the first doping layer 120 is divided into two parts by the separation groove 160. A portion is surrounded by the separation groove 160, while the other portion is not surrounded by the separation groove 160 and is located between the edge 170 of the solar cell and the separation groove 160. For the sake of explanation, the portion of the first doping layer 120 surrounded by the separation groove 160 will be referred to as the internal doping layer 121, and the portion of the first doping layer not surrounded by the separation groove 160 will be referred to as the peripheral doping layer 122. The internal doping layer 121 is connected to the first electrode 140 by contact, and carriers (e.g., holes or electrons) in the internal doping layer 121 can be transmitted to the outside of the solar cell via the first electrode 140. Due to the division of the separation groove 160, the internal doping layer 121 does not come into contact with the peripheral doping layer 122, so there is no electrical connection between the internal doping layer 121 and the peripheral doping layer 122 (and naturally, there is no electrical connection between the peripheral doping layer 122 and the first electrode). If there is a connection between the peripheral doping layer 122 and the second doping layer 130, the separation action of the separation groove 160 prevents the internal doping layer 121 and the second doping layer 130 from being connected, thus avoiding leakage current from the solar cell due to a short circuit.

[0043] The shape of the separation groove 160 is not limited to the rectangle shown in Figure 1. The separation groove 160 may be other shapes surrounding the first electrode 140, such as a circle, an ellipse, or another polygon.

[0044] As shown in Figures 1 and 2, in one embodiment, the first doping layer 120 has an edge 123 that points to the outermost part of the first doping layer 120 in a first direction D1. The edge 123 is a rectangle surrounding the separation groove 160, and the distance between the separation groove 160 and the edge 123 is smaller than a predetermined distance, which is one of the values ​​from 10 μm to 2000 μm, for example, 10 μm, 50 μm, 100 μm, 200 μm, 300 μm, 400 μm, 500 μm, 1000 μm, 1500 μm, or 2000 μm. Specifically, as shown in Figure 1, edge 123 may be divided into four parts: a first edge 123a located on the right, a second edge 123b located below, a third edge 123c located on the left, and a fourth edge 123d located above. Similarly, separation groove 160 may be divided into four parts: a first separation groove 160a located on the right, a second separation groove 160b located below, a third separation groove 160c located on the left, and a fourth separation groove 160d located above. Referring to the partially enlarged schematic diagram of Figure 1, the first separation groove 160a and the first edge 123a are separated by a distance D1 in the second direction D2, the second separation groove 160b and the second edge 123b are separated by a distance d2 in the first direction D1, similarly, the third separation groove 160c and the third edge 123c are separated by a distance d3 in the second direction D2, and the fourth separation groove 160d and the fourth edge 123d are separated by a distance d4 in the first direction D1 (distances d3 and d4 are not shown). Distances d1, d2, d3, and d4 are all smaller than a predetermined distance, and distances d1, d2, d3, and d4 may be the same or different.

[0045] As shown in Figures 1 and 2, the first doping layer 120 forms a PN junction with the silicon substrate 110. When the solar cell is operating, carriers in the internal doping layer 121 are output via the first electrode 140 connected to the internal doping layer 12, while carriers in the peripheral doping layer 122 are not output via the first electrode 140 due to the separation action of the separation groove 160. In short, when the solar cell is operating, the internal doping layer 121 is involved in the output of electrical energy, while the peripheral doping layer 122 is not. To increase the electrical energy from the solar cell, the area of ​​the internal doping layer 121 should be made as large as possible. Reducing the distance between the separation groove 160 and the edge of the first doping layer 120 to a predetermined distance helps to increase the area of ​​the internal doping layer 121.

[0046] In Figure 1, both the separation groove 160 and the edge 123 are rectangular. The separation groove 160 may be divided into multiple segments, for example, by dividing the second separation groove 160b and the fourth separation groove 160d into multiple segments in the first direction D1, and dividing the first separation groove 160a and the third separation groove 160c into multiple segments in the second direction D2. In this case, the minimum distance between each segment and the edge 123 is smaller than a preset distance. In this way, the area of ​​the internal doping layer 121 can be made as large as possible. That is, the distance between the separation groove 160 and the edge 123 is set to maximize the area of ​​the internal doping layer 121 as much as possible, contributing to maximizing the electrical energy from the solar cell.

[0047] Referring to Figure 2, the cross-section of the separation groove 160 is U-shaped, and in other embodiments, the cross-section of the separation groove 160 may be V-shaped. In this application, the depth and width of the separation groove 160 are not limited, but the depth and width must be such that the internal doping layer 121 is electrically isolated from the surrounding doping layer 122. The depth may be any value between 2 μm and 50 μm, and the width may be any value between 5 μm and 60 μm.

[0048] As shown in Figure 2, in one embodiment, the solar cell further comprises a tunnel layer 180. The tunnel layer 180 is provided on the second surface 112, and the second doping layer 130 is provided on the surface away from the silicon substrate 110 in the thickness direction D3 of the tunnel layer 180. The tunnel layer 180 has a tunneling effect. The tunnel layer 180 helps to reduce carrier recombination by allowing the passage of multiple particles (e.g., electrons) and preventing the passage of fewer particles (e.g., holes). In one embodiment, the tunnel layer 180 is a layer of silicon oxide (SiOx) on which polycrystalline silicon doped as a second doping layer 130 can be formed on the surface away from the silicon substrate 110, and the silicon oxide layer and the doped polycrystalline silicon layer can together constitute a passivation structure. Even if fewer particles pass through the silicon oxide layer, they are blocked by the internal electric field due to the difference in doping concentration between the doped polycrystalline silicon layer and the silicon substrate, making it difficult for them to reach the interface where the second electrode and the doped polycrystalline silicon layer come into contact, thus avoiding recombination of multiple particles and fewer particles at the interface.

[0049] Figure 3 is a schematic cross-sectional view of the solar cell of Figure 1 along line AA in another embodiment. The difference between Figure 3 and Figure 2 is that the tunnel layer 180 in Figure 3 extends to the side surface 113 of the silicon substrate 110 and covers a portion of the side surface 113. That is, the tunnel layer 180 is formed on the second surface 112 and a portion of the side surface 113, and the tunnel layer located on the second surface 112 and the tunnel layer located on the side surface 113 are continuous. For the sake of explanation, in Figure 3, the tunnel layer located on the second surface 112 is referred to as the main body 181, and the tunnel layer located on the side surface 113 is referred to as the extension 182. To make it easier to understand what the main body 181 and the extension 182 specifically refer to, the boundary line between them is shown in Figure 3 using the dotted line B.

[0050] Another difference between Figure 3 and Figure 2 is that the second doping layer 130 extends from the main body 181 to the extension 182, the second doping layer 130 covers the surface of the main body 181 away from the silicon substrate 110 in the thickness direction D3, and the extension 182 covers the surface away from the silicon substrate 110 in the first direction D1. For the sake of explanation, the second doping layer located on the main body 181 will be referred to as the main body 131, and the second doping layer located on the extension 182 will be referred to as the extension 132. To make it easier to understand what the main body 131 and the extension 132 specifically refer to, the boundary line between them is shown in Figure 3 using a dotted line B.

[0051] As shown in Figure 3, the extensions 182 and 132 have the same or approximately the same height. The height h1 of both is 0.1 μm or more, and less than or equal to the thickness of the silicon substrate. Note that height h1 refers to the dimension in the thickness direction D3. In Figure 3, the extensions 182 and 132 are formed on a part of the side surface 113. In some other embodiments, the extensions 182 and 132 may be formed on the entire side surface 113, in which case the height h1 is equal to the thickness of the silicon substrate. By extending the tunnel layer 180 and the second doping layer 130 to the side surface 113, the carrier collection area can be increased. On the other hand, the passivation contact area between the passivation structure and the silicon substrate 110 can be increased, and carrier recombination at the edges of the solar cell can be reduced.

[0052] As shown in Figures 1 and 2, the solar cell further comprises a first passivation layer 190. The first passivation layer 190 is provided so as to be away from the surface of the silicon substrate 110 in the thickness direction D3 of the first doping layer 120. In Figure 2, the first passivation layer 190 covers the bottom and side walls of the isolation groove 160. In Figure 3, the first passivation layer 190 does not cover the bottom and side walls of the isolation groove 160. The difference is that in Figure 2, the process step for forming the first passivation layer 190 is after the process step for forming the isolation groove 160, while in Figure 3, the process step for forming the first passivation layer 190 is before the process step for forming the isolation groove 160.

[0053] The first passivation layer 190 has a passivation effect on the solar cell, reducing carrier recombination and helping to improve battery efficiency. The first passivation layer 190 may be an electric field passivation layer having an electric field passivation effect, a chemical passivation layer having a chemical passivation effect, or a laminated passivation structure with a common composition of electric field passivation layer-chemical passivation layer. In some embodiments, the solar cell further comprises a first anti-reflection layer disposed on the surface of the first passivation layer 190 that is separated from the silicon substrate 110. The first anti-reflection layer can reduce the reflection of incident light rays by the solar cell and increase the utilization rate of incident light rays.

[0054] As shown in Figure 3, the first passivation layer 190 extends to the side surface 113 of the silicon substrate 110 and contacts the extension portion 132 and extension portion 182, and a portion (or the entire surface) of the extension portion 132 that is separated from the silicon substrate 110 in the first direction D1 is covered by the first passivation layer 190.

[0055] As shown in Figure 2, in one embodiment, the solar cell further comprises a second passivation layer 210. The second passivation layer 210 is located on the surface of the second doping layer 130 that is separated from the silicon substrate 110. The second passivation layer 210 has a passivation effect on the solar cell, reducing carrier recombination and helping to improve battery efficiency. The second passivation layer 210 may be an electric field passivation layer having an electric field passivation effect, a chemical passivation layer having a chemical passivation effect, or a laminated passivation structure with a joint composition of an electric field passivation layer and a chemical passivation layer. In some embodiments, the solar cell further comprises a second anti-reflection layer located on the surface of the second passivation layer 210 that is separated from the silicon substrate 110. The second anti-reflection layer can reduce the reflection of incident light by the solar cell and increase the utilization rate of incident light.

[0056] Other embodiments of the present invention further propose a method for manufacturing a solar cell. Figure 4 is an exemplary flowchart of a method for manufacturing a solar cell according to one embodiment. As shown in Figure 4, the manufacturing method of this embodiment comprises the following steps.

[0057] Step S110: Provide a silicon substrate having opposing first and second surfaces; Step S120: Form a first doping layer on the first surface of the silicon substrate; Step S130: A tunnel layer and a second doping layer are sequentially formed on the second surface of the silicon substrate, wherein the doping type of the first doping layer is opposite to that of the second doping layer; Step S140: Form the first electrode connected to the first doping layer; Step S150: Form a second electrode connected to the second doping layer; Step S160: The first doping layer penetrates the silicon substrate in the thickness direction and forms a separation groove surrounding the first electrode.

[0058] Figures 5 to 13 are schematic cross-sectional views of intermediate products in the manufacturing process of a solar cell in one embodiment. Steps S110 to S160 described above will be explained in detail below using Figures 5 to 13.

[0059] As shown in Figure 5, in step S110, a silicon substrate 110 is provided having a first surface 111 and a second surface 112 facing each other in the thickness direction D3. The silicon substrate 110 may be a doped single-crystal silicon wafer or a doped polycrystalline silicon wafer, and the doping type may be N-type doping or P-type doping. Next, a silicon substrate 110 made of N-type doped single-crystal silicon will be described as an example.

[0060] As shown in Figures 5 and 7, in step S120, a first doping layer 120 is formed on the first surface 111. The first doping layer 120 may be P-type doped single crystal silicon, N-type doped single crystal silicon, P-type doped polycrystalline silicon, or N-type doped polycrystalline silicon. Hereinafter, we will describe it as P-type doped single crystal silicon. The first doping layer 120 of P-type doped single crystal silicon forms a PN junction together with the N-type doped single crystal silicon silicon substrate 110.

[0061] In one embodiment, a method for forming the first doping layer 120 comprises performing a doping treatment on the silicon substrate 110, and then retaining the doping layer on the first surface 111. For example, referring to Figures 5, 6, and 7, an initial first doping layer 120a is formed by performing a boron diffusion treatment on the silicon substrate 110, thereby penetrating the boron element into the silicon substrate 110 to a certain depth. The initial first doping layer 120a is also formed on surfaces of the silicon substrate 110 other than the first surface 111, and the first doping layer 120 is formed by removing the initial first doping layer 120a on surfaces other than the first surface 111. The initial first doping layer 120a on surfaces other than the first surface 111 can be removed by wet etching.

[0062] As shown in Figures 5 and 9, in step S130, a tunnel layer 180 and a second doping layer 130 are sequentially formed on the second surface 112. The doping type of the second doping layer 130 is the opposite of the doping type of the first doping layer 120, and the second doping layer 130, which has an N-type doping, will be described below as an example. The doping concentration of the second doping layer 130 may be greater than the doping concentration of the silicon substrate 110.

[0063] In some embodiments, the method for forming the tunnel layer 180 and the second doping layer 130 comprises the following steps.

[0064] Step S131: Form an initial tunnel layer on the second surface, the side of the silicon substrate, and at least a portion of the first doping layer on the surface away from the silicon substrate; Step S132: Form an initial second doping layer on the surface of the initial tunnel layer that is separated from the silicon substrate; Step S133: Remove the initial tunnel layer and the initial second doping layer from the first doping layer to form the tunnel layer and the second doping layer.

[0065] The following is a detailed explanation of steps S131-S133.

[0066] As shown in Figures 7 and 8, the surface 123 of the first doping layer 120 is separated from the silicon substrate 110 in the thickness direction D3. In step S131, an initial tunnel layer 180a is formed on the second surface 112, the side surface 113, and part of the surface 123. Due to the nature of the process of forming the initial tunnel layer 180a, the initial tunnel layer 180a also covers areas other than the second surface 112. Expanding, the process for forming the initial tunnel layer 180a can be selected from atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD). When forming the initial tunnel layer 180a using the above processes, ideally, the initial tunnel layer 180a should be formed on the target area, which is the second surface 112 or at least part of the second surface 112 and side surface 113. However, due to the nature of the process itself, the initial tunnel layer 180a also deposits in other non-target regions (e.g., surface 123).

[0067] As shown in Figure 7, the initial tunnel layer 180a is formed on the second surface 112, the side surface 113, and a portion of the surface 123. In step S132, the initial second doping layer 130a is formed on the initial tunnel layer 180a. Ideally, the initial second doping layer 130a should be formed on the initial tunnel layer located on the second surface 112 and the side surface 113, and not on the initial tunnel layer located on the surface 123.

[0068] As shown in Figures 7 and 9, in step S133, the initial tunnel layer and initial second doping layer on the first doping layer 120 are removed, as well as the initial tunnel layer and initial second doping layer that are partially located on the side surface 113, forming the tunnel layer 180 and second doping layer 130 shown in Figure 9. As shown in Figures 8, 9 and 3, the upper parts of the initial tunnel layer and initial second doping layer located on the side surface 113 are removed, and the extensions 182 and 132 located on the side surface 113 are retained so that the height h1 of the extensions 182 and 132 is 0.1 μm or more and less than the thickness of the silicon substrate 110. In other embodiments, the initial tunnel layer and initial second doping layer on the first doping layer 120 are removed, but the initial tunnel layer and initial second doping layer on the side surface 113 are not removed. In this case, the height h1 of the extensions 182 and 132 is equal to the thickness of the silicon substrate 110. The method for removing the initial tunnel layer and the initial second doping layer comprises a wet etching process.

[0069] Referring to the flowcharts shown in Figures 10 and 14, in one embodiment, after the step of forming the initial tunnel layer 180a and the initial second doping layer 130a (i.e., step S132), a separation groove 160 is formed (i.e., step S160) before the step of removing the initial tunnel layer and the initial second doping layer on the first doping layer 120 (i.e., step S133), and step S133 is performed after the separation groove 160 has been formed. Figure 10 shows a separation groove 160 formed using the steps in Figure 14, and the separation groove 160 penetrates the initial tunnel layer 180a, the initial second doping layer 130a, and the first doping layer 120.

[0070] The method for forming the separation groove 160 comprises etching the initial tunnel layer 180a, the initial second doping layer 130a, and the first doping layer 120 using a laser to form a separation groove 160 that penetrates the initial tunnel layer 180a, the initial second doping layer 130a, and the first doping layer 120. In the process of forming the separation groove 160 using laser light, the laser light may damage the silicon substrate 110, the initial tunnel layer 180a, the initial second doping layer 130a, and the first doping layer 120 exposed in the separation groove 160. By providing the step of forming the separation groove 160 between step S132 and step S133, the laser damage can be removed using step S133. Specifically, step S133 can remove the initial tunnel layer and the initial second doping layer while simultaneously removing the laser damage.

[0071] Referring to the flowchart shown in Figure 15, in other embodiments, the separation groove 160 can be formed after the step of removing the initial tunnel layer and the initial second doping layer on the first doping layer 120 (i.e., step S133) (i.e., step S160). Figure 11 shows the separation groove formed using the steps in Figure 15. Comparing Figure 11 with Figure 10, it can be seen that in Figure 15, the initial tunnel layer and the initial second doping layer on the first doping layer 120 were removed before step S160, so the separation groove 160 in Figure 11 does not penetrate the initial tunnel layer and the initial second doping layer.

[0072] As shown in Figures 5, 6, and 7, in the step of removing the initial first doping layer 120a to form the first doping layer 120, ideally only the initial doping layer located on the first surface 111 should remain. However, due to process limitations, the initial first doping layer may remain on other surfaces. For example, the initial first doping layer may remain on the side surface 113 and / or the second surface 112. As shown in Figure 9, these remaining initial first doping layers can connect the first doping layer 120 and the second doping layer 130, potentially causing a short circuit between the first doping layer 120 and the second doping layer 130, and reducing the efficiency of the solar cell.

[0073] As shown in Figures 1 and 2, the isolation groove 160 penetrates the first doping layer 120 in the thickness direction D3, and the isolation groove 160 is a closed rectangle surrounding all of the first electrodes 140. The first doping layer 120 is divided into two parts by the isolation groove 160. One part is surrounded by the isolation groove 160 (this part is referred to as the internal doping layer 121), and the other part is not surrounded by the isolation groove 160 and is located between the edge 170 of the solar cell and the isolation groove 160 (this part is referred to as the peripheral doping layer 122). The internal doping layer 121 is in contact with and connected to the first electrodes 140, and carriers (e.g., holes or electrons) in the internal doping layer 121 can be transmitted to the outside of the solar cell via the first electrodes 140. Due to the division of the separation groove 160, the internal doping layer 121 does not come into contact with the peripheral doping layer 122, and there is no electrical connection between the internal doping layer 121 and the peripheral doping layer 122. Therefore, even if the remaining initial first doping layer 120a connects the first doping layer 120 and the second doping layer 130, the presence of the separation groove 160 prevents the internal doping layer 121 connected to the first electrode 140 from coming into contact with the second doping layer 130. This prevents a short circuit from occurring between the first doping layer 120 and the second doping layer 130, or more precisely, prevents a short circuit from occurring between the internal doping layer 121 and the second doping layer 130.

[0074] As shown in Figure 1, the distance between the separation groove 160 and the edge 123 of the first doping layer 120 is set to be smaller than a predetermined distance of any value between 10 μm and 2000 μm. As mentioned above, due to the separation action of the separation groove 160, when the solar cell is operating, the internal doping layer 121 is involved in the output of electrical energy, while the peripheral doping layer 122 is not. In order to increase the electrical energy from the solar cell, the area of ​​the internal doping layer 121 should be made as large as possible. Limiting the distance between the separation groove 160 and the edge of the first doping layer 120 helps to increase the area of ​​the internal doping layer 121 and increase the area that the solar cell can use for power generation.

[0075] As shown in Figures 11 and 12, the surface 124 of the first doping layer 120 is separated from the silicon substrate 110 in the thickness direction D3. The first passivation layer 190 is formed on the surface 124, and also on the side surface 113 of the silicon substrate 110. The first passivation layer 190 further covers the bottom and side surfaces of the separation groove 160. By forming the first passivation layer 190 after forming the separation groove 160, the bottom and side surfaces of the separation groove 160 can be covered with the first passivation layer 190, thereby allowing the first passivation layer 190 to come into contact with the silicon substrate 110 and the first doping layer 120 exposed in the separation groove 160, thereby enabling good passivation of the first passivation layer 190 in the separation groove 160. In other embodiments, the first passivation layer 190 may be formed only on the surface 124.

[0076] In one embodiment, the isolation groove 160 may be formed after the first passivation layer 190 is formed. Figure 3 shows a solar cell manufactured sequentially using the above steps, in which the isolation groove 160 penetrates the first passivation layer 190 and the first doping layer 120 sequentially. Since the isolation groove 160 is formed after the first passivation layer 190 is formed, the first passivation layer 190 does not cover the bottom and sides of the isolation groove 160. Details of the first passivation layer 190 are described above and will not be elaborated here.

[0077] As shown in Figures 12 and 13, in one embodiment, the surface 133 of the second doping layer 130 is separated from the silicon substrate 110 in the thickness direction D3, and the second passivation layer 210 is formed on the surface 133. In some embodiments, the separation groove 160 can be formed after the step of forming the second passivation layer 210. In other embodiments, the first electrode 140 and the second electrode 150 are formed after the second passivation layer 210 is formed, and then the separation groove 160 is formed.

[0078] As described above, the basic concepts have been explained, but it will be obvious to those skilled in the art that the above disclosure is merely an example and does not limit the present application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and amendments to the present application. Such modifications, improvements, and amendments are proposed in the present application and therefore fall within the spirit and scope of the exemplary embodiments of the present application.

[0079] At the same time, this application uses specific terminology to describe embodiments of the application. For example, “one embodiment,” “one example,” and / or “several embodiments” mean features, configurations, or characteristics relating to at least one embodiment of the application. Accordingly, it should be emphasized and noted that “one embodiment,” “one example,” or “one alternative embodiment” mentioned more than once in different places in this specification do not necessarily mean the same embodiment. Furthermore, several features, configurations, or characteristics in one or more embodiments of the application can be appropriately combined.

[0080] In some embodiments, numbers are used to describe the number of components and attributes, but it should be understood that in some embodiments, the numbers used to describe such embodiments are modified using the modifiers “approximately,” “roughly,” or “approximately.” Unless otherwise stated, “approximately,” “roughly,” or “approximately” means that the numerical value is allowed to vary by ±20%. Thus, in some embodiments, the numerical parameters used in the specification and claims are approximations, and these approximations may be modified depending on the features required for the individual embodiments. In some embodiments, the numerical parameters should take into account a predetermined number of significant digits and employ a general method of digit retention. In some embodiments of this application, the numerical fields and parameters used to confirm their range are approximations, but in certain embodiments, the setting of such numerical values ​​is as accurate as possible. [Explanation of Symbols]

[0081] Silicon substrate 110 1st surface 111 2nd surface 112 Side view 113 First doping layer: 120 Internal doping layer 121 Peripheral doping layer 122 Edge 123 surface 124 First edge 123a Second edge 123b Third edge 123c 4th edge 123d Initial doping layer 120a Second doping layer: 130 Main body 131 Extension part 132 surface 133 Initial second doping layer 130a 1st electrode 140 Gate 1 Line 141 Gate 2 Line 142 2nd electrode 150 Separation groove 160 1st separation groove 160a 2nd separation groove 160b Third separation groove 160c 4th separation groove 160d Solar cell edge 170 Tunnel layer 180 Main body 181 Extension 182 Initial tunnel layer 180a First Passivation Layer 190 Second Passivation Layer 210

Claims

1. A silicon substrate having opposing first and second surfaces, The first doping layer provided on the first surface, A second doping layer is provided on the second surface, and the doping type of the second doping layer is the opposite of the doping type of the first doping layer. A first electrode connected to the first doping layer, A second electrode connected to the second doping layer, A separation groove extends through the first doping layer along the thickness direction of the silicon substrate and surrounds the first electrode, The tunnel layer provided on the second surface, The first doping layer comprises a first passivation layer disposed on the surface of the first doping layer away from the silicon substrate, The second doping layer is provided on the surface of the tunnel layer that is separated from the silicon substrate, The tunnel layer extends to the side surface of the silicon substrate and covers at least a portion of the side surface of the silicon substrate, the second doping layer covers the surface of the tunnel layer that is away from the silicon substrate, the height of the tunnel layer located on the side surface of the silicon substrate is 0.1 μm or more and less than or equal to the thickness of the silicon substrate, The first passivation layer extends to the side surface of the silicon substrate and is in contact with the tunnel layer and the second doping layer located on the side surface. A solar cell characterized in that the tunnel layer is made of silicon oxide.

2. The solar cell according to claim 1, characterized in that the distance between the separation groove and the edge of the first doping layer is smaller than a preset distance, and the preset distance is 10 μm to 2000 μm.

3. The solar cell according to claim 1, characterized in that the first passivation layer covers the bottom and side walls of the separation groove.

4. The solar cell according to claim 1, further comprising a second passivation layer disposed on the surface of the second doping layer that is separated from the silicon substrate.

5. The steps include providing a silicon substrate having opposing first and second surfaces, The steps include forming a first doping layer on the first surface of the silicon substrate, A tunnel layer and a second doping layer are sequentially formed on the second surface of the silicon substrate, wherein the doping type of the first doping layer is opposite to that of the second doping layer. The steps include forming a first electrode connected to the first doping layer, The steps include forming a second electrode connected to the second doping layer, The steps include forming a separation groove that penetrates the first doping layer along the thickness direction of the silicon substrate and surrounds the first electrode, The process includes the step of forming a first passivation layer on the surface of the first doping layer that is separated from the silicon substrate, The method for forming the tunnel layer and the second doping layer is: An initial tunnel layer is formed on the second surface, the side surface of the silicon substrate, and at least a portion of the first doping layer on the surface away from the silicon substrate. An initial second doping layer is formed on the surface of the initial tunnel layer that is separated from the silicon substrate, The tunnel layer and the second doping layer are formed by removing the initial tunnel layer and the initial second doping layer from the first doping layer. The method involves further removing a portion of the initial tunnel layer and the initial second doping layer on the side surface of the silicon substrate so that the height of the tunnel layer and the second doping layer located on the side surface of the silicon substrate is 0.1 μm or more and less than or equal to the thickness of the silicon substrate. The first passivation layer extends to the side surface of the silicon substrate and is in contact with the tunnel layer and the second doping layer located on the side surface. A method for manufacturing a solar cell, characterized in that the tunnel layer is made of silicon oxide.

6. The manufacturing method according to claim 5, characterized in that the separation groove is formed after the step of forming the initial tunnel layer and the initial second doping layer, and before the step of removing the initial tunnel layer and the initial second doping layer from the first doping layer.

7. The manufacturing method according to claim 5, characterized in that the distance between the separation groove and the edge of the first doping layer is smaller than a preset distance, and the preset distance is 10 μm to 2000 μm.

8. The manufacturing method according to claim 5, characterized in that the first passivation layer is formed after the step of forming the separation groove.

9. The manufacturing method according to claim 5, characterized in that a second passivation layer is formed on the surface of the second doping layer that is separated from the silicon substrate.

10. The manufacturing method according to claim 9, characterized in that the separation groove is formed after the step of forming the second passivation layer.

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