2D material-integrated halide perovskite thin-film semiconductor device and method for manufacturing the same

Abstract

The present invention provides a halide perovskite semiconductor for easily converting perovskite types or preventing damage to perovskite thin films that occur during processing. [Solution] The halide perovskite thin-film semiconductor device 100 includes a substrate 120, a halide perovskite layer 140 formed on the upper surface of the substrate, a two-dimensional material layer 150 formed on the halide perovskite layer, an electrode unit 160 disposed on the halide perovskite layer and including a drain electrode and a source electrode, and a polymer layer 170 formed on the two-dimensional material layer and the electrode unit. The two-dimensional material layer 150 is manufactured by laminating it on the halide perovskite layer by a dry transfer method.

Description

Technical Field

[0001] <Cross - Reference to Related Applications> This application claims priority and benefit to Korean Patent Application No. 10 - 2025 - 0034439, filed on March 18, 2025, the entire disclosure of which is incorporated herein by reference. The present invention relates to the fields of electronics and semiconductor engineering, and more specifically, to a semiconductor device structure including a two - dimensional material and a halide perovskite material, and a method for manufacturing the same.

Background Art

[0002] Halide perovskite materials have advantages such as excellent optoelectronic conversion efficiency, high charge mobility, the possibility of low - cost mass production, and flexibility. However, there are several limitations regarding actual device manufacturing and applications.

[0003] The most important problem is that the electrical property (n - type or p - type) conversion of perovskite strongly depends on the chemical composition. This restricts the design and property control of devices, making it difficult to stably achieve desired electrical properties. In particular, a complex composition control process is required to adjust the electrical properties of devices, and even for materials with the same composition, significant performance variations may occur depending on the manufacturing process conditions, making it difficult to realize reliable devices.

[0004] Another limitation is that perovskite materials have low compatibility with existing semiconductor processes. Perovskite is very vulnerable to moisture and organic solvents generated during processing, so it is particularly difficult to apply processes such as photolithography, which are essential for fine patterning and integration. This vulnerability significantly reduces the structural stability of devices and poses a major technical barrier to the manufacture of high - resolution devices or the utilization of existing silicon - based semiconductor manufacturing technologies.

[0005] Due to these constraints, most studies reported to date have primarily employed methods of coating the device channel with perovskite material as an upper layer rather than a lower layer. Placing the perovskite as an lower layer increases the risk of physical and chemical damage during subsequent processes and makes precise control of process variables more difficult. Therefore, there is a need for novel device structures and manufacturing methods that can overcome these limitations while maximizing the advantages of perovskite materials. [Overview of the Initiative]

[0006] One problem that the present invention aims to solve is to provide a halide perovskite semiconductor device and a method for manufacturing the same that allows for easy conversion of the perovskite type.

[0007] Another problem that the present invention aims to solve is to provide a halide perovskite semiconductor device and a method for manufacturing the same that prevents damage to the perovskite thin film that occurs during processing.

[0008] The problems that this invention aims to solve are not limited to those described above, and other undescribed problems will be clearly understood by those skilled in the art from this specification and the accompanying drawings.

[0009] A halide perovskite semiconductor device according to one embodiment of the present invention includes a substrate, a halide perovskite layer formed on the upper surface of the substrate, a two-dimensional material layer formed on the halide perovskite layer, an electrode unit disposed on the halide perovskite layer and including a drain electrode and a source electrode, and a polymer layer formed on the two-dimensional material layer and the electrode unit. The two-dimensional material layer may be characterized by being manufactured by laminating it on the halide perovskite layer by a dry transfer method.

[0010] The means for solving the problems of the present invention are not limited to those described above, and other means not described herein will be clearly understood by those skilled in the art from this specification and the accompanying drawings.

[0011] According to one embodiment of the present invention, a halide perovskite semiconductor device and a method for manufacturing the same, by laminating a two-dimensional material onto a perovskite thin film using a dry transfer method, it is possible to minimize physical damage that may occur during the lamination process between the two-dimensional material and the perovskite. Furthermore, this makes it possible to more stably control the electrical properties of the semiconductor device.

[0012] According to one embodiment of the present invention, a halide perovskite semiconductor device and a method for manufacturing the same can be provided, which allows for easy control of the conversion between N-type and P-type semiconductors by precisely controlling the gap between the two-dimensional material and the electrode.

[0013] According to one embodiment of the present invention, a halide perovskite semiconductor device and a method for manufacturing the same, by applying a top-gate and bottom-gate structure, it is possible to realize a semiconductor device in various substrate environments, including glass substrates or flexible substrates.

[0014] A halide perovskite semiconductor device and a method for manufacturing the same according to one embodiment of the present invention can overcome the limitations of existing perovskite semiconductor devices and contribute to the realization of next-generation semiconductor devices with high performance and high stability by controlling the interface between the two-dimensional material and the perovskite, optimizing the gap with the electrode, and applying a dry transfer process.

[0015] The effects of the present invention are not limited to those described above, and other effects not described herein will be clearly understood by those skilled in the art from this specification and the accompanying drawings. [Brief explanation of the drawing]

[0016] The above and other objects, features and advantages of the present invention will become more apparent to those skilled in the art by describing in detail exemplary embodiments of the invention with reference to the accompanying drawings. [Figure 1] This is a schematic diagram of a halide perovskite thin-film semiconductor device containing a two-dimensional material according to one embodiment of the present invention, viewed from above. [Figure 2] This is a schematic diagram showing a cross-section of a halide perovskite thin-film semiconductor device containing a two-dimensional material according to one embodiment of the present invention. [Figure 3] Figures 1 and 2 are flowcharts relating to the manufacturing method of semiconductor devices. [Figure 4] This figure illustrates a manufacturing method corresponding to the manufacturing method of the semiconductor device 100 shown in Figure 3. [Figure 5] This figure illustrates an embodiment of realizing n-type and p-type TFTs using a two-dimensional material according to one embodiment of the present invention. [Figure 6] This is a schematic diagram showing a cross-section of a semiconductor device having a top gate and bottom gate structure according to another embodiment of the present invention. [Modes for carrying out the invention]

[0017] The above-mentioned objectives, features, and advantages of this application will become more apparent from the following detailed description with respect to the attached drawings. However, since this application can be modified in various ways and can have various embodiments, specific embodiments are shown in the drawings and described in detail below.

[0018] Throughout this specification, the same reference numerals generally refer to the same components. Furthermore, components that have the same function within the scope of the same concept appearing in the drawings of each embodiment are described using the same reference numeral, and redundant descriptions are omitted.

[0019] If it is determined that a detailed description of well-known functions and configurations related to this application may unnecessarily obscure the gist of this application, the detailed description will be omitted. Also, the numbers used in the description process of this specification (for example, the first, the second, etc.) are merely identification symbols for distinguishing one component from other components.

[0020] In addition, the suffixes "module" and "unit" of the components used in the following embodiments are given or used interchangeably only for the purpose of facilitating the preparation of the specification, and do not have clearly distinguishable meanings or roles from each other.

[0021] In the following embodiments, the singular form includes the plural form unless otherwise specified by the context.

[0022] In the following embodiments, terms such as "comprising" or "having" mean that the features or components described in this specification exist, and do not preclude the possibility of adding one or more other features or components in advance.

[0023] In the drawings, for the convenience of explanation, the sizes of the components may be exaggerated or reduced. For example, the sizes and thicknesses of each component shown in the drawings are arbitrarily shown for the convenience of explanation, and the present invention is not necessarily limited to what is shown in the drawings.

[0024] If a certain embodiment can be implemented in a different way, the order of a specific process may be executed differently from the described order. For example, two processes described consecutively may be executed substantially simultaneously, or may proceed in the reverse order of the described order.

[0025] In the following embodiments, when it is stated that components are connected, this includes not only cases where components are directly connected, but also cases where components are indirectly connected through the interposition of other components. For example, in this specification, when it is stated that components are electrically connected, this includes not only cases where components are directly electrically connected, but also cases where components are indirectly electrically connected through the interposition of other components.

[0026] A halide perovskite semiconductor device according to one embodiment of the present invention includes a substrate, a halide perovskite layer formed on the upper surface of the substrate, a two-dimensional material layer formed on the halide perovskite layer, an electrode unit disposed on the halide perovskite layer and including a drain electrode and a source electrode, and a polymer layer formed on the two-dimensional material layer and the electrode unit. The two-dimensional material layer may be characterized by being manufactured by laminating it on the halide perovskite layer by a dry transfer method.

[0027] According to one embodiment of this application, the gap between a two-dimensional material layer and either the drain electrode or the source electrode is adjusted based on a predetermined length, thereby controlling the electrical characteristics of the semiconductor device.

[0028] According to one embodiment of this application, when the gap between the two-dimensional material layer and either of the electrodes is greater than or equal to a predetermined length, the two-dimensional material layer can induce doping of the halide perovskite layer so that relative charge transport occurs through the halide perovskite layer.

[0029] According to one embodiment of this application, when the gap between the two-dimensional material layer and either of the electrodes is less than a predetermined length, a current flow is generated in the two-dimensional material of the two-dimensional material layer.

[0030] According to one embodiment of this application, the predetermined length may be characterized by being in a range of lengths including 50 nm.

[0031] According to one embodiment of this application, the halide perovskite layer can be characterized by being selected from the group consisting of MAPbI3, FAPbI3, CsPbI3, RbPbI3, MASnI3, FASnI3, CsSnI3, MAPbBr3, FAPbBr3, CsPbBr3, RbPbBr3, MASnBr3, FASnBr3, CsSnBr3, PEA2PbI4, PEA2PbBr4, PEA2SnI4, PEA2SnBr4, BDA2PbI4, BDA2PbBr4, BDA2SnI4, BDA2SnBr4, and combinations thereof.

[0032] According to one embodiment of this application, the halide perovskite layer may be characterized by being composed of one of a three-dimensional thin film structure, a two-dimensional thin film structure, or a mixture thereof.

[0033] According to one embodiment of this application, the two-dimensional material layer may be characterized by comprising a two-dimensional material which comprises one of the transition metal chalcogenide materials selected from WS2, MoS2, WSe2, and MoSe2, h-BN, BP, and MXene.

[0034] According to one embodiment of this application, the drain electrode is connected to the power supply voltage (VDD) and the source electrode is connected to the ground voltage (VSS).

[0035] According to one embodiment of this application, the semiconductor device may further include a back-side input electrode layer formed on the back side of the substrate, the back-side input electrode layer being configured to provide an input voltage (Vin) to an electrode unit.

[0036] According to one embodiment of the present application, the semiconductor device may further include a gate insulating layer formed between a substrate and a halide perovskite layer, the halide perovskite layer being formed on at least a portion of the surface of the gate insulating layer.

[0037] According to one embodiment of this application, the substrate is formed of glass or a flexible substrate and further includes a halide perovskite layer, an electrode unit, or a gate insulating layer formed on a two-dimensional material layer. A gate electrode is formed on the gate insulating layer and is configured to provide an input electrode (Vin) to the electrode unit.

[0038] According to one embodiment of this application, the substrate is formed of glass or a flexible substrate and further includes a gate insulating layer formed between the substrate and a halide perovskite layer. A gate electrode is formed on the gate insulating layer and is configured to provide an input electrode (Vin) to the electrode unit.

[0039] A semiconductor device using a halide perovskite thin film according to one embodiment of this application, and its manufacturing process, will be described in more detail below with reference to Figures 1 to 6.

[0040] Figure 1 is a schematic diagram of a halide perovskite thin-film semiconductor device 100 containing a two-dimensional material according to one embodiment of the present invention, viewed from above. Figure 2 is a schematic diagram showing a cross-section of the halide perovskite thin-film semiconductor device 100 containing a two-dimensional material according to one embodiment of the present invention. Specifically, Figure 2 is a schematic diagram showing a cross-section of the semiconductor device 100 of Figure 1, cut along the line A-A'.

[0041] Referring to Figures 1 and 2, a halide perovskite thin-film semiconductor device 100 (or thin-film transistor, hereinafter referred to as a semiconductor device) according to one embodiment of the present invention is shown. The semiconductor device 100 may include a substrate 120, a gate insulating layer 130, a halide perovskite layer 140, a two-dimensional material layer 150, an electrode unit 160, and a polymer layer 170.

[0042] The substrate 120 is a structure that functions as the base for the semiconductor device 100, and may be composed of various materials such as a silicon substrate, a glass substrate, or a flexible substrate. For example, the substrate 120 may be a silicon substrate in the form of a silicon wafer.

[0043] The gate insulating layer 130 is formed on the substrate 120 and may be composed of an oxide insulator or the like. Specifically, the gate insulating layer 130 may be formed on the upper surface side of the substrate 120. The gate control characteristics of the device can be improved and leakage current can be reduced via the gate insulating layer 130.

[0044] The halide perovskite layer 140 is formed on the gate insulating layer 130 and may be composed of a halide perovskite material selected from the group consisting of MAPbI3, FAPbI3, CsPbI3, RbPbI3, MASnI3, FASnI3, CsSnI3, MAPbBr3, FAPbBr3, CsPbBr3, RbPbBr3, MASnBr3, FASnBr3, CsSnBr3, PEA2PbI4, PEA2PbBr4, PEA2SnI4, PEA2SnBr4, BDA2PbI4, BDA2PbBr4, BDA2SnI4, BDA2SnBr4, and combinations thereof.

[0045] The halide perovskite layer 140 according to one embodiment may be composed of any one of the following halide perovskite materials: a three-dimensional thin film structure, a two-dimensional thin film structure, or a mixture thereof. The three-dimensional (3D) thin film structure may be in the form of an ABX3 structure (A: organic or inorganic cation, B: metal cation, X: halogen anion). Examples of halide perovskite materials having a three-dimensional thin film structure include MAPbI3, FAPbI3, CsPbI3, RbPbI3, MASnI3, FASnI3, CsSnI3, MAPbBr3, FAPbBr3, CsPbBr3, RbPbBr3, MASnBr3, FASnBr3, and CsSnBr3. The three-dimensional thin film structure has the advantage of having excellent charge mobility, allowing electrons and holes to move easily in all directions. The two-dimensional (2D) thin film structure may be a layered structure in the form of (R-NH3)2BX4 or A2BX4. Examples of halide perovskite materials having a two-dimensional thin film structure include PEA2PbI4, PEA2PbBr4, PEA2SnI4, PEA2SnBr4, BDA2PbI4, BDA2PbBr4, BDA2SnI4, and BDA2SnBr4. Compared to three-dimensional structures, two-dimensional thin film structures have higher stability, a band gap that can be adjusted by quantum confinement effects, smooth in-plane charge transport, but low interlayer charge mobility.

[0046] The two-dimensional material layer 150 may be formed on the halide perovskite layer 140. Specifically, the two-dimensional material layer 150 may be formed on at least a portion of the surface of the halide perovskite layer 140. That is, according to one embodiment of the present application, the halide perovskite layer 140 may be located below the channel of the semiconductor device 100. Furthermore, the two-dimensional material layer 150 may be composed of a transition metal chalcogenide (e.g., a transition metal dichalcogenide (TMD)) material. The two-dimensional material layer 150 may be composed of a transition metal chalcogenide material containing any one of WS2, MoS2, WSe2, or MoSe2. Alternatively, the two-dimensional material layer 150 may be composed of a two-dimensional material containing any one of h-BN, BP, and / or MXene. On the other hand, the two-dimensional material layer 150 may be placed on the region of the halide perovskite layer 140 located between the source electrode 160-1 and the drain electrode 160-2 of the electrode unit 160, which will be described later.

[0047] A two-dimensional material layer 150 according to one embodiment of this application can function as a protective layer for the halide perovskite layer 140 and can act as a doping layer at the interface with the halide perovskite layer 140.

[0048] Specifically, the two-dimensional material layer 150 is positioned on top of the halide perovskite layer 140 and can function to protect the halide perovskite layer 140 from the external environment (moisture, oxygen, heat, etc.). This improves the structural stability and durability of the halide perovskite layer 140. In particular, this prevents damage to the perovskite material of the halide perovskite layer 140 due to moisture and solvents during the manufacturing process of the semiconductor device 100.

[0049] Furthermore, the two-dimensional material layer 150 functions as a doping layer, inducing charge transport at the interface between the two-dimensional material layer 150 and the halide perovskite layer 140, thereby controlling the doping properties of the halide perovskite layer 140. The charge transport at the interface between the two-dimensional material layer 150 and the halide perovskite layer 140 can be varied depending on the gap between the two-dimensional material layer 150 and the electrode (160-1 or 160-2) of the electrode unit 160, thereby providing an effect that allows for easy control of the electrical properties of the semiconductor device 100. This will be explained in more detail with reference to Figure 5.

[0050] On the other hand, the two-dimensional material layer 150 according to one embodiment of this application can be manufactured by laminating it onto the halide perovskite layer 140 by a dry transfer method. By laminating the two-dimensional material layer 150 onto the halide perovskite layer 140 by a dry transfer method, the halide perovskite layer 140 can be positioned below the channel of the semiconductor device 100. The manufacturing method will be described in more detail with reference to Figures 3 and 4.

[0051] The electrode unit 160 is formed on a halide perovskite layer 140 and may include a source electrode 160-1 and a drain electrode 160-2. The source electrode 160-1 is connected to the ground voltage (VSS), and the drain electrode 160-2 is connected to the power supply voltage (VDD). A back-side input electrode layer 110 may also be formed on the back side of the substrate 120 (i.e., the side of the substrate 120 opposite to where the gate insulating layer 130 is formed), and the back-side input electrode layer 110 can provide an input voltage (Vin) to the electrode unit 160.

[0052] The polymer layer 170 may be formed on the halide perovskite layer 140, the two-dimensional material layer 150, and / or the electrode unit 160 so as to cover the two-dimensional material layer 150 and / or the electrode unit 160. The polymer layer 170 may be composed of a material selected from the group consisting of PMMA (polymethyl methacrylate), PVA (polyvinyl alcohol), PDMS (polydimethylsiloxane), polyimide, PET (polyethylene terephthalate), PPC (polypropylene carbonate), PS (polystyrene), paraffin, and mixtures thereof. The polymer layer 170 can perform the function of protecting the semiconductor device 100 from the external environment and improving its stability. In particular, the polymer layer 170 stably fixes the two-dimensional material layer 150 and the electrode unit 160, contributes to precise gap adjustment between the two-dimensional material layer 150 and the electrodes contained in the electrode unit 160, and thereby contributes to precise control of the electrical properties of the semiconductor device 100.

[0053] The manufacturing method of the semiconductor device 100 according to one embodiment of this application will be described in more detail below with reference to Figures 3 and 4. In describing the manufacturing method of the semiconductor device 100, some content that overlaps with the content described in relation to Figures 1 and 2 may be omitted. However, this is merely for the convenience of explanation and should not be interpreted as being limited to this.

[0054] Figure 3 is a flowchart illustrating the manufacturing method of the semiconductor device 100 shown in Figures 1 and 2. Figure 4 is a diagram illustrating the manufacturing method corresponding to the manufacturing method of the semiconductor device 100 shown in Figure 3.

[0055] A method for manufacturing a semiconductor device 100 according to one embodiment of this application includes the steps of: preparing a two-dimensional material layer 150 (S110); forming an electrode unit 160 (S120); forming a polymer layer 170 (S130); preparing and cleaning a substrate 120 (S140); depositing a gate insulating layer 130 (S150); forming a back-side input electrode layer 110 (S160); forming a halide perovskite layer 140 (S170); and depositing the two-dimensional material layer 150, the electrode unit 160, and the polymer layer 170 (S180).

[0056] In step S110, a two-dimensional material layer 150 may be prepared on a separate substrate 120'. Specifically, the two-dimensional material layer 150 may be prepared by growing a two-dimensional material on the separate substrate 120'. The two-dimensional material may be formed on the separate substrate 120' by a direct growth method (e.g., chemical vapor deposition (CVD)) or by a dry transfer or wet transfer method that adheres the two-dimensional material to the substrate.

[0057] In step S120, the electrode unit 160 may be formed on a separate substrate 120'. Specifically, a source electrode 160-1 and a drain electrode 160-2 may be formed on at least a portion of the region of the separate substrate 120'. In this case, the electrode unit 160 may be formed on the separate substrate 120' such that the two-dimensional material layer 150 described above is positioned between the source electrode 160-1 and the drain electrode 160-2.

[0058] In step S130, a polymer layer 170 may be formed to cover the electrode unit 160 and the two-dimensional material layer 150. The polymer layer 170 can serve to protect the devices or materials contained in the semiconductor device 100. Furthermore, in step S130, the other substrate 120' can be removed to obtain a polymer support film (SF) composed of the two-dimensional material layer 150, the electrode unit 160, and the polymer layer 170.

[0059] In step S140, a substrate 120, which is a structure that functions as the base for the semiconductor device 100, may be provided and cleaned. The substrate 120 may be made of various materials such as a silicon substrate (e.g., a silicon wafer), a glass substrate, or a flexible substrate.

[0060] In step S150, the gate insulating layer 130 may be deposited on the substrate 120 prepared in step S140. Specifically, the gate insulating layer 130 may be deposited on the upper surface of the substrate 120.

[0061] In step S160, a back-side input electrode layer 110 may be formed on the back side of the substrate 120 prepared in step S140. The back-side input electrode layer 110 can provide an input voltage (Vin) to electrodes 160-1 and 160-2 of the electrode unit 160.

[0062] In step S170, a halide perovskite layer 140 may be formed on the gate insulating layer 130 formed in step S150. The halide perovskite layer 140 may be composed of a halide perovskite material selected from the group consisting of MAPbI3, FAPbI3, CsPbI3, RbPbI3, MASnI3, FASnI3, CsSnI3, MAPbBr3, FAPbBr3, CsPbBr3, RbPbBr3, MASnBr3, FASnBr3, CsSnBr3, PEA2PbI4, PEA2PbBr4, PEA2SnI4, PEA2SnBr4, BDA2PbI4, BDA2PbBr4, BDA2SnI4, BDA2SnBr4, and combinations thereof.

[0063] In step S180, the polymer support film (SF), consisting of the two-dimensional material layer 150, electrode unit 160, and polymer layer 170 obtained in step S130, may be deposited on a thin film (F) containing the halide perovskite layer 140 formed in step S170. According to one embodiment of this application, the polymer support film (SF) may be laminated on the thin film (F) containing the halide perovskite layer 140 by a dry transfer method. This dry transfer method allows for the transfer of the two-dimensional device of the two-dimensional material layer 150 without the use of solvents or chemicals, thereby providing the advantageous effect of manufacturing the device without damaging the halide perovskite layer 140, which is sensitive to moisture and solvents.

[0064] Hereinafter, with reference to Figure 5, a method for controlling the electrical characteristics of a semiconductor device 100 according to one embodiment of this application will be described in more detail.

[0065] Figure 5 is a diagram illustrating an embodiment of realizing n-type and p-type TFTs using a two-dimensional material according to one embodiment of the present invention.

[0066] Referring to Figure 5, according to one embodiment of the present invention, the gap (d) between the two-dimensional material layer 150 and either the drain electrode 160-2 or the source electrode 160-1 is adjusted based on a predetermined length, thereby controlling the electrical characteristics of the semiconductor device.

[0067] According to one embodiment, when the gap (d) between the two-dimensional material layer 150 and either the drain electrode 160-2 or the source electrode 160-1 is greater than or equal to a predetermined length, the two-dimensional material layer 150 induces doping of the halide perovskite layer 140 so that relative charge transport can be performed through the halide perovskite layer 140.

[0068] The two-dimensional material of the two-dimensional material layer 150 may have the property of donating or accepting electrons (e-) depending on vacancies or electron affinity. For example, as shown in Figure 5a, when the two-dimensional material emits electrons (e-) and the halide perovskite layer 140 accepts electrons (e-), the halide perovskite layer 140 exhibits N-type semiconductor properties. As another example, as shown in Figure 5b, when the two-dimensional material accepts electrons (e-), the halide perovskite layer 140 exhibits P-type semiconductor properties with increased holes (h+).

[0069] Thus, when the gap (d) between the two-dimensional material layer 150 and either the drain electrode 160-2 or the source electrode 160-1 is greater than or equal to a predetermined length, that is, when the two-dimensional material and the electrode are physically relatively separated, the two-dimensional material does not directly interact with the electrode, and the two-dimensional material can exchange charge with the halide perovskite layer 140, thereby inducing doping of the halide perovskite layer 140. In this case, the halide perovskite layer 140 becomes the center of the charge transport pathway, and the electrical properties of the semiconductor device can be controlled to have N-type or P-type characteristics depending on the electron affinity of the two-dimensional material.

[0070] According to one embodiment, if the gap (d) between the two-dimensional material layer 150 and either the drain electrode 160-2 or the source electrode 160-1 is less than a predetermined length, current can flow through the two-dimensional material of the two-dimensional material layer 150. Specifically, if the gap (d) between the two-dimensional material layer 150 and either the drain electrode 160-2 or the source electrode 160-1 is less than a predetermined length, that is, if the two-dimensional material and the electrode are arranged in relatively close proximity, the two-dimensional material directly interacts with the electrode, and a direct current flows through the two-dimensional material. In this case, the two-dimensional material of the two-dimensional material layer 150 itself is directly connected to the electrode and acts as a semiconductor channel, and the conductive properties of the two-dimensional material itself can be controlled to affect the operating mechanism of the semiconductor device.

[0071] On the other hand, referring to Figure 5c, according to one embodiment of the present application, the predetermined length of the gap (d) between the two-dimensional material layer 150 and either the drain electrode 160-2 or the source electrode 160-1 is characterized in that the length is in the range of 50 nm.

[0072] By utilizing the structural characteristics of the semiconductor device 100 according to one embodiment of this application, it is possible to realize an n-type or p-type transistor within a single device simply by adjusting the gap (d) between the two-dimensional material layer 150 and the electrodes 160-1 and 160-2 of the electrode unit 160. This has the advantageous effect of enabling type conversion, which was previously only possible through compositional changes of conventional halide perovskite materials, to be achieved with a simple structural change.

[0073] Hereinafter, with reference to Figure 6, semiconductor devices 200 and 300 according to another embodiment of this application will be described in more detail. On the other hand, the halide perovskite layer 140, two-dimensional material layer 150, electrode unit 160, and polymer layer 170 described in Figures 1 to 5 are substantially applicable in the same way as the two-dimensional material layers 230 and 350, halide perovskite layers 220 and 340, electrode units 240 and 360, and polymer layers 270 and 370 which will be described in relation to Figure 6, so their description will be omitted, and the focus will be on the substrates 210 and 310, gate insulating layers 250 and 330, and gate electrodes 260 and 330 which have been modified compared to the embodiments in Figures 1 to 5. However, this is for the convenience of explanation and should not be interpreted as being limited thereto.

[0074] Figure 6 is a schematic diagram showing a cross-section of a semiconductor device having a top-gate and bottom-gate structure according to another embodiment of the present invention. Specifically, Figure 6(a) is a schematic diagram showing a cross-section of a semiconductor device 200 having a top-gate structure, and Figure 6(b) is a schematic diagram showing a cross-section of a semiconductor device 300 having a bottom-gate structure.

[0075] The semiconductor devices 200 and 300 according to this embodiment use a glass substrate or a flexible substrate 210 or 310 instead of a silicon wafer substrate 120, and have a structure in which the arrangement of the gate insulating layers 250 and 330 and the gate electrodes 260 and 320 is changed.

[0076] Referring to Figure 6(a), in the top gate structure, a halide perovskite layer 220, a two-dimensional material layer 230, and the source electrode 240-1 and drain electrode 240-2 of the electrode unit 240 are sequentially formed on the substrate 210. A gate insulating layer 250 may be formed to cover the halide perovskite layer 220, the two-dimensional material layer 230, and the source electrode 240-1 and drain electrode 240-2 of the electrode unit 240. Furthermore, a gate electrode 260 may be formed on the gate insulating layer 250, and the gate electrode 260 may be configured to provide an input electrode (Vin) to the electrode unit 240.

[0077] Referring to Figure 6(b), in the bottom gate structure, a gate insulating layer 330 may be formed on the substrate 310. In this case, a gate electrode 320 may be formed on the substrate 310 via or through the gate insulating layer 330, and the gate electrode 320 may be configured to provide an input electrode (Vin) to the electrode unit 360, which will be described later. Furthermore, a halide perovskite layer 340, a two-dimensional material layer 350, and the source electrode 360-1 and drain electrode 360-2 of the electrode unit 360 may be formed sequentially on the gate insulating layer 330 and / or the gate electrode 320.

[0078] The semiconductor devices 200 and 300 according to this embodiment do not require the use of a silicon wafer substrate, and are therefore applicable to various substrates, including glass substrates or flexible substrates, and may be particularly suitable for realizing flexible electronic devices.

[0079] Semiconductor devices according to embodiments of the present invention can be applied to a variety of fields. Specifically, by combining the excellent light absorption properties of halide perovskites with the high charge mobility of two-dimensional materials, high-efficiency solar cells, photodetectors, and other optoelectronic devices can be realized. Furthermore, by utilizing properties that enable formation on glass or flexible substrates, they can be applied to flexible electronic devices such as foldable displays and flexible centers. The devices of the present invention can achieve both n-type and p-type properties, enabling their use in CMOS logic circuit configurations. Moreover, by combining the ion migration properties of halide perovskites with the stability of two-dimensional materials, they can also be used as non-volatile memory devices, offering broad applicability in the field of next-generation electronic devices.

[0080] The features, structures, and effects described in the above embodiments are included in at least one embodiment of the present invention, but are not necessarily limited to one embodiment. Furthermore, the features, structures, and effects exemplified in each embodiment can be combined or modified for other embodiments by a person with ordinary skill in the art to which the embodiment belongs. Accordingly, such combinations and modifications should also be interpreted as being within the scope of the present invention.

[0081] Furthermore, although the above embodiments have been described in detail, these are merely examples and do not limit the present invention. A person with ordinary skill in the art to which the present invention belongs will understand that various modifications and applications other than those exemplified above are possible, as long as they do not depart from the essential features of these embodiments. In other words, each component specifically shown in the embodiments can be modified and implemented. Differences relating to such modifications and applications should be interpreted as being within the scope of the present invention as defined in the appended claims. [Explanation of Symbols]

[0082] 100: Semiconductor devices 120: Circuit board 140: Halide perovskite layer 150: Two-dimensional material layer 160: Electrode Unit

Claims

1. It is a semiconductor device, circuit board and A halide perovskite layer formed on the upper surface side of the substrate, A two-dimensional material layer formed on the aforementioned halide perovskite layer, Displaced on the halide perovskite layer, the electrode unit includes a drain electrode and a source electrode, The two-dimensional material layer and the polymer layer formed on the electrode unit are included, The two-dimensional material layer is laminated on the halide perovskite layer, A semiconductor device characterized in that the gap between the two-dimensional material layer and either the drain electrode or the source electrode is adjusted based on a predetermined length, thereby controlling the electrical characteristics of the semiconductor device.

2. The semiconductor device according to claim 1, characterized in that, when the gap between the two-dimensional material layer and either of the electrodes is greater than or equal to the predetermined length, the two-dimensional material layer induces doping of the halide perovskite layer so that relative charge transport occurs through the halide perovskite layer.

3. The semiconductor device according to claim 1, characterized in that when the gap between the two-dimensional material layer and either of the electrodes is less than the predetermined length, a current flow occurs in the two-dimensional material of the two-dimensional material layer.

4. The semiconductor device according to claim 1, characterized in that the predetermined length is within a range of lengths including 50 nm.

5. The halide perovskite layer is MAPbI ４ , ４ , ４ , ４ , ４ , ２ , ２ , ２ , ２ , ２ 、FAPbI ３ 、CsPbI ３ 、RbPbI ３ 、MASnI ３ 、FASnI ３ 、CsSnI ３ 、MAPbBr ３ 、FAPbBr ３ 、CsPbBr ３ 、RbPbBr ３ 、MASnBr ３ 、FASnBr ３ 、CsSnBr ３ 、PEA ２ PbI ４ 、PEA ２ PbBr ４ 、PEA ２ SnI ４ 、PEA ２ SnBr ４ 、BDA ２ PbI ４ 、BDA ２ PbBr ４ 、BDA ２ SnI ４ 、BDA ２ SnBr ４ 、and is selected from the group consisting of combinations thereof, The semiconductor device according to claim 1, characterized in that.

6. The semiconductor device according to claim 1, characterized in that the halide perovskite layer is composed of one of a three-dimensional thin film structure, a two-dimensional thin film structure, or a mixture thereof.

7. The aforementioned two-dimensional material layer is WS ２ MoS ２ , WSe ２ , and MoSe ２ The semiconductor device according to claim 1, characterized by comprising a two-dimensional material comprising one of the transition metal chalcogenide materials selected from h-BN, BP, and MXene.

8. The semiconductor device according to claim 1, characterized in that the drain electrode is connected to the power supply voltage (VDD) and the source electrode is connected to the ground voltage (VSS).

9. The semiconductor device according to claim 8, further comprising a back-side input electrode layer formed on the back side of the substrate, wherein the back-side input electrode layer is configured to provide an input voltage (Vin) to the electrode unit.

10. The semiconductor device according to claim 1, further comprising a gate insulating layer formed between the substrate and the halide perovskite layer, wherein the halide perovskite layer is formed on at least a portion of the surface of the gate insulating layer.

11. The semiconductor device according to claim 1, wherein the substrate is formed of glass or a flexible substrate, and the semiconductor device further includes the halide perovskite layer, the electrode unit, and a gate insulating layer formed on the two-dimensional material layer, and a gate electrode is formed on the gate insulating layer to provide an input electrode (Vin) to the electrode unit.

12. The semiconductor device according to claim 1, characterized in that the substrate is formed of glass or a flexible substrate, the semiconductor device further includes a gate insulating layer formed between the substrate and the halide perovskite layer, a gate electrode is formed on the substrate via the gate insulating layer, and is configured to provide an input electrode (Vin) to the electrode unit.

Images