Gate drive circuit and power converter

Abstract

To provide a gate driving circuit and a power conversion device in which an increase of a circuit scale can be suppressed even if a gate clamp circuit is provided.SOLUTION: A gate driving circuit for driving an insulation gate-type semiconductor switching element (SW1), includes: an off gate circuit (30) that is connected to a gate terminal of the insulation gate-type semiconductor switching element through a gate resistor (Rg), and receives an off driving signal (A) and turns off the insulation gate-type semiconductor switching element in response to the off driving signal; and a gate clamp circuit (100) having a switching element (SW2) that makes a short-circuit between the gate terminal of the insulation gate-type semiconductor switching element and a reference potential terminal, and a driving circuit part (101) that drives the switching element. The driving circuit part receives the off driving signal and drives the switching element.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a gate drive circuit for driving a switching element and a power conversion device including a gate drive circuit for driving a main switching element.

Background Art

[0002] In an insulated gate type semiconductor switching element such as an IGBT or a MOSFET, when a steep voltage is applied in the off state, the gate voltage rises due to the influence of the feedback capacitance. Therefore, there is a risk that the semiconductor switching element may conduct temporarily.

[0003] In the main circuit of a power conversion device, when a circulating current flows through the diode of one arm of the upper and lower arms and the semiconductor switching element of the other arm turns on, in one arm, while the diode recovers, a steep voltage is applied to the semiconductor switching element. In this case, if the semiconductor switching element of one arm conducts temporarily, the power loss of the main circuit increases.

[0004] As a conventional technique for preventing conduction of such a semiconductor switching element, the technique described in Patent Document 1 is known.

[0005] In this conventional technique, a MOSFET that shorts the gate and emitter of an IGBT and clamps the gate voltage is provided in the gate drive circuit of the IGBT while the IGBT is off.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] In the conventional technology described above, a drive circuit requiring a power supply is used to drive the MOSFET, which is a switching element for gate clamping. As a result, the circuit size of the gate drive circuit becomes large.

[0008] Therefore, the present invention provides a gate drive circuit and a power conversion device that can suppress an increase in circuit size while still incorporating a gate clamp circuit. [Means for solving the problem]

[0009] To solve the above problems, the gate drive circuit according to the present invention drives an insulated gate semiconductor switching element and comprises an off-gate circuit connected to the gate terminal of the insulated gate semiconductor switching element via a gate resistor, which receives an off-drive signal and turns off the insulated gate semiconductor switching element in accordance with the off-drive signal; a switch element that short-circuits the gate terminal and a reference potential terminal of the insulated gate semiconductor switching element; and a drive circuit section that drives the switch element. The drive circuit section receives an off-drive signal and drives the switch element.

[0010] Furthermore, the power conversion device according to the present invention comprises a leg consisting of a series connection of arms including an insulated gate type semiconductor switching element, and a gate drive circuit for driving the insulated gate type semiconductor switching element, wherein the gate drive circuit is the gate drive circuit according to the present invention described above. [Effects of the Invention]

[0011] According to the present invention, it is possible to suppress an increase in the circuit size of the gate drive circuit and power converter while still incorporating a gate clamp circuit. [Brief explanation of the drawing]

[0012] [Figure 1] This is a circuit diagram showing the configuration of a gate drive circuit, which is an embodiment of the design. [Figure 2]This is a circuit diagram showing the configurations of an off-gate circuit and a gate clamp circuit in the gate drive circuit of Example 1. [Figure 3] This is a time chart showing the circuit operation of Example 1. [Figure 4] This is a circuit diagram showing the configuration of a gate clamp circuit in the gate drive circuit which is a modification of Example 1. [Figure 5] This is a circuit diagram showing the configurations of an off-gate circuit and a gate clamp circuit in the gate drive circuit of Example 2. [Figure 6] This is a time chart showing the circuit operation of Example 2. [Figure 7] This is a circuit diagram showing the configuration of a gate clamp circuit in the gate drive circuit which is a modification of Example 2. [Figure 8] This is a circuit diagram showing the configuration of a power conversion device of Example 3.

Mode for Carrying Out the Invention

[0013] FIG. 1 is a circuit diagram showing the configuration of a gate drive circuit which is an embodiment of the present invention.

[0014] The gate drive circuit shown in FIG. 1 includes an on-gate circuit 20 that turns on an n-channel insulated gate bipolar transistor SW1 (hereinafter referred to as "IGBT (SW1)") which constitutes the main circuit of the power conversion device, and an off-gate circuit 30 that turns off the IGBT (SW1). The on-gate voltage output by the on-gate circuit 20 and the off-gate voltage output by the off-gate circuit 30 are supplied to the gate of the IGBT (SW1) via a gate resistor Rg.

[0015] The on-gate circuit 20 generates an on-gate voltage from the gate power supply V

[0016] , , , G , ,<00(00087 In this embodiment, the off-gate voltage output by the off-gate circuit 30 is 0V.

[0016] The signal generation circuit 10 generates an on-drive signal B for driving the on-gate circuit 20 and an off-drive signal A for driving the off-gate circuit 30 according to an on / off command signal S from a control circuit (not shown), from a signal power supply V S therefrom.

[0017] Note that the gate power supply V G and the signal power supply V S may be the same power supply.

[0018] As shown in FIG. 1, the gate drive circuit of the present embodiment has a gate clamp circuit 100 that clamps the gate voltage of an IGBT (SW1). The gate clamp circuit 100 includes an N-channel MOS field effect transistor SW2 (hereinafter referred to as "NMOS (SW2)"), which is a switch element that short-circuits between the gate terminal, which is the control terminal of the IGBT (SW1), and the emitter terminal, which is the reference potential terminal, and a drive circuit section 101 that drives the NMOS (SW2).

[0019] The drive circuit section 101 inputs the off-drive signal A together with the off-gate circuit 30. When the IGBT (SW1) is in the off state, the drive circuit section 101 operates by the power of the off-drive signal A to turn on the NMOS (SW2). Thereby, the gate voltage of the IGBT (SW1) is clamped by the NMOS (SW2).

[0020] According to the present embodiment, the drive circuit section 101 in the gate clamp circuit 100 inputs the off-drive signal A of the off-gate circuit 30 and operates by the power of this off-drive signal A. That is, the gate clamp circuit 100 can operate without being connected to a power supply circuit, that is, even without power supply from a power supply circuit. Therefore, according to the present embodiment, it is possible to suppress an increase in the circuit scale of the gate drive circuit while including a gate clamp circuit.

[0021] Furthermore, since the gate clamp circuit 100 clamps the gate voltage of IGBT(SW1) when IGBT(SW1) is in the off state, the operation of the gate clamp circuit 100 does not affect the turn-off characteristics of IGBT(SW1) (turn-off time, turn-off loss, etc.).

[0022] The gate drive circuit according to this embodiment is not limited to IGBTs, but can also be applied to insulated-gate semiconductor switching elements that constitute the main circuit of a power conversion device, such as power MOS field-effect transistors.

[0023] Embodiments of the present invention will be described below with reference to the drawings. In each figure (including Figure 1 mentioned above), elements with the same reference number represent the same or similar functional elements. [Examples]

[0024] Figure 2 is a circuit diagram showing the configuration of the off-gate circuit and gate clamp circuit in the gate drive circuit of Embodiment 1 of the present invention.

[0025] The off-gate circuit 30 includes an n-channel MOS field-effect transistor SWoff (hereinafter referred to as "NMOS(SWoff)") as a switching element that generates the off-gate voltage.

[0026] One end of the gate resistor Rg is connected to the drain terminal of the NMOS(SWoff), and the other end of the gate resistor Rg is connected to the gate terminal of the IGBT(SW1). In other words, the drain terminal of the NMOS(SWoff) is connected to the gate terminal of the IGBT(SW1) via the gate resistor Rg. The source terminal of the NMOS(SWoff) is connected to the emitter terminal of the IGBT(SW1). The off-drive signal A is input to the gate terminal of the NMOS(SWoff).

[0027] In this embodiment 1, the signal generation circuit 10 generates the voltage Vce between the collector terminal, which is the output terminal of the IGBT (SW1), and the emitter terminal, which is the reference potential terminal, from the power supply (indicated as "V" in Figure 1).S It consists of a CMOS circuit as described above. Note that the power supply for the signal generation circuit 10 is not limited to Vce, but may also be supplied by a power supply circuit.

[0028] As shown in Figure 1, in this embodiment 1, the drive circuit section 101 in the gate clamp circuit 100 is configured by an inverting circuit (hereinafter referred to as "CMOS inverting circuit") consisting of complementary MOS field-effect transistor circuits.

[0029] This CMOS inverting circuit consists of a p-channel MOS field-effect transistor QP (hereinafter referred to as "PMOS(QP)") and an n-channel MOS field-effect transistor QN (hereinafter referred to as "NMOS(QN)").

[0030] The PMOS (QP) and NMOS (QN) are connected in series by connecting their respective drain terminals. The off-drive signal A is input to the source terminal of the PMOS (QP). The source terminal of the NMOS (QN) is connected to the source terminal of the NMOS (SWoff) and the emitter terminal of the IGBT (SW1). The gate terminals of the PMOS (QP) and NMOS (QN) are connected to each other to form a common gate terminal. This common gate terminal is connected to the connection point between the gate terminal of the IGBT (SW1) and the gate resistor Rg. The series connection point of the PMOS (QP) and NMOS (QN) is connected to the gate terminal of the NMOS (SW2).

[0031] The common gate terminal of the PMOS (QP) and NMOS (QN) becomes the input terminal IN of the CMOS inverting circuit. Therefore, the voltage Vge between the gate terminal and emitter terminal of the IGBT (SW1) is input to the input terminal IN of the CMOS inverting circuit. Also, the series connection point of the PMOS (QP) and NMOS (QN) becomes the inverting output terminal OUT of the CMOS inverting circuit. Therefore, the NMOS (SW2) is driven by the inverting output of the CMOS inverting circuit.

[0032] In this embodiment 1, the IGBT (SW1) is an NMOS (SW) that is turned on by the off-drive signal A.off ) and turns off by discharging the charge of the gate-emitter capacitance of the IGBT (SW1) through the gate resistor Rg. At this time, Vge decreases toward 0V. Therefore, the voltage level of the input terminal IN of the CMOS inverter circuit transitions from a high level (= the output voltage of the on-gate circuit 20 (FIG. 1)) to a low level. Accordingly, the voltage level of the output terminal OUT of the CMOS inverter circuit is inverted from a low level (= 0V) to a high level (the voltage level of the off-drive signal A). As a result, the NMOS (SW2) is turned on, and the gate voltage of the IGBT (SW1) is clamped.

[0033] By setting the inversion threshold voltage (Vth2) of the CMOS inverter circuit to be equal to or lower than the gate threshold voltage Vth1 of the IGBT (SW1) (Vth2 ≤ Vth1), the gate clamp circuit 100 operates after the IGBT (SW1) is turned off to clamp the gate voltage of the IGBT (SW1). Therefore, the influence of the operation of the gate clamp circuit 100 on the turn-off characteristics (turn-off time, turn-off loss, etc.) of the IGBT (SW1) is prevented. Note that Vth2 is smaller than the voltage of the off-drive signal A.

[0034] Preferably, the inversion threshold voltage (Vth2) of the CMOS inverter circuit is made lower than the gate threshold voltage Vth1 of the IGBT (SW1) (Vth2 < Vth1). Thereby, the gate clamp circuit 100 surely clamps the gate voltage of the IGBT (SW1) after the IGBT (SW1) is turned off.

[0035] FIG. 3 is a time chart showing the circuit operation of the first embodiment.

[0036] The time chart in Figure 3 shows, from top to bottom, the off-drive signal A, the voltage Vge between the gate terminal and emitter terminal of IGBT(SW1) (input voltage (IN) of the CMOS inverting circuit constituting the drive circuit 101), the voltage Vce between the collector terminal and emitter terminal of IGBT(SW1), the collector current Ic of IGBT(SW1), the inverted output voltage (OUT) of the CMOS inverting circuit constituting the drive circuit 101, the on / off state of NMOS(SW2) in the gate clamp circuit, and the drain current Id of NMOS(SW2).

[0037] In the voltage and current time charts, the high (H) and low (L) levels of voltage and current are indicated.

[0038] At time t1, when the off-drive signal A is output from the signal generation circuit 10, the Vge of the IGBT(SW1) begins to decay from a high level (=output voltage of the on-gate circuit 20 (Figure 1)) to a low level (=0V). As described above, Vge decays due to the discharge of charge from the gate-emitter capacitance (Cge (not shown)) of the IGBT(SW1) through the NMOS(SWoff) and gate resistor Rg in the off-gate circuit 30, which is turned on by the off-drive signal A. Therefore, Vge decays with a time constant corresponding to Rg and Cge.

[0039] At time t2, when Vge decreases to the gate threshold voltage Vth1 of IGBT(SW1), IGBT(SW1) turns off and Ic is cut off. After time t2, IGBT(SW1) remains in the off state, and the voltage of the main circuit power supply is applied to IGBT(SW1) as Vce.

[0040] At time t3, when Vge decreases to the inversion threshold voltage Vth2 of the CMOS inverting circuit constituting the drive circuit section 101, the voltage at the output terminal OUT of the CMOS inverting circuit transitions from a low level (=0V) to a high level (=voltage of the off-drive signal A). As a result, the NMOS (SW2) in the gate clamp circuit 100 turns on, and the gate voltage of the IGBT (SW1) is clamped. In this embodiment 1, as shown in Figure 3, Vth2 is smaller than Vth1. This ensures that the gate voltage of the IGBT (SW1) is clamped at the timing after the IGBT (SW1) has turned off.

[0041] At time t4, the signal generation circuit 10 (Figure 1) terminates the output of the off-drive signal A and begins outputting the on-drive signal B to the on-gate circuit 20 (Figure 1). At this time, as the off-drive signal A changes from a high level to a low level (=0V), the voltage at the output terminal OUT of the CMOS inverter circuit also changes from a high level to a low level (=0V). As a result, the NMOS (SW2) in the gate clamp circuit 100 turns off, and the clamping of the gate voltage of the IGBT (SW1) by the gate clamp circuit 100 is stopped.

[0042] Furthermore, at time t4, the gate-emitter capacitance (Cge (not shown)) of IGBT(SW1) is charged by the output voltage of the on-gate circuit 20 (Figure 1), which is driven by the ON drive signal B (Figure 1) from the signal generation circuit 10. As a result, the Vge of IGBT(SW1) increases from a low level (=0V) to a high level (=output voltage of the on-gate circuit 20 (Figure 1)).

[0043] At time t5, when Vge increases to the gate threshold voltage Vth1 of IGBT(SW1), IGBT(SW1) turns on and Ic flows.

[0044] Here, as shown by the dashed line in Figure 3, we assume that Vce increases sharply at time tr while IGBT(SW1) is in the off state (t3~t4). In this case, a current of a magnitude corresponding to the rate of change of Vce over time (dVce / dt) flows through the feedback capacitance of IGBT(SW1) (i.e., the parasitic capacitance between the collector and gate). In this embodiment, since the NMOS(SW2) in the gate clamp circuit 100 is in the ON state while IGBT(SW1) is in the off state (t3~t4), the current flowing through the feedback capacitance is bypassed by NMOS(SW2), as shown by Id (dashed line) in Figure 3. This prevents Vge from rising, thus preventing IGBT(SW1) from temporarily conducting.

[0045] As described above, according to this embodiment 1, the inverting circuit constituting the drive circuit section 101 that drives the NMOS(SW2) in the gate clamp circuit 100 receives an off-drive signal A that drives the off-gate circuit 30. The drive circuit section 101 operates using the power of this off-drive signal A without having a power supply circuit. Therefore, according to this embodiment 1, it is possible to suppress an increase in the circuit size of the gate drive circuit while still having a gate clamp circuit.

[0046] Figure 4 is a circuit diagram showing the configuration of a gate clamp circuit in a gate drive circuit, which is a modified example of Example 1. The differences from Example 1 (Figure 2) will be explained below.

[0047] In this modified example, the drive circuit section 101 in the gate clamp circuit 100 is composed of an inverting circuit. Unlike in Example 1 (Figure 2), this inverting circuit is composed of a series connection circuit of an n-channel MOS field-effect transistor QN (hereinafter referred to as "NMOS(QN)") and a load resistor RL.

[0048] As shown in Figure 4, the drain terminal of the NMOS(QN) is connected to one end of the load resistor RL, thereby connecting the load resistor RL and the NMOS(QN) in series. An off-drive signal A is input to the other end of the load resistor RL. The gate terminal of the NMOS(QN) becomes the input terminal of the inverting circuit, and the series connection point of the load resistor RL and the NMOS(QN) becomes the inverting output terminal OUT of the inverting circuit.

[0049] The circuit operation of this modified example is the same as in Example 1 (see Figure 3).

[0050] According to this modified example, similar to Example 1, it is possible to suppress an increase in the circuit size of the gate drive circuit while still including a gate clamp circuit. [Examples]

[0051] Figure 5 is a circuit diagram showing the configuration of the off-gate circuit and gate clamp circuit in the gate drive circuit of Embodiment 2 of the present invention. The following mainly describes the differences from Embodiment 1 (Figure 2).

[0052] In this second embodiment, the drive circuit section 101 in the gate clamp circuit 100 is composed of a delay circuit consisting of a resistor R and a capacitor C (hereinafter referred to as a "CR delay circuit").

[0053] As shown in Figure 5, in this CR delay circuit, resistor R and capacitor C are connected in series by connecting one end of resistor R to one end of capacitor C. The other end of resistor R is input to the off-drive signal A. That is, the other end of resistor R becomes the input terminal IN. The other end of capacitor C is connected to the source terminal of NMOS (SW2). The point where resistor R and capacitor C are connected in series becomes the output terminal OUT, which outputs the delayed off-drive signal A.

[0054] Furthermore, the cathode and anode terminals of diode D are connected to one end (input terminal IN) and the other end (output terminal OUT) of resistor R, respectively. In other words, diode D is connected in parallel with resistor R in the direction that allows the discharge current of capacitor C to flow. This allows capacitor C to discharge quickly at the end of gate clamping, regardless of the time constant of the CR delay circuit.

[0055] In this embodiment 2, the NMOS(SW2) is driven by a drive signal obtained by delaying the off-drive signal A, which drives the off-gate circuit 30, according to the time constant of the CR delay circuit. As a result, when the IGBT(SW1) is in the off state, the gate voltage of the IGBT(SW1) is clamped.

[0056] According to this embodiment 2, the CR delay circuit operates using the power of the off-drive signal A without requiring a power supply circuit. Furthermore, the diode D operates using the charging voltage of the capacitor C during gate clamping. Therefore, according to this embodiment 2, it is possible to suppress an increase in the circuit size of the gate drive circuit while still including a gate clamping circuit.

[0057] Figure 6 is a time chart showing the circuit operation of this embodiment 2.

[0058] The time chart in Figure 6 shows, from top to bottom, the off-drive signal A (input voltage (IN) of the CR delay circuit constituting the drive circuit 101), the voltage Vge between the gate terminal and emitter terminal of IGBT(SW1), the voltage Vce between the collector terminal and emitter terminal of IGBT(SW1), the collector current Ic of IGBT(SW1), the output voltage (OUT) of the CR delay circuit constituting the drive circuit 101, the on / off state of NMOS(SW2) in the gate clamp circuit, and the drain current Id of NMOS(SW2).

[0059] The following will mainly explain the differences from Example 1 (Figure 3).

[0060] Similar to Example 1, when the off-drive signal A is output from the signal generation circuit 10 at time t1, the Vge of the IGBT (SW1) begins to decay from a high level (=output voltage of the on-gate circuit 20 (Figure 1)) to a low level (=0V).

[0061] Furthermore, in this embodiment 2, as shown in Figure 6, when the CR delay circuit receives the off-drive signal A at time t1, the output voltage (OUT) of the CR delay circuit increases according to the time constant of the CR delay circuit.

[0062] Similar to Example 1, at time t2, when Vge decreases to the gate threshold voltage Vth1 of IGBT(SW1), IGBT(SW1) turns off and Ic is blocked. After time t2, IGBT(SW1) is in the off state, and the voltage of the main circuit power supply is applied to IGBT(SW1) as Vce.

[0063] At time t3, when the output voltage (OUT) of the CR delay circuit increases to the gate threshold voltage Vth3 of NMOS(SW2), NMOS(SW2) transitions from the OFF state to the ON state. As a result, the gate voltage of IGBT(SW1) is clamped with a time delay td from the rising edge (t1) of the off-drive signal A. In other words, the gate voltage of IGBT(SW1) is clamped while IGBT(SW1) is in the OFF state. Note that Vth3 is smaller than the voltage of the off-drive signal A.

[0064] The circuit operation from time t3 onward, as well as the circuit operation at time tr in Figure 6, is the same as in Example 1 (Figure 3).

[0065] In this embodiment 2, the time constant of the CR delay circuit is greater than the turn-off time of the IGBT(SW1). This allows the clamping of the gate voltage of the IGBT(SW1) to begin after the IGBT(SW1) has turned off. Therefore, the influence of the gate clamp circuit 100's operation on the turn-off characteristics of the IGBT(SW1) is prevented.

[0066] Preferably, the time constant of the CR delay circuit is set based on the voltage of the off-drive signal A, the gate threshold voltage Vth3 of the NMOS (SW2), and the turn-off time of the IGBT (SW1), such that the output voltage (OUT) of the CR delay circuit becomes equal to Vth3 when the turn-off time of the IGBT (SW1) has elapsed from the start of the increase (t1). In this case, for example, the time constant can be set by considering the transient response of the CR series circuit. This ensures that the clamping of the gate voltage of the IGBT (SW1) starts after the IGBT (SW1) is turned off.

[0067] In this embodiment 2, the NMOS(SW2) is driven by a drive signal obtained by delaying the off-drive signal A, which drives the off-gate circuit 30, according to the time constant of the CR delay circuit. As a result, when the IGBT(SW1) is in the off state, the gate voltage of the IGBT(SW1) is clamped.

[0068] According to this embodiment 2, the CR delay circuit operates using the power of the off-drive signal A without requiring a power supply circuit. Furthermore, the diode D operates using the charging voltage of the capacitor C during gate clamping. Therefore, according to this embodiment 2, it is possible to suppress an increase in the circuit size of the gate drive circuit while still including a gate clamping circuit.

[0069] As described above, according to this embodiment 2, the CR delay circuit constituting the drive circuit section 101 that drives the NMOS(SW2) in the gate clamp circuit 100 receives an off-drive signal A that drives the off-gate circuit 30. The drive circuit section 101 operates using the power of this off-drive signal A without having a power supply circuit. Therefore, according to this embodiment 1, it is possible to suppress an increase in the circuit size of the gate drive circuit while still having a gate clamp circuit.

[0070] Figure 7 is a circuit diagram showing the configuration of a gate clamp circuit in a gate drive circuit, which is a modified example of Example 2. The differences from Example 2 (Figure 5) will be explained below.

[0071] In this modified example, the drive circuit section 101 in the gate clamp circuit 100 is composed of a delay circuit consisting of a series connection of multiple (but an even number) CMOS inverting circuits.

[0072] As shown in Figure 7, the m-th stage (where m is a natural number: 1 ≤ m ≤ 2n (where n is a natural number)) of the CMOS inverting circuit consists of a p-channel MOS field-effect transistor QPm (hereinafter referred to as "PMOS(QPm)") and an n-channel MOS field-effect transistor QNm (hereinafter referred to as "NMOS(QNm)").

[0073] The PMOS (QPm) and NMOS (Qm) transistors are connected in series by connecting their respective drain terminals. The gate terminals of the PMOS (QPm) and NMOS (QNm) transistors are connected to each other to form a common gate terminal. This common gate terminal becomes the input terminal of the m-th stage CMOS circuit. Furthermore, the series connection point of the PMOS (QPm) and NMOS (QNm) transistors becomes the inverting output terminal of the m-th stage CMOS inverting circuit.

[0074] By connecting the input terminal of the (m+1)-stage CMOS inverting circuit to the output terminal of the m-stage CMOS inverting circuit, 2n CMOS inverting circuits are connected in series. The source terminals of the 2n PMOS (QPm) are connected to each other and also to the input terminal IN of the delay circuit. In addition, the source terminals of the 2n NMOS (QNm) are connected to each other and also to the source terminal of the NMOS (SW2) (see Figure 5).

[0075] The input terminal of the first-stage CMOS circuit becomes the input terminal IN of the delay circuit, and the output terminal of the 2n-stage CMOS inverting circuit becomes the output terminal OUT of the delay circuit. When an off-drive signal A is input to the input terminal, a signal obtained by delaying the off-drive signal A according to the number of CMOS inverting circuits is output from the output terminal OUT.

[0076] In this modified example, since there is an even number of CMOS inverting circuits, the signal output from the output terminal OUT is a non-inverting signal. Therefore, by driving the NMOS (SW2) with the signal output from the output terminal OUT, the gate voltage of the IGBT (SW1) is clamped when the IGBT (SW1) is in the off state.

[0077] The circuit operation of this modified example is the same as in Example 2, except for the output voltage (OUT) of the delay circuit constituting the drive circuit section 101 (see Figure 6).

[0078] In this modified example, the output voltage (OUT) of the delay circuit constituting the drive circuit section 101 rises at time t3, similar to the on / off time chart of the NMOS (SW2) shown in Figure 6 above.

[0079] As shown in Figure 6, the time td from the point t1 when the off-drive signal A rises to the point t3 when the NMOS (SW2) transitions to the ON state is set in this modified example by a delay circuit consisting of 2n CMOS circuits. By making the delay time of the delay circuit greater than the turn-off time of the IGBT (SW1), the gate voltage of the IGBT (SW1) is reliably clamped after the IGBT (SW1) is turned off. Therefore, the influence of the gate clamp circuit 100 on the turn-off characteristics of the IGBT (SW1) is prevented.

[0080] In this embodiment, the delay circuit operates using the power of the off-drive signal A without having a power supply circuit. Therefore, according to this modification, similar to Embodiment 2, it is possible to suppress an increase in the circuit size of the gate drive circuit while still having a gate clamp circuit. [Examples]

[0081] Figure 8 is a circuit diagram showing the configuration of a power conversion device according to Embodiment 3 of the present invention.

[0082] The power converter 60 has two arms, each in which an IGBT and a freewheeling diode are connected in parallel, and three legs in series, corresponding to the number of phases of the AC current, in this embodiment 3.

[0083] The series connection of the upper arm for the U-phase, in which the IGBT (SW11) and freewheeling diode D11 are connected in parallel, and the lower arm for the U-phase, in which the IGBT (SW12) and freewheeling diode D12 are connected in parallel, constitutes the U-phase leg.

[0084] The V-phase leg is formed by a series connection between the upper arm for the V-phase, in which the IGBT (SW13) and freewheeling diode D13 are connected in parallel, and the lower arm for the V-phase, in which the IGBT (SW14) and freewheeling diode D14 are connected in parallel.

[0085] The W-phase leg is formed by a series connection between the upper arm for the W phase, which consists of an IGBT (SW15) and a freewheeling diode D15 connected in parallel, and the lower arm for the W phase, which consists of an IGBT (SW16) and a freewheeling diode D16 connected in parallel.

[0086] The DC connection points of the upper and lower arms in the U-phase leg, V-phase leg, and W-phase leg are connected to the U-phase AC terminal U, the V-phase AC terminal V, and the W-phase AC terminal W, respectively.

[0087] Of the two ends of the U-phase, V-phase, and W-phase legs, one end on the upper arm side is connected to the positive DC terminal P. The other end of the U-phase, V-phase, and W-phase legs, on the lower arm side, is connected to the negative DC terminal N.

[0088] In this embodiment 3, three-phase AC motors 58 are connected to the U-phase AC terminal U, the V-phase AC terminal V, and the W-phase AC terminal W. For example, a three-phase induction motor or a three-phase synchronous motor can be used as the three-phase AC motor 58. In addition, a DC power supply 70 is connected to the positive DC terminal P and the negative DC terminal N.

[0089] Gate drive circuits 81, 82, 83, 84, 85, and 86 are connected between the gate terminal and emitter terminal of IGBT(SW11), IGBT(SW12), IGBT(SW13), IGBT(SW14), IGBT(SW15), and IGBT(SW16), respectively.

[0090] In response to a control command signal (e.g., a PWM control command signal) from a control device (not shown), gate drive circuits 81, 82, 83, 84, 85, and 86 drive IGBTs (SW11), (SW12), (SW13), (SW14), (SW15), and (SW16) on and off, respectively. As a result, the power converter 60 converts the DC power from the DC power supply 70 into three-phase AC power and outputs this three-phase AC power from the AC terminals (U, V, W). The three-phase AC motor 58 is rotated by the three-phase AC power output from the power converter 60.

[0091] As gate drive circuits 81 to 86, any of the gate drive circuits described above (Figure 1), Example 1 (Figure 2), modified example of Example 1 (Figure 4), Example 2 (Figure 5), or modified example of Example 2 (Figure 7) will be applied.

[0092] The gate clamp circuits provided by the gate drive circuits 81-86 prevent the IGBT from temporarily conducting when the recirculation diode connected in parallel to an IGBT that is in the off state on one of the two arms constituting a leg reverses, causing the gate voltage of the IGBT to rise. Therefore, the increase in power loss and the decrease in operational reliability of the power converter due to the temporary conduction of the IGBT are prevented.

[0093] Furthermore, each gate clamp circuit operates using the power of the drive signal that drives the off-gate circuit, without requiring a separate power supply circuit. This suppresses the increase in circuit size for each gate drive circuit, even while incorporating a gate clamp circuit. Consequently, the increase in circuit size of the power converter is also suppressed.

[0094] The power converter 60 may be composed of a semiconductor integrated circuit. In this case, each gate drive circuit is equipped with a gate clamp circuit, while the increase in the semiconductor chip size on which the integrated circuit is formed is suppressed. The gate drive circuits 81 to 86 may also be composed of semiconductor integrated circuits. In this case as well, the increase in the semiconductor chip size is suppressed.

[0095] Alternatively, a power MOS field-effect transistor may be used instead of an IGBT. In the case of a power MOS field-effect transistor, the body diode can be used as a freewheeling diode.

[0096] It should be noted that the present invention is not limited to the embodiments described above, and various modifications are included. For example, the embodiments described above are described in detail to make the present invention easier to understand, and are not necessarily limited to those having all the configurations described. In addition, some of the configurations in each embodiment can be deleted, other configurations can be added, or other configurations can be replaced. [Explanation of Symbols]

[0097] 10 signal generation circuit, 20 On-gate circuits, 30 Off-gate circuits, 58 Three-phase AC motor, 60 Power converters, 70 DC power supply, 100 gate clamp circuits, 101 Drive circuit section

Claims

1. In a gate drive circuit for driving an insulated gate semiconductor switching element, An off-gate circuit is connected to the gate terminal of the insulated-gate semiconductor switching element via a gate resistor, receives an off-drive signal, and turns off the insulated-gate semiconductor switching element in response to the off-drive signal. A gate clamp circuit having a switch element that short-circuits the gate terminal and a reference potential terminal of the insulated gate type semiconductor switching element, and a drive circuit section that drives the switch element, Equipped with, The drive circuit section has an inverting circuit composed of a complementary MOS field-effect transistor inverting circuit that operates with the power of the off-drive signal, The input terminal of the inverting circuit is connected to the connection point between the gate terminal of the insulated gate semiconductor switching element and the gate resistor. The gate drive circuit is characterized in that the switch element is driven by the inverting output of the inverting circuit.

2. A gate drive circuit for driving an insulated gate type semiconductor switching element, An off-gate circuit is connected to the gate terminal of the insulated-gate semiconductor switching element via a gate resistor, receives an off-drive signal, and turns off the insulated-gate semiconductor switching element in response to the off-drive signal. A gate clamp circuit having a switch element that short-circuits the gate terminal and a reference potential terminal of the insulated gate type semiconductor switching element, and a drive circuit section that drives the switch element, Equipped with, The drive circuit section has an inverting circuit that operates using the power of the off-drive signal, The inverting circuit has a series connection circuit of a MOS field-effect transistor and a load resistor, the gate terminal of the MOS field-effect transistor is the input terminal, and the series connection point of the MOS field-effect transistor and the load resistor is the inverting output terminal. The input terminal of the inverting circuit is connected to the connection point between the gate terminal of the insulated gate semiconductor switching element and the gate resistor. The gate drive circuit is characterized in that the switch element is driven by the inverting output of the inverting circuit.

3. In the gate drive circuit according to claim 1 or 2, A gate drive circuit characterized in that the inversion threshold voltage of the inverting circuit is less than or equal to the gate threshold voltage of the insulated gate semiconductor switching element.

4. A gate drive circuit for driving an insulated gate type semiconductor switching element, An off-gate circuit is connected to the gate terminal of the insulated-gate semiconductor switching element via a gate resistor, receives an off-drive signal, and turns off the insulated-gate semiconductor switching element in response to the off-drive signal. A gate clamp circuit having a switch element that short-circuits the gate terminal and a reference potential terminal of the insulated gate type semiconductor switching element, and a drive circuit section that drives the switch element, Equipped with, The drive circuit section has a delay circuit, The delay circuit receives the off-drive signal as input and outputs a signal that is a delayed version of the off-drive signal to drive the switch element. The delay circuit is a gate drive circuit characterized by having an even number of complementary MOS field-effect transistor inverting circuits connected in series.

5. A power conversion device having a leg consisting of a series connection of arms including an insulated gate semiconductor switching element, and a gate drive circuit for driving the insulated gate semiconductor switching element, A power conversion device characterized in that the gate drive circuit is a gate drive circuit described in any one of claims 1 to 2 or 4.

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