Filters, multiplexers, and communication modules

Abstract

To provide a filter capable of suppressing change in attenuation characteristics.SOLUTION: A filter comprises: a first resonance circuit that has a first capacitor C1 and a first inductor L1 connected in parallel with each other between a ground terminal Tg and a first node N1 connected with a first signal terminal not via a capacitor, with an inductor not connected in series with the first capacitor between the first node and the ground terminal; a second resonance circuit that has a second capacitor C4 and a second inductor L4 connected in parallel with each other between the ground terminal and a second node N4 connected with a second signal terminal not via a capacitor; and a third resonance circuit that has a third capacitor C3 and a third inductor L3 connected in parallel with each other between the ground terminal and a third node N3 located within a path SL that can transmit a high-frequency signal between the first node and the second node, and a first serial inductor L7 connected in series with the third capacitor between the third node and the ground terminal.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a filter, a multiplexer, and a communication module, for example, a filter, a multiplexer, and a communication module having a parallel resonance circuit.

Background Art

[0002] Filters for removing unnecessary interference waves are used in wireless communication terminals such as LTE (Long Term Evolution) and 5G (5th Generation) mobile communication systems. As a filter, a filter having a plurality of LC parallel resonance circuits between a path for transmitting a high-frequency signal and a ground terminal is known. It is known to provide an LC sub-parallel resonance circuit between the plurality of LC parallel resonance circuits and the ground terminal (Patent Document 1). It is known to connect an inductor in series to the capacitors of the plurality of LD parallel resonance circuits.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] In Patent Documents 1 and 2, the frequency of the attenuation pole located at a frequency higher than the passband can be adjusted. However, in Patent Document 1, when attempting to adjust the frequency of the attenuation pole, the attenuation characteristics at frequencies lower than the passband change. In Patent Document 2, when attempting to adjust the frequency of the attenuation pole, the attenuation characteristics in the frequency range higher than the attenuation pole deteriorate.

[0005] This invention has been made in view of the above problems, and aims to suppress changes in other attenuation characteristics when adjusting the frequency of the attenuation pole. [Means for solving the problem]

[0006] The present invention comprises a first resonant circuit comprising a first signal terminal, a second signal terminal, a ground terminal, a first capacitor and a first inductor connected in parallel between a first node electrically connected to the first signal terminal without a capacitor and the ground terminal, wherein no inductor is connected in series with the first capacitor between the first node and the ground terminal, a second resonant circuit comprising a second capacitor and a second inductor connected in parallel between a second node electrically connected to the second signal terminal without a capacitor and the ground terminal, a third capacitor and a third inductor connected in parallel between a third node located in a path where a high-frequency signal can be transmitted between the first node and the second node and the ground terminal, and the third A filter comprising: a first series inductor connected in series with a capacitor; a third resonant circuit comprising a plurality of dielectric layers stacked, the first series inductor including a first line pattern provided on a first surface between adjacent dielectric layers among the plurality of dielectric layers; the first resonant circuit being connected in series with the first capacitor between the first node and the ground terminal and not comprising a line pattern provided on a surface between the plurality of dielectric layers; the third inductor being provided on a second surface different from the first surface and provided between adjacent dielectric layers among the plurality of dielectric layers, electrically connected to the first line pattern via via wiring penetrating at least one dielectric layer among the plurality of dielectric layers, and including a second line pattern extending in a direction intersecting the direction in which the first line pattern extends.

[0007] In the above configuration, the second resonant circuit may be configured such that no inductor is connected in series with the second capacitor between the second node and the ground terminal.

[0008] In the above configuration, a plurality of dielectric layers are stacked, the first series inductor includes a first transmission line pattern provided on the first surface between adjacent dielectric layers, and the first resonant circuit is connected in series with the first capacitor between the first node and the ground terminal and does not include a transmission line pattern provided on the surface between the plurality of dielectric layers.

[0010] In the above configuration, the first inductor and at least of the two added inductors on the other hand The inductor can be configured to include a third line pattern provided on the first surface.

[0011] In the above configuration, a fourth resonant circuit can be provided, comprising a fourth capacitor and a fourth inductor connected in parallel between a fourth node located between the third node and the second node in the path and the ground terminal, and a second series inductor connected in series with the fourth capacitor between the fourth node and the ground terminal.

[0012] In the above configuration, the first node and the third node are electrically connected via a fifth capacitor, and the second node and the third node are electrically connected via a sixth capacitor.

[0013] In the above configuration, the filter can be configured as a bandpass filter.

[0014] In the above configuration, the first capacitor, the second capacitor, and the third capacitor, and the inductance component between the first capacitor, the second capacitor, and the third capacitor and the ground terminal, can be configured to form an attenuation pole at a frequency higher than the passband of the filter.

[0015] The present invention is a multiplexer including the above-mentioned filter.

[0016] The present invention is a communication module including the above filter.

Effects of the Invention

[0017] According to the present invention, a filter, a multiplexer, and a communication module having desired frequency characteristics can be provided.

Brief Description of the Drawings

[0018] [Figure 1] FIG. 1 is a circuit diagram of the filter according to Example 1. [Figure 2] FIGS. 2(a) and 2(b) are perspective and cross-sectional views of the filter according to Example 1. [Figure 3] FIG. 3 is an exploded perspective view of the dielectric layer in Example 1. [Figure 4] FIG. 4 is an exploded perspective view of the dielectric layer in Example 1. [Figure 5] FIG. 5 is a circuit diagram of the filter according to Comparative Example 1. [Figure 6] FIG. 6 is an exploded perspective view of the dielectric layer in Comparative Example 1. [Figure 7] FIG. 7 is an exploded perspective view of the dielectric layer in Comparative Example 1. <� [Figure 8] FIG. 8 is a diagram showing the passing characteristics of Example 1 and Comparative Example 1 in Simulation 1. [Figure 9] FIG. 9 is a diagram showing the passing characteristics of Comparative Example 2 and Comparative Example 1 in Simulation 2. [Figure 10] FIG. 10 is a circuit diagram of the filter according to Comparative Example 3. [Figure 11] FIG. 11 is an exploded perspective view of the dielectric layer in Comparative Example 3. [Figure 12] FIG. 12 is an exploded perspective view of the dielectric layer in Comparative Example 3. [Figure 13] FIG. 13 is a diagram showing the passing characteristics of Comparative Example 3 and Comparative Example 1 in Simulation 3. [Figure 14]Figure 14 is a circuit diagram of the filter according to Comparative Example 4. [Figure 15] Figure 15 is a perspective view of the disassembled dielectric layer in Comparative Example 4. [Figure 16] Figure 16 is a perspective view of the disassembled dielectric layer in Comparative Example 4. [Figure 17] Figure 17 shows the transmission characteristics of Comparative Example 4 and Comparative Example 1 in Simulation 4. [Figure 18] Figure 18 is a circuit diagram of a filter according to a modified example 1 of Example 1. [Figure 19] Figure 19 is a perspective view of the disassembled dielectric layer in Modification 1 of Example 1. [Figure 20] Figure 20 is a perspective view of the disassembled dielectric layer in Modification 1 of Example 1. [Figure 21] Figure 21 shows the passage characteristics of Modification 1 and Comparative Example 1 of Example 1 in Simulation 5. [Figure 22] Figure 22 is a circuit diagram of a filter according to a modified example 2 of Example 1. [Figure 23] Figure 23 is a circuit diagram of the triplexer according to Example 2. [Figure 24] Figure 24 is a circuit diagram of a communication module according to a modified example 1 of Embodiment 2. [Modes for carrying out the invention]

[0019] The embodiments of the present invention will be described below with reference to the drawings. [Examples]

[0020] As Example 1, a bandpass filter (BPF) will be described as an example. Figure 1 is a circuit diagram of the filter according to Example 1. As shown in Figure 1, the filter 100 of Example 1 has an input terminal Tin, an output terminal Tout, a ground terminal Tg, capacitors C1 to C7, and inductors L1 to L7. The high-frequency signal input from the input terminal Tin is output from the output terminal Tout via the path SL. The path SL consists of a capacitor C5 and inductors. L2This includes a portion of inductor L5, a portion of inductor L3, and capacitor C6. Nodes N1 to N4 are located within path SL.

[0021] A parallel resonant circuit R1 is provided between node N1 and the ground terminal Tg. The parallel resonant circuit R1 has an inductor L1 and a capacitor C1 connected in parallel between node N1 and the ground terminal Tg. A parallel resonant circuit R2 is provided between node N2 and the ground terminal Tg. The parallel resonant circuit R2 has an inductor L2 and a capacitor C2 connected in parallel between node N2 and the ground terminal Tg. A parallel resonant circuit R3 is provided between node N3 and the ground terminal Tg. The parallel resonant circuit R3 has an inductor L3 and a capacitor C3 connected in parallel between node N3 and the ground terminal Tg. A parallel resonant circuit R4 is provided between node N4 and the ground terminal Tg. The parallel resonant circuit R4 has an inductor L3 and a capacitor C3 connected in parallel between node N3 and the ground terminal Tg. N4 It has an inductor L4 and a capacitor C4 connected in parallel between it and the ground terminal Tg.

[0022] The parallel resonant circuit R2 includes an inductor L6 connected in series with capacitor C2 between node N2 and ground terminal Tg. The parallel resonant circuit R3 includes an inductor L7 connected in series with capacitor C3 between node N3 and ground terminal Tg.

[0023] Node N1 is directly connected to the input terminal Tin. That is, there is no capacitor between node N1 and the input terminal Tin. Node N4 is directly connected to the output terminal Tout. That is, there is no capacitor between node N4 and the output terminal Tout. Capacitor C5 is provided between nodes N1 and N2, with one end of capacitor C5 electrically connected to node N1 and the other end electrically connected to node N2. Capacitor C6 is provided between nodes N3 and N4, with one end of capacitor C6 electrically connected to node N4 and the other end electrically connected to node N3. There is no capacitor between nodes N2 and N3. Capacitor C7 is connected in parallel to path SL between nodes N1 and N4. Inductors L1 and L2 are magnetically coupled M1, and inductors L3 and L4 are magnetically coupled M2.

[0024] Figures 2(a) and 2(b) are perspective and cross-sectional views of the filter according to Embodiment 1. The stacking direction of the dielectric layers 11a to 11i is the Z direction, the arrangement direction of the terminals 14 in the planar direction of the dielectric layers 11a to 11i is the X direction, and the direction perpendicular to the X direction is the Y direction. As shown in Figures 2(a) and 2(b), the filter 100 has a laminate 10. The laminate 10 comprises a plurality of stacked dielectric layers 11a to 11i. Terminals 14 are provided on the lower surface of the laminate 10 (the surface of the laminate 10 in the stacking direction). The terminals 14 are, for example, an input terminal Tin, an output terminal Tout, and a ground terminal Tg. Direction identification marks are provided on the upper surface of the laminate 10 by a conductive pattern 12a.

[0025] Figures 3 and 4 are disassembled perspective views of the dielectric layers in Example 1. In Figures 3 and 4, via wirings 13b to 13i that penetrate each dielectric layer 11b to 11i are indicated by black circles on the upper surface of each dielectric layer 11b to 11i. If via wirings 13b to 13g that penetrate the dielectric layer directly above 11b to 11g do not penetrate the corresponding dielectric layer 11c to 11i, they are indicated by white circles. As shown in Figures 3 and 4, conductive patterns 12a to 12i are provided on the upper surface of dielectric layers 11a to 11i, respectively. Via wirings 13b to 13i are provided that penetrate each dielectric layer 11b to 11i, respectively. A terminal 14 is provided on the lower surface of dielectric layer 11i.

[0026] A conductive pattern 12a is provided on the upper surface of the dielectric layer 11a to form direction identification marks. A conductive pattern 12b is provided on the upper surface of the dielectric layer 11b to form line patterns L1a to L4a. A conductive pattern 12c is provided on the upper surface of the dielectric layer 11c to form line patterns L2b, L5a and L3b. A conductive pattern 12c is provided on the upper surface of the dielectric layer 11d to form line patterns L1b, L4b, L6a and L7a. 12d A system is in place.

[0027] Inductor L1 is formed by line patterns L1a, L1b and via wirings 13b to 13i. Inductor L2 is formed by line patterns L2a, L2b and via wirings 13b to 13i. Inductor L3 is formed by line patterns L3a, L3b and via wirings 13b to 13i. Inductor L4 is formed by line patterns L4a, L4b and via wirings 13b to 13i. Inductor L5 is formed by line pattern L5a. Inductor L6 is formed by line pattern L6a and via wirings 13d to 13g. Inductor L7 is formed by line pattern L7a and via wirings 13d to 13g.

[0028] A conductive pattern 12e is provided on the upper surface of the dielectric layer 11e to form electrode C7a. A conductive pattern 12f is provided on the upper surface of the dielectric layer 11f to form electrodes C5a, C6a, and C7b. A conductive pattern 12g is provided on the upper surface of the dielectric layer 11g to form electrodes C5b and C6b. A conductive pattern 12h is provided on the upper surface of the dielectric layer 11h to form electrodes C1a, C2a, C3a, C4a, C5c, and C6c. A conductive pattern 12i is provided on the upper surface of the dielectric layer 11i, which is electrodes C1b, C2b, C3b, and C4b and also forms a ground pattern G.

[0029] Capacitor C1 is formed by electrodes C1a and C1b sandwiching the dielectric layer 11h. Capacitor C2 is formed by electrodes C2a and C2b sandwiching the dielectric layer 11h. Capacitor C3 is formed by electrodes C3a and C3b sandwiching the dielectric layer 11h. Capacitor C4 is formed by electrodes C4a and C4b sandwiching the dielectric layer 11h. Capacitor C5 is formed by electrodes C5a and C5b sandwiching the dielectric layer 11f and electrodes C5b and C5c sandwiching the dielectric layer 11g. Capacitor C6 is formed by electrodes C6a and C6b sandwiching the dielectric layer 11f and electrodes C6b and C6c sandwiching the dielectric layer 11g. Capacitor C7 is formed by electrodes C7a and C7b sandwiching the dielectric layer 11e. A terminal 14 is formed on the lower surface of the dielectric layer 11i. Terminal 14 includes an input terminal Tin, an output terminal Tout, and a ground terminal Tg.

[0030] One end of line pattern L1a is electrically connected to electrode C1a (corresponding to node N1) and input terminal Tin via via wirings 13b to 13i. In this way, electrode C1a of capacitor C1 and input terminal Tin are electrically connected without passing through a line pattern. One end of line pattern L2a is electrically connected to electrode C5b (corresponding to node N2) via via wirings 13b to 13f, and is also electrically connected to electrode C2a via line pattern L6a and via wirings 13d to 13g. In this way, electrode C2a of capacitor C2 is electrically connected to electrode C5b, which corresponds to node N2, via line pattern L6a. Similarly to capacitor C2, electrode C3a of capacitor C3 is electrically connected to electrode C6b, which corresponds to node N3, via line pattern L7a. Similar to capacitor C1, electrode C4a of capacitor C4 and output terminal Tout are electrically connected without passing through a line pattern.

[0031] The dielectric layers 11a to 11i are made of ceramic material and mainly contain oxides of Si, Ca, and Mg (for example, diopside crystals such as CaMgSi2O6). The main components of dielectric layers 11a to 11i may also be oxides other than Si, Ca, and / or Mg. Furthermore, dielectric layers 11a to 11h may contain at least one oxide of Ti, Zr, and Al as an insulating material.

[0032] The conductive patterns 12a to 12i, via wirings 13b to 13i, and the upper part of terminal 14 are metal layers mainly composed of, for example, Ag, Pd, Pt, Cu, Ni, Au, Au-Pd alloy, or Ag-Pt alloy. The upper part of terminal 14 may also contain nonconductive materials such as TiO2, ZrO2, or Al2O3 in addition to the above metal materials. The lower part of terminal 14 is a Ni film and a Sn film.

[0033] [Comparative Example 1] Figure 5 is a circuit diagram of the filter according to Comparative Example 1. As shown in Figure 5, in the filter 110 of Comparative Example 1, the inductor L6 connected in series with capacitor C2 is not provided in the parallel resonant circuit R2. In the parallel resonant circuit R3, the inductor L7 connected in series with capacitor C3 is not provided. An inductor L10 is provided between the parallel resonant circuits R1 to R4 and the ground terminal Tg. The other circuit configurations are the same as in Figure 1 of Example 1.

[0034] Figures 6 and 7 are disassembled perspective views of the dielectric layer in Comparative Example 1. As shown in Figures 6 and 7, no line patterns L6a and L7a are provided on the upper surface of the dielectric layer 11d. One end of line pattern L2a is electrically connected to electrode C5b via via wirings 13b to 13g, and electrode C2a is also electrically connected. Thus, electrode C2a of capacitor C2 is electrically connected to electrode C5b, which corresponds to node N2, without going through a line pattern. Similarly, electrode C3a of capacitor C3 is electrically connected to electrode C6b, which corresponds to node N3, without going through a line pattern. The via wiring 13i that electrically connects the ground pattern G formed by the conductive pattern 12i to the ground terminal Tg corresponds to inductor L10. The other configurations are the same as in Figures 3 and 4 of Example 1.

[0035] [Simulation 1] For Example 1 and Comparative Example 1, a three-dimensional electromagnetic field simulation was performed using the finite element method to calculate the transmission characteristics.

[0036] Each dielectric layer 11a to 11i is mainly composed of CaMgSi2O6. Because the filter 100 handles high frequencies from 1 GHz to 20 GHz, the filter 100 functions as a distributed-parameter circuit. For this reason, the capacitances of capacitors C1 to C7 and the inductances of inductors L1 to L7 are not fixed, but Table 1 shows the approximate values ​​of the capacitances of capacitors C1 to C7 and the inductances of inductors L1 to L7 in Example 1. [Table 1]

[0037] Figure 8 shows the passband characteristics of Example 1 and Comparative Example 1 in Simulation 1. As mentioned above, the number of via connections 13i in Comparative Example 1 is the same as in Example 1, at 2. As shown in Figure 8, the passband Pass is around 4.2 to 5 GHz. The passband Pass is mainly formed by the parallel resonance of parallel resonant circuits R1 to R4. Four attenuation poles A1 to A4 are formed. The lowest attenuation pole A1 and the attenuation pole A2 located at the low frequency end of the passband Pass are mainly formed by the parallel resonance of capacitor C5 and magnetic field coupling M1, and the parallel resonance of capacitor C6 and magnetic field coupling M2. By providing capacitor C7, the frequencies of attenuation poles A1 and A2 are separated. The attenuation pole A3 located at the high frequency end of the passband Pass is mainly formed by the parallel resonance of capacitor C7 and inductor L5. The highest frequency attenuation pole A4 is mainly formed by the series resonance of capacitors C1 to C4 and the inductance between capacitors C1 to C4 and the ground terminal Tg.

[0038] The passband (Pass) and attenuation poles A1-A3 are almost the same in Example 1 and Comparative Example 1. As indicated by arrow 50, the frequency of attenuation pole A4 is lower in Example 1 than in Comparative Example 1. Thus, the frequency of attenuation pole A4 changes by providing inductors L6 and L7. By adjusting the inductance of inductors L6 and L7 during the design phase, attenuation pole A4 can be adjusted without changing the characteristics of the passband (Pass) and attenuation poles A1-A3.

[0039] [Comparative Example 2] In Figure 6, Comparative Example 2 is a filter in which there is one via wiring 13i electrically connecting the ground pattern G and the ground terminal Tg. In Comparative Example 2, the inductance of inductor L10 is larger than in Comparative Example 1.

[0040] [Simulation 2] The transmission characteristics were calculated for Comparative Example 2. The simulation method was the same as for Simulation 1. Table 2 shows the approximate capacitance and inductance values ​​for Comparative Example 2. [Table 2]

[0041] As shown in Table 2, the capacitances of capacitors C1 to C7 and the inductances of inductors L1 to L5 are the same as in Example 1. The inductance of inductor L10 is 0.1 nH.

[0042] Figure 9 shows the pass characteristics of Comparative Example 2 and Comparative Example 1 in Simulation 2. In Comparative Example 2, compared to Comparative Example 1, the frequency of the attenuation pole A4 is shifted to the lower frequency side, as indicated by arrow 50. The attenuation amount in the region 52, which is lower in frequency than the attenuation pole A1, deteriorates. As in Simulation 2, adjusting the inductance of inductor L10 to adjust the frequency of the attenuation pole A4 worsens the attenuation characteristics in region 52.

[0043] [Comparative Example 3] Figure 10 is a circuit diagram of the filter according to Comparative Example 3. As shown in Figure 10, in the filter 112 of Comparative Example 3, inductors L8, L6, L7, and L9 are provided in series with capacitors C1 to C4, respectively, in the parallel resonant circuits R1 to R4.

[0044] Figures 11 and 12 are disassembled perspective views of the dielectric layer in Comparative Example 3. As shown in Figures 11 and 12, line patterns L6a, L7a, L8a, and L9a are provided on the upper surface of the dielectric layer 11d. One end of line pattern L1a is electrically connected to electrode C5a and input terminal Tin via via wirings 13b to 13i, and is also electrically connected to electrode C1a via line pattern L8a. Thus, electrode C1a of capacitor C1 is electrically connected to electrode C5a corresponding to node N1 via line pattern L8a. Similarly, electrode C4a of capacitor C4 is electrically connected to electrode C6a corresponding to node N4 via line pattern L9a. Similar to Figures 3 and 4 of Example 1, electrode C2a of capacitor C2 is electrically connected to electrode C5b corresponding to node N2 via line pattern L6a, and electrode C3a of capacitor C3 is electrically connected to electrode C6b corresponding to node N3 via line pattern L7a. The other components are the same as in Example 1.

[0045] [Simulation 3] The transmission characteristics were calculated for Comparative Example 3. The simulation method was the same as for Simulation 1. Table 3 shows the approximate capacitance and inductance values ​​for Comparative Example 3. [Table 3]

[0046] As shown in Table 3, the capacitances of capacitors C1 to C7 and the inductances of inductors L1 to L7 are the same as in Example 1. The inductances of inductors L8 and L9 are the same as those of inductors L6 and L7.

[0047] Figure 13 shows the pass characteristics of Comparative Example 3 and Comparative Example 1 in Simulation 3. In Comparative Example 3, the frequency of the attenuation pole A4 is shifted to the lower frequency side, as indicated by arrow 50, compared to Comparative Example 1. The amount of shift of the attenuation pole A4 in Comparative Example 3 is greater than that of Example 1 in Figure 8. In Comparative Example 3, the attenuation characteristics in the region below the attenuation pole A1 are about the same as in Comparative Example 1. However, in Comparative Example 3, the attenuation in the region 54, which is higher than 16 GHz, is worse than in Comparative Example 1. As in Simulation 3, by providing inductors L8 and L9, the frequency of the attenuation pole A4 can be adjusted and the deterioration of the attenuation characteristics in region 52 can be suppressed, but the attenuation characteristics in region 54 deteriorate.

[0048] [Comparative Example 4] Figure 14 is a circuit diagram of the filter according to Comparative Example 4. As shown in Figure 14, in the filter 114 of Comparative Example 4, inductors L8 and L9 are provided in series with capacitors C1 and C4, respectively, in the parallel resonant circuits R1 and R4. In the parallel resonant circuits R2 and R3, no inductors are provided in series with capacitors C2 and C3, respectively.

[0049] Figures 15 and 16 are disassembled perspective views of the dielectric layer in Comparative Example 4. As shown in Figures 15 and 16, line patterns L8a and L9a are provided on the upper surface of the dielectric layer 11d, while line patterns L6a and L7a are not provided. Similar to Comparative Example 3, electrode C1a of capacitor C1 is electrically connected to electrode C5a corresponding to node N1 via line pattern L8a. Electrode C4a of capacitor C4 is electrically connected to electrode C6a corresponding to node N4 via line pattern L9a. Similar to Comparative Example 1, electrode C2a of capacitor C2 is electrically connected to electrode C5b corresponding to node N2 without a line pattern, and electrode C3a of capacitor C3 is electrically connected to electrode C6b corresponding to node N3 without a line pattern. The other configurations are the same as in Example 1.

[0050] [Simulation 4] The transmission characteristics were calculated for Comparative Example 4. The simulation method was the same as for Simulation 1. Table 4 shows the approximate capacitance and inductance values ​​for Comparative Example 4. [Table 4]

[0051] As shown in Table 4, the capacitances of capacitors C1 to C7 and the inductances of inductors L1 to L5 are the same as in Example 1. The inductances of inductors L8 and L9 are the same as in Comparative Example 3.

[0052] Figure 17 shows the pass characteristics of Comparative Example 4 and Comparative Example 1 in Simulation 4. In Comparative Example 4, the frequency of the attenuation pole A4 is shifted to the lower frequency side, as indicated by arrow 50, compared to Comparative Example 1. The amount of shift of the attenuation pole A4 in Comparative Example 4 is about the same as that of Example 1 in Figure 8. In Comparative Example 4, the attenuation characteristics in the region below the attenuation pole A1 are about the same as those of Comparative Example 1. In Comparative Example 4, the attenuation in the region 54 above 16 GHz is worse than that of Comparative Example 1. As in Simulation 4, by providing inductors L8 and L9, the frequency of the attenuation pole A4 can be adjusted and the deterioration of the attenuation characteristics in region 52 can be suppressed, but the attenuation characteristics in region 54 deteriorate. The deterioration of the attenuation characteristics in region 54 is about the same as that of Comparative Example 3 in Figure 13.

[0053] [Example 1 Modification 1] Figure 18 is a circuit diagram of a filter according to Modification 1 of Example 1. As shown in Figure 18, in the filter 102 of Modification 1 of Example 1, inductors L8 and L7 are provided in series with capacitors C1 and C3, respectively, in the parallel resonant circuits R1 and R3. In the parallel resonant circuits R2 and R4, no inductors are provided in series with capacitors C2 and C4, respectively.

[0054] Figures 19 and 20 are disassembled perspective views of the dielectric layer in Modification 1 of Example 1. As shown in Figures 19 and 20, line patterns L7a and L8a are provided on the upper surface of the dielectric layer 11d, while line patterns L6a and L9a are not provided. Similar to Comparative Example 3, electrode C1a of capacitor C1 is electrically connected to electrode C5a corresponding to node N1 via line pattern L8a. Electrode C3a of capacitor C3 is electrically connected to electrode C6b corresponding to node N3 via line pattern L7a. Similar to Comparative Example 1, electrode C2a of capacitor C2 is electrically connected to electrode C5b corresponding to node N2 without using a line pattern. Electrode C4a of capacitor C4 is electrically connected to electrode C6a corresponding to node N4 without using a line pattern, and the other configurations are the same as in Example 1.

[0055] [Simulation 5] The transmission characteristics were calculated for Modification 1 of Example 1. The simulation method was the same as in Simulation 1. Table 5 shows the approximate capacitance and inductance values ​​for Modification 1 of Example 1. [Table 5]

[0056] As shown in Table 5, the capacitances of capacitors C1 to C7 and the inductances of inductors L1 to L5 are the same as in Example 1. The inductances of inductors L7 and L8 are the same as in Comparative Example 3.

[0057] Figure 21 shows the pass characteristics of Modification 1 and Comparative Example 1 of Example 1 in Simulation 5. In Modification 1 of Example 1, the frequency of the attenuation pole A4 is shifted to the lower frequency side, as indicated by arrow 50, compared to Comparative Example 1. The amount of shift of the attenuation pole A4 in Modification 1 of Example 1 is about the same as that of Example 1 in Figure 8. In Modification 1 of Example 1, the attenuation characteristics in the region below the attenuation pole A1 are about the same as those of Comparative Example 1. In Modification 1 of Example 1, the attenuation in the region 54 above 16 GHz is worse than that of Comparative Example 1. As in Simulation 5, by providing inductors L7 and L8, the frequency of the attenuation pole A4 can be adjusted and the deterioration of the attenuation characteristics in region 52 can be suppressed, but the attenuation characteristics in region 54 deteriorate. The deterioration of the attenuation characteristics in region 54 is slightly smaller than that of Comparative Example 3 in Figure 13 and Comparative Example 4 in Figure 17. Thus, in Modification 1 of Example 1, the deterioration of the attenuation characteristics in region 54 can be suppressed more than that of Comparative Examples 3 and 4.

[0058] Summarizing simulations 1-5, by providing inductors L6-L9 in series with capacitors C1-C4 in at least one of the parallel resonant circuits R1-R4, and adjusting the inductance of inductors L6-L9 during the design phase, the frequency of the damping pole A4 can be adjusted without changing the damping characteristics in region 52. The amount of shift of the damping pole A4 increases as the number of inductors L6-L9 increases. By not providing inductors L8 and L9 in at least one of the parallel resonant circuits R1 directly connected to the input terminal Tin and the parallel resonant circuit R4 directly connected to the output terminal Tout, changes in the damping characteristics in region 54 can be suppressed. By not providing inductors L8 and L9 in both parallel resonant circuits R1 and R4, changes in the damping characteristics in region 54 can be further suppressed.

[0059] According to Example 1 and its Modification 1, the parallel resonant circuit R4 (first resonant circuit) includes a capacitor C4 (first capacitor) and an inductor L4 (first inductor) connected in parallel between node N4 (first node), which is electrically connected to the output terminal Tout (first signal terminal) without a capacitor, and the ground terminal. The inductor L9 is not connected in series with capacitor C4 between node N4 and the ground terminal Tg. The parallel resonant circuit R1 (second resonant circuit) includes a capacitor C1 (second capacitor) and an inductor L1 (second inductor) connected in parallel between node N1 (second node), which is electrically connected to the input terminal Tin (second signal terminal) without a capacitor, and the ground terminal Tg. The parallel resonant circuit R3 (third resonant circuit) comprises a capacitor C3 (third capacitor) and an inductor L3 (third inductor) connected in parallel between node N3 (third node), which is located in a path SL within which high-frequency signals can be transmitted between nodes N4 and N1, and the ground terminal Tg, and an inductor L7 (first series inductor) connected in series with capacitor C3 between node N3 and the ground terminal Tg.

[0060] By providing inductor L7, changes in the damping characteristics in region 52 are suppressed, and the frequency of the damping pole A4 can be easily adjusted. By not providing inductor L9 in the parallel resonant circuit R4, changes in the damping characteristics in region 54 can be suppressed, as shown in Figures 8 and 21.

[0061] As in Example 1, the parallel resonant circuit R1 does not have an inductor L8 connected in series with the capacitor C1 between node N1 and the ground terminal Tg. This allows for further suppression of changes in the damping characteristics in region 54, as shown in Figure 8.

[0062] In Example 1, an example was described in which an inductor L8 is provided in the parallel resonant circuit R1, and an inductor L9 is not provided in the parallel resonant circuit R4. However, it is also possible that an inductor L8 is not provided in the parallel resonant circuit R1, and an inductor L9 is provided in the parallel resonant circuit R4.

[0063] As shown in Figures 3, 4, 19, and 20, multiple dielectric layers 11a to 11i are stacked. Inductor L7 includes a transmission line pattern L7a (first transmission line pattern) provided on the first surface between adjacent dielectric layers 11c and 11d. The parallel resonant circuit R4 is connected in series with capacitor C4 between node N4 and ground terminal Tg and does not have a transmission line pattern provided on the surface between the multiple dielectric layers 11a to 11i. This makes it possible to provide inductor L7 and not inductor L9.

[0064] Inductor L3 includes a transmission line pattern L3a (second transmission line pattern) provided between adjacent dielectric layers 11a and 11b and on a second surface different from the first surface. Transmission line pattern L3a is electrically connected to transmission line pattern L7a via via wirings 13b to 13c that penetrate dielectric layers 11b to 11c. When transmission line patterns L3a and L7a are magnetically coupled, the resonance characteristics of the parallel resonant circuit R3 change. Therefore, it is preferable that the direction in which transmission line pattern L3a extends and the direction in which transmission line pattern L7a extends intersect when viewed from the thickness direction of the laminate 10. The angle between the direction in which transmission line pattern L3a extends and the direction in which transmission line pattern L7a extends is preferably 45° or more and 135° or less, more preferably 80° or more and 100° or less, and even more preferably approximately 90° (i.e., approximately orthogonal). The same applies to transmission line patterns L2a and L6a.

[0065] If the transmission line patterns of inductors L1 to L9 are close to the ground pattern on the mounting board on which the filter is mounted, the Q values ​​of inductors L1 to L9 will decrease due to eddy current losses, etc. For this reason, electrodes that form capacitors C1 to C7 are provided between the transmission line patterns forming inductors L1 to L9 and terminal 14. This improves the Q values ​​of inductors L1 to L9. In particular, it is preferable that the Q values ​​of inductors L1 to L4 that form the parallel resonant circuit R1 to R4 be high. Therefore, it is preferable that the transmission line pattern L6a (and L7a) is formed by the conductive pattern between the longest transmission line pattern L2a (and L3a) that forms inductor L2 (and L3) and the electrodes that form capacitors C1 to C7.

[0066] At least one of the inductors L1 to L4 is provided with line patterns L1b and L4b (third line pattern) on the first surface. This helps to suppress the increase in the size of the filter.

[0067] The parallel resonant circuit R2 (fourth resonant circuit) comprises a capacitor C2 (fourth capacitor) and an inductor L2 (fourth inductor) connected in parallel between node N2 (fourth node), located between node N3 and node N1 in the path SL, and the ground terminal Tg, and an inductor L6 (second series inductor) connected in series with capacitor C2 between node N2 and the ground terminal Tg. This allows the frequency of the attenuation pole A4 to be adjusted by adjusting the inductances of inductors L6 and L7. Furthermore, since the number of inductors increases, the amount of shift of the attenuation pole A4 can be increased. Thus, the adjustment range of the frequency of the attenuation pole A1 can be increased.

[0068] Nodes N4 and N3 are electrically connected via capacitor C6 (fifth capacitor), and node N1 and node N3 are electrically connected via capacitor C5 (sixth capacitor). An inductor L7 is provided in the parallel resonant circuit R3, which is provided between node N3, which is electrically connected to both the input terminal Tin and the output terminal Tout via capacitors C5 and C6, and the ground terminal Tg. This suppresses changes in the attenuation characteristics in regions 52 and 54 and facilitates adjustment of the frequency of the attenuation pole A4.

[0069] In Example 1 and its modifications, an example was described in which inductor L6 is electrically connected between node N2 and capacitor C2, and inductor L7 is electrically connected between node N3 and capacitor C3. Inductor L6 may be electrically connected between the ground terminal Tg and capacitor C2, and inductor L7 may be electrically connected between the ground terminal Tg and capacitor C3.

[0070] Filters 100 and 102 are bandpass filters. The inductance components of capacitors C1-C4 and between capacitors C1-C4 and the ground terminal Tg form an attenuation pole A4 at a frequency higher than the filter's passband Pass. This allows the frequency of the attenuation pole A4 to be adjusted by adjusting the inductances of inductors L6 and L7.

[0071] [Modification 2 of Example 1] Figure 22 is a circuit diagram of a filter according to a modified example 2 of Example 1. As shown in Figure 22, the filter 104 of the modified example 2 of Example 1 does not have a parallel resonant circuit R2. Nodes N1 and N3 are electrically connected via capacitor C5. The high-frequency signal transmission path SL goes from node N1 through capacitors C5 and C6 to node N4. The parallel resonant circuit R3 is equipped with inductor L6, while the parallel resonant circuits R1 and R4 are not equipped with inductors L8 and L9. The other circuit configurations are the same as in Example 1 and will not be described further.

[0072] Table 6 is a table showing examples of the capacitances of capacitors C1, C3-C7 and the inductances of inductors L1, L3, L4, and L7 in Modification 2 of Example 1. [Table 6]

[0073] A bandpass filter can be formed by using the element values ​​shown in Table 6. Although examples of 3 and 4 parallel resonant circuits R1~R4 have been described, it is sufficient for multiple parallel resonators to be connected at different positions within the path SL. Two adjacent nodes among nodes N1~N4 may be connected via a capacitor, as in the case of nodes N1 and N2, nodes N3 and N4 in Example 1 and its modified example 1, and nodes N1 and N3, and nodes N3 and N4 in modified example 2 of Example 1. Adjacent nodes may be connected via an inductor, as in the case of nodes N2 and N3 in Example 1 and its modified example 1. Adjacent nodes may also be connected by magnetic field coupling. [Examples]

[0074] Figure 23 is a circuit diagram of a triplexer according to Embodiment 2. As shown in Figure 23, the triplexer 20 includes filters 22, 24, and 26. Filters 22, 24, and 26 are connected between the common terminal Ant and terminals LB, MB, and HB, respectively. Antenna 28 is connected to the common terminal Ant. Filter 22 is, for example, a low-pass filter (LPF), which allows low-band high-frequency signals to pass through and suppresses signals of other frequencies. Filter 24 is, for example, a band-pass filter (BPF), which allows middle-band high-frequency signals with frequencies higher than the low-band to pass through and suppresses signals of other frequencies. Filter 26 is, for example, a high-pass filter (HPF), which allows high-band high-frequency signals with frequencies higher than the middle-band to pass through and suppresses signals of other frequencies.

[0075] At least one of filters 22, 24, and 26 can be a filter of Example 1 and its variations. Although a triplexer was described as an example of a multiplexer, the multiplexer may be a diplexer, duplexer, or quadplexer.

[0076] [Modification 1 of Example 2] Figure 24 is a circuit diagram of a communication module according to a modified example 1 of Embodiment 2. As shown in Figure 24, the module 30 includes a filter 31, a switch 32, a low-noise amplifier LNA 33, and a power amplifier PA 34.

[0077] Antenna 28 is connected to antenna terminal TA. One end of filter 31 is connected to antenna terminal TA. Switch 32 is connected to the other end of filter 31. The input terminal of LNA 33 and the output terminal of PA 34 are connected to switch 32. The output terminal of LNA 33 is connected to receiver terminal TR. The input terminal of PA 34 is connected to transmit terminal TT. RFIC (Radio Frequency Integrated Circuit) is connected to receiver terminal TR and transmit terminal TT.

[0078] Module 30 is, for example, a communication module for the TDD (Time Division Duplex) communication method. In the TDD communication method, the transmission bandwidth and the reception bandwidth are the same. Filter 31 is, for example, a bandpass filter, which allows high-frequency signals in the passband, which includes the transmission bandwidth and the reception bandwidth, to pass through while suppressing signals of other frequencies.

[0079] When receiving a signal, switch 32 connects filter 31 and LNA 33. As a result, the high-frequency signal received by antenna 28 is filtered by filter 31 to a signal within the reception band, amplified by LNA 33, and output to RFIC 35. When transmitting a signal, switch 32 connects filter 31 and PA 34. As a result, the high-frequency signal output from RFIC 35 is amplified by PA, filtered by filter 31 to a signal within the transmission band, and output from antenna 28.

[0080] The filter 31 in the communication module of Example 2 Modification 1 can be replaced with the filter of Example 1 and its modifications. Other types of communication modules may also be used as the module.

[0081] Although embodiments of the present invention have been described in detail above, the present invention is not limited to these specific embodiments, and various modifications and changes are possible within the scope of the gist of the present invention as described in the claims. [Explanation of symbols]

[0082] 10 Laminate 11a-11i dielectric layer 12a-12i Conductive Pattern 13b-13i via wiring 14 terminals

Claims

1. First signal terminal and, The second signal terminal and, Ground terminal and A first resonant circuit comprising a first node electrically connected to the first signal terminal without a capacitor and a first capacitor and a first inductor connected in parallel between the first node and the ground terminal, wherein the inductor is not connected in series with the first capacitor between the first node and the ground terminal, A second resonant circuit comprising a second capacitor and a second inductor connected in parallel between a second node electrically connected to the second signal terminal without a capacitor and the ground terminal, A third resonant circuit comprising a third capacitor and a third inductor connected in parallel between a third node located in a path capable of transmitting high-frequency signals between the first node and the second node and the ground terminal, and a first series inductor connected in series with the third capacitor between the third node and the ground terminal, Multiple dielectric layers are stacked, The first series inductor includes a first line pattern provided on the first surface between adjacent dielectric layers among the plurality of dielectric layers, The first resonant circuit is connected in series with the first capacitor between the first node and the ground terminal and does not have a line pattern provided on the surface between the plurality of dielectric layers. The third inductor is provided between adjacent dielectric layers among the plurality of dielectric layers and on a second surface different from the first surface, electrically connected to the first transmission line pattern via via wiring that penetrates at least one dielectric layer among the plurality of dielectric layers, and includes a second transmission line pattern that extends in a direction intersecting the direction in which the first transmission line pattern extends.

2. The filter according to claim 1, wherein the second resonant circuit is such that an inductor is not connected in series with the second capacitor between the second node and the ground terminal.

3. The filter according to claim 1 or 2, wherein at least one of the first inductor and the second inductor is provided with a third line pattern on the first surface.

4. The filter according to claim 1 or 2, comprising a fourth resonant circuit comprising a fourth capacitor and a fourth inductor connected in parallel between a fourth node located between the third node and the second node in the aforementioned path and the ground terminal, and a second series inductor connected in series with the fourth capacitor between the fourth node and the ground terminal.

5. The filter according to any one of claims 1 to 4, wherein the first node and the third node are electrically connected via a fifth capacitor, and the second node and the third node are electrically connected via a sixth capacitor.

6. The filter according to any one of claims 1 to 5, wherein the filter is a bandpass filter.

7. The filter according to claim 6, wherein the first capacitor, the second capacitor, and the third capacitor, and the inductance component between the first capacitor, the second capacitor, and the third capacitor and the ground terminal, form an attenuation pole at a frequency higher than the passband of the filter.

8. A multiplexer comprising the filter according to any one of claims 1 to 7.

9. A communication module comprising the filter according to any one of claims 1 to 7.

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