Barista array including matched varistors

Abstract

The varistor array can include a monolithic body including multiple dielectric layers. A first varistor can be formed in the monolithic body. The first varistor can include a first external terminal at a first end of the monolithic body, a first plurality of electrodes connected to the first external terminal, a second external terminal at a second end of the monolithic body, and a second plurality of electrodes connected to the second external terminal. The second plurality of electrodes can be interleaved with the first plurality of electrodes and can overlap the first plurality of electrodes with an overlap area that is insensitive to relative misalignment between the first and second plurality of electrodes when the misalignment is less than a threshold value. The second varistor can be formed in the monolithic body and can be separate from the first varistor.

Description

[Technical Field]

[0001] Cross-references of related applications

[0001] This application asserts the benefit of having filed a U.S. provisional patent application, serial number 63 / 159514, with a filing date of March 11, 2021, and incorporates the entirety of that application by this reference.

[0002] Background of the Invention

[0002] The subject matter herein generally relates to electronic components that have been modified to be mounted on a circuit board, and more specifically to varistor arrays. [Background technology]

[0003]

[0003] Multilayer ceramic devices, such as varistor arrays, are typically constructed using multiple stacked dielectric-electrode layers. During manufacturing, these layers are often pressed and formed into a vertically stacked structure. A multilayer ceramic device can contain one or more components in a single array.

[0004]

[0004] A varistor is a voltage-dependent, nonlinear resistor used as a surge absorber, arrester, and voltage stabilizer. A varistor can be connected in parallel with, for example, a highly sensitive electrical component. The nonlinear resistance response of a varistor is often characterized by a parameter known as the clamp voltage. With an applied voltage smaller than the varistor's clamp voltage, the varistor generally has very high resistance and therefore behaves similarly to an open circuit. However, when the varistor is exposed to a voltage greater than its clamp voltage, its resistance decreases, and the varistor behaves similarly to a short circuit, allowing a large current to flow. This nonlinear response can be used to bypass current surges and / or to prevent damage to highly sensitive electrical components from voltage spikes.

[0005]

[0005] Some applications can benefit from two or more varistors having closely matched characteristics, such as capacitance. However, individual varistors generally do not have sufficiently similar characteristics. [Overview of the Initiative]

[0006]

[0006] According to one embodiment of the present disclosure, a varistor array may include a monolithic body comprising a plurality of dielectric layers stacked in the Z direction perpendicular to the longitudinal direction. The monolithic body may have a first end and a second end separated longitudinally from the first end. A first varistor may be formed in the monolithic body. The first varistor may include a first external terminal at the first end of the monolithic body, a first plurality of electrodes connected to the first external terminal, a second external terminal at the second end of the monolithic body, and a second plurality of electrodes connected to the second external terminal. The second plurality of electrodes may be interleaved with the first plurality of electrodes, or may overlap with the first plurality of electrodes in an overlap area, which is insensitive to misalignment if the relative misalignment between the first plurality of electrodes and the second plurality of electrodes is less than a threshold. A second varistor can be formed in a monolithic body. The second varistor may be distinct from the first varistor and may include a first external terminal at the first end of the monolithic body and a second external terminal at the second end of the monolithic body.

[0007]

[0007] According to another embodiment of the present disclosure, a varistor array may include a monolithic body comprising a plurality of dielectric layers stacked in the Z direction perpendicular to the longitudinal direction. The monolithic body may have a first end and a second end separated longitudinally from the first end. A first varistor may be formed in the monolithic body, and a second varistor may be formed in the monolithic body and may be separate from the first varistor. The first varistor may include a first external terminal at the first end of the monolithic body, a first plurality of active electrodes connected to the first external terminal, a second external terminal at the second end of the monolithic body, and a second plurality of active electrodes connected to the second external terminal. Each active electrode of the second plurality of active electrodes may be coplane with each active electrode of the first plurality of active electrodes. Multiple floating electrodes can overlap with a first set of active electrodes along a first overlap area, and the first overlap area is insensitive to relative misalignment between the first set of active electrodes and the multiple floating electrodes. The floating electrodes can overlap with a second set of active electrodes along a second overlap area, and the second overlap area is insensitive to relative misalignment between the second set of active electrodes and the multiple floating electrodes that is below a threshold.

[0008]

[0008] According to another embodiment of the present disclosure, the varistor array may include a monolithic body comprising a plurality of dielectric layers stacked in the Z direction perpendicular to the longitudinal direction. The monolithic body may have a first end and a second end separated longitudinally from the first end. A first varistor may be formed in the monolithic body. The first varistor may include a first external terminal at the first end of the monolithic body and a second external terminal at the second end of the monolithic body, a first plurality of electrodes connected to the first external terminal and a second plurality of electrodes connected to the second external terminal. The second plurality of electrodes of the first varistor may be interleaved with the first plurality of electrodes of the first varistor and may overlap with the first plurality of electrodes of the first varistor in a first overlap area. A second varistor may be formed in the monolithic body. The second varistor may be separate from the first varistor and may include a first external terminal at the first end of the monolithic body and a second external terminal at the second end of the monolithic body. The first plurality of electrodes may be connected to the first external terminal. The second plurality of electrodes may be connected to the second external terminal. The second plurality of electrodes of the second varistor overlap with the first plurality of electrodes of the second varistor in a second overlap area. The ratio of the first overlap area to the second overlap area may be in the range of 0.9 to 1.1.

[0009]

[0009] With respect to the subject matter herein, a complete and implementable disclosure is provided in the specification, which includes the best aspects of the subject matter, is intended for those skilled in the art, and the specification refers to the accompanying drawings. [Brief explanation of the drawing]

[0010] [Figure 1A] Figure 1A is a simplified top-down view of a varistor array according to the features of this disclosure. [Figure 1B]Figure 1B is a side view of the varistor array in Figure 1A, along the AA cross-section of Figure 1A. [Figure 1C] Figure 1C shows the first layer of the varistor array from Figures 1A and 1B. [Figure 1D] Figure 1D shows the second layer of the varistor array from Figures 1A and 1B. [Figure 2A] Figure 2A shows a simplified top-down view of a varistor array according to the features of this disclosure. [Figure 2B] Figure 2B is a side view of the varistor array in Figure 2A, along the AA cross-section of Figure 2A. [Figure 3] Figure 3 shows an embodiment of another example of a varistor array according to the features of this disclosure. [Figure 4] Figure 4 is a flowchart of a method for forming a varistor array according to the features of this disclosure. [Figure 5] Figure 5 shows the current waveform for testing a varistor according to ANSI standard C62.1. [Figure 6] Figure 6 shows the voltage response curve of a varistor according to the features of this disclosure. [Modes for carrying out the invention]

[0011]

[0020] The reference numerals used repeatedly throughout this specification and the accompanying drawings are intended to represent identical or similar features, electrodes, or steps in the subject matter herein.

[0012] Detailed description of preferred embodiments

[0021] Those skilled in the art will understand that this disclosure is merely an illustrative description of embodiments and is not intended to limit the broad features of the subject matter herein, which are realized in the exemplary configurations.

[0013]

[0022] Generally, the present disclosure relates to a varistor array having two or more varistors. Those varistors can have closely matched electrical performance characteristics, such as characteristics like capacitance, insertion loss, etc. During manufacturing, a slight misalignment between various layers of a multilayer ceramic component can cause a slight change in the size of the overlap area between electrodes. However, a varistor array according to the features of the present disclosure can provide two or more varistors having an alignment-insensitive overlap area. As a result, the varistor array can represent a plurality of capacitance values and / or a plurality of other electrical performance characteristics that are closely matched to each other, despite the small misalignments of the various layers that can occur during the manufacture of the varistor array.

[0014]

[0023] For example, the varistor array can include a first varistor having an overlap electrode that overlaps along a first overlap area, and a second varistor having an overlap electrode that overlaps along a second overlap area. The ratio of the first overlap area to the second overlap area can range from about 0.9 to about 1.1, in some embodiments from about 0.92 to about 1.08, in some embodiments from about 0.94 to about 1.06, in some embodiments from about 0.96 to about 1.04, and in some embodiments from about 0.98 to about 1.02. However, in alternative embodiments, the ratio of the first overlap area to the second overlap area can be any suitable number desired in the design considerations.

[0015]

[0024] For example, the varistors of a varistor array can include a plurality of electrodes having an appropriate geometric configuration such that their individual overlap areas are insensitive to small misalignments between various layers. In other words, small misalignments can be made to have little or no effect on the absolute size of the first overlap area and the second overlap area, and / or on the ratio between the first overlap area and the second overlap area. As a result, the varistor array can include a plurality of individual varistors having closely controlled overlap areas, which can provide very closely matched performance characteristics.

[0016]

[0025] A varistor array according to the features of the present disclosure can include a monolithic body including a plurality of dielectric layers laminated in the Z direction. The varistor array can include a first varistor formed in the monolithic body. The first varistor can include a first external terminal at a first end of the monolithic body. The first varistor can include a first plurality of electrodes connected to the first external terminal. The first varistor can include a second external terminal at a second end of the monolithic body. The first varistor can include a second plurality of electrodes connected to the second external terminal. The second plurality of electrodes can be interleaved with the first plurality of electrodes and can overlap the first plurality of electrodes in an overlap area, and this overlap area is insensitive to relative misalignment between the first plurality of electrodes and the second plurality of electrodes when the misalignment is smaller than a threshold.

[0017]

[0026] For example, the second plurality of electrodes can have a lateral width that is greater than the lateral width of the first plurality of electrodes. The width of the overlap area between the first plurality of electrodes and the second plurality of electrodes can be First multiple electrodes equal to the width of. Alternatively, the width of the second plurality of electrodes can be greater than the width of the first plurality of electrodes small It is possible. The width of the overlap area between the first set of electrodes and the second set of electrodes is Second set of electrodes It can be made equal to the width.

[0018]

[0027] The second varistor can be formed in a monolithic body. The second varistor can be separate from the first varistor. For example, the second varistor may lack the internal electrodes (e.g., floating electrodes, active electrodes, etc.) included in the first varistor. The second varistor may lack the external terminals included in and / or connected to the first varistor. Furthermore, the second varistor may be separated from the first varistor in the lateral direction.

[0019]

[0028] The first varistor may include a first external terminal at the first end of the monolithic body and a second external terminal at the second end of the monolithic body. The second varistor may include a first plurality of electrodes connected to the first external terminal and a second plurality of electrodes connected to the second external terminal. The second plurality of electrodes of the second varistor may overlap with the first plurality of electrodes of the second varistor in an overlap area, which is insensitive to misalignment if the relative misalignment between the first plurality of electrodes of the second varistor and the second plurality of electrodes of the second varistor is less than a threshold.

[0020]

[0029] As described here, a varistor array may include two varistors. However, a varistor array may include four or more varistors in some embodiments, six or more varistors in some embodiments, eight or more varistors in some embodiments, and ten or more varistors in some embodiments.

[0021]

[0030] The total overlap area of ​​the first varistor can be, in some embodiments, about 10% or less of the total overlap area of ​​the second varistor, in some embodiments about 5% or less, in some embodiments about 3% or less, in some embodiments about 2% or less, in some embodiments about 1% or less, and in some embodiments about 0.5% or less.

[0022]

[0031] One or more varistors can represent a capacitance less than 50 pF when using a 0.0 volt DC bias and a 0.5 volt root mean square sinusoidal signal at an operating frequency of 1 MHz, a temperature of approximately 23°C, and a relative humidity of 25%. For example, the first varistor can represent the first capacitance, and the second varistor can represent the second capacitance, which is within 5% of the first capacitance represented by the first varistor.

[0023]

[0032] According to the features of this disclosure, a varistor array may include floating electrodes. The varistor array may include a monolithic body comprising a plurality of dielectric layers stacked in the Z direction. A first varistor may be formed in the monolithic body, and a second varistor may be formed in the monolithic body, which is distinct from the first varistor.

[0024]

[0033] The first varistor may include a first external terminal at the first end of the monolithic body and a first plurality of active electrodes connected to the first external terminal. The first varistor may include a second external terminal at the second end of the monolithic body. A second plurality of active electrodes may be connected to the second external terminal. Each active electrode of the second plurality of active electrodes may be coplane with each active electrode of the first plurality of active electrodes. A plurality of floating electrodes may overlap with the first plurality of active electrodes along a first overlap area, the first overlap area being insensitive to relative misalignment between the first plurality of active electrodes and the plurality of floating electrodes. The floating electrodes may overlap with a second plurality of active electrodes along a second overlap area, the second overlap area being insensitive to relative misalignment between the second plurality of active electrodes and the plurality of floating electrodes that is below a threshold.

[0025]

[0034] For example, the floating electrodes may have a lateral width greater than the width of the first set of active electrodes in the lateral direction, and the width of the first overlap area between the floating electrodes and the first set of active electrodes may be equal to the width of the first set of active electrodes. In another example, the floating electrodes may have a lateral width smaller than the width of the first set of active electrodes in the lateral direction, and the width of the first overlap area between the floating electrodes and the first set of active electrodes may be equal to the width of the floating electrodes.

[0026]

[0035] The second varistor may include multiple floating electrodes separate from those of the first varistor. The floating electrodes of the second varistor can be electrically isolated from those of the first varistor. For example, the floating electrodes of the second varistor may be positioned laterally away from those of the first varistor.

[0027]

[0036] The second varistor can generally be configured similarly to the first varistor. For example, the second varistor may include a first set of active electrodes that overlap with a set of floating electrodes in a first overlap area. The second varistor may also include a second set of active electrodes that overlap with a set of floating electrodes in a second overlap area.

[0028]

[0037] In some embodiments, a varistor array according to the features of this disclosure may also exhibit low capacitance. For example, one or more varistors in a varistor array may have a capacitance less than about 50 picofarads ("pF") when using a 0.0 volt DC bias and a 0.5 volt mean-square sinusoidal signal at an operating frequency of 1 MHz, a temperature of about 23°C, and a relative humidity of 25%. For example, the capacitance that a varistor may have under the above conditions may be less than about 45 pF in some embodiments, less than about 40 pF in some embodiments, less than about 10 pF in some embodiments, and less than about 5 pF in some embodiments, less than about 2 pF in some embodiments, and less than about 1 pF in some embodiments. For example, a varistor may have a capacitance ranging from about 0.1pF to about 50pF in some embodiments, from about 0.1pF to about 10pF in some embodiments, from about 0.7pF to about 7pF in some embodiments, from about 1pF to about 5pF in some embodiments, and from about 0.1pF to about 1pF in some embodiments.

[0029]

[0038] A varistor array according to the features of this disclosure may also represent other capacitance values. For example, one or more varistors in a varistor array may have a capacitance greater than about 50 picofarads ("pF") when using a 0.0 volt DC bias and a 0.5 volts-root-mean-square sinusoidal signal at an operating frequency of 1 MHz, a temperature of about 23°C, and a relative humidity of 25%. For example, the capacitance that a varistor may have under the above conditions may be greater than about 50 pF in some embodiments, greater than about 75 pF in some embodiments, greater than about 100 pF in some embodiments, greater than about 200 pF in some embodiments, greater than about 300 pF in some embodiments, greater than about 400 pF in some embodiments, and greater than about 500 pF in some embodiments. Further examples include the capacitance that a varistor may have under the above conditions may be greater than about 600 pF in some embodiments, greater than about 750 pF in some embodiments, and greater than about 1000 pF in some embodiments. For example, a varistor may have a capacitance ranging from about 50 pF to about 1000 pF in some embodiments, from about 75 pF to about 750 pF in some embodiments, and from about 100 pF to about 500 pF in some embodiments.

[0030]

[0039] In some embodiments, the varistor array and / or one or more varistors in the varistor array may exhibit low leakage current. For example, the leakage current at an operating voltage of about 30 volts may be less than about 10 microamperes (μA). For example, the leakage current at an operating voltage of about 30 volts may range from 0.01 μA to about 5 μA in some embodiments, from about 0.005 μA to about 1 μA in some embodiments, and from about 0.05 μA to about 0.15 μA in some embodiments, and may be, for example, 0.1 μA.

[0031]

[0040] In some embodiments, one or more varistors in a varistor array exhibit a current of at least approximately 0.05 J / mm² when tested with a 10 × 1000 μs current wave. 3 In some embodiments, at least about 0.1 J / mm² 3In some embodiments, at least about 0.2 J / mm² 3 In some embodiments, at least about 0.5 J / mm² 3 In addition, in some embodiments, at least about 1.0 J / mm 3 It may have a transient energy capability per unit active volume. The transient energy capability per unit active volume of one or more varistors can be determined by dividing the transient energy capability of the varistor by the active volume of the varistor. The active volume of a varistor can be defined as the area of ​​the active electrodes multiplied by the number of active electrodes and the thickness of the dielectric layer between the active electrodes.

[0032]

[0041] According to the features of this disclosure, a varistor array can exhibit a nonlinear resistive response, which can deflect voltage spikes and / or current voltages so as not to damage nearby or connected electrical components. For example, a varistor array can be configured to provide a relatively low current flow for voltages applied to the varistor array that are lower than the breakdown voltage of the varistor array. As the applied voltage increases and exceeds the breakdown voltage, the varistor array can facilitate a larger relative current flow through the varistor array, which can prevent or reduce voltage spikes through the varistor array, thereby preventing or reducing voltage spikes to nearby or adjacent components.

[0033]

[0042] For example, a varistor array and / or one or more varistors in a varistor array can represent resistance following a first resistance curve that is nonlinear over a first voltage range below the clamp voltage of the varistor / varistor array, and resistance following a second resistance curve that is nearly linear over a second voltage range above the clamp voltage.

[0034]

[0043] A varistor array can exhibit a nonlinear response. The voltage per unit length across a varistor array can vary with respect to the current per unit area through the varistor array. Over the prebreakdown voltage range, a varistor array, or one or more varistors within a varistor array, can generally exhibit a first response curve, and over the nonlinear voltage range above the prebreakdown voltage range and below the clamp voltage, they can generally exhibit a second response curve. A varistor / varistor array can generally exhibit voltages that follow approximately the following relationships:

[0035]

number

[0036] Here, V represents voltage, I represents current, C is a constant, and α is defined in the nonlinear region as follows.

[0037]

number

[0038]

[0044] In the pre-breakdown voltage range, the voltage per unit length generally increases faster with respect to current per unit area through the varistor / varistor array than in the nonlinear region. Over the upturn voltage range above the clamp voltage, the varistor or varistor array can generally exhibit a third response curve, where the voltage per unit length generally increases faster with respect to current per unit area through the varistor / varistor array than in the nonlinear region.

[0039]

[0045] In some embodiments, a varistor array according to the features of this disclosure, or one or more varistors in a varistor array described herein, may be able to withstand repeated electrostatic discharge strikes with substantially no degradation in performance. For example, the breakdown voltage of a varistor array after 5,000 or more electrostatic discharge strikes of about 8,000 volts may be greater than about 0.9 times the initial breakdown voltage of the varistor array, in some embodiments it may be greater than about 0.95 times the initial breakdown voltage, and in some embodiments it may be greater than about 0.98 times the initial breakdown voltage.

[0040]

[0046] Multiple dielectric layers are pressed together and sintered to form a single structure. The dielectric layers may include any suitable dielectric material, such as barium titanate, zinc oxide, or any other suitable dielectric material. For example, various additives that create or enhance the voltage-dependent resistance of the dielectric material may be added to the dielectric material. For example, in some embodiments, the additives may include oxides of cobalt, bismuth, manganese, praseodymium, or combinations thereof. In some embodiments, the additives may include oxides of gallium, aluminum, antimony, chromium, titanium, lead, barium, nickel, vanadium, tin, or combinations thereof. The dielectric material may be doped with additives in the range of about 0.5 mol percent to about 3 mol percent (1 or more), and in some embodiments, from about 1 mol percent to about 2 mol percent. The average grain size of the dielectric material may contribute to the nonlinear properties of the dielectric material. In some embodiments, the average grain size may be in the range of about 1 micron to 100 microns, and in some embodiments, from about 2 microns to 80 microns.

[0041]

[0047] Herein, an embodiment as an example of a multilayer varistor array will be referred to in detail. Referring here to the drawings, Figure 1A shows a simplified top-down view of a varistor array 100 according to the features of the present disclosure. Figure 1B is a side view of the varistor array 100 of Figure 1A along section AA of Figure 1A. The varistor array 100 is at the first end 106 And, in the vertical direction 108, the first end 106 The second end is separated from it. 104 The monolithic body 102 may include a plurality of dielectric layers stacked in the Z direction 110 which is perpendicular to the longitudinal direction 108 and the transverse direction 112.

[0042]

[0048] The first varistor 114 can be formed in the monolithic body 102. The first varistor 114 may include a first external terminal 116 at the first end 106 of the monolithic body 102. The first varistor 114 may include a first plurality of electrodes 118 connected to the first external terminal 116. The first varistor 114 may include a second external terminal 120 at the second end 104 of the monolithic body 102. The first varistor 114 may include a second plurality of electrodes 122 connected to the second external terminal 120. The second set of electrodes 122 can be interleaved with the first set of electrodes 118, and can also overlap with the first set of electrodes 118 in an overlap area 123, which is insensitive to misalignment if the relative misalignment between the first set of electrodes 118 and the second set of electrodes 122 is less than a threshold 127. In this example, the threshold 127 is equal to half the difference between the width 126 of the first set of electrodes 118 and the width 128 of the overlap area 123.

[0043]

[0049] For example, the second set of electrodes 122 may have a lateral width 124 that is smaller than the lateral width 126 of the first set of electrodes 118, so that the width 128 of the overlap area 123 between the first set of electrodes 118 and the second set of electrodes 122 is equal to the width 124 of the second set of electrodes 122. Alternatively, the width 124 of the second set of electrodes 122 may be larger than the width 126 of the first set of electrodes 118, so that the width 128 of the overlap area 123 between the first set of electrodes 118 and the second set of electrodes 122 is equal to the width 126 of the first set of electrodes 118.

[0044]

[0050] As shown in Figure 1B, the overlap area 123 may have a length 125 in the longitudinal direction 108. The length 125 may vary, for example, based on the length 108 of the first set of electrodes 118 and / or the length 108 of the second set of electrodes 122.

[0045]

[0051] The second varistor 130 can be formed in the monolithic body 102. The second varistor 130 can be separate from the first varistor 114. The second varistor 130 can be positioned laterally 112 away from the first varistor 114. 2 Barista 130 This may include a first external terminal 132 at the first end 106 of the monolithic body 120 and a second external terminal 134 at the second end 104 of the monolithic body 102.

[0046]

[0052] The second varistor 130 may include a first set of electrodes 136 connected to the first external terminal 132 and a second set of electrodes 138 connected to the second external terminal 134. 130 The second set of electrodes 138 are in the overlap area 140 of the second varistor 130The overlap area 140 can overlap with the first plurality of electrodes 186 of the second varistor, and is insensitive to misalignment if the relative misalignment between the first plurality of electrodes of the second varistor and the second plurality of electrodes of the second varistor is less than the threshold 127.

[0047]

[0053] In some embodiments, the area of ​​the overlap area 123 of the first varistor 114 can be approximately equal to the area of ​​the overlap area 140 of the second varistor 130. For example, the ratio of the area of ​​the overlap area 123 of the first varistor 114 to the area of ​​the overlap area 140 of the second varistor 130 can range from about 0.9 to about 1.1.

[0048]

[0054] Either or both of the first varistor 114 and the second varistor 130 can represent a capacitance less than 50 pF when using a 0.0 volt DC bias and a 0.5 volt root mean square sinusoidal signal at an operating frequency of 1 MHz, a temperature of approximately 23°C, and a relative humidity of 25%. For example, the first varistor 114 may represent a first capacitance, and the second varistor 130 may represent a second capacitance that is within 5% of the first capacitance represented by the first varistor 114.

[0049]

[0055] Figures 1C and 1D show the alternating first layer 160 and second layer 162 of the varistor array 100 in Figures 1A and 1B, respectively. The first layer 160 and the second layer 162 can be alternately stacked to form a monolithic body 102. In some embodiments, a dielectric layer (e.g., without electrodes or other patterned conductive material) can be placed between the first layer 160 and the second layer 162.

[0050]

[0056] Figure 2A shows a simplified top-down view of a varistor array 200 according to the features of this disclosure. Figure 2B is a side view of the varistor array 200 of Figure 2A along the AA section of Figure 2A. The varistor array 200 may include a monolithic body 202 comprising a plurality of dielectric layers stacked in the Z direction 210 which is perpendicular to the longitudinal direction 208. The monolithic body 202 is at the first end 206 And the first end 206 The second end is located 208 units away in the vertical direction. 204 The first varistor 214 can be formed in the monolithic body 202. The second varistor 230 can be formed in the monolithic body 202. The second varistor 230 can be different from the first varistor 214.

[0051]

[0057] The first varistor 214 may include a first external terminal 216 at a first end 206 of the monolithic body 202 and a first plurality of active electrodes 218 connected to the first external terminal 216. The first varistor 214 may include a second external terminal 220 at a second end 204 of the monolithic body 202. A second plurality of active electrodes 222 may be connected to the second external terminal 220. Each active electrode 222 of the second plurality of active electrodes 222 may be coplane with each active electrode 218 of the first plurality of active electrodes 218. A plurality of floating electrodes 224 may overlap with the first plurality of active electrodes 218 along a first overlap area 226, the first overlap area 226 being insensitive to relative misalignment between the first plurality of active electrodes 218 and the plurality of floating electrodes 224. The floating electrode 224 can overlap with a second plurality of active electrodes 222 along a second overlap area 228, and the second overlap area 228 is insensitive to relative misalignments below a threshold between the second plurality of active electrodes 222 and the plurality of floating electrodes 224.

[0052]

[0058] For example, the multiple floating electrodes 224 may have a lateral width 233 greater than the lateral width 236 of the first multiple active electrodes 218, and the width 238 of the first overlap area 226 between the multiple floating electrodes 224 and the first multiple active electrodes 218 may be equal to the width 236 of the first multiple active electrodes 218. As another example, the width 236 of the first multiple active electrodes 218 may be greater than the width 233 of the floating electrodes 224, for example, as will be described later in connection with Figure 3.

[0053]

[0059] In this embodiment, the combined area of ​​overlap areas 226 and 228 can be made insensitive to misalignment if the relative misalignment between the first and second plurality of electrodes 218 and 222 and the floating electrode 224 is less than a threshold 227 in the lateral direction 212. In this example, the threshold 227 is equal to half the difference between the width 223 of the floating electrode 224 and the width 236 of the first plurality of electrodes 218. The second plurality of electrodes 222 can generally have the same width 236.

[0054]

[0060] The second varistor 230 may include a plurality of floating electrodes 240 separate from the plurality of floating electrodes 224 of the first varistor 214. The floating electrodes 240 of the second varistor 230 can be electrically isolated from the floating electrodes 224 of the first varistor 214. For example, the floating electrodes 240 of the second varistor 230 may be positioned a distance 242 in the lateral direction 212 from the floating electrodes 224 of the first varistor 214. The distance 242 may range from 10% to 200% of the width 238 of the overlap areas 226 and 228.

[0055]

[0061] The second varistor 230 can generally be configured similarly to the first varistor 214. For example, the second varistor 230 may include a first set of active electrodes 232 that overlap with a set of floating electrodes 240 in a first overlap area 244. The second varistor 230 may also include a second set of active electrodes 246 that overlap with a set of floating electrodes 240 in a second overlap area 248.

[0056]

[0062] Figure 3 shows an embodiment of another example of a varistor array 300 according to the features of this disclosure. In Figure 3, Figure 2 A Reference numerals similar to those in are shown. For example, the first varistor 314 may include a plurality of first active electrodes 318, a plurality of floating electrodes 324, and a plurality of second active electrodes 322.

[0057]

[0063] In some embodiments, the multiple floating electrodes 324 may have a lateral width 336 smaller than the lateral width 333 of the first multiple active electrodes 316, and the width 338 of the first overlap area 326 between the multiple floating electrodes 324 and the first multiple active electrodes 318 may be equal to the width 336 of the multiple floating electrodes 324.

[0058]

[0064] In this embodiment, the combined area of ​​overlap areas 326 and 328 can be made insensitive to misalignment if the relative misalignment between the first and second plurality of electrodes 318 and 322 and the floating electrode 324 is less than the threshold 327 in the lateral direction 312. In this example, the threshold 327 is equal to half the difference between the width 336 of the floating electrode 324 and the width 333 of the first plurality of electrodes 218. The second plurality of electrodes 322 can generally have the same width 333.

[0059]

[0065] Figure 4 is a simplified flowchart of method 400 for forming a varistor array. The method may include patterning a first plurality of electrodes and a third plurality of electrodes into a first plurality of dielectric layers in 402. Referring again to Figure 1C, electrodes 118 and 136 may be patterned into the first dielectric layer 160.

[0060]

[0066] The method may include patterning a second plurality of electrodes and a fourth plurality of electrodes into the second plurality of dielectric layers in 404. For example, referring again to Figure 1D, electrodes 122 and 138 may be patterned into the second dielectric layer 162.

[0061]

[0067] The method may include, in 406, stacking a first plurality of dielectric layers and a second plurality of dielectric layers to form a monolithic body such that a first varistor is formed between a first plurality of electrodes and a second plurality of electrodes, and a second varistor is formed between a third plurality of electrodes and a fourth plurality of electrodes. The second varistor may be different from the first varistor. For example, referring again to Figures 1A to 1D, the first and second dielectric layers 160 and 162 can be alternately stacked to form a monolithic body 102 including varistors 114 and 130. External terminals 116, 120, 132, and 134 can be formed by plating or other suitable methods.

[0062] application

[0068] The varistor array disclosed herein can be applied to a wide variety of devices. For example, varistors can be used in various devices such as radio frequency antennas and amplifier circuits, and in communication lines such as Ethernet®. The varistor array will be particularly suitable for high-frequency applications such as 5G frequencies (e.g., greater than 10 GHz).

[0063]

[0069] Furthermore, varistor arrays can be applied to a wide range of technologies, including laser drivers, sensors, radar, RFID chips, short-range communications, data lines, Bluetooth®, optics, Ethernet®, and any suitable circuit. The improved electrical matching between varistors in a varistor array facilitates increased communication bandwidth.

[0064]

[0070] Furthermore, the varistor array disclosed herein may also have specific applications in the automotive industry. For example, the varistor array could be used in any of the above circuits in automotive applications. The improved communication bandwidth can facilitate communication between multiple devices on the same communication line. As a result, the total length and / or number of communication lines within a given vehicle can be significantly reduced.

[0065] Testing method

[0071] The following paragraphs provide examples of methods for testing varistors and / or varistor arrays to determine the characteristics of various varistors.

[0066] Transient energy capability

[0072] The transient energy capabilities of the varistors and / or varistor arrays described herein can be measured using a waveform generator and / or pulse generator, such as the Frothingham FEC CV300B. The varistor / varistor array may be subjected to a current wave of 10 × 1000 μs. The peak current value can be empirically selected to determine the maximum energy that the varistor / varistor array can dissipate without failure (e.g., due to overheating). An example of a pulse or wave of current is shown in Figure 5. The current (vertical axis 502) is plotted against time (horizontal axis 504). The current increases to a peak current value 506 and then decays. The "rise" time period (shown by the vertical dotted line 505) is from the start of the current pulse (t=0) until the current reaches 90% of the peak current value 506 (shown by the horizontal dotted line 508). The "decay time" (shown by the vertical dotted line 510) is the time from the start of the current pulse (t=0) until the current returns to 50% of the peak current value 506 (shown by the horizontal dotted line 512). For a pulse of 10 × 1000 μs, the "rise time" is 10 μs and the decay time is 1000 μs.

[0067]

[0073] The voltage across a varistor / varistor array can be measured while a pulse passes through it. Figure 6 shows an example of a plot of the current (horizontal axis 602) passing through a varistor / varistor array against the voltage (vertical axis 604). Figure 6 will be explained in detail below.

[0068]

[0074] The transient energy handling capability of a varistor or varistor array in accordance with this subject matter can be determined by calculating the amount of energy that passes through the varistor / varistor array. More specifically, the transient energy rating can be calculated by integrating the product of the measured current and the measured voltage over the time between pulses.

[0069]

Number

[0070] Here, E is the total energy dissipated by the varistor / varistor array, I is the instantaneous current through the varistor / varistor array, V is the instantaneous voltage of the varistor array, and t represents time.

[0071]

[0075] Alternatively, a rectangular current pulse with a fixed duration of 2 ms can be applied to the varistor / varistor array using a waveform generator and / or a pulse generator such as the Frothingham FEC CV300B. The current through the varistor / varistor array and the voltage of the varistor / varistor array can be detected as described above. The total energy (joules) absorbed by the varistor / varistor array can be determined based on the measured current and voltage as described above. The current amplitude of the applied rectangular current pulse can be determined based on the active volume of the varistor / varistor array. The active volume of the varistor / varistor array can be defined as the product of the number of active electrodes by the area of the active electrodes and multiplied by the thickness of the dielectric layer between the active electrodes.

[0072]

[0076] When using any of the above methods to determine the transient energy capability of the varistor / varistor array, the transient energy capability per unit active volume of the varistor / varistor array can be determined by dividing the transient energy capability of the varistor / varistor array by the active volume of the varistor / varistor array. The varistor / varistor array, when tested with a 10×1000 μs current wave, is at least about 0.05 J / mm 3 , in some embodiments at least about 0.1 J / mm 3 , in some embodiments at least about 0.2 J / mm 3 , in some embodiments at least about 0.5 J / mm 3In addition, in some embodiments, at least about 1.0 J / mm 3 It may possess transient energy capabilities per unit active volume.

[0073]

[0077] Furthermore, a series of iterative electrostatic discharge attacks may be applied to determine the electrostatic discharge capability of a varistor or varistor array. For example, electrostatic discharge attacks of 5000 to 8000 volts can be applied to a varistor / varistor array. The breakdown voltage of the varistor / varistor array can be measured at regular intervals during this series of attacks (described later). The breakdown voltage of the varistor / varistor array after the electrostatic discharge attacks can be measured and compared to the initial breakdown voltage before the attacks.

[0074] Breakdown voltage

[0003] The breakdown voltage of a varistor or varistor array can be measured using a Keithley 2400 series source measure unit (SMU), such as the Keithley 2410-C SMU. By definition, the breakdown voltage is the voltage of a varistor / varistor array at low current. Typically, the breakdown voltage is measured at a current of 1 milliampere (mA).

[0075] Clamp voltage

[0078] The clamp voltage is the transition voltage or conduction start voltage of a varistor / varistor array. A varistor / varistor array can receive an 8 / 20 μs current wave, for example, according to ANSI standard C62.1. Typically, the clamp voltage is measured at currents of 1 ampere (A), 5 A, or 10 A.

[0076] Peak current

[0079] The peak current is the maximum current that a varistor / varistor array can withstand, measured, for example, using an 8 / 20 μs current pulse or other current pulses. Examples of current pulses, such as 8 / 20 μs and 10 / 1000 μs, are shown in Figure 5. Current (vertical axis 502) is plotted against time (horizontal axis 504). The current may increase to a peak current value 506 and then decay. The "rise" time period (shown by the vertical dotted line 505) is from the start of the current pulse (t=0) until the current reaches 90% of the peak current value 506 (shown by the horizontal dotted line 508). The "rise" time may be, for example, 8 μs. The "decay time" (shown by the vertical dotted line 510) is from the start of the current pulse (t=0) until the current reaches 50% of the peak current value 506 (shown by the horizontal dotted line 512). The "decay time" may be, for example, 20 μs. The clamp voltage is measured as the maximum voltage of the varistor / varistor array during a current wave.

[0077]

[0080] Referring to Figure 6, the current per unit area (horizontal axis 602) through the varistor / varistor array is plotted against the voltage per unit length (vertical axis 604) of the varistor / varistor array. Over the pre-breakdown voltage range 612, the varistor / varistor array can generally represent a first response curve, and over the nonlinear voltage range 614, which is above the pre-breakdown voltage range 612 and below the clamp voltage 606, the varistor / varistor array can generally represent a second response curve. An ideal varistor / varistor array can generally represent voltages that follow approximately the following relationship.

[0078]

number

[0079] Here, V represents voltage, I represents current, C is a constant, and α is defined as follows in the nonlinear region 614.

[0080]

number

[0081]

[0081] In the pre-breakdown voltage range 612, the voltage per unit length generally increases at a larger rate with respect to the current per unit area through the varistor / varistor array than in the nonlinear region 614. Over the upturn voltage range 616 above the clamp voltage 606, the varistor / varistor array can generally exhibit a third response curve, where the voltage per unit length generally increases at a larger rate with respect to the current per unit area through the varistor / varistor array than in the nonlinear region 614.

[0082] capacitance

[0082] The capacitance of the varistor / varistor array can be measured using a Keithley 3330 Precision LCZ meter with a DC bias of 0.0 volts (a sinusoidal signal with a mean-squared ratio of 0.5 volts). The operating frequency is 1 MHz. The temperature is room temperature (approximately 23°C) and the relative humidity is 25%.

[0083]

[0083] These and other modifications and variations of the present invention can be carried out by those skilled in the art without departing from the spirit and scope of the invention. Furthermore, it should be understood that the features of various embodiments can be replaced in whole or in part. Furthermore, those skilled in the art will understand that the above description is merely illustrative and is not intended to limit the invention described in the appended claims.

Claims

1. It is a barista array, A monolithic body comprising a plurality of dielectric layers stacked in the Z direction perpendicular to the vertical direction, having a first end and a second end separated from the first end in the vertical direction, The first varistor formed in the monolithic body, The monolithic body includes a second varistor, which is separate from the first varistor, The first barista was, The first external terminal located at the first end of the monolithic body, A plurality of first active electrodes connected to the first external terminal, The second external terminal located at the second end of the monolithic body, A second plurality of active electrodes connected to the second external terminal, wherein each active electrode of the second plurality of active electrodes is on the same plane as each active electrode of the first plurality of active electrodes, A plurality of floating electrodes overlapping the first plurality of active electrodes along a first overlap area, wherein the first overlap area is insensitive to relative misalignment between the first plurality of active electrodes and the plurality of floating electrodes, and the floating electrodes overlap the second plurality of active electrodes along a second overlap area, wherein the second overlap area is insensitive to relative misalignment between the second plurality of active electrodes and the plurality of floating electrodes that is below a threshold, Includes, The aforementioned second barista, A first external terminal located at the first end of the monolithic body, which is separate from the first external terminal of the first varistor, A first plurality of active electrodes connected to the first external terminal, which are different from the first plurality of active electrodes of the first varistor, and the first plurality of active electrodes of the second varistor, A second external terminal located at the second end of the monolithic body, which is separate from the second external terminal of the first varistor, A second plurality of active electrodes connected to the second external terminal of the second varistor, which are separate from the second plurality of active electrodes of the first varistor, and each of the second plurality of active electrodes of the second varistor is on the same plane as each of the active electrodes of the first plurality of active electrodes of the second varistor, A plurality of floating electrodes, separate from the plurality of floating electrodes of the first varistor, which overlap with the first plurality of active electrodes of the second varistor along a first overlap area, the first overlap area being insensitive to relative misalignments below a threshold between the first plurality of active electrodes of the second varistor and the plurality of floating electrodes of the second varistor, and which overlap with the second plurality of active electrodes of the second varistor along a second overlap area, including, Barista Array.

2. A varistor array according to claim 1, wherein each of the plurality of floating electrodes of the first varistor and the second varistor has a lateral width that is greater in the lateral direction than the width of the first plurality of active electrodes of the first varistor or the second varistor, and the width of the first overlap area between the plurality of floating electrodes and the first plurality of active electrodes is equal to the width of the first plurality of active electrodes.

3. A varistor array according to claim 1, wherein each of the plurality of floating electrodes of the first varistor and the second varistor has a lateral width that is smaller in the lateral direction than the width of the first plurality of active electrodes of the first varistor or the second varistor, and the width of the first overlap area between the plurality of floating electrodes and the first plurality of active electrodes is equal to the width of the plurality of floating electrodes.

4. A varistor array according to claim 1, wherein the first varistor exhibits a capacitance less than 50 pF when a DC bias of 0.0 volts and a mean square sinusoidal signal of 0.5 volts are used at an operating frequency of 1 MHz, a temperature of approximately 23°C, and a relative humidity of 25%.

5. A varistor array according to claim 4, wherein the second varistor, at an operating frequency of 1 MHz, a temperature of approximately 23°C, and a relative humidity of 25%, exhibits a second capacitance when a 0.0 volt DC bias and a 0.5 volt root mean square sinusoidal signal are used. A varistor array in which the second capacitance represented by the second varistor is within 5% of the capacitance represented by the first varistor.

6. It is a barista array, A monolithic body comprising a plurality of dielectric layers stacked in the Z direction perpendicular to the vertical direction, the monolithic body having a first end and a second end separated from the first end in the vertical direction, The first varistor formed in the monolithic body, The monolithic body includes a second varistor, which is separate from the first varistor, The first barista was, The first external terminal located at the first end of the monolithic body, A plurality of first active electrodes connected to the first external terminal, The second external terminal located at the second end of the monolithic body, A second plurality of active electrodes connected to the second external terminal, wherein each active electrode of the second plurality of active electrodes is on the same plane as each active electrode of the first plurality of active electrodes, A plurality of floating electrodes overlapping the first plurality of active electrodes along a first overlap area, wherein the floating electrodes include a plurality of floating electrodes overlapping the second plurality of active electrodes along a second overlap area. The ratio of the first overlap area to the second overlap area is in the range of 0.9 to 1.

1. The aforementioned second barista, A first external terminal located at the first end of the monolithic body, which is separate from the first external terminal of the first varistor, A first plurality of active electrodes connected to the first external terminal, which are different from the first plurality of active electrodes of the first varistor, and the first plurality of active electrodes of the second varistor, A second external terminal located at the second end of the monolithic body, which is separate from the second external terminal of the first varistor, A second plurality of active electrodes connected to the second external terminal, which are separate from the second plurality of active electrodes of the first varistor, and each of the second plurality of active electrodes of the second varistor is on the same plane as each of the active electrodes of the first plurality of active electrodes of the second varistor, A plurality of floating electrodes, separate from the plurality of floating electrodes of the first varistor, which overlap with the first plurality of active electrodes of the second varistor along a first overlap area and overlap with the second plurality of active electrodes of the second varistor along a second overlap area, Includes, The ratio of the first overlap area to the second overlap area is in the range of 0.9 to 1.

1. Barista Array.

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