Circuits and waveform sensors

Abstract

To increase the frequency of sampling by a waveform sensor.SOLUTION: There is provided a circuit including: a first circuit and a second circuit; and a controller, the first circuit and the second circuit each having a sample hold circuit and an analog-digital conversion circuit, the sample hold circuit holding the level of an input signal at a specific point of time and the analog-digital conversion circuit converting the level of the input signal held in the sample hold circuit to digital data and outputting the digital data, and the controller outputting the level of the input signal at the first point of time to the first circuit and outputting the level of the input signal at a second point of time to the second circuit.SELECTED DRAWING: Figure 13

Description

[Technical Field]

[0001] This disclosure relates to circuits and waveform sensors. [Background technology]

[0002] Conventionally, there is a known technology for detecting the position of an electronic pen by detecting a waveform such as a sine wave transmitted wirelessly from the electronic pen using a tablet or the like. As a technology for converting the analog signal indicating the position of the electronic pen into a digital signal, for example, successive approximation register (SAR) analog-to-digital converter (ADC) and column ADCs, which provide an ADC for each column, are known technologies. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Patent No. 5745712 [Overview of the project] [Problems that the invention aims to solve]

[0004] However, with conventional technology, it can be difficult to improve the sampling frequency in, for example, waveform sensors. Other challenges and novel features will become apparent from the description and accompanying drawings herein. [Means for solving the problem]

[0005] In one embodiment, a circuit is provided that includes a first circuit and a second circuit, each having a sample-and-hold circuit that holds the level of an input signal at a specific point in time, and an analog-to-digital conversion circuit that converts the level of the input signal held by the sample-and-hold circuit into digital data and outputs it, and a control unit that causes the first circuit to output the level of the input signal at a first point in time, and the second circuit to output the level of the input signal at a second point in time. [Effects of the Invention]

[0006] From one perspective, it is possible to improve the sampling frequency of the waveform sensor. [Brief explanation of the drawing]

[0007] [Figure 1] This figure shows an example of the configuration of a waveform sensor according to the first embodiment. [Figure 2] This is a timing chart showing an example of the processing of a waveform sensor according to the first embodiment. [Figure 3] This is a timing chart showing an example of the processing of a waveform sensor according to the first embodiment. [Figure 4] This figure shows an example of a process in which the value being sampled and held by the second capacitor is performed AD conversion while the sampled and held value is being sampled and held by the first capacitor in the sampled and held circuit according to the first embodiment. [Figure 5] This figure shows an example of a process in which a value sampled and held by the first capacitor is AD converted while a sample is being sampled and held by the second capacitor of the sample-and-hold circuit according to the first embodiment. [Figure 6] This figure shows an example of the configuration of a waveform sensor according to the second embodiment. [Figure 7] This figure shows an example of the voltage amplitude of an analog signal according to the second embodiment. [Figure 8] This figure shows an example of the absolute value of the change in the amplitude of the analog signal voltage from the previous sampling point at each sampling point according to the second embodiment. [Figure 9]It is a diagram showing an example of the polarity value of the amount of change in the amplitude of an analog signal voltage from the previous sampling time point at each sampling time point according to the second embodiment. [Figure 10] It is a diagram showing an example of the calculation result of the amplitude of the voltage of an analog signal at each sampling time point according to the second embodiment. [Figure 11] It is a flowchart showing an example of the processing of a waveform sensor according to the second embodiment. [Figure 12] It is a timing chart showing an example of the processing of a waveform sensor according to the second embodiment. [Figure 13] It is a diagram showing an example of the configuration of a waveform sensor according to the third embodiment. [Figure 14] It is a timing chart showing an example of the process of storing the calibration value DCAL in the calibration value storage latch according to the third embodiment. [Figure 15] It is a timing chart showing an example of the AD conversion process of an analog signal according to the third embodiment.

Modes for Carrying Out the Invention

[0008] The principles of the present disclosure are described with reference to several exemplary embodiments. These embodiments are described for illustrative purposes only and are intended to assist those skilled in the art in understanding and implementing the present disclosure without suggesting any limitation on the scope of the present disclosure. The disclosure described herein may be implemented in various ways other than those described below. In the following description and claims, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0009] (First Embodiment) <Configuration> Referring to Figure 1, the configuration of the waveform sensor 1 according to the first embodiment will be described. Figure 1 is a diagram showing an example of the configuration of the waveform sensor 1 according to the first embodiment. The waveform sensor 1 has a circuit 10 and an antenna coil group 20.

[0010] Each antenna coil in the antenna coil group 20 receives a sinusoidal analog signal transmitted from an electronic pen in the vertical or horizontal (column) direction on the screen of an information processing device such as a tablet, smartphone, or laptop computer. Of the antenna coils in the antenna coil group 20, the antenna coil closest to the electronic pen detects the sinusoidal wave with the largest amplitude. Therefore, the position of the electronic pen on the screen can be calculated by stacking a waveform sensor 1 with a vertical column and a waveform sensor 1 with a horizontal column.

[0011] Circuit 10 includes an antenna coil switching switch 11, a gain amplifier 12, an input signal reset switch 13, a RAMP generation circuit 14, a control unit 15, a bias 17, and a global counter 18. Circuit 10 also includes ADC (Analog-to-Digital Converter) circuits 16-1, 16-2, ..., 16-n (hereinafter referred to simply as "ADC circuit 16" unless otherwise specified). Hereinafter, n is any natural number. Each of the ADC circuits 16-1, 16-2, ..., 16-n includes a sample-and-hold circuit 161-1, 161-2, ..., 161-n (hereinafter referred to simply as "sample-and-hold circuit 161" unless otherwise specified).

[0012] Each of the ADC circuits 16-1, 16-2, ..., 16-n has a first terminal 160A-1, 160A-2, ..., 160A-n (hereinafter referred to simply as "first terminal 160A" when there is no need to distinguish between them) and a second terminal 160B-1, 160B-2, ..., 160B-n (hereinafter referred to simply as "second terminal 160B" when there is no need to distinguish between them).

[0013] Furthermore, circuit 10 has latches 19-1, 19-2, ..., 19-n (hereinafter, unless otherwise specified, they will simply be referred to as "latch 19"). Note that circuit 10 may be implemented as a single chip (integrated circuit).

[0014] The antenna coil selector switch 11 switches (selects) the antenna coil that outputs a signal to the circuit 10 from among the antenna coils included in the antenna coil group 20. The RAMP generation circuit 14 outputs a signal (RAMP signal, reference signal) to each ADC circuit 16 in which the voltage increases or decreases linearly (like a linear function) with respect to time (changing with a constant slope).

[0015] The control unit 15 controls each ADC circuit 16 by transmitting signals to each ADC circuit 16. The control unit 15 transmits the same auto-zero signal AZ (common to each ADC circuit 16) and control signals TH[1:n] (TH[1]~TH[n]) that specify the sampling timing for each ADC circuit 16 to each ADC circuit 16.

[0016] The control unit 15 turns on the switches of each sample-and-hold circuit 161 by setting (changing) the auto-zero signal AZ to LOW at a certain time point t0, causing the analog signal SIG to be input (captured) into each ADC circuit 16. Then, the control unit 15 sequentially turns off the switches of each sample-and-hold circuit 161 at different time points, causing each sample-and-hold circuit 161 to record the amplitude value of the analog signal SIG at each time point. Then, the control unit 15 performs AD conversion on the values ​​recorded in each sample-and-hold circuit 161 and outputs them. More specifically, the control unit 15 performs AD conversion on each time point t1, ..., t n The input voltage VINP[1:n] of the analog signal SIG is recorded in the sample-and-hold circuits 161-1, 161-2, ..., 161-n of each ADC circuit 16, and the recorded values ​​(level and amplitude values) are converted using AD conversion and output. As a result, for example, by providing 32 ADC circuits capable of sampling at a maximum of 250 kHz for one column, that column can be sampled at 8 MHz.

[0017] The bias 17 supplies power to each ADC circuit 16. The global counter 18 supplies counter signals to each latch 19.

[0018] The ADC circuit 16 has a first terminal (first input section) 160A that receives an analog signal SIG from one of the antenna coils included in the antenna coil group 20, and a second terminal (second input section) 160B that receives a RAMP signal from the RAMP generation circuit 14. The ADC circuit 16 converts the analog signal SIG into a digital (discrete) signal.

[0019] The ADC circuit 16 has a so-called single-slope ADC. Therefore, the ADC circuit 16 starts the counter while the voltage of the RAMP signal input to the second terminal 160B is changing. When the voltage of the RAMP signal input to the second terminal 160B exceeds (crosses) the voltage (pixel voltage) of the sample-and-hold analog signal SIG input to the first terminal 160A, the comparator inverts, and as a result, the counter value is held in the latch 19. Therefore, the longer the time from when the counter is started until it is stopped, the larger the counter value (counter code) obtained becomes. In the first embodiment, the counter value is a digital value corresponding to the voltage of the analog signal SIG.

[0020] <Processing (Action)> Next, an example of the processing of the waveform sensor 1 according to the first embodiment will be described with reference to Figures 2 to 5. Figures 2 and 3 are timing charts showing an example of the processing of the waveform sensor 1 according to the first embodiment. Figure 4 is a diagram showing an example of the process of performing AD conversion on the value sampled and held in the second capacitor while the sampled and held circuit 161 according to the first embodiment is being sampled and held in the first capacitor. Figure 5 is a diagram showing an example of the process of performing AD conversion on the value sampled and held in the first capacitor while the sampled and held circuit 161 according to the first embodiment is being sampled and held in the second capacitor.

[0021] Figures 2 and 3 show an example where the number n of ADC circuits 16 is 16, with time on the horizontal axis, and the waveform 201 of the voltage amplitude of the analog signal SIG from one antenna coil, the auto-zero signal AZ, the state RS of the input signal reset switch 13, the control signals TH[1]~

[16] from the control unit 15 to each ADC circuit 16, and the value of the global counter 18.

[0022] Figure 2 also shows a comparison between the waveform 202 of the input voltage VINP[1] at the first terminal 160A, where the analog signal SIG is input, and the waveform 203 of the input voltage VINM[1] at the second terminal 160B, where the RAMP signal is input (the waveform of the common RAMP signal voltage). Since the ADC circuit 16 is a so-called single-slope ADC, the digital value corresponding to the voltage of the analog signal SIG when waveforms 302 and 303 cross is converted from analog to digital and output. The input voltages VINP[1:n] correspond to the signals input to the input terminal of the first amplifier AMP (1st AMP) in each ADC circuit 16-1 to n. Therefore, the input voltage VINP[1] corresponds to the signal input to the input terminal of the first amplifier AMP in the ADC circuit 16-1.

[0023] Figure 2 also shows the output state COMPOUT[1] from ADC circuit 16-1 to latch 19-1, and the AD conversion result (ADC1 conversion result) of ADC circuit 16-1.

[0024] The state RS of the input signal reset switch 13, as shown in Figure 1, indicates that it is connected to ground (earth) when HIGH (high, H, 1) and to the antenna coil when LOW (low, L, 0). The output state COMPOUT[1] indicates that there is no output when LOW (L, 0) and that there is an output when HIGH (H, 1).

[0025] Figure 3 also shows a comparison between the waveform 301 of the input voltage VINP

[13] at the first terminal 160A, where the analog signal SIG is input, and the waveform 203 of the input voltage VINM

[13] at the second terminal 160B, where the RAMP signal is input (the waveform of the common RAMP signal voltage). Figure 3 also shows the output state COMPOUT

[13] from ADC circuit 16-13 to latch 19-13, and the AD conversion result in ADC circuit 16-13 (ADC13 conversion result). The input voltage VINP

[13] corresponds to the signal input to the input terminal of the first amplifier AMP in ADC circuit 16-13.

[0026] (An example of a configuration that operates in a pipeline) As shown in Figures 4 and 5, the waveform sensor 1 may operate the sample-and-hold circuit 161 and the ADC circuit 16 in a pipeline configuration. This allows, for example, the sample-and-hold process using one of the multiple capacitors included in the sample-and-hold circuit 161 to be performed in parallel with the AD conversion process of the value being sampled and held using the other capacitors included in the same multiple capacitors.

[0027] In the examples shown in Figures 4 and 5, the sample-and-hold circuit 161 includes capacitors 1611 and 1612, switches 1613, 1614, 1615, and 1616, etc. The number of capacitors and switches in the sample-and-hold circuit 161 is not limited to the examples in Figures 4 and 5.

[0028] In the example shown in Figure 4, while the sample-and-hold circuit 161 is being sampled and held at capacitor 1611, the sampled and held value at capacitor 1612 is converted by ADC circuit 16. Once the sampled and held value at capacitor 1612 is converted, switches 1613, 1614, 1615, and 1616 are switched on and off respectively, resulting in the state shown in Figure 5.

[0029] In the example shown in Figure 5, while the sample-and-hold circuit 161 is being sampled and held at capacitor 1612, the value being sampled and held at capacitor 1611 is converted by ADC circuit 16. Once the value being sampled and held at capacitor 1611 is converted, switches 1613, 1614, 1615, and 1616 are switched on and off respectively, and the system returns to the state shown in Figure 4.

[0030] (Second Embodiment) In the first embodiment, an example was described in which AD conversion was performed after sampling and holding in all sample-and-hold circuits 161. In the second embodiment, an example is described in which the dynamic range of the RAMP signal (ramp wave) is narrowed compared to the first embodiment by inputting the difference voltage between the previous voltage and the current voltage into the first amplifier AMP in each ADC circuit 16. The period for performing AD conversion in a single-slope ADC changes according to the period for increasing or decreasing the ramp wave. When the dynamic range of the ramp wave decreases, the period for increasing or decreasing the ramp decreases. Therefore, according to the second embodiment, the period for performing AD conversion processing can be shortened compared to the first embodiment. As a result, the sampling frequency can be further improved. Below, the differences between the second embodiment and the first embodiment will be mainly described. Note that the configuration of the second embodiment and at least a part of the configuration of the first embodiment (for example, the pipeline operation configuration described above) can be combined as appropriate.

[0031] <Structure> Referring to Figure 6, the configuration of the waveform sensor 1 according to the second embodiment will be described. Figure 6 is a diagram showing an example of the configuration of the waveform sensor 1 according to the second embodiment. The waveform sensor 1 according to the second embodiment differs from the waveform sensor 1 according to the first embodiment in Figure 1 in that it has a RAMP generation circuit 14A and a control unit 15A instead of the RAMP generation circuit 14 and control unit 15. It also differs in that it has a multiply-accumulate operation circuit 21. Furthermore, each ADC circuit 16-1, 16-2, ..., 16-n mainly differs in that it has an up / down lamp switching switch 162-1, 162-2, ..., 162-n (hereinafter referred to simply as "up / down lamp switching switch 162" when there is no need to distinguish between them) and a code determination device 163-1, 163-2, ..., 163-n (hereinafter referred to simply as "code determination device 163" when there is no need to distinguish between them). In the example in Figure 6, the code determination device 163 is implemented using a so-called D latch.

[0032] The RAMP generation circuit 14A sets the intercept to a specific voltage (for example, a voltage about half the power supply voltage) and outputs a signal whose voltage increases linearly (linearly) with respect to time (upward RAMP signal) and a signal whose voltage decreases linearly (linearly) with respect to time (downward RAMP signal) to each ADC circuit 16.

[0033] The control unit 15A controls each ADC circuit 16 by transmitting signals to each ADC circuit 16. The control unit 15A transmits an auto-zero signal AZ[1:n](AZ[1]~AZ[n]) to each ADC circuit 16, instructing it to acquire the data sampled at the previous sampling point. In addition, the control unit 15A transmits a control signal TH[1:n](TH[1]~TH[n]) to each ADC circuit 16, similar to the control unit 15 in the first embodiment, specifying the sampling timing for each ADC circuit 16. Furthermore, the control unit 15A transmits the same signal GT (common to each ADC circuit 16) to each ADC circuit 16 to control the code discriminator 163 of each ADC circuit 16.

[0034] In the example shown in Figure 6, similar to the first embodiment in Figure 1, the ADC circuit 16 has a so-called single-slope ADC. Therefore, when the voltage of the RAMP signal input to the second terminal 160B exceeds (crosses) the voltage (pixel voltage) of the sample-and-hold analog signal SIG input to the first terminal 160A, the comparator inverts and the counter stops. In the second embodiment, the counter value is a digital value corresponding to the change in the voltage of the analog signal SIG (the derivative of the waveform of the analog signal SIG).

[0035] <Processing (Action)> Next, an example of the processing of the waveform sensor 1 according to the second embodiment will be described with reference to Figures 7 to 10. Figure 7 is a diagram showing an example of the amplitude of the voltage of the analog signal SIG according to the second embodiment. Figure 8 is a diagram showing an example of the absolute value of the change in the amplitude of the voltage of the analog signal SIG from the previous sampling time at each sampling time according to the second embodiment. Figure 9 is a diagram showing an example of the polarity value of the change in the amplitude of the voltage of the analog signal SIG from the previous sampling time at each sampling time according to the second embodiment. Figure 10 is a diagram showing an example of the calculation result of the amplitude of the voltage of the analog signal SIG at each sampling time according to the second embodiment.

[0036] The control unit 15A determines the sampling time t for each ADC circuit 16 (hereinafter referred to as "ADC circuit 16-i," where i is a natural number from 1 to n). i From the previous sampling point t i-1 By setting (changing) the auto-zero signal AZ[i] for the ADC circuit 16-i to LOW, the analog signal SIG is input to (captured by) the ADC circuit 16-i.

[0037] Then, the control unit 15A determines the sampling time t i By setting (changing) the control signal TH[i] for the ADC circuit 16-i to LOW, the switch of the ADC circuit 16-i is turned off, at time t i-1 From point t iThe value indicating the amount of change (differential voltage) in the amplitude of the analog signal SIG up to a certain point is recorded in the sample-and-hold circuit 161-i. Then, the control unit 15A outputs the value DOUT[i], which is the result of AD-converting the counter value corresponding to the level recorded in the sample-and-hold circuit 161-i, to the multiplication and summation circuit 21.

[0038] Also, the control unit 15A, during the period from the sampling time point t i to the next sampling time point in the ADC circuit 16-i, for the period from the time point t i-1 to the time point t i causes the sign determination unit 163-i to output to the multiplication and summation circuit 21 a value SIGN[i] indicating the polarity (sign, + or -) of the amount of change in the amplitude of the analog signal SIG. For example, if the output from the sign determination unit 163 is LOW, it is set to -1, and if it is HIGH, it is set to +1.

[0039] Then, the multiplication and summation circuit 21 calculates the value CODE[i] indicating the amplitude of the analog signal SIG at a certain time point t i as shown in the following formula (1).

Equation

[0040] According to formula (1), for each ADC circuit 16 from the ADC circuit 16-1 to the ADC circuit 16-i, the value obtained by multiplying the value DOUT and the value SIGN is calculated, and the values at each ADC circuit 16 are added (summed).

[0041] In FIG. 7, an example of the waveform 701 of the analog signal SIG is shown, with the horizontal axis representing time and the vertical axis representing the voltage of the analog signal SIG. In FIG. 8, with the number n of ADC circuits 16 being 32, an example of the waveform 801 of the absolute value DOUT[i] of the amount of change in amplitude with respect to the waveform 701 of the analog signal SIG in FIG. 7 is shown, with the horizontal axis representing each sampling time point and the vertical axis representing the value DOUT[i] of the AD conversion result at each ADC circuit 16.

[0042] Figure 9 shows an example of the waveform 901 of the polarity SIGN[i] for the amplitude change of the analog signal SIG waveform 701 in Figure 7, with the number of ADC circuits 16 n set to 32, the horizontal axis representing each sampling time, and the vertical axis representing the value of SIGN[i] at each ADC circuit 16. Figure 10 shows an example of the waveform 1001 of CODE[i] for the analog signal SIG waveform 701 in Figure 7, with the number of ADC circuits 16 n set to 32, the horizontal axis representing each sampling time, and the vertical axis representing the value of CODE[i], which indicates the amplitude of the analog signal SIG. It can be seen that the sine wave analog signal SIG is digitized (restored) by CODE[i] through the above process.

[0043] Next, with reference to Figures 11 and 12, a more detailed example of the processing of the waveform sensor 1 according to the second embodiment will be described. Figure 11 is a flowchart showing an example of the processing of the waveform sensor 1 according to the second embodiment. Figure 12 is a timing chart showing an example of the processing of the waveform sensor 1 according to the second embodiment. Note that the order of processing in Figure 11 may be changed as appropriate, as long as it is not contradictory.

[0044] In step S101, the control unit 15A sets the state RS of the input signal reset switch 13 to LOW, thereby inputting (receiving) the analog signal SIG from the antenna coil into each ADC circuit 16. Next, the control unit 15A initializes by setting all auto-zero signals AZ[1:n] and control signals TH[1:n] to HIGH (step S102). Subsequently, the control unit 15A sets the index i of the ADC circuit 16 to 1 (step S103).

[0045] Next, the control unit 15A determines the previous sampling time t i-1 In this case, by setting the auto-zero signal AZ[i] to the ADC circuit 16-i to LOW, at time t i-1 The analog signal SIG[i-1] is input to the sample-and-hold circuit 161-i (step S104).

[0046] Next, the control unit 15A determines the sampling time t iBy setting (changing) the control signal TH[i] for the ADC circuit 16-i to LOW, the switch of the ADC circuit 16-i is turned on, at time t i-1 From point t i The sample-and-hold circuit 161-i is instructed to record (sample and hold) a value representing the absolute amount of change in the amplitude of the analog signal SIG up to that point (step S105).

[0047] Next, the control unit 15A determines whether i is equal to n (step S106). If i is not equal to n (NO in step S106), the control unit 15A increments the value of i by 1 (step S107) and proceeds to the process in step S104.

[0048] On the other hand, if i is equal to n (YES in step S106), the control unit 15A latches the output result of the second amplifier of each ADC circuit 16 as the signal for SIGN by setting the signal GT to HIGH (step S108).

[0049] Next, the control unit 15A sets the signal GT to LOW to maintain the value SIGN[1:n] indicating the polarity of each ADC circuit 16 (step S109). Subsequently, the control unit 15A selects (determines) the RAMP signal to be used for each ADC circuit 16 from the up RAMP signal and the down RAMP signal, based on the value SIGN[1:n] indicating the polarity of the output of each ADC circuit 16 (step S110).

[0050] Next, each ADC circuit 16 uses the RAMP signal for the selected ADC circuit 16 to AD-convert the counter value corresponding to the level held by the sample-and-hold circuit 161, and outputs the resulting value DOUT to the multiply-accumulate circuit 21 (step S111).

[0051] Next, the sum-of-products circuit 21 performs a sum-of-products operation on the AD conversion result value DOUT from each ADC circuit 16 and the polarity value SIGN from each ADC circuit 16 using equation (1) (step S112). Here, the polarity value SIGN from each ADC circuit 16 is the polarity value of the change in the amplitude of the analog signal SIG voltage from the previous sampling point to each sampling point in each ADC circuit 16 (voltage difference). If the amplitude of the analog signal SIG voltage has increased from the previous sampling point to the current sampling point, the polarity value is +1. On the other hand, if the amplitude of the analog signal SIG voltage has decreased from the previous sampling point to the current sampling point, the polarity value is -1.

[0052] Figure 12 shows an example where the number n of ADC circuits 16 is 16, with time on the horizontal axis, and includes the amplitude 1201 of the voltage of the analog signal SIG from one antenna coil, the state RS of the input signal reset switch 13, the auto-zero signals AZ[1]~

[16] , the control signals TH[1]~

[16] from the control unit 15A to each ADC circuit 16, the signal GT, and the value of the global counter 18. Figure 12 also shows the waveform 1202 of the upwave RAMP signal (URAMP) and the waveform 1203 of the downwave RAMP signal (DRAMP).

[0053] Since the polarity value SIGN[1] of ADC circuit 16-1 is -1, the downstream RAMP signal is selected as the RAMP signal for ADC circuit 16-1.

[0054] Figure 12 also shows a comparison between the waveform 1211 of the input voltage VINP[1] at the first terminal 160A, where the analog signal SIG is input, and the waveform 1212 (waveform of the RAMP signal voltage) of the input voltage VINM[1] at the second terminal 160B, where the RAMP signal is input. Since the ADC circuit 16 is a so-called single-slope ADC, the digital value corresponding to the voltage of the analog signal SIG when waveforms 1211 and 1212 cross is converted from analog to digital and output.

[0055] Figure 12 also shows the polarity value SIGN[1] of ADC circuit 16-1, the output state COMPOUT[1] from ADC circuit 16-1 to latch 19-1, and the AD conversion result (ADC1 conversion result) of ADC circuit 16-1.

[0056] (Third embodiment) In the second embodiment, for example, if the output of the ADC circuit 16 is relatively close to 0, device noise or the like may cause an error in the value SIGN, which indicates the polarity of the output. In this case, an error occurs in the selection of the RAMP signal during the processing of step S110 in Figure 11, so the waveform of the input voltage VINP at the first terminal 160A to which the analog signal SIG is input and the waveform of the input voltage VINM at the second terminal 160B to which the RAMP signal is input do not cross. In this case, since the ADC circuit 16 is a so-called single-slope ADC, the maximum value of the counter is output as the AD conversion result. Therefore, a relatively large AD conversion error occurs.

[0057] In the third embodiment, an error correction function is incorporated to reduce AD ​​conversion errors when an error occurs in the output polarity value SIGN due to device noise or the like, as in the second embodiment. The following will mainly describe the differences between the third embodiment and the second embodiment.

[0058] <Structure> Referring to Figure 13, the configuration of the waveform sensor 1 according to the third embodiment will be described. Figure 13 is a diagram showing an example of the configuration of the waveform sensor 1 according to the third embodiment. The waveform sensor 1 according to the third embodiment differs from the waveform sensor 1 according to the second embodiment shown in Figure 6 in that it has a RAMP generation circuit 14B, a control unit 15B, and a multiply-accumulate circuit 21B instead of a RAMP generation circuit 14A, a control unit 15A, and a multiply-accumulate circuit 21.

[0059] Furthermore, the waveform sensor 1 according to the third embodiment differs from the waveform sensor 1 according to the second embodiment shown in Figure 6 mainly in that it has calibration value storage latches 30-1, 30-2, ..., 30-n (hereinafter, when there is no need to distinguish between them, they will also simply be referred to as "calibration value storage latches 30") which are associated with each of the ADC circuits 16-1, 16-2, ..., 16-n and store calibration values ​​for each ADC circuit 16.

[0060] The calibration value DCAL[i] for each ADC circuit 16, stored in each calibration value storage latch 30, is a value used to calibrate the AD conversion result value DOUT[i] in each ADC circuit 16 according to the device noise and other factors occurring in each ADC circuit 16.

[0061] The control unit 15B differs from the control unit 15A in the second embodiment in that it transmits a control signal DCAL_LATCH to the calibration value storage latch 30.

[0062] The RAMP generation circuit 14B outputs to each ADC circuit 16 a signal with a specific negative intercept that increases in voltage linearly (linearly) with respect to time (redundant upstream RAMP signal) and a signal with a specific positive intercept that decreases in voltage linearly (linearly) with respect to time (redundant downstream RAMP signal). As a result, even if an error occurs in the value SIGN indicating the output polarity due to device noise, etc., and an error occurs in the selection of the RAMP signal, the waveform of the input voltage VINP at the first terminal 160A to which the analog signal SIG is input and the waveform of the input voltage VINM at the second terminal 160B to which the RAMP signal is input will cross.

[0063] The sum-of-accumulate circuit 21B operates at a certain time t i The value CODE[i], which represents the amplitude of the analog signal SIG, is calculated as shown in equation (2) below.

number

[0064] According to equation (2), for each ADC circuit 16 from ADC circuit 16-1 to ADC circuit 16-i, a value is calculated by multiplying the value DOUT (DOUT[i]-DCAL[i]), which is obtained by calibrating the value DOUT with the calibration value DCAL, by the value SIGN, and these values ​​for each ADC circuit 16 are added together (summed). Note that the value of DOUT[i]-DCAL[i] is 0 or greater under normal circumstances, and becomes a negative value when an error occurs due to device noise, etc. Also, when an error occurs, the sign of the polarity value SIGN is incorrect (positive and negative are reversed). Therefore, by multiplying the value of DOUT[i]-DCAL[i] by the value of the polarity value SIGN[i], the sign of the polarity is corrected when an error occurs.

[0065] <Processing (Action)> In the third embodiment, the waveform sensor 1 stores the calibration value DCAL in the calibration value storage latch 30 before performing AD conversion processing on the analog signal SIG.

[0066] <<Process to store the calibration value DCAL in the calibration value storage latch 30>> Referring to Figures 11 and 14, an example of the process of storing the calibration value DCAL in the calibration value storage latch 30 according to the third embodiment will be described. Figure 14 is a timing chart showing an example of the process of storing the calibration value DCAL in the calibration value storage latch 30 according to the third embodiment.

[0067] The process of storing the calibration value DCAL in the calibration value storage latch 30 is the same as the process of performing AD conversion of the analog signal SIG in the waveform sensor 1 according to the second embodiment shown in Figure 11, except that the input to the first terminal 160A is ground (GND) instead of the analog signal SIG. Therefore, an example of a flowchart for the process of storing the calibration value DCAL in the calibration value storage latch 30 can be seen in Figure 11 by replacing "analog signal SIG" with "ground (GND)" or the like.

[0068] In the third embodiment, instead of step S101 in Figure 11, the waveform sensor 1 sets (switches) the state RS of the input signal reset switch 13 to HIGH, thereby inputting ground (GND) to the first terminal 160A for inputting the analog signal SIG of each ADC circuit 16. Then, in this state, the waveform sensor 1 in the third embodiment performs AD conversion on the value DOUT, which is obtained by AD conversion of the counter value corresponding to the level held by each sample-and-hold circuit 161 with ground input, in the same process as the process from step S102 onwards in Figure 11. Then, the waveform sensor 1 in the third embodiment stores the data of the value DOUT in the calibration value storage latch 30 by setting the control signal DCAL_LATCH to HIGH.

[0069] Figure 14 shows an example of the following parameters when the number n of ADC circuits 16 is 16, with time on the horizontal axis: the amplitude 1401 of the voltage input to the first terminal 160A, the state RS of the input signal reset switch 13, the auto-zero signals AZ[1]~

[16] , the control signals TH[1]~

[16] from the control unit 15B to each ADC circuit 16, the signal GT, and the value of the global counter 18 (Global Counter). Figure 14 also shows the waveform 1402 of the redundant upstream RAMP signal (URAMP) and the waveform 1403 of the redundant downstream RAMP signal (DRAMP).

[0070] Since the polarity value SIGN[1] of ADC circuit 16-1 is -1, the redundant downstream RAMP signal is selected as the RAMP signal for ADC circuit 16-1.

[0071] Figure 14 also shows a comparison between the waveform 1411 of the input voltage VINP[1] at the first terminal 160A, where the analog signal SIG is input, and the waveform 1412 (waveform of the RAMP signal voltage) of the input voltage VINM[1] at the second terminal 160B, where the RAMP signal is input. Since the ADC circuit 16 is a so-called single-slope ADC, the digital value corresponding to the voltage of the analog signal SIG when waveforms 1411 and 1412 cross is converted from analog to digital and output.

[0072] Figure 14 also shows the polarity value SIGN[1] of ADC circuit 16-1, the output state COMPOUT[1] from ADC circuit 16-1 to latch 19-1, and the AD conversion result (ADC1 conversion result) DOUT[1] from ADC circuit 16-1.

[0073] Figure 14 also shows the state of the control signal DCAL_LATCH and the calibration value DCAL[1] stored in the calibration value storage latch 30-1.

[0074] <<Performs AD conversion processing on the analog signal SIG>> Referring to Figures 11 and 15, an example of the AD conversion process of the analog signal SIG according to the third embodiment will be described. Figure 15 is a timing chart showing an example of the AD conversion process of the analog signal SIG according to the third embodiment.

[0075] The waveform sensor 1 according to the third embodiment performs the same processing as the waveform sensor 1 according to the second embodiment shown in Figure 11 after storing the calibration value DCAL in the calibration value storage latch 30 described above. However, in step S112 of Figure 11, the sum-of-products operation is performed using equation (2) instead of equation (1).

[0076] Figure 15 shows an example of the following parameters when the number n of ADC circuits 16 is 16, with time on the horizontal axis: the amplitude 1501 of the voltage input to the first terminal 160A, the state RS of the input signal reset switch 13, the auto-zero signals AZ[1]~

[16] , the control signals TH[1]~

[16] from the control unit 15B to each ADC circuit 16, the signal GT, and the value of the global counter 18 (Global Counter). Figure 15 also shows the waveform 1502 of the redundant upstream RAMP signal (URAMP) and the waveform 1503 of the redundant downstream RAMP signal (DRAMP).

[0077] Furthermore, Figure 15 shows the polarity value SIGN[6] of ADC circuit 16-1. Figure 15 also shows an example where the polarity value SIGN[6] of ADC circuit 16-6 is incorrectly determined to be -1 due to errors such as device noise. Therefore, a redundant downstream RAMP signal is selected as the RAMP signal for ADC circuit 16-6.

[0078] Figure 15 also shows a comparison between the waveform 1511 of the input voltage VINP[6] at the first terminal 160A, where the analog signal SIG is input, and the waveform 1512 (waveform of the RAMP signal voltage) of the input voltage VINM[6] at the second terminal 160B, where the RAMP signal is input. Since the ADC circuit 16 is a so-called single-slope ADC, the digital value corresponding to the voltage of the analog signal SIG when waveforms 1511 and 1512 cross is converted from analog to digital and output.

[0079] Figure 15 also shows the output state COMPOUT[6] from ADC circuit 16-1 to latch 19-1, and the AD conversion result (ADC6 conversion result) DOUT[6] from ADC circuit 16-6.

[0080] <Example of interleaved operation> In the second and third embodiments, multiple circuits 10 may be provided to enable interleaved operation. This allows for a longer sampling period, thereby improving the accuracy of position detection and other functions. In this case, the waveform sensor 1 may share a single set of components in the circuit 10, such as the antenna coil switching switch 11, the gain amplifier 12, and the input signal reset switch 13, across multiple circuits 10. Each circuit 10 may then perform AD conversion on analog signals SIG for different periods.

[0081] <Other> The above example describes an example of detecting a wireless waveform such as a sine wave from an electronic pen using a tablet or the like, but the waveform sensor 1 of this disclosure is not limited to this. The waveform sensor 1 of this disclosure can also be applied to (used as) an ADC for detecting a received light wave in a TOF (Time of Flight) sensor that measures the distance to a measurement target based on the phase difference between a projected light wave such as a sine wave and a received light wave.

[0082] The present invention has been described in detail above based on embodiments, but it goes without saying that the present invention is not limited to the embodiments already described, and various modifications are possible without departing from the spirit of the invention. [Explanation of Symbols]

[0083] 1. Waveform sensor 10 circuits 11 switches 12 Gain Amplifier 13. Input signal reset switch 14, 14A, 14B RAMP generation circuit 15, 15A, 15B Control Unit 16 ADC circuit 161 Sample-and-Hold Circuit 160A Terminal 1 160B 2nd terminal 162 switches 163 Sign checker 1611 capacity 1612 capacity 1613 Switch 1614 Switch 1615 Switch 1616 Switch 17. Bias 18 Global Counter 19 Latch 20 Antenna coil group 21, 21B Multiply-accumulate circuit 30 Calibration value storage latch

Claims

1. A first circuit and a second circuit each have a sample-and-hold circuit that holds the level of an input signal at a specific point in time, and an analog-to-digital conversion circuit that converts the level of the input signal held by the sample-and-hold circuit into digital data and outputs it. A control unit that outputs the level of the input signal at a first time point to the first circuit, and outputs the level of the input signal at a second time point to the second circuit, It has, Each of the first circuit and the second circuit is, A first terminal that receives the aforementioned input signal, It has a second terminal that receives a reference signal that changes with a constant slope, The analog-to-digital conversion circuit acquires the value of a counter from the time the voltage of the reference signal changes until the input signal and the reference signal cross over each other. Based on the polarity value of the difference between the amplitude of the input signal at the first time point and the amplitude of the input signal at the second time point, the reference signal is selected from a first reference signal that changes with a constant positive slope and a second reference signal that changes with a constant negative slope. It has a sum-of-products circuit that sums the values ​​obtained by multiplying the difference value and the polarity value, The first reference signal and the second reference signal cross at a specific point in time. The sum-of-accumulate circuit calculates the sum of the values ​​obtained by subtracting the calibration value (which is the result of analog-to-digital conversion with the input signal as ground) from the difference value and multiplying it by the polarity value. circuit.

2. The input signal is a sinusoidal signal detected by the antenna coil corresponding to the column of the waveform sensor. The circuit according to claim 1.

3. The sample-and-hold circuit, when sampling of the input signal is completed with the first capacitor, disconnects the first capacitor from the input signal and converts it into digital data, and simultaneously samples the input signal with the second capacitor. The circuit according to claim 1.

4. A first circuit and a second circuit each have an input section that receives an input signal that changes over time, a sample-and-hold circuit that holds the level of the input signal at a specific point in time, and an analog-to-digital conversion circuit that converts the level of the input signal held by the sample-and-hold circuit into digital data and outputs it. A control unit that outputs the level of the input signal at a first time point to the first circuit, and outputs the level of the input signal at a second time point to the second circuit, It has, Each of the first circuit and the second circuit is, A first terminal that receives the aforementioned input signal, It has a second terminal that receives a reference signal that changes with a constant slope, The analog-to-digital conversion circuit acquires the value of a counter from the time the voltage of the reference signal changes until the input signal and the reference signal cross over each other. Based on the polarity value of the difference between the amplitude of the input signal at the first time point and the amplitude of the input signal at the second time point, the reference signal is selected from a first reference signal that changes with a constant positive slope and a second reference signal that changes with a constant negative slope. It has a sum-of-products circuit that sums the values ​​obtained by multiplying the difference value and the polarity value, The first reference signal and the second reference signal cross at a specific point in time. The sum-of-accumulate circuit calculates the sum of the values ​​obtained by subtracting the calibration value (which is the result of analog-to-digital conversion with the input signal as ground) from the difference value and multiplying it by the polarity value. Waveform sensor.

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