Electronic circuits and their testing methods

Abstract

Provided is an electronic circuit which has a functional circuit and is capable of preventing a mistaken test mode operation from occurring when used in a shopping market, etc. An electronic circuit according to the present invention is equipped with a functional circuit which has a prescribed function, and a test circuit for testing in order to debug the functional circuit. The electronic circuit is equipped with: an input circuit for decoding an enable signal for switching the electronic circuit to an operational state, and outputting the decoded enable signal to the functional circuit; a test signal generator for producing a trigger signal for a test signal on the basis of a signal change included in the enable signal; and a computing element for computing a NOR operation of the decoded enable signal and the trigger signal, and outputting the signal from the computing results to the test circuit as a test signal for instructing so as to execute said test.

Description

Technical Field

[0001] The present invention relates to an electronic circuit including a functional circuit having a predetermined function and a method for inspecting the same.

Background Art

[0002] It has already been known that a test mode operation is mounted for use in a shipping test or debugging that is not used by users in the market.

[0003] For example, Patent Document 1 provides an integrated circuit, an electronic circuit board, a DC-DC converter, and a method for inspecting these circuits that can achieve miniaturization. In the integrated circuit according to this conventional example, when a specific test signal is input to the functional circuit FC, a monitor signal corresponding to the test signal is output from its output terminals SW,E(V OUT ). If the functional circuit is normal, the value of the monitor signal input to the discriminator becomes the signal expected when the functional circuit is normal, and if it is abnormal, it becomes different from the signal in the normal state. Therefore, by inputting a test signal from the test circuit to the functional circuit, the functional circuit can be inspected. Since the test signal is input to the test circuit via the power supply terminal Vcc of the functional circuit, no additional terminal for inspection is required, and the device can be miniaturized.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, in the conventional test signal entry circuit, there has been a problem that it cannot be invalidated after inspection and retested, or if it is not invalidated, it may accidentally enter the test mode operation in the market and cause unexpected operations.

[0006] The object of the present invention is to solve the above problems and to provide an electronic circuit having a functional circuit that can prevent it from mistakenly entering test mode when used in the market, and a method for testing the same. [Means for solving the problem]

[0007] An electronic circuit according to a first aspect of the present invention is: An electronic circuit comprising a functional circuit having a predetermined function and a test circuit for performing tests for debugging the functional circuit, An input circuit that decodes the enable signal that puts the aforementioned electronic circuit into an operating state and outputs the decoded enable signal to the aforementioned functional circuit, A test signal generator that generates a trigger signal for a test signal based on the signal change included in the enable signal, A calculation element that performs a negative OR operation between the decoding enable signal and the trigger signal, and outputs the resulting signal to the test circuit as a test signal instructing the test to be performed, It is equipped with.

[0008] An electronic circuit according to a second aspect of the present invention is: An electronic circuit comprising a functional circuit having a predetermined function and a test circuit for performing tests for debugging the functional circuit, A first input circuit that decodes the enable signal that puts the aforementioned electronic circuit into an operating state and outputs the decoded enable signal to the functional circuit, A second input circuit that decodes a predetermined command signal and outputs a decoded command signal to the functional circuit, A test signal generator that generates a trigger signal for a test signal based on the signal change contained in the command signal, A calculation element that performs a negative OR operation between the decoding enable signal and the trigger signal, and outputs the resulting signal to the test circuit as a test signal instructing the test to be performed, It is equipped with.

[0009] An electronic circuit according to a third aspect of the present invention is: An electronic circuit comprising a functional circuit having a predetermined function and a test circuit for performing tests for debugging the functional circuit, A first input circuit that decodes the enable signal that puts the aforementioned electronic circuit into an operating state and outputs the decoded enable signal to the functional circuit, A second input circuit that decodes a predetermined first command signal and outputs a first decoded command signal to the functional circuit, A first test signal generator that generates a first trigger signal for a test signal based on a signal change included in the first command signal, A third input circuit that decodes a predetermined second command signal and outputs a second decoded command signal to the functional circuit, A second test signal generator that generates a second trigger signal for a test signal based on the signal changes contained in the second command signal, A calculation element that performs a negative OR operation between the decoding enable signal, the first trigger signal, and the second trigger signal, and outputs the resulting signal to the test circuit as a test signal instructing the test to be performed, It is equipped with. [Effects of the Invention]

[0010] Therefore, the electronic circuit, etc. according to the present invention includes a calculation element that performs a negative OR operation between the decoding enable signal or the coding command signal and the trigger signal, and outputs the result of the calculation as a test signal to the test circuit to instruct the test to perform the test. Thus, in an electronic circuit having the function circuit, it is possible to prevent it from accidentally entering test mode when used in the market. [Brief explanation of the drawing]

[0011] [Figure 1] This is a block diagram showing an example configuration of the electronic circuit 1 according to Embodiment 1. [Figure 2] This is a timing chart of each voltage showing the operation of electronic circuit 1 in Figure 1. [Figure 3]It is a circuit diagram showing a configuration example of the test signal generator 13A according to Modification 1. [Figure 4] It is a timing chart of each voltage showing the operation of the test signal generator 13A in FIG. 3. [Figure 5] It is a circuit diagram showing a configuration example of the test signal generator 13B according to Modification 2. [Figure 6] It is a timing chart of each voltage showing the operation of the test signal generator 13B in FIG. 5. [Figure 7] It is a circuit diagram showing a configuration example of the test signal generator 13C according to Modification 3. [Figure 8] It is a circuit diagram showing a configuration example of the test signal generator 13D according to Modification 4. [Figure 9] It is a block diagram showing a configuration example of the electronic circuit 1A according to Embodiment 2. [Figure 10] It is a timing chart of each voltage showing the operation of the electronic circuit 1A in FIG. 9. [Figure 11] It is a block diagram showing a configuration example of the electronic circuit 1B according to Embodiment 3. [Figure 12] It is a block diagram showing a configuration example of the electronic circuit 1C according to Embodiment 4. [Figure 13] It is a block diagram showing the configuration of the electronic circuit 101 according to the comparative example. [Figure 14] It is a circuit diagram showing the configuration of the test signal generator 13 in FIG. 13. [Figure 15] It is a timing chart of each voltage showing the operation of the test signal generator 13 in FIG. 14. [Figure 16] It is a timing chart of each voltage when noise is superimposed on the ground wire in the test signal generator 13 in FIG. 14. [Figure 17] It is a timing chart of each voltage when noise is superimposed on the connection wire of terminal T2 in the test signal generator 13 in FIG. 14.

Embodiments of the Invention

[0012] Embodiments and modified examples of the present invention will be described below with reference to the drawings. The same or similar components are denoted by the same reference numerals.

[0013] (Inventor's insights) Patent Document 1 discloses a configuration that allows testing without adding a dedicated test terminal for testing purposes, but it does not resolve the problem that retesting is not possible because the test function is disabled after testing. In other words, when the functional circuit is operating and the "chip enable signal EN=H level", the state does not transition even if the entry conditions for the test mode are met, so malfunctions in actual use can be avoided without disabling the test function after testing.

[0014] Figure 13 is a block diagram showing the configuration of the electronic circuit 101 in a comparative example.

[0015] In Figure 13, the electronic circuit 101 comprises terminals T1 and T2, input interfaces 11 and 12, a test signal generator 13, and a functional circuit 10 that performs a predetermined function and incorporates a test circuit 20. Input interface 11 decodes the chip enable signal EN input to terminal T1 into a chip enable signal ENa, which is a predetermined rising edge signal, and then outputs it to the functional circuit 10. Input interface 12 decodes the command signal XXX input to terminal T2 into a command signal XXXa, which is a predetermined rising edge signal, and then outputs it to the functional circuit 10. Furthermore, the test signal generator 13 outputs an H-level test signal TEST to the functional circuit 10 when the command signal XXX input to terminal T2 meets the signal conditions for a predetermined test mode. In response to the H-level test signal TEST, the test circuit 20 built into the functional circuit 10 performs a predetermined test for debugging purposes on the functional circuit 10.

[0016] Figure 14 is a circuit diagram showing the configuration of the test signal generator 13 in Figure 13. Figure 15 is a timing chart of each voltage showing the operation of the test signal generator 13 in Figure 14. In Figure 15 and the other diagrams, Vxxx represents the voltage of the command signal XXX.

[0017] In Figure 14, the test signal generator 13 comprises an N-channel MOS transistor Mtest, a resistor R11, and an inverter INV1. Here, the power supply voltage Vdd is connected to terminal T2 via resistor R11 and the drain and source of the MOS transistor Mtest. The gate of the MOS transistor Mtest is grounded, and the MOS transistor Mtest is in the off state. The signal from the drain of the MOS transistor Mtest is inverted by the inverter INV1 and then output as the test signal TEST.

[0018] In the test signal generator 13 configured as described above, as shown in Figure 15, the test signal TEST becomes high when the voltage at terminal T2 falls below the threshold voltage Vgstest of the MOS transistor Mtest.

[0019] In other words, in the circuits of Figures 13 and 14, in order to enter the functional circuit 10 into test mode without adding a dedicated terminal, the entry condition is set to be outside the recommended operating conditions for the terminals used to control the integrated circuit.

[0020] However, when electronic circuit 101 is used in a switching regulator, not only the output voltage but also the power supply voltage and ground voltage may change due to switching noise, thus satisfying the entry conditions. In addition, noise may be introduced into the voltage of the command signal XXX at the external input terminal T2.

[0021] Figure 16 is a timing chart of each voltage when noise is superimposed on the ground wire in the test signal generator 13 of Figure 14. In Figure 16 and the other diagrams, Vgnd represents the ground voltage. As is clear from Figure 16, the ground voltage may change, causing the test signal TEST to incorrectly become high level.

[0022] Figure 17 is a timing chart of each voltage when noise is superimposed on the connection line of terminal T2 in the test signal generator 13 of Figure 14. As is clear from Figure 17, the voltage of the command signal XXX may change, causing the test signal TEST to reach a high level.

[0023] Normally, the entry state of the test mode is latched, so if the test signal TEST goes to a high level even once, as shown in Figure 16 or Figure 17, there was a problem that it could not be restored without restarting the functional circuit 10 of the electronic circuit 101.

[0024] The inventors have devised the following embodiments and modifications to solve the above problems. The embodiments of the present invention have the following features when a test mode is implemented for the purpose of shipment testing or debugging: "When the functional circuit 10 is operating in the state of "chip enable signal EN = H level", the test signal TEST does not transition from L level to H level even if the entry conditions for the test mode are met."

[0025] (Embodiment 1) Figure 1 is a block diagram showing an example configuration of the electronic circuit 1 according to Embodiment 1. Figure 2 is a timing chart of each voltage showing the operation of the electronic circuit 1. Here, the test signal generator 13 in Figure 1 has, for example, the circuit configuration shown in Figure 14. The electronic circuit 1 in Figure 1 differs from the electronic circuit 101 in Figure 13 in the following respects. (1) The test signal from the test signal generator 13 is used as the trigger signal TRG. (2) The system further includes a Norgate 14, which is an arithmetic element that performs a negative OR operation between the enable signal ENa and the trigger signal TRG and outputs the result of the operation as a test signal TEST to the functional circuit 10.

[0026] The rest of the configuration is the same as that of the electronic circuit 101 in Figure 13. As shown in Figures 14 and 15, the test signal generator 13 raises the test signal TEST to a high level when the voltage at terminal T2 falls below the threshold voltage Vgstest of the MOS transistor Mtest. In response to the high-level test signal TEST, the inspection circuit 20 built into the functional circuit 10 performs predetermined tests for debugging purposes on the functional circuit 10.

[0027] Furthermore, the test mode is not disabled even after the shipping inspection. Also, input interfaces 11 and 12 are examples of input circuits that decode input signals and output encoded signals.

[0028] In the electronic circuit 1 configured as described above, when the enable signal ENa is at a high level, the Noah gate 14 prevents the test signal generator 13 from outputting a high-level test signal TEST, even if it outputs a high-level trigger signal TRG. In other words, as shown in Figure 2, even if noise is superimposed on the ground voltage, and even if a high-level trigger signal TRG is output, the circuit is configured not to output a high-level test signal TEST if the enable signal ENa is at a high level.

[0029] As described above, according to Embodiment 1, in the state where the functional circuit 10 is operating and the "chip enable signal EN = H level", even if the entry conditions for test mode are met, the test signal TEST does not transition from L level to H level, that is, it is possible to prevent the generation of an H level test signal TEST. Therefore, in the electronic circuit 1 having a functional circuit, it is possible to prevent it from accidentally entering test mode when used in the market.

[0030] The functional circuits 10 in Figure 1 and subsequent figures include, for example, linear regulators, switching regulators, reference voltage generation circuits, protection circuits for electronic circuits, memory circuits, digital processing circuits, and so on.

[0031] (Variation 1) Figure 3 is a circuit diagram showing an example configuration of the test signal generator 13A according to Modification 1. Figure 4 is a timing chart of each voltage showing the operation of the test signal generator 13A in Figure 3.

[0032] In Figure 3, the test signal generator 13A is configured with an offset DC voltage source 15 that applies a predetermined offset voltage to the command signal, and a comparator 16. The command signal XXX input to terminal T2 is DC-offset in the positive voltage direction by the DC voltage source 15, and then input to the inverting input terminal of the comparator 16. The non-inverting input terminal of the comparator 16 is grounded. The comparator 16 outputs a high-level test signal TEST when the voltage at the inverting input terminal becomes less than or equal to the voltage at the non-inverting input terminal (signal change included in the command signal XXX). That is, as shown in Figure 4, the high-level test signal TEST is output when the voltage Vxxx of the command signal XXX becomes less than or equal to -Voffset.

[0033] According to the modified example 1 configured as described above, similar to embodiment 1, in the "chip enable signal EN = H level" state when the functional circuit 10 is operating, even if the entry conditions for test mode are met, the test signal TEST does not transition from L level to H level, that is, it is possible to prevent the generation of an H level test signal TEST. Therefore, in the electronic circuit 1 having a functional circuit, it is possible to prevent it from accidentally entering test mode when used in the market.

[0034] (Modification 2) Figure 5 is a circuit diagram showing an example configuration of the test signal generator 13B according to Modification 2. Figure 6 is a timing chart of each voltage showing the operation of the test signal generator 13B in Figure 5.

[0035] In Figure 5, the test signal generator 13BThe system comprises an offset DC voltage source 15 that applies a predetermined offset voltage to the command signal, and a comparator 16. The command signal XXX input to terminal T2 is DC-offset in the direction of a negative voltage by the DC voltage source 15, and then input to the non-inverting input terminal of the comparator 16. The inverting input terminal of the comparator 16 is connected to the power supply voltage Vdd. The comparator 16 outputs a high-level test signal TEST when the voltage at the non-inverting input terminal becomes equal to or greater than the voltage at the inverting input terminal. That is, as shown in Figure 6, the high-level test signal TEST is output when the voltage Vxxx of the command signal XXX becomes (Vdd + Voffset) or greater.

[0036] According to the modified example 2 configured as described above, similar to Embodiment 1 and Modified Example 1, in the "chip enable signal EN = H level" state when the functional circuit 10 is operating, even if the entry conditions for test mode are met, the test signal TEST does not transition from L level to H level, that is, it is possible to prevent the generation of an H level test signal TEST. Therefore, in the electronic circuit 1 having a functional circuit, it is possible to prevent it from accidentally entering test mode when used in the market.

[0037] (Variation 3) Figure 7 is a circuit diagram showing an example configuration of the test signal generator 13C according to Modification 3. In Figure 7, the test signal generator 13C differs from the test signal generator 13B in Figure 5 in the following respects. (1) Instead of the offset DC voltage source 15, voltage divider resistors R1 and R2 are provided, connected in series with each other and inserted between terminal T2 and ground.

[0038] In Figure 7, the voltage of the command signal XXX input to terminal T2 is divided by voltage divider resistors R1 and R2, and the divided voltages are input to the non-inverting input terminal of comparator 16. The test signal generator 13C configured as described above operates in the same manner as the modified example 2 in Figure 5 and has the same effects.

[0039] (Modification 4) Figure 8 is a circuit diagram showing an example configuration of the test signal generator 13D according to Modification 4. In Figure 8, the test signal generator 13D differs from the test signal generator 13C in Figure 7 in the following respects. (1) The power supply voltage Vdd is divided by voltage divider resistors R3 and R4, which are connected in series, and the divided voltages are input to the inverting input terminal of comparator 16.

[0040] In Figure 8, the test signal generator 13D configured as described above operates in the same manner as in Modification 3 of Figure 7, and has the same effects, except that the comparison reference voltage of the comparator 16 becomes a predetermined voltage lower than the power supply voltage Vdd.

[0041] (Embodiment 2) Figure 9 is a block diagram showing an example configuration of electronic circuit 1A according to Embodiment 2. Electronic circuit 1A in Figure 9 differs from electronic circuit 1 in Figure 1 in the following ways. (1) A delay circuit 17 is inserted between the output terminal of the test signal generator 13 and the input terminal of the Noah gate 14 to delay the input signal by a predetermined delay time Td. Here, the delay time Td corresponds to the signal processing time of the input interface 11. The differences are explained below.

[0042] In Figure 9, the delay circuit 17 delays the trigger signal TRG from the test signal generator 13 by a predetermined delay time Td, and then outputs the delayed signal TDLY to the Noah gate 14.

[0043] Figure 10 is a timing chart of each voltage showing the operation of the electronic circuit 1A in Figure 9. As is clear from Figure 10, the circuit that fixes the test signal TEST to a low level when the enable signal ENa is at a high level has the unique effect of being able to adjust the timing of the delay signal TDLY, taking into account the signal processing time of the input interface 11, etc. Other effects are the same as in Embodiment 1.

[0044] Note that if the signal processing time of the input interface 11 is not considered, the delay circuit 17 may be omitted.

[0045] (Embodiment 3) Figure 11 is a block diagram showing an example configuration of electronic circuit 1B according to Embodiment 3. Electronic circuit 1B in Figure 11 differs from electronic circuit 1A in Figure 9 in the following ways. (1) It further includes a terminal T3 that receives another command signal YYY. (2) Further comprising an input interface 22 connected to terminal T3 and a test signal generator 23. (3) Instead of the Noahgate 14, a Noahgate 14A having three input terminals is provided. (4) A delay circuit 17A having the same configuration as the delay circuit 17 was inserted between the test signal generator 23 and the Noah gate 14A. The differences are explained below.

[0046] In Figure 11, the input interface 22 decodes the command signal YYY input to terminal T3 into a command signal YYYa, which is a predetermined rising edge signal, and then outputs it to the function circuit 10. The test signal generator 23 outputs a high-level trigger signal TRGA to the function circuit 10 as a delayed signal TDLYA via the delay circuit 17A when the command signal YYY input to terminal T3 meets the signal conditions for a predetermined test mode.

[0047] According to Embodiment 3 configured as described above, a test signal TEST can be generated in response to two command signals XXX,YYY, taking into account the signal processing time of the input interface 11. Other effects are the same as in Embodiment 2.

[0048] Furthermore, if the signal processing time of the input interface 11 is not considered, the delay circuits 17 and 17A may be omitted. Also, in Embodiment 4, the test signal TEST is generated using two trigger signals TRG and TRGA, but the present invention is not limited to this, and for example, the test signal TEST may be generated using three or more trigger signals.

[0049] (Embodiment 4) Figure 12 is a block diagram showing an example configuration of electronic circuit 1C according to Embodiment 4. Electronic circuit 1C in Figure 12 differs from electronic circuit 1 in Figure 1 in the following ways. (1) Terminal T2 and input interface 12 were removed. (2) Based on the enable signal EN input to terminal T1, the test signal generator 13 generates a trigger signal TRG under predetermined signal conditions (Embodiment 1, Modification 1, Modification 2, etc.) similar to the command signal XXX, and outputs it to the Noah gate 14 as a delayed signal TDLY via the delay circuit 17.

[0050] According to Embodiment 4 configured as described above, based on the enable signal EN, a trigger signal TRG is generated under predetermined signal conditions, similar to the command signal XXX. This eliminates the need for a command signal XXX and terminal T2, and allows the enable signal EN to also serve as the entry condition for the command signal XXX, thereby generating the trigger signal TRG and the test signal TEST. Embodiment 4 has the same effects and advantages as Embodiment 1, except for this limitation.

[0051] Note that in Figure 12, if the signal processing time of the input interface 11 is not considered, the delay circuit 17 may not be provided. Also, the test signal generators 13 and 23 may be composed of the test signal generators 13A to 13D described above. [Industrial applicability]

[0052] As detailed above, the electronic circuit, etc., according to the present invention makes it possible to prevent an electronic circuit having a functional circuit from accidentally entering test mode when used by a user in the market. [Explanation of symbols]

[0053] 1,1A~1C,101 Electronic circuit 10 Functional Circuits 11,12,22 Input Interfaces 13, 13A~13D, 23 Test signal generator 14,14A Noahgate 15 DC voltage source 16 Comparators 17,17A Delay Circuit 20 Test Circuits INV1 Inverter Mtest MOS transistor R1~R11 Resistors T1~T3 terminals

Claims

1. An electronic circuit comprising a functional circuit having a predetermined function and a test circuit for performing tests for debugging the functional circuit, An input circuit that decodes the enable signal that puts the aforementioned electronic circuit into an operating state and outputs the decoded enable signal to the aforementioned functional circuit, A test signal generator that generates a trigger signal for a test signal based on the signal change included in the enable signal, A calculation element that performs a negative OR operation between the decoding enable signal and the trigger signal, and outputs the resulting signal to the test circuit as a test signal instructing the test to be performed, An electronic circuit equipped with the following features.

2. The aforementioned electronic circuit further, A delay circuit is inserted between the test signal generator and the computing element, delaying the trigger signal by the processing time of the input circuit, and outputting the delayed trigger signal to the computing element. The electronic circuit according to claim 1, comprising:

3. A method for testing an electronic circuit comprising a functional circuit having a predetermined function and a test circuit for performing tests for debugging the functional circuit, The input circuit decodes the enable signal that puts the electronic circuit into an operating state and outputs the decoded enable signal to the functional circuit. The test signal generator generates a trigger signal for the test signal based on the signal change included in the enable signal, The arithmetic element performs a negative OR operation between the decoding enable signal and the trigger signal, and outputs the resulting signal to the test circuit as a test signal instructing the test to be performed. A method for testing electronic circuits, including [specific components / features].

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