Memory system

Abstract

To provide a memory system capable of suppressing, by simple management, the number of error bits occurring on read data.SOLUTION: A controller acquires a first temperature detection value from a temperature sensor at a first timing, and performs an acquisition operation for a first storage area, and converts, on the basis of the first temperature detection value, a first voltage value into a second voltage value, which is a determination voltage at a temperature set value. The acquisition operation is an operation of determining whether a plurality of memory cells is in an ON state or an OFF state using the determination voltage and acquiring the first voltage value, which is the determination voltage that suppresses the number of occurrences of error bits, on the basis of a determination result. The controller acquires a second temperature detection value from the temperature sensor after the first timing and converts the second voltage value into a third voltage value, which is the determination voltage at the second temperature detection value, and reads data from the plurality of memory cells using a voltage of the third voltage value as the determination voltage.SELECTED DRAWING: Figure 19

Description

Technical Field

[0001] This embodiment relates to a memory system.

Background Art

[0002] Conventionally, a memory system having memory cell transistors is widely known. In such a memory system, in a read operation, data held in the memory cell transistor is determined based on a comparison between the threshold voltage of the memory cell transistor and a determination voltage.

[0003] The threshold voltage of a memory cell transistor can vary due to various factors. Therefore, the memory system is configured to be able to change the value of the determination voltage, and when an error determination of data occurs in a read operation, it can execute a shift read by changing the value of the determination voltage and performing the read operation.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] One embodiment aims to provide a memory system capable of suppressing the number of error bits occurring in read data with simple management.

Means for Solving the Problems

[0006] According to one embodiment, the memory system comprises a non-volatile first memory, a second memory, a third memory, a temperature sensor, and a controller. The first memory includes a first storage area comprising a word line and a plurality of memory cells connected to the word line. The second memory is configured to store first information corresponding to the temperature dependence of the threshold voltages of the plurality of memory cells. The third memory is configured to store second information in which the value of a determination voltage corresponding to the threshold voltages of the plurality of memory cells is recorded. At a first timing, the controller acquires a first temperature detection value from the temperature sensor, performs an acquisition operation on the first storage area, converts the first voltage value into a second voltage value which is the value of the determination voltage at a temperature setpoint based on the first temperature detection value and the first information, and records the second voltage value in the second information. The acquisition operation is an operation to determine whether the plurality of memory cells are on or off using the determination voltage, and acquire a first voltage value which is the value of the determination voltage that suppresses the number of error bits based on the determination result. At a second timing after the first timing, the controller acquires a second temperature detection value from the temperature sensor, converts the second voltage value recorded in the second information into a third voltage value which is the value of the determination voltage at the second temperature detection value based on the second temperature detection value and the first information, and performs a first read operation to acquire data from multiple memory cells using the voltage of the third voltage value as the determination voltage. [Brief explanation of the drawing]

[0007] [Figure 1] A diagram showing an example configuration of the memory system of the embodiment. [Figure 2] A diagram showing an example configuration of a memory chip in an embodiment. [Figure 3] A diagram showing the circuit configuration of the block in the embodiment. [Figure 4] A diagram illustrating an example of data coding in an embodiment. [Figure 5] A figure showing another example of the threshold voltage that the memory cell of the embodiment may take. [Figure 6] A diagram illustrating the shift read operation performed in the first optimal value acquisition operation of the embodiment. [Figure 7] A diagram showing the data of the determination result obtained by each shift read performed in the first optimal value acquisition operation of the embodiment, the data of the determination result obtained by the mask data read, and each section. [Figure 8] A diagram illustrating the process of acquiring the optimal determination voltage in the first optimal value acquisition operation of the embodiment. [Figure 9] A diagram illustrating the second optimal value acquisition operation of the embodiment. [Figure 10] A diagram illustrating the second optimal value acquisition operation of the embodiment. [Figure 11] A figure showing an example of the temperature dependence of the determination voltage in a memory chip of an embodiment. [Figure 12] A diagram showing an example of temperature compensation information in an embodiment. [Figure 13] A diagram showing an example of the configuration of a memory cell array in an embodiment. [Figure 14] This figure shows an example of a command sequence for acquiring temperature detection values ​​from the memory chip CP of the embodiment. [Figure 15] A diagram showing an example of a method for managing the reference determination voltage in the embodiment. [Figure 16] A diagram showing an example of the information that the memory system of the embodiment holds in RAM while it is in operation. [Figure 17] A diagram showing an example of the startup operation of the memory system of the embodiment. [Figure 18] A flowchart illustrating an example of the operation of the memory system in an embodiment during program execution. [Figure 19] A flowchart illustrating an example of the operation of a memory system in an embodiment in response to a read command from a host device. [Figure 20] A flowchart illustrating an example of the operation of the patrol read of the memory system in the embodiment. [Figure 21] A diagram showing an example of how the contents of the reference determination voltage table change in the embodiment. [Figure 22] A flowchart showing an example of the operation of the memory system in Modification 1 during program execution. [Figure 23] A diagram showing an example of changes in the content of the reference determination voltage table of Modification 1. [Figure 24] A diagram showing an example of information held in the RAM during operation of the memory system of Modification 2. [Figure 25] A diagram showing an example of the data structure of the shift index table of Modification 2. [Figure 26] A flowchart showing an example of a method for obtaining a set of reference determination voltages using the reference determination voltage table and the shift index table in Modification 2. [Figure 27] A flowchart showing an example of a method for recording a set of reference determination voltages in Modification 2. [Figure 28] A diagram showing an example of a management method for a set of initial setting values in Modification 3. [Figure 29] A flowchart showing an example of an update method for a set of initial setting values in Modification 3. <000009(此处原文可能有误,推测应为 )

Best Mode for Carrying Out the Invention

[0008] Hereinafter, a memory system according to an embodiment will be described in detail with reference to the accompanying drawings. It should be noted that the present invention is not limited by these embodiments.

[0009] (Embodiment) FIG. 1 is a diagram showing a configuration example of the memory system of the embodiment. As shown in FIG. 1, the memory system 1 can be connected to a host device 300. The host device 300 corresponds to, for example, a server, a personal computer, or a mobile information processing device. The memory system 1 functions as an external storage device of the host device 300. The host device 300 can issue commands to the memory system 1. Commands to the memory system 1 include read commands and write commands.

[0010] The memory system 1 comprises one or more memory chips CP and one controller 200 as NAND flash memory 100. Here, the memory system 1 comprises memory chips CP0, CP1, CP2, and CP3 as one or more memory chips CP. The number of memory chips CP provided in the memory system 1 is not limited to four.

[0011] Note that the NAND flash memory 100 is an example of a non-volatile first memory.

[0012] Each memory chip CP is equipped with multiple memory cell transistors and can store data nonvolatilically. The memory chip CP is connected to the controller 200 by a NAND bus 400.

[0013] The controller 200 includes a host interface circuit (HOST I / F) 201, RAM (Random Access Memory) 202, a CPU (Central Processing Unit) 203, a buffer memory (Buffer Memory) 204, a NAND interface circuit (NAND I / F) 205, an ECC circuit (Error Correction Code circuit: ECC) 206, and a temperature sensor 207.

[0014] The controller 200 may be configured, for example, as a System-On-a-Chip (SoC). The controller 200 may be composed of multiple chips. The controller 200 may have an FPGA (field-programmable gate array) or an ASIC (application-specific integrated circuit) instead of a CPU 203. In other words, the controller 200 may be composed of software, hardware, or a combination thereof. The RAM 202 may be located outside the controller 200. The temperature sensor 207 may also be located outside the controller 200.

[0015] The host interface circuit 201 is connected to the host device 300 via a bus compliant with standards such as SATA (Serial Advanced Technology Attachment), SAS (Serial Attached SCSI), or PCI (Peripheral Components Interconnect) Express™, and is responsible for communication between the controller 200 and the host device 300.

[0016] The NAND interface circuit 205 is connected to each memory chip CP via the NAND bus 400 and is responsible for communication between the controller 200 and the memory chip CP.

[0017] The CPU 203 controls the operation of the controller 200.

[0018] RAM 202 is used as a workspace for the CPU 203. Buffer memory 204 temporarily holds data sent to and received from the memory chip CP. RAM 202 and buffer memory 204 may be composed of, for example, DRAM (dynamic random access memory), SRAM (static random access memory), or a combination thereof. However, the types of memory constituting RAM 202 and buffer memory 204 are not limited to these.

[0019] The ECC circuit 206 uses error correction codes to detect and correct errors. The process of detecting and correcting errors is simply referred to as error correction.

[0020] The temperature sensor 207 detects the temperature of the memory system 1. The CPU 203 uses the temperature detected by the temperature sensor 207 for various controls of the memory system 1.

[0021] Figure 2 shows an example configuration of a memory chip CP according to an embodiment. As shown in the figure, the memory chip CP comprises a processing circuit 110, a memory cell array 111, and a temperature sensor 112.

[0022] The memory cell array 111 is divided into multiple planes (plane 0, plane 1). Each plane is a sub-array that can be accessed in parallel. Each plane comprises multiple blocks BLK (BLK0, BLK1, ...), each of which is a set of multiple non-volatile memory cell transistors. Each block BLK comprises multiple string units SU (SU0, SU1, ...), each of which is a set of memory cell transistors associated with word lines and bit lines. Each string unit SU comprises multiple NAND strings 114, in which memory cell transistors are connected in series. The number of NAND strings 114 in a string unit SU is arbitrary. The number of planes in the memory cell array 111 is not limited to 2. Also, the memory cell array 111 does not necessarily have to be divided.

[0023] The processing circuit 110 includes, for example, a row decoder, a column decoder, a sense amplifier, a latch circuit, and a voltage generation circuit. The processing circuit 110 performs program operations, sense operations, and erase operations on the memory cell array 111 of each plane in response to instructions from the controller 200.

[0024] The program operation is the operation of writing data to the memory cell array 111. The sense operation is the operation of reading data from the memory cell array 111.

[0025] The series of operations by which the controller 200 writes data to the memory chip CP will be referred to as a write operation. The write operation consists of a data-in operation in which the controller 200 transfers data to the memory chip CP, and a program operation in which the processing circuit 110 writes the data received by the data-in operation to the memory cell array 111.

[0026] The series of operations by which the controller 200 reads data from the memory chip CP is referred to as a read operation. The read operation consists of a sense operation in which the processing circuit 110 reads data from the memory cell array 111, and a data out operation in which the controller 200 retrieves the data read by the sense operation from the memory chip CP.

[0027] The temperature sensor 112 detects the temperature of the memory chip CP. When the controller 200 performs a read operation, it obtains the temperature detected by the temperature sensor 112 from the memory chip CP and uses the obtained temperature detected value to control the memory chip CP.

[0028] Figure 3 shows the circuit configuration of a block BLK in an embodiment. Each block BLK has the same configuration. A block BLK has, for example, four string units SU0 to SU3. Each string unit SU contains multiple NAND strings 114.

[0029] Each NAND string 114 contains, for example, 64 memory cell transistors MT (MT0 to MT63) and selection transistors ST1 and ST2. Each memory cell transistor MT comprises a control gate and a charge storage layer to non-volatilely retain data. The 64 memory cell transistors MT (MT0 to MT63) are connected in series between the source of selection transistor ST1 and the drain of selection transistor ST2. The memory cell transistors MT may be of the MONOS type with an insulating film in the charge storage layer, or of the FG type with a conductive film in the charge storage layer. Furthermore, the number of memory cell transistors MT in the NAND string 114 is not limited to 64.

[0030] The gates of the selection transistor ST1 in each of the string units SU0 to SU3 are connected to the selection gate lines SGD0 to SGD3, respectively. In contrast, the gates of the selection transistor ST2 in each of the string units SU0 to SU3 are connected in common to, for example, the selection gate line SGS. The gates of the selection transistor ST2 in each of the string units SU0 to SU3 may be connected to different selection gate lines SGS0 to SGS4 for each string unit SU. The control gates of the memory cell transistors MT0 to MT63 within the same block BLK are connected in common to the word lines WL0 to WL63, respectively.

[0031] The drain of the selection transistor ST1 of each NAND string 114 within the string unit SU is connected to a different bit line BL (BL0 to BL(L-1), where L is a natural number greater than or equal to 2). Furthermore, the bit line BL connects one NAND string 114 within each string unit SU to multiple blocks BLK. Additionally, the source of each selection transistor ST2 is connected to the source line SL.

[0032] In other words, a string unit SU is a collection of NAND strings 114 connected to different bit lines BL and the same selected gate line SGD. A block BLK is a collection of multiple string units SU that share a common word line WL. The memory cell array 111 is a collection of multiple block BLK that share a common bit line BL.

[0033] The program and sense operations performed by the processing circuit 110 on a single plane are carried out collectively on the memory cell transistor MT connected to a single word line WL in a single string unit SU. Hereafter, the group of memory cell transistors MT selected collectively during the program and sense operations on a single plane will be referred to as the "memory cell group MCG". The storage area of ​​a collection of 1-bit data written to or read from a single memory cell group MCG will be referred to as a "page".

[0034] The erase operation on a single plane by the processing circuit 110 can be performed in units of block BLK or smaller units than block BLK.

[0035] Furthermore, a single logical page may be composed of multiple pages stored in different planes or different memory chips CP, and the controller 200 may instruct program operations or sense operations in parallel for the multiple pages constituting a single logical page. Also, a single logical block may be composed of multiple block BLKs provided in different planes or different memory chips CP, and the controller 200 may instruct erase operations in parallel for the multiple block BLKs constituting a single logical block.

[0036] Hereafter, the memory cell transistor MT will be simply referred to as the memory cell.

[0037] Each memory cell can be written to n (n≧1) bits of data. When n bits of data are written to each memory cell, the storage capacity per memory cell group (MCG) is equal to the size of n pages. The mode where n is 1 is called SLC (Single Level Cell) mode. The mode where n is 2 is called MLC (Multi Level Cell) mode. The mode where n is 3 is called TLC (Triple Level Cell) mode. The mode where n is 4 is called QLC (Quad Level Cell) mode.

[0038] The threshold voltage of each memory cell is controlled within a certain range by the processing circuit 110. The controllable range of the threshold voltage is divided into 2 to the power of n divisions, and a different n-bit value is assigned to each division.

[0039] The embodiments and subsequent embodiments describe examples in which memory cells are used in TLC mode. Note that the embodiments and subsequent embodiments are applicable not only to systems in which memory cells are used in TLC mode, but also to systems in which memory cells are used in any mode.

[0040] Figure 4 is a diagram illustrating an example of data coding in an embodiment.

[0041] As mentioned above, in TLC mode, 3 bits of data are stored per memory cell. The bits that make up the 3 bits of data stored in the memory cell are referred to as the upper bit, middle bit, and lower bit, according to their order. Of the three pages that a memory cell group MSG has, the page where the upper bits are stored is referred to as the upper page, the page where the middle bits are stored is referred to as the middle page, and the page where the lower bits are stored is referred to as the lower page.

[0042] According to the TLC mode, the range of possible threshold voltages is divided into eight ranges. These eight ranges, in order from lowest to highest threshold voltage, will be called the “Er” state, “A” state, “B” state, “C” state, “D” state, “E” state, “F” state, and “G” state. The threshold voltage of each memory cell is controlled by the processing circuit 110 so that it belongs to one of the “Er” state, “A” state, “B” state, “C” state, “D” state, “E” state, “F” state, and “G state.” As a result, when the number of memory cells is plotted against the threshold voltage, the memory cells ideally form a distribution of eight non-overlapping lobes, each belonging to a different state, as shown in the middle of Figure 4. Hereafter, the distribution for each state may simply be referred to as a lobe.

[0043] The eight states correspond to 3 bits of data. The upper table in Figure 4 shows an example of the correspondence between states and 3 bits of data, i.e., data coding. In this example, the “Er” state corresponds to “111”, the “A” state corresponds to “110”, the “B” state corresponds to “100”, the “C” state corresponds to “000”, the “D” state corresponds to “010”, the “E” state corresponds to “011”, the “F” state corresponds to “001”, and the “G” state corresponds to “101”. When the 3 bits of data are written as “abc”, “a” is the upper bit, “b” is the middle bit, and “c” is the lower bit. In this way, each memory cell can hold data corresponding to the state to which its threshold voltage belongs. Note that the correspondence between states and data shown in Figure 4 is just one example of data coding. Data coding is not limited to the example in this figure.

[0044] The threshold voltage is reduced to the "Er" state by the erase operation. Alternatively, the threshold voltage can be maintained in the "Er" state or increased to one of the following states by the program operation: "A", "B", "C", "D", "E", "F", or "G".

[0045] Specifically, during program operation, the processing circuit 110 selects a bit line BL corresponding to the column address. The processing circuit 110 sets the potential of the selected bit line BL to zero. The processing circuit 110 selects a word line WL corresponding to the row address and applies a programming pulse to the selected word line WL. As a result, electrons are injected into the charge storage layer of the memory cell located at the intersection of the selected bit line BL and the selected word line WL, and the threshold voltage of the memory cell rises. The processing circuit 110 performs a data read at a predetermined timing to check whether the threshold voltage of the memory cell has reached the target state corresponding to the data of the written data (verify read). The processing circuit 110 continues to apply the program pulse until the threshold voltage of the memory cell reaches the target state.

[0046] From now on, a memory cell whose threshold voltage has been set to a certain state by program operation may be referred to as a memory cell belonging to that state.

[0047] A determination voltage is set between two adjacent states to determine the data. For example, as illustrated in Figure 4, a determination voltage VA is set between the “Er” state and the “A” state, a determination voltage VB is set between the “A” state and the “B” state, a determination voltage VC is set between the “B” state and the “C” state, a determination voltage VC is set between the “C” state and the “D” state, a determination voltage VE is set between the “D” state and the “E” state, a determination voltage VF is set between the “E” state and the “F” state, and a determination voltage VG is set between the “F” state and the “G” state.

[0048] In the sense operation, the processing circuit 110 sequentially applies multiple types of determination voltages to the selection word line WL and determines for each memory cell whether it is in a conductive state (in other words, on state) or a non-conductive state (in other words, off state) when each determination voltage is applied. Then, the processing circuit 110 determines the data associated with the state to which the memory cell belongs by performing a logical operation using the determination result obtained for each applied determination voltage.

[0049] Hereafter, the operation of applying a single type of determination voltage VX (where X is one of A to G) to the selection word line WL to determine whether each memory cell is in the ON or OFF state will be referred to as X read, or in some diagrams, further abbreviated as XR. The determination result obtained by X read will be referred to as determination result XR.

[0050] When the data coding shown in Figure 4 is adopted, if a memory cell belongs to any of the "Er", "E", "F", or "G" states, the lower bit of the data held by that memory cell is "1". If a memory cell belongs to any of the "A", "B", "C", or "D" states, the lower bit of the data held by that memory cell is "0". Therefore, the processing circuit 110 determines the upper page data by using two types of judgment voltages, VA and VE. Specifically, the processing circuit 110 performs an A read and an E read, and obtains the lower page data by performing a logical operation using the judgment result AR obtained from the A read and the judgment result ER obtained from the E read.

[0051] If a memory cell belongs to one of the following states: "Er", "A", "D", or "E", the middle bit of the data held by that memory cell is "1". If a memory cell belongs to one of the following states: "B", "C", "F", or "G", the middle bit of the data held by that memory cell is "0". Therefore, the processing circuit 110 determines the middle page data by using three types of determination voltages: VB, VD, and VF. Specifically, the processing circuit 110 performs B read, D read, and F read. Then, the processing circuit 110 obtains the middle page data by performing logical operations using the determination result BR obtained from the B read, the determination result DR obtained from the D read, and the determination result DF obtained from the F read.

[0052] If a memory cell belongs to any of the "Er", "A", "B", or "G" states, the upper bit of the data held by that memory cell is "1". If a memory cell belongs to any of the "C", "D", "E", or "F" states, the upper bit of the data held by that memory cell is "0". Therefore, the processing circuit 110 determines the upper page data by using two types of determination voltages, VC and VG. Specifically, the processing circuit 110 performs a C read and a G read, and obtains the upper page data by performing a logical operation using the determination result CR obtained from the C read and the determination result GR obtained from the G read.

[0053] Thus, the type of determination voltage used for data determination differs depending on the type of page being read. The processing circuit 110 acquires the data from the page being read by combining the determination results of whether the threshold voltage of the memory cell is higher or lower than the determination voltage, using each of the multiple types of determination voltages corresponding to the type of page being sensed individually.

[0054] Figure 4 illustrates the case where a memory cell forms eight non-overlapping lobes. However, the threshold voltage of a memory cell can change due to various factors. For example, the threshold voltage of a memory cell tends to change with the elapsed time since the completion of a program operation. The rate of change in the threshold voltage of a memory cell is fastest immediately after the completion of a program operation and slows down with elapsed time. Memory cells that have undergone many cycles of erase operation and program operation are more prone to threshold voltage changes. Furthermore, the change in the threshold voltage of a memory cell can be influenced not only by the elapsed time since the completion of a program operation, but also by the sense operation on the memory cell in question, the sense operation on adjacent memory cells, the temperature during access, etc. Because the threshold voltage of a memory cell can change, in reality, there may be cases where two adjacent lobes overlap during a sense operation.

[0055] Figure 5 shows another example of the threshold voltages that the memory cells of the embodiment can take. For simplicity of explanation, the distribution of memory cells belonging to either state "A" or state "B" is shown here. The solid line shows the distribution of memory cells belonging to either state "A" or state "B". The dashed line shows the lobe of state "A", and the dotted line shows the lobe of state "B". In this example, the tails of the lobes of state "A" and state "B" overlap. In other words, the maximum threshold voltage of memory cells belonging to state "A" exceeds the determination voltage VB, and the minimum threshold voltage of memory cells belonging to state "B" is below the determination voltage VB. When a memory cell belonging to state "A" and with a threshold voltage greater than the determination voltage VB is read, that memory cell is recognized as belonging to state "B". That is, data programmed as "110" is read as "100". If a memory cell belonging to state "B" and whose threshold voltage is less than the judgment voltage VB is read, that memory cell is recognized as belonging to state "A". In other words, data programmed as "100" is read as "110".

[0056] Thus, data read by the sense operation may change from its value at the time of program operation due to changes in the threshold voltage. The controller 200 responds to changes in data and threshold voltage by error correction and shifting the judgment voltage. Specifically, the controller 200 performs error correction on the read data using the ECC circuit 206. If error correction fails, the controller 200 changes the judgment voltage and performs the read operation again. Error correction failure means that the pre-change data cannot be restored from the changed data. Specifically, error correction failure means that the error bits contained in the read data cannot be corrected. Error correction success means that all error bits contained in the read data have been corrected. A read operation that reads data while changing the judgment voltage is called a shift read.

[0057] The determination voltage can be expressed in various quantities. For example, a fixed value is pre-set for each type of determination voltage (VA to VG), and the determination voltage is expressed as a shift amount (i.e., difference) from the fixed value. In addition, the fixed value is recorded for each type of determination voltage at a predetermined location within the memory chip CP. During shift read, the controller 200 instructs the memory chip CP to shift the amount from the fixed value for each type of determination voltage.

[0058] The method of representing and indicating the determination voltage is not limited to this. For example, the value of the determination voltage may be expressed as a net voltage value rather than a difference, and the determination voltage may be indicated to the memory chip CP as a net voltage value.

[0059] The controller 200 can obtain a judgment voltage value that can suppress the number of error bits generated in the read data. For convenience, this judgment voltage value that can suppress the number of error bits generated in the read data is referred to as the optimal judgment voltage. For example, if the threshold voltage is distributed as shown in the graph in Figure 5, the voltage value VB' at which the distribution of memory cells belonging to either state "A" or state "B" takes a minimum value is considered to be the optimal judgment voltage VB_opt with respect to the judgment voltage VB.

[0060] The controller 200 acquires the optimal judgment voltage when a predetermined condition is triggered. Hereafter, the operation of acquiring the optimal judgment voltage will simply be referred to as the "optimal value acquisition operation."

[0061] As an example of an optimal value acquisition operation, the first optimal value acquisition operation will be explained. The first optimal value acquisition operation is also called Vth tracking. In the first optimal value acquisition operation, it is possible to individually acquire a set of optimal judgment voltages for each of the following: judgment voltages VA and VE required for the lower page read operation, judgment voltages VB, VD, and VF required for the middle page read operation, and judgment voltages VC and VG required for the upper page read operation. Here, as an example, the operation of acquiring the optimal judgment voltages for judgment voltages VA and VE required for the lower page read operation will be explained.

[0062] In the first optimal value acquisition operation, multiple shift reads are performed with slightly different values ​​for each judgment voltage. If the judgment voltages VA and VE, which are the judgment voltages required for the lower page read operation, are the targets for measurement of the optimal judgment voltage, the controller 200 performs multiple shift reads on the memory chip CP to read the lower page. The controller 200 slightly differs the values ​​of each judgment voltage VA and VE with each shift read.

[0063] Figure 6 illustrates the shift read operation performed in the first optimal value acquisition operation of the embodiment.

[0064] In the example in Figure 6, five shift reads are performed. In the i-th shift read (SFTi) (where i is an integer between 1 and 5), Shift_ai is used as the judgment voltage VA and Shift_ei is used as the judgment voltage VE. Specifically, in the first shift read (SFT1), Shift_a1 is used as the judgment voltage VA and Shift_e1 is used as the judgment voltage VE. In the second shift read (SFT2), Shift_a2 is used as the judgment voltage VA and Shift_e2 is used as the judgment voltage VE. In the third shift read (SFT3), Shift_a3 is used as the judgment voltage VA and Shift_e3 is used as the judgment voltage VE. In the fourth shift read (SFT4), Shift_a4 is used as the judgment voltage VA and Shift_e4 is used as the judgment voltage VE. In the fifth shift read (SFT5), Shift_a5 is used as the judgment voltage VA and Shift_e5 is used as the judgment voltage VE. The amount of change for each judgment voltage with each shift read execution may be constant or not. In this example, each judgment voltage is changed by a predetermined step size each time a shift read is executed.

[0065] Furthermore, in the first optimal value acquisition operation, in addition to multiple shift reads, a read is performed to acquire mask data. In the sense operation targeting lower pages, the data of the lower page is determined based on the judgment result AR from the A read and the judgment result ER from the E read. Mask data is used to separate the judgment result AR from the A read and the judgment result ER from the E read from the lower page data obtained by the shift read. The read performed to acquire mask data is referred to as the mask data read.

[0066] In mask data reading, the voltage between two adjacent determination voltages that are targeted for acquisition of the optimal determination voltage is used as the determination voltage. For example, a voltage that is sufficiently far from the voltage between two adjacent determination voltages that are targeted for acquisition of the optimal determination voltage is adopted as the determination voltage in mask data reading.

[0067] In this example, the decision voltage VC is used in mask data read. In other words, a C read is performed in mask data read.

[0068] The range in which a threshold voltage for each memory cell can exist is divided into a total of 12 divisions (Figure 6 (1) to (12)) by the determination voltages used in the five shift reads and the determination voltage VC used in one C read. Figure 7 shows the determination result data obtained by the five shift reads (SFT1 to SFT5) and the determination result data obtained by the mask data read, for each division. Here, as an example, the processing circuit 110 determines that in the determination result from the mask data read, "0" indicates that the memory cell is ON and "1" indicates that the memory cell is OFF.

[0069] For example, consider a memory cell in category (3) that contains a threshold voltage. The processing circuit 110 obtains "0" from that memory cell by mask data read (in this case, C read). The processing circuit 110 also determines that the lower bit held by that memory cell is "0" according to shift read SFT1 and shift read SFT2, and "1" according to shift read SFT3, shift read SFT4, and shift read SFT5.

[0070] Furthermore, for example, a memory cell containing the threshold voltage in category (1) and a memory cell containing the threshold voltage in category (12) will yield the same result after 5 shift reads, but the determination results from the mask data read will differ. In other words, the mask data read can be used to distinguish between memory cells containing the threshold voltage in category (1) and memory cells containing the threshold voltage in category (12).

[0071] A C-read determination result of "0" for a memory cell indicates that the memory cell belongs to the Er state or A state, that is, it is included in categories (1) to (6). A C-read determination result of "1" for a memory cell indicates that the memory cell belongs to the D state or E state, that is, it is included in categories (7) to (12). By performing a masking process using the C-read determination result CR on the read data obtained by shift reads, it is possible to obtain the A-read determination result AR for memory cells belonging to the Er state or A state, and the E-read determination result ER for memory cells belonging to the D state or E state.

[0072] The controller 200 obtains the A-read judgment result AR for each of the five shift reads by masking the judgment results obtained from memory cells belonging to the D-state or E-state using the C-read judgment result CR on the read data of the five shift reads. Then, based on the judgment result AR obtained for each of the five shift reads, the controller 200 calculates the number of memory cells belonging to the Er-state or A-state whose threshold voltage is lower than Shift_a1, the number of memory cells whose threshold voltage is lower than Shift_a2, the number of memory cells whose threshold voltage is lower than Shift_a3, the number of memory cells whose threshold voltage is lower than Shift_a4, and the number of memory cells whose threshold voltage is lower than Shift_a5. In addition, the controller 200 obtains the E-read judgment result ER for each of the five shift reads by masking the judgment results obtained from memory cells belonging to the Er-state or A-state using the C-read judgment result CR on the read data of the five shift reads. The controller 200 then calculates, based on the determination result ER obtained for each of the five shift reads, the number of memory cells belonging to state D or state E whose threshold voltage is lower than Shift_e1, lower than Shift_e2, lower than Shift_e3, lower than Shift_e4, and lower than Shift_e5. The graph in the middle of Figure 8 plots the number of memory cells calculated by this operation.

[0073] Next, the controller 200 calculates the number of memory cells included in each of the categories (1) to (12) based on the number of memory cells whose threshold voltage is lower than Shift_a1, Shift_a2, Shift_a3, Shift_a4, Shift_a5, Shift_e1, Shift_e2, Shift_e3, Shift_e4, and Shift_e5. The graph in the lower part of Figure 8 plots the number of memory cells included in each of the categories (1) to (12).

[0074] The graph plotting the number of memory cells in each of the categories (1) to (12) can be considered an approximation of the distribution of memory cells belonging to either the Er state or the A state, and the distribution of memory cells belonging to either the D state or the E state. Therefore, the controller 200 obtains the voltage value at which the number of memory cells is minimal in the range of categories (1) to (6) among the number of memory cells in each of the categories (1) to (12), as the optimal decision voltage VA_opt applied to the decision voltage VA. The controller 200 also obtains the voltage value at which the number of memory cells is minimal in the range of categories (7) to (12) among the number of memory cells in each of the categories (1) to (12), as the optimal decision voltage VE_opt applied to the decision voltage VE.

[0075] When measuring the optimal judgment voltages VB, VD, and VF required for middle page read operations, the optimal judgment voltages for each of the judgment voltages VB, VD, and VF can be measured by performing multiple shift reads targeting the middle page, a mask data read using the voltage between judgment voltages VB and VD (e.g., VC) as the judgment voltage, and a mask data read using the voltage between judgment voltages VD and VF (e.g., VE) as the judgment voltage.

[0076] Furthermore, when measuring the optimal judgment voltages VC and VG required for upper page read operations, the optimal judgment voltages for each of the judgment voltages VC and VG can be measured by performing multiple shift reads targeting the upper page and a mask data read using the voltage between the judgment voltages VC and VG (e.g., VE) as the judgment voltage.

[0077] Thus, according to the first optimal value acquisition operation, the ON or OFF state of multiple memory cells is determined multiple times by varying the value of the determination voltage, and the optimal determination voltage is acquired based on the group of determination results.

[0078] In the first optimal value acquisition operation, mask data reading is not necessarily required. For example, the processing circuit 110 may perform multiple shift reads while slightly varying a single type of determination voltage to obtain an approximation of the distribution of memory cells around that single type of determination voltage, and then obtain the optimal determination voltage for that single type of determination voltage based on the obtained approximation of the memory cell distribution.

[0079] As another example of the optimal value acquisition operation, we will explain the second optimal value acquisition operation.

[0080] In the second optimal value acquisition operation, the controller 200 compares the read data obtained from the NAND flash memory 100 before any error correction has been performed (referred to as pre-correction data) with the read data after it has been corrected to the expected data by error correction (referred to as post-correction data). The controller 200 then obtains an evaluation index based on the number of bits in which data corresponding to the "Si" state was mistakenly read as data corresponding to the adjacent "Si+1" state, and the number of bits in which data corresponding to the "Si+1" state was mistakenly read as data corresponding to the "Si" state. Based on the evaluation index, the controller 200 then calculates a voltage value for the judgment voltage corresponding to the boundary between the "Si" state and the "Si+1" state that can suppress the number of error bits.

[0081] Hereafter, a bit in which data corresponding to the “Si” state is mistakenly read as data corresponding to the “Si+1” state will be denoted as bit SitoSi+1. A bit in which data corresponding to the “Si+1” state is mistakenly read as data corresponding to the “Si” state will be denoted as bit Si+1toSi. The number of bits SitoSi+1 will be denoted as count SitoSi+1. The number of bits Si+1toSi will be denoted as count Si+1toSi.

[0082] Figures 9 and 10 are diagrams illustrating the second optimal value acquisition operation of the embodiment. In Figures 9 and 10, "A" state and "B" state are given as examples of two adjacent states.

[0083] Figure 9 shows lobes corresponding to state "A" and state "B". These two lobes change due to various factors and overlap with each other. When a read operation is performed on these two lobes using voltages VB1 to VB5 as judgment voltages, the ratio of the number of bits A to B (i.e., count A to B) to the number of bits B to A (i.e., count B to A) changes depending on the judgment voltage.

[0084] When VB3 is used as the judgment voltage, the count A to B is equal to the count B to A. When VB4 or VB5 is used as the judgment voltage, the count A to B is less than the count B to A. When VB5 is used as the judgment voltage, the difference between the count A to B and the count B to A is greater than when VB4 is used as the judgment voltage. When VB1 or VB2 is used as the judgment voltage, the count A to B is greater than the count B to A. When VB1 is used as the judgment voltage, the difference between the count A to B and the count B to A is greater than when VB2 is used as the judgment voltage.

[0085] When the judgment voltage VB3 is used, which is equal to the voltages of counts A to B and B to A, the number of error bits can be minimized. In other words, voltage VB3 is considered to correspond to the optimal value VB_opt for the judgment voltage VB. Furthermore, the greater the judgment voltage VB is than voltage VB3, the greater the ratio of count A to B to count B to A. The smaller the judgment voltage VB is than voltage VB3, the smaller the ratio of count A to B to count B to A.

[0086] Figure 10 is a graph showing the relationship between the common logarithm of the ratio of counts A to B to counts B to A, and the differences d1 to d5 between voltage VB_opt (i.e., VB3) and voltages VB1 to VB5. From this example, it can be seen that there is a linear relationship between the common logarithm of the ratio of counts A to B to counts B to A and the differences d1 to d5.

[0087] The designer stores the relationship shown in Figure 10 in the controller 200, either directly or in a table format. The controller 200 obtains counts A to B and B to A based on a comparison between the pre-correction data and the post-correction data. The controller 200 then calculates the common logarithm of the ratio of count A to B to count B to A as an evaluation metric. The controller 200 then calculates the differential voltage at which the common logarithm of the ratio of count A to B to count B to A can be set to 0, based on the evaluation metric obtained through the calculation and the relationship described above. The controller 200 then obtains the voltage VB_opt by applying the obtained differential voltage to the value of the judgment voltage used to acquire the read data.

[0088] The controller 200 obtains pairs of pre-correction and post-correction data for each page by performing read operations on the lower, middle, and upper pages of a single memory cell group MSG. Based on the set of pre-correction data for all pages and the set of post-correction data for all pages, the controller 200 identifies the memory cell corresponding to bit SitoSi+1 and the memory cell corresponding to bit Si+1toSi at each state boundary. The controller 200 then calculates the count SitoSi+1 and the count Si+1toSi at each state boundary. Based on the pairs of count SitoSi+1 and count Si+1toSi calculated at each state boundary, the controller 200 obtains the optimal decision voltage VA to VG.

[0089] Furthermore, in order to obtain the optimal judgment voltage for all judgment voltages AR to GR, it is necessary to read data from all pages of a single memory cell group MSG, as described above. In the second optimal value acquisition operation, as in the first optimal value acquisition operation, it is possible to obtain the optimal judgment voltage only for the judgment voltage required for the read operation of a specific page among the judgment voltages AR to GR by using mask data.

[0090] For example, a bit that changes from "0" to "1" due to error correction of the read data from the lower page is either bit A to Er or bit D to E. Also, a bit that changes from "1" to "0" due to error correction of the read data from the lower page is either bit Er to A or bit E to D. The controller 200 identifies bit A to Er and bit Er to A among the bits that changed from "0" to "1" by masking the bits read from memory cells belonging to the D state or E state in the read data from the lower page using, for example, the judgment result CR from a C read. The controller 200 also identifies bit D to E among the bits that changed from "0" to "1" and bit E to D among the bits that changed from "1" to "0" by masking the bits read from memory cells belonging to the Er state or A state in the read data from the lower page using, for example, the judgment result CR from a C read. The controller 200 calculates the optimal decision voltage VA_opt for the decision voltage VA based on the number of bits A to Er and the number of bits Er to A. The controller 200 also calculates the optimal decision voltage VE_opt for the decision voltage VE based on the number of bits D to E and the number of bits E to D.

[0091] Thus, in the second optimal value acquisition operation, the optimal judgment voltage is obtained based on a comparison between the read data before error correction and the read data after error correction.

[0092] In the first and second optimal value acquisition operations, the result of at least one read operation (i.e., read data) is used. In the read operation, read data is acquired using the determination result obtained by determining whether the memory cell is on or off using at least one determination voltage. Therefore, the first and second optimal value acquisition operations can be considered as operations that determine whether the memory cell is on or off using a determination voltage and acquire an optimal determination voltage based on the determination result.

[0093] As mentioned above, the threshold voltage of a memory cell can change due to various factors. One of the factors that causes a change in the threshold voltage of a memory cell is the temperature of the memory chip CP when accessing the memory cell array 111.

[0094] Some memory chips have a built-in function to autonomously change the judgment voltage to cancel out changes in the threshold voltage. However, even with such a function, it is difficult to completely cancel out changes in the threshold voltage. If changes in the threshold voltage cannot be completely canceled out, the number of error bits included in the read data increases. The increase in the number of error bits due to the inability to completely cancel out changes in the threshold voltage tends to be larger the larger the number of bits of data written to a single memory cell.

[0095] Figure 11 shows an example of the temperature dependence of the determination voltage in a memory chip CP of an embodiment. Figure (A) is a graph showing the distribution of the threshold voltage and determination voltage of the memory cells when the temperature of the memory chip CP is higher than a certain temperature (here, 50°C as an example) which is the reference temperature. Figure (B) is a graph showing the distribution of the threshold voltage and determination voltage of the memory cells when the temperature of the memory chip CP is the reference temperature. Figure (C) is a graph showing the distribution of the threshold voltage and determination voltage of the memory cells when the temperature of the memory chip CP is lower than the reference temperature.

[0096] In the example shown in Figure 11, the lobes of each state shift towards the negative voltage side as the temperature increases. This indicates that in order to suppress the number of error bits included in the read data, it is necessary to shift each judgment voltage towards the negative voltage side as the temperature increases. In other words, even if an optimal judgment voltage is obtained at one temperature, when using that optimal judgment voltage at a different temperature, it is necessary to correct the optimal judgment voltage according to the difference between the temperature at which the optimal judgment voltage was obtained and the temperature at which it is used.

[0097] The memory chip CP may or may not have a function to change the judgment voltage according to temperature in order to cancel out changes in the threshold voltage. If the memory chip CP does not have a function to change the judgment voltage according to temperature, the temperature fluctuations of each lobe and each judgment voltage shown in Figure 11 can be considered to represent the actual temperature fluctuations of each lobe and each judgment voltage. If the memory chip CP has a function to change the judgment voltage according to temperature information, the temperature fluctuations of each lobe and each judgment voltage shown in Figure 11 can be considered to represent the components of the actual temperature fluctuations of each lobe and each judgment voltage that could not be canceled out by the function of the memory chip CP.

[0098] During read operations, the controller 200 changes the judgment voltage instructed to the memory chip CP according to the temperature at the time of the read operation. Specifically, when the controller 200 obtains a voltage value as the optimal judgment voltage through an optimal value acquisition operation, it converts the obtained optimal judgment voltage value to a voltage value at a reference temperature based on the temperature information at the time of acquisition and stores it. Then, when performing a read operation thereafter, the controller 200 corrects the stored voltage value at the reference temperature based on the temperature at the time of the read operation and executes the read operation using the corrected voltage value as the judgment voltage.

[0099] Note that the reference temperature is just one example of a temperature setting value.

[0100] This section describes technologies that are comparable to the embodiments. Technologies that are comparable to the embodiments will be referred to as comparative examples. According to the comparative example, when the memory controller uses an optimal determination voltage during a read operation, it corrects the optimal determination voltage based on the temperature information at the time of the optimal value acquisition operation that obtained the optimal determination voltage and the temperature information at the time of the read operation, and uses the corrected optimal determination voltage. However, according to this comparative example, it is necessary to save the temperature at the time of the optimal value acquisition operation, and the management of changing the determination voltage according to the temperature becomes complicated.

[0101] According to this embodiment, the controller 200 converts the optimal judgment voltage obtained by the optimal value acquisition operation into a voltage value at a reference temperature and stores it. Therefore, there is no need to store the temperature at the time the optimal value acquisition operation is performed, and management of changing the judgment voltage according to the temperature becomes easier.

[0102] Hereafter, the voltage value at the reference temperature converted from the optimal judgment voltage will be referred to as the reference judgment voltage. The voltage value obtained by correcting the reference judgment voltage based on the temperature during the read operation will be referred to as the corrected judgment voltage. Unless otherwise specified, the optimal judgment voltage will refer to the voltage value obtained by the optimal value acquisition operation.

[0103] When the controller 200 converts the optimal decision voltage to a reference decision voltage, or converts the reference decision voltage to a corrected decision voltage, it uses temperature correction information corresponding to the temperature dependence of the threshold voltage of the memory cell.

[0104] Figure 12 shows an example of temperature correction information 210 in the embodiment. In the example shown in this figure, the temperature correction information 210 shows the relationship between temperature and correction amount.

[0105] In the temperature correction information 210, the correction amount is set to 0 at the reference temperature. In this example, the relationship between temperature and the correction amount is defined as a linear function in which the correction amount increases with temperature.

[0106] For example, when converting the optimal judgment voltage to a reference judgment voltage, the controller 200 obtains a correction amount corresponding to the temperature at the time the optimal judgment voltage was acquired, based on the temperature correction information 210. Then, the controller 200 obtains the reference judgment voltage by adding the correction amount to the optimal judgment voltage.

[0107] Furthermore, during a read operation, the controller 200 obtains a correction amount corresponding to the temperature during the read operation based on the temperature correction information 210. The controller 200 then obtains a corrected judgment voltage by subtracting the correction amount from the reference judgment voltage.

[0108] The relationship between temperature and correction amount defined by the temperature correction information 210 is not limited to the example shown in Figure 12. As long as the temperature correction information 210 corresponds to the temperature dependence of the memory cell and is information that can convert or correct the determination voltage based on that temperature dependence, the format of the temperature correction information 210 is not limited to a specific format. The temperature correction information 210 may be information expressed as a mathematical formula or information in table format.

[0109] Furthermore, the temperature correction information 210 may define the relationship between temperature and correction amount for each of the determination voltages VA to VG. Alternatively, it may be common to several or all of the determination voltages VA to VG.

[0110] Furthermore, the temperature dependence of the threshold voltage of the memory cell may differ for each memory chip CP. Therefore, for example, the temperature compensation information 210 is generated individually for each memory chip CP by the manufacturer of the memory chip CP. The temperature compensation information 210 for each memory chip CP is stored, for example, in a predetermined area of ​​the memory chip CP.

[0111] As shown in Figure 13, the memory cell array 111 includes a ROM fuse 121 and a user ROM 122.

[0112] The ROM fuse 121 contains various setting information pre-stored by the manufacturer of the memory chip CP, which is essential for the proper control of the memory chip CP. For example, defective block information is stored in the ROM fuse 121. During the manufacturing process, blocks with defects exceeding acceptable levels are detected as defective blocks. The defective block information is a record of a list of detected defective blocks. The controller 200 obtains the defective block information from the memory chip CP and disables the use of the blocks recorded in the obtained defective block information.

[0113] The user ROM 122 contains various setting information that can be used to control the memory chip CP but is not essential for control, pre-stored by the memory chip CP manufacturer. In one example, the temperature compensation information 210 is stored in this user ROM 122. The controller 200 loads the temperature compensation information 210 from the user ROM 122 into the RAM 202 and refers to the temperature compensation information 210 loaded into the RAM 202 as needed.

[0114] In the correspondence defined by the temperature correction information 210, "temperature" refers, for example, to the temperature of the memory chip CP. In this case, the controller 200 obtains the temperature used for searching to acquire the correction amount from the temperature correction information 210 from the temperature sensor 112 provided on the memory chip CP. In other words, when the controller 200 acquires the correction amount based on the temperature correction information 210, it sends a command to the memory chip CP requesting the output of the temperature detection value.

[0115] Figure 14 shows an example of a command sequence for acquiring a temperature detection value from a memory chip CP in an embodiment. In the example shown in this figure, the controller 200 sends a temperature query command and address information, which includes at least the memory chip address indicating the memory chip CP that will output the temperature detection value, to the memory chip CP in this order. The memory chip CP acquires a temperature detection value from the temperature sensor 112 it is equipped with. The state of the memory chip CP is kept busy during the period for acquiring the temperature detection value. Once the acquisition of the temperature detection value is complete, the memory chip CP transitions to a ready state and outputs the temperature detection value to the controller 200.

[0116] The controller 200 obtains a correction amount by referring to the temperature correction information 210 using the acquired temperature detection value.

[0117] In the correspondence defined by the temperature correction information 210, "temperature" may be the temperature at any location different from the memory chip CP, as long as it correlates with the temperature of the memory chip CP. For example, if there is a correlation between the temperature of the controller 200 and the temperature of the memory chip CP, the temperature correction information 210 may be configured to obtain a correction amount from the temperature of the controller 200. In that case, the controller 200 can obtain a temperature detection value from its own temperature sensor 207 and obtain a correction amount by referring to the temperature correction information 210 using that temperature detection value.

[0118] Furthermore, the location where the temperature compensation information 210 is pre-stored is not limited to the user ROM 122 of each memory chip CP. Also, one piece of temperature compensation information 210 may be shared by two or more memory chip CPs (for example, all memory chip CPs). In addition, multiple pieces of temperature compensation information 210 may be provided per memory chip CP. For example, temperature compensation information 210 may be provided for each plane.

[0119] Figure 15 shows an example of a method for managing the reference judgment voltage in the embodiment.

[0120] In the example shown in Figure 15, one set of reference decision voltages is associated with and stored for each block. The set of reference decision voltages consists of the reference decision voltage for decision voltage VA, the reference decision voltage for decision voltage VB, the reference decision voltage for decision voltage VC, the reference decision voltage for decision voltage VD, the reference decision voltage for decision voltage VE, the reference decision voltage for decision voltage VF, and the reference decision voltage for decision voltage VG. The set of reference decision voltages is recorded in the reference decision voltage table 211 for each block and is updated as needed.

[0121] The reference determination voltage table 211 is stored in, for example, RAM 202 and updated in RAM 202. When the power is lost, the reference determination voltage table 211 in RAM 202 may or may not be transferred to a predetermined non-volatile storage area (e.g., NAND flash memory 100).

[0122] Furthermore, the reference voltage set does not necessarily have to be managed on a block basis. The reference voltage set may be managed on a memory area larger than a block, or on a memory area smaller than a block.

[0123] Figure 16 shows an example of the information that the memory system 1 of the embodiment holds in RAM 202 during operation. As shown in this figure, during operation, RAM 202 holds temperature compensation information 210-0 acquired from memory chip CP0, temperature compensation information 210-1 acquired from memory chip CP1, temperature compensation information 210-2 acquired from memory chip CP2, and temperature compensation information 210-3 acquired from memory chip CP3. In addition, RAM 202 holds a reference judgment voltage table 211.

[0124] Note that the temperature correction information 210 is an example of the first information. The reference judgment voltage table 211 is an example of the second information. RAM 202 is an example of a second memory configured to store the first information, and is also an example of a third memory configured to store the second information. The second memory and the third memory may be configured by a single RAM 202 as in the embodiment, or they may be configured by different memories.

[0125] Next, the operation of the memory system 1 of the embodiment will be described.

[0126] Figure 17 shows an example of the operation of the memory system 1 of the embodiment during startup.

[0127] When memory system 1 is powered on, controller 200 powers on each memory chip CP (S101). In Figure 17, the operation for one memory chip CP is shown for simplicity.

[0128] When the memory chip CP completes the processing corresponding to power-on, it notifies the controller 200 that power-on is complete (S102).

[0129] Upon notification that power-on is complete, the controller 200 requests defective block information (S103).

[0130] During the power-on process, the memory chip CP reads the management information stored in the ROM fuse 121, which includes defective block information, from the ROM fuse 121 and sets it in a predetermined register within the memory chip CP. The memory chip CP outputs the defective block information from the management information in the register in response to a request received through the process in S103 (S104).

[0131] Next, the controller 200 requests temperature compensation information 210 (S105). In response to the request received through processing in S104, the memory chip CP reads the temperature compensation information 210 stored in the user ROM 122 and outputs the temperature compensation information 210 (S106). The controller 200 stores the acquired temperature compensation information 210 in the RAM 202.

[0132] In this example, the controller 200 acquires temperature compensation information 210 from each memory chip CP at startup.

[0133] Figure 18 is a flowchart showing an example of the operation of the memory system 1 in the embodiment during program execution.

[0134] The controller 200 executes a program operation for one block (S201). In the explanation of Figure 18, the block in which the S201 process is executed is referred to as the target block. The S201 process is repeatedly executed until there are no more available slots in the target block.

[0135] The controller 200 determines whether the program operation on the target block is complete (S202). Completion of the program operation on the target block means, for example, that the target block is filled with data and there is no longer any area available to store other data.

[0136] If the program operation for the target block is not yet complete (S202: No), the controller 200 executes the process in S201 again.

[0137] When the program operation for the target block is completed (S202: Yes), the controller 200 acquires the initial setting value of the judgment voltage (S203). Then, the controller 200 associates the initial setting value of the judgment voltage with the target block as the reference judgment voltage set and records it in the reference judgment voltage table 211 (S204), and the operation ends.

[0138] The initial setting of the judgment voltage is pre-configured. For example, the initial setting of the judgment voltage is common to all memory chip CPs. In cases where a fixed value is pre-configured for each type of judgment voltage (VA~VG) for each memory chip CP, and the judgment voltage is managed by the controller 200 as a shift amount (i.e., difference) from the fixed value, the initial setting of the judgment voltage is set to all zeros. However, the examples of initial setting of the judgment voltage are not limited to these.

[0139] In one embodiment, the set of reference setting values ​​is recorded on a block-by-block basis. Therefore, as shown in Figure 18, when a program operation for a block is completed and no further program operations are performed for that block until an erase operation is executed, the initial setting value of the judgment voltage is recorded in the reference judgment voltage table 211.

[0140] Figure 19 is a flowchart showing an example of the operation of the memory system 1 in an embodiment in response to a read command from the host device 300.

[0141] When the controller 200 receives a read command from the host device 300 (S301), the controller 200 obtains the temperature for use in referencing temperature correction information 210, etc. (S302). The temperature is, for example, the temperature detected by the temperature sensor 112 or the temperature detected by the temperature sensor 207. In the explanation of Figure 19, the page to be read by the read command received in S301 is referred to as the target page.

[0142] The controller 200 obtains a reference decision voltage from the reference decision voltage table 211 that is associated with the block containing the target page (S303). In S303, the controller 200 obtains the type of reference decision voltage required for the read operation on the target page from the set of reference decision voltages associated with the block containing the target page. In the explanation of Figure 19, unless otherwise specified, the decision voltage including the reference decision voltage and the correction decision voltage refers to the type of decision voltage required for the read operation on the target page from the decision voltages VA to VG.

[0143] The controller 200 calculates a correction judgment voltage based on the temperature obtained by the process in S302, the reference judgment voltage obtained by the process in S303, and the temperature correction information 210 (S304). Then, the controller 200 performs a read operation on the target page using the correction judgment voltage (S305).

[0144] The controller 200 performs error correction on the read data acquired by the read operation (S306). In S306, the controller 200 performs error correction, for example, using the ECC circuit 206.

[0145] The controller 200 determines whether or not the error correction was successful (S307). If the error correction fails (S307: No), the controller 200 obtains the optimal judgment voltage by the first optimal value acquisition operation (S308). The controller 200 performs a read operation on the target page using the optimal judgment voltage (S309). Then, the controller 200 performs error correction on the read data obtained by the process in S309 (S310). In S310, the controller 200 performs error correction, for example, by the ECC circuit 206.

[0146] The controller 200 determines whether the error correction was successful (S311). If the error correction is successful (S311: Yes), the controller 200 calculates a new reference judgment voltage based on the temperature obtained by the process in S302, the optimal judgment voltage obtained by the process in S309, and the temperature correction information 210 (S312). Then, the controller 200 overwrites the reference judgment voltage table 211 with the new reference judgment voltage (S313).

[0147] If the error correction fails (S311: No), the controller 200 performs a second error correction with higher correction capability than the error correction performed in S306 or S310 (S314). Any method can be used for the second error correction, as long as it has high correction capability and can recover the read data with a very high probability. For example, the controller 200 may perform error correction using soft judgment as the second error correction. In another example, the controller 200 may perform error correction by compounding product codes.

[0148] If error correction is successful (S307: Yes), after S313 or after the read data has been restored by S314, the controller 200 outputs the read data to the host device 300 (S315). Then, the operation of the memory system 1 in response to the read command is completed.

[0149] Thus, if error correction fails during a read operation in response to a read command from the host device 300, an optimal value acquisition operation (the first optimal value acquisition operation in this example) is initiated. Then, based on the optimal judgment voltage acquired by the optimal value acquisition operation, the reference judgment voltage recorded in the reference judgment voltage table 211 is updated.

[0150] Furthermore, as one of the management functions of the NAND flash memory 100, the controller 200 can perform a transfer operation to transfer data between blocks. The transfer operation includes, for example, garbage collection. The transfer operation includes a read operation to read data from the NAND flash memory 100 and a write operation to write data to the NAND flash memory 100. The controller 200 may also be configured to perform the operations S302 to S314 during a read operation as part of the transfer operation.

[0151] Furthermore, the triggers for the optimal value acquisition operation and the updating of the reference judgment voltage table 211 are not limited to errors occurring only when error correction fails during a read operation in response to a write operation from the host device 300 or during a read operation as part of a transcription process.

[0152] For example, the controller 200 can perform patrol reads as another way of managing the NAND flash memory 100. A patrol read is a read operation performed on the memory chip CP regardless of requests from the host device 300. The purpose of a patrol read is to pre-determine an optimal judgment voltage in order to increase the probability of successful error correction when a read request comes from the host device 300. The controller 200 performs patrol reads, for example, at predetermined intervals. The controller 200 may skip the execution of patrol reads or temporarily or permanently change the execution interval of patrol reads in response to the reception of write or read commands from the host device 300. In other words, patrol reads are performed multiple times at different timings, regardless of read commands from the host device 300.

[0153] In this embodiment, the controller 200 can perform optimal value acquisition operations and update the reference judgment voltage table 211 during patrol read operations.

[0154] Figure 20 is a flowchart illustrating an example of the operation of a patrol read in the memory system 1 of the embodiment. Here, as an example, the operation of a patrol read applied to one block is explained.

[0155] The controller 200 determines the memory cell group MSG to be patrolled by some method (S401). In the explanation of Figure 20, the memory cell group MSG to be patrolled is referred to as the target memory cell group MSG.

[0156] The controller 200 acquires the temperature to be used for referencing the temperature correction information 210, etc. (S402). The temperature is, for example, the temperature detected by the temperature sensor 112 or the temperature detected by the temperature sensor 207.

[0157] The controller 200 obtains a set of reference decision voltages associated with the block containing the target memory cell group MSG from the reference decision voltage table 211 (S403). Then, the controller 200 calculates a set of correction decision voltages based on the temperature obtained in the process of S402, the set of reference decision voltages obtained in the process of S403, and the temperature correction information 210 (S404).

[0158] The controller 200 sequentially performs read operations on each page constituting the target memory cell group MSG. In Figure 20, each of the three pages of the memory cell group MSG is denoted as page i, using the identifier i (where i is an integer from 0 to 2). For example, page 0 represents the lower page, page 1 represents the middle page, and page 2 represents the upper page. Note that the correspondence between identifier i and the three pages is not limited to this.

[0159] The controller 200 initializes identifier i to 0 (S405). Then, the controller 200 selects page i, one of the three pages constituting the target memory cell group MSG, as the read target and performs a read operation using the correction determination voltage (S406).

[0160] The controller 200 stores the read data acquired by the read operation in the RAM 202 as pre-correction data (S407), and separately from the stored pre-correction data, performs error correction on the read data (S408). In S408, the controller 200 performs error correction, for example, using the ECC circuit 206.

[0161] The controller 200 determines whether the error correction was successful (S409). If the error correction is successful (S409: Yes), the controller 200 stores the corrected read data in the RAM 202 as corrected data (S410). Then, the controller 200 determines whether the identifier i is equal to 2 (S411).

[0162] If identifier i is not equal to 2 (S411: No), that is, if identifier i is 0 or 1, the controller 200 increments i by 1 (S412). Then, the controller 200 repeats the series of processes from S406.

[0163] If identifier i is equal to 2 (S411: Yes), the controller 200 obtains a set of optimal judgment voltages by a second optimal value acquisition operation using the pre-correction data and post-correction data acquired for each page (S413).

[0164] If error correction fails during a read operation for any page (S409: No), the second optimal value acquisition operation cannot be performed. Therefore, the controller 200 acquires the optimal judgment voltage set by the first optimal value acquisition operation (S414).

[0165] After S413 or S414, the controller 200 calculates a new set of reference decision voltages based on the temperature obtained by processing S402, the set of optimal decision voltages obtained by processing S413 or S414, and the temperature correction information 210 (S415). The controller 200 then overwrites the reference decision voltage table 211 with the new set of reference decision voltages (S416). The patrol read operation for one block then ends.

[0166] Figure 21 shows an example of the changes in the contents of the reference determination voltage table 211 in the embodiment.

[0167] Figure 21(A) shows the initial reference decision voltage table 211. In the initial state, the set of reference decision voltages for each block is undefined.

[0168] For example, once the program operation on block #0 and block #1 is complete (S501), the contents of the reference determination voltage table 211 change to the state shown in (B). In the reference determination voltage table 211 shown in (B), the set of initial setting values ​​for the determination voltages Vdec_def is recorded as a set of reference determination voltages applicable to block #0 and block #1.

[0169] Next, for example, a read operation is performed on block #0 in response to a read command from the host device 300 (S502). Assume that the temperature at the time of the read operation was Ta. During the read operation, a new set of optimal judgment voltages Vdec_opt is acquired, and the contents of the reference judgment voltage table 211 change to the state shown in (C). According to the reference judgment voltage table 211 shown in (C), block #0 has a set of values ​​obtained by adding the set of optimal judgment voltages Vdec_opt and the correction amount Diff(Ta to 50℃) corresponding to the temperature Ta, recorded as the set of reference judgment voltages for block #0.

[0170] The controller 200 of the embodiment has the configuration described above. Therefore, for example, if a read operation is performed on a certain block at a certain timing (referred to as the first timing) and error correction fails (see, for example, S307 in Figure 19), or if a patrol read is performed at the first timing (see, for example, Figure 20), and the next read operation (see Figure 19) is performed at a timing after the first (referred to as the second timing), the controller 200 operates as follows. That is, at the first timing, the controller 200 acquires a temperature detection value (referred to as the first temperature detection value) from the temperature sensor 112 or temperature sensor 207, and acquires an optimal judgment voltage by the first optimal value acquisition operation or the second optimal value acquisition operation. Then, the controller 200 converts the optimal judgment voltage into a reference judgment voltage based on the first temperature detection value and the temperature correction information 210, and records the reference judgment voltage in the reference judgment voltage table 211. Then, at the second timing, the controller 200 acquires a new temperature detection value (referred to as the second temperature detection value) from the temperature sensor 112 or temperature sensor 207, converts the reference judgment voltage recorded in the reference judgment voltage table 211 into a corrected judgment voltage, which is the judgment voltage at the temperature of the second temperature detection value, based on the second temperature detection value and the temperature correction information 210, and uses the corrected judgment voltage as the judgment voltage to perform a read operation.

[0171] In this way, the optimal judgment voltage is converted to a voltage value at the temperature setpoint based on the temperature correction information 210 and managed accordingly. This makes it possible to suppress the number of error bits generated in the read data without complicating the management of changing the judgment voltage according to the temperature. In other words, it is possible to suppress the number of error bits generated in the read data with simple management.

[0172] The technology of the embodiment can be modified in various ways. Several modifications of the technology of the embodiment are described below. In the description of the modifications, we will describe the differences from the technology of the embodiment described above. Matters that are the same as those of the technology of the embodiment will be omitted or described in a simplified manner.

[0173] (Variation 1) Figure 22 is a flowchart showing an example of the operation of the memory system 1 in modified example 1 during program execution.

[0174] In modified example 1, the controller 200 executes the same processes in S601 to S602 as in S201 to S202 shown in Figure 18.

[0175] When the program operation for the target block is completed (S602: Yes), the controller 200 acquires the temperature (S603). The temperature is, for example, the temperature detected by temperature sensor 112 or temperature sensor 207.

[0176] Next, the controller 200 obtains a set of initial values ​​for the judgment voltage (S604). Then, the controller 200 calculates a reference judgment voltage based on the temperature obtained in the process of S603, the set of initial values ​​for the judgment voltage obtained in the process of S604, and the temperature correction information 210 (S605). Specifically, the controller 200 obtains a correction amount corresponding to the temperature based on the temperature correction information 210. Then, the controller 200 obtains a reference judgment voltage by adding the correction amount to the initial value of each judgment voltage.

[0177] The controller 200 records the set of reference judgment voltages obtained through the processing in S605 in the reference judgment voltage table 211, associating it with the target block (S606), and then the operation ends.

[0178] Figure 23 shows an example of the changes in the contents of the reference judgment voltage table 211 in the modified example 1.

[0179] Figure 23(A) shows the initial reference decision voltage table 211. In the initial state, the set of reference decision voltages for each block is undefined.

[0180] For example, once the program operation on block #0 and block #1 is complete (S701), the contents of the reference judgment voltage table 211 change to the state shown in (B). Note that the temperature during the program operation on block #0 is Tb, and the temperature during the program operation on block #1 is Tc. The reference judgment voltage table 211 shown in (B) records a set of values ​​obtained by adding the initial setting value set of judgment voltages Vdec_def and the correction amount Diff (Tb to 50℃) corresponding to the temperature Tb, as the set of reference judgment voltages for block #0. In addition, a set of values ​​obtained by adding the initial setting value set of judgment voltages Vdec_def and the correction amount Diff (Tc to 50℃) corresponding to the temperature Tc is recorded as the set of reference judgment voltages for block #1.

[0181] Next, for example, a read operation is performed on block #0 in response to a read command from host device 300 (S702). Assume the temperature at the time of the read operation was Td. During the read operation, a new set of optimal judgment voltages Vdec_opt is acquired, and the contents of the reference judgment voltage table 211 change to the state shown in (C). According to the reference judgment voltage table 211 shown in (C), the set of values ​​obtained by adding the set of optimal judgment voltages Vdec_opt and the correction amount Diff(Td to 50℃) corresponding to the temperature Td is recorded as the set of reference judgment voltages for block #0.

[0182] Thus, in the modified example 1, the controller 200 is configured to perform a conversion based on the temperature correction information 210 even when recording the reference judgment voltage during program operation.

[0183] In other words, according to Modification 1, when a program operation is performed on a certain block, and then a read operation is performed on that block in response to a read command from the host device 300, or as part of a transcription operation, the controller 200 operates as follows: During the program operation, the controller 200 calculates a set of reference judgment voltages by performing a conversion on the initial setting value of the judgment voltages based on the temperature and temperature correction information 210 during the program operation, and records this set of reference judgment voltages in the reference judgment voltage table 211. During the subsequent read operation, the controller 200 obtains a corrected judgment voltage by performing a conversion on the reference judgment voltages recorded in the reference judgment voltage table 211 based on the temperature and temperature correction information 210 during the read operation, and executes the read operation using the corrected judgment voltages.

[0184] (Modification 2) In Modification 2, a set of candidate values ​​for the judgment voltage is prepared in advance. An index is associated with each set of candidate values ​​for the judgment voltage, and the controller 200 stores the index corresponding to the set of candidate values ​​that are close to the set of immediate values, rather than the set of reference judgment voltages as an immediate value set. The set of candidate values ​​for the judgment voltage is referred to as a shift pattern. The shift pattern is pre-recorded in the shift index table 212.

[0185] Figure 24 shows an example of the information held in RAM 202 during operation of the memory system 1 of Modification 2. As shown in this figure, during operation, RAM 202 holds temperature compensation information 210-0 acquired from memory chip CP0, temperature compensation information 210-1 acquired from memory chip CP1, temperature compensation information 210-2 acquired from memory chip CP2, temperature compensation information 210-3 acquired from memory chip CP3, a reference judgment voltage table 211, and a shift index table 212.

[0186] Note that the temperature compensation information 210 is an example of the first information. The reference judgment voltage table 211 is an example of the second information. The shift index table 212 is an example of the third information. RAM 202 is an example of a second memory configured to store the first information, an example of a third memory configured to store the second information, and an example of a fourth memory configured to store the third information. The second memory, third memory, and fourth memory may be configured by a single RAM 202 as in Modification Example 2, or they may each be configured by different memories.

[0187] Figure 25 shows an example of the data structure of the shift index table 212 in the modified example 2.

[0188] The shift index table 220 contains multiple entries, each containing one shift pattern. A shift pattern is a set containing one value for each type of judgment voltage, and represents a candidate value for the judgment voltage.

[0189] Each entry in the shift index table 220 is distinguished by an index. A shift pattern is recorded for each entry. The shift pattern recorded for each entry represents a candidate value for the determination voltage. In other words, the shift pattern is associated with an index value.

[0190] Figure 26 is a flowchart showing an example of how to obtain a set of reference determination voltages using the reference determination voltage table 211 and the shift index table 212 in Modification Example 2. The series of operations shown in Figure 26 are performed in S303 of Figure 19 and S403 of Figure 20.

[0191] The reference determination voltage table 211 records indices instead of sets of immediate reference determination voltages. Therefore, the controller 200 obtains the index associated with the block of interest from the reference determination voltage table 211 (S801). Then, the controller 200 refers to the shift index table 212 and obtains the shift pattern corresponding to the index obtained in the process of S801 as a set of reference determination voltages (S802). The operation of obtaining a set of reference determination voltages using the reference determination voltage table 211 and the shift index table 212 is then completed.

[0192] Figure 27 is a flowchart showing an example of a method for recording the set of reference judgment voltages in Modification 2. The series of operations shown in Figure 27 are performed in S313 of Figure 19, S416 of Figure 20, and S606 of Figure 22.

[0193] The controller 200 identifies the shift pattern that is most similar to the set of reference decision voltages among the multiple shift patterns recorded in the shift index table 212 (S901). Any metric can be used as an indicator of similarity between the set of reference decision voltages and the shift pattern. For example, Euclidean distance, cosine similarity, etc., can be used as indicators of similarity.

[0194] Furthermore, if the series of operations shown in Figure 27 is performed in S313 of Figure 19, the controller 200 updates the old set of reference judgment voltages, that is, the set of reference judgment voltages obtained by the S802 process of the series of operations in Figure 26 which replaces the S303 process in Figure 19, with the new set of reference judgment voltages obtained by the S312 process in Figure 19, thereby obtaining a new set of reference judgment voltages. Then, the controller 200 performs the S901 process on this new set of reference judgment voltages.

[0195] After S801, the controller 200 records the index corresponding to the identified shift pattern in the reference judgment voltage table 211 (S902). Then, the operation of recording the set of reference judgment voltages is completed.

[0196] Thus, the reference decision voltage table 211 may be configured such that an index corresponding to one shift pattern selected from multiple shift patterns is recorded as a set of reference decision voltages.

[0197] Furthermore, the above-described modification 2 can be applied not only to the embodiment but also in conjunction with modification 1.

[0198] (Variation 3) In Embodiment 1 and Modification 2, the initial settings were basically fixed. The initial settings may be configured to be variable.

[0199] As already mentioned, the rate of change in the threshold voltage of a memory cell is fastest immediately after the completion of a program operation and slows down with elapsed time. Also, in the relatively short period immediately after the completion of a program operation, the number of accesses since the completion of the program operation is not large, so it is thought that the threshold voltage changes in a similar pattern in multiple memory areas with similar characteristics. In addition, the reference judgment voltage corresponding to a block for which a relatively short time has elapsed since the completion of the program operation may not have been updated by a patrol read. If the series of operations related to the read operation shown in Figure 19 is executed based on a reference judgment voltage that has not been updated by a patrol read, there is a considerable possibility that error correction of the read data will fail.

[0200] In Modification 3, the initial settings are updated by a predetermined operation to suppress the probability of error correction failure during read operations on blocks where the elapsed time since the completion of program operation is relatively short. One set of initial settings is used in common for groups of blocks whose threshold voltage change characteristics are considered to be similar. The rules for grouping blocks can be arbitrarily determined by the manufacturer. For example, one group may be formed per memory chip CP. Or, one group may be formed per plane. Or, the memory cell array 111 may be divided into multiple sub-regions according to the distance from the sense amplifier, and one group may be formed per sub-region.

[0201] Figure 28 shows an example of a management method for modified example 3 of the initial setting value set.

[0202] Initial settings are recorded in the initial settings table 213. Specifically, the initial settings table 213 has an entry for each block group, and each entry records a set of initial settings.

[0203] For example, in the process of S203 in Figure 18 and the process of S204 in Figure 22, the controller 200 obtains a set of initial settings for the block group to which the block whose program operation has been completed belongs from the initial setting value table 213.

[0204] The initial setting value table 213 is stored, for example, in RAM 202, and updates to the initial setting value table 213 are performed on RAM 202.

[0205] Figure 29 is a flowchart showing an example of how to update the initial setting set, as shown in Modification 3.

[0206] In variation 3, a representative block is set for each block group. The method for setting the representative block is not limited to a specific method.

[0207] When the controller 200 completes the program operation for the representative block (S1001), and a predetermined short time (e.g., 6 hours) has elapsed since the completion of the program operation for the representative block (S1002), it performs various processes, including an optimal value acquisition operation, to acquire a set of reference judgment voltages for the representative block (S1003). In one example, the controller 200 selects a memory cell group MSG from the representative block by some method, and performs the processes S402 to S415 in Figure 20 on the memory cell group MSG to acquire a set of reference judgment voltages for the representative block.

[0208] The controller 200 overwrites the initial setting value table 213 with the acquired set of reference judgment voltages as the set of initial settings for the block group to which the representative block belongs (S1004). Then, the operation of updating the set of initial settings is completed.

[0209] Thus, according to Modification 3, the controller 200 updates the set of initial values ​​for the block group based on the optimal value acquisition operation for the representative block selected from the block group.

[0210] Therefore, it is possible to suppress the probability of error correction failure during read operations on blocks where the elapsed time since the completion of program execution is relatively short.

[0211] Furthermore, the above-described modification 3 can be applied not only to the embodiment, but also to modification 1, modification 2, or both.

[0212] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0213] 1 Memory system, 100 NAND flash memory, 110 Processing circuit, 111 Memory cell array, 112 Temperature sensor, 114 NAND string, 121 ROM fuse, 122 User ROM, 200 Controller, 201 Host interface circuit, 202 RAM, 203 CPU, 204 Buffer memory, 205 NAND interface circuit, 206 ECC circuit, 207 Temperature sensor, 210 Temperature compensation information, 211 Reference judgment voltage table, 212 Shift index table, 213 Initial setting value table, 220 Shift index table, 300 Host device, 400 NAND bus, CP memory chip.

Claims

1. A non-volatile first memory comprising a first storage area having a word line and a plurality of memory cells connected to the word line, A second memory configured to store first information corresponding to the temperature dependence of the threshold voltage of the plurality of memory cells, A third memory configured to store second information, in which the value of a determination voltage corresponding to the threshold voltage of the plurality of memory cells is recorded, A temperature sensor and A first temperature detection value is obtained from the temperature sensor, A first read operation is performed to acquire data from the plurality of memory cells using the determination voltage, error correction is performed on the data acquired by the first read operation, and if the error correction is successful, a first voltage value, which is the value of the determination voltage that suppresses the number of error bits, is acquired based on a comparison of the data before the error correction and the data after the error correction. The first voltage value is converted to a second voltage value, which is the value of the determination voltage at the temperature setpoint, based on the first temperature detection value and the first information, and the second voltage value is recorded in the second information. Controller and Equipped with, In a second read operation performed after recording the second voltage value to the second information, the controller acquires data from the plurality of memory cells, A second temperature detection value is obtained from the aforementioned temperature sensor. The second voltage value recorded in the second information is converted into a third voltage value, which is the value of the determination voltage at the second temperature detection value, based on the second temperature detection value and the first information. The voltage of the third voltage value is used as the determination voltage to acquire data from the plurality of memory cells. Memory system.

2. The memory system is connectable to a host device, The first read operation is an operation based on a read request from the host device. The memory system according to claim 1.

3. The acquisition operation involves determining whether the multiple memory cells are in an on state or an off state multiple times by varying the value of the determination voltage, and acquiring the first voltage value based on the group of determination results. The memory system according to claim 1 or claim 2.

4. A non-volatile first memory comprising a first storage area having a word line and a plurality of memory cells connected to the word line, A second memory configured to store first information corresponding to the temperature dependence of the threshold voltage of the plurality of memory cells, A third memory configured to store second information, in which the value of a determination voltage corresponding to the threshold voltage of the plurality of memory cells is recorded, A temperature sensor and The program executes an operation to set the threshold voltage of the plurality of memory cells to a value corresponding to the data. A first temperature detection value is obtained from the temperature sensor, The first voltage value, which is the initial setting value of the determination voltage, is converted to a second voltage value, which is the value of the determination voltage at the temperature set value, based on the first temperature detection value and the first information, and the second voltage value is recorded in the second information. Controller and Equipped with, In a first read operation performed after recording the second voltage value to the second information, the controller acquires data from the plurality of memory cells, A second temperature detection value is obtained from the aforementioned temperature sensor. The value of the determination voltage is obtained from the second information, The third voltage value, which is the value of the determination voltage obtained from the second information, is converted to a fourth voltage value, which is the value of the determination voltage at the second temperature detection value, based on the second temperature detection value and the first information. Error correction is performed on the data obtained using the voltage of the fourth voltage value as the determination voltage. If the aforementioned error correction fails, The acquisition operation is performed for the first storage area to determine whether the plurality of memory cells are on or off using the determination voltage, and to obtain a fifth voltage value, which is the value of the determination voltage that suppresses the number of error bits generated, based on the determination result. The fifth voltage value is converted into a sixth voltage value, which is the value of the determination voltage at the temperature setpoint, based on the second temperature detection value and the first information, and the sixth voltage value is recorded in the second information. In a second read operation performed after recording the sixth voltage value to the second information, the controller acquires data from the plurality of memory cells, A third temperature detection value is obtained from the aforementioned temperature sensor. The sixth voltage value recorded in the second information is converted into a seventh voltage value, which is the value of the determination voltage at the third temperature detection value, based on the third temperature detection value and the first information. The voltage of the seventh voltage value is used as the determination voltage to acquire data from the plurality of memory cells. Memory system.

5. The first memory comprises a plurality of second storage areas, including the first storage area. Each of the plurality of second memory regions comprises a word line and a plurality of memory cells connected to the word line, The aforementioned controller, The acquisition operation is performed on the third storage area selected from the plurality of second storage areas. The initial setting value is updated based on the acquisition operation for the third memory area. The memory system according to claim 4.

6. The acquisition operation is an operation in which the multiple memory cells are determined multiple times to be on or off by varying the value of the determination voltage, and the fifth voltage value is acquired based on the group of determination results. The memory system according to claim 4 or claim 5.

7. It includes a fourth memory in which a third piece of information is stored, each containing multiple candidate values ​​associated with an index. The second information includes an index corresponding to the value selected from the plurality of candidate values, which is recorded as the value of the determination voltage. The memory system according to claim 1 or claim 4.

8. Each of the plurality of memory cells is capable of storing 4 bits of data. The memory system according to claim 1 or claim 4.

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