Semiconductor equipment

Abstract

To provide a semiconductor device with an increased area of an active region.SOLUTION: A semiconductor device 100 comprises a semiconductor substrate including a transistor part 70 and a diode part 80 and is provided with a plurality of trench parts 30 and 40. The transistor part comprises an emitter region 12 of a first conductivity type provided on a front surface of the semiconductor substrate, a base region 14 of a second conductivity type provided on the semiconductor substrate, and a contact region 15 of the second conductivity type provided on the front surface of the semiconductor substrate and having a higher doping concentration than the base region. The diode part is provided on the front surface of the semiconductor substrate and includes an anode region 84 of the second conductivity type having a lower doping concentration than the base region. The transistor part includes a main region 72 separated from the diode part and a first boundary region 73 provided between the main region and the diode part and including emitter regions and base regions alternately provided in a trench extension direction.SELECTED DRAWING: Figure 1A

Description

[Technical Field]

[0001] This invention relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 describes that in an RC-IGBT, in order to suppress the injection of holes from the IGBT region to the diode region during reverse recovery, a boundary region is provided between the IGBT region and the diode region in which the proportion of the high-concentration P-type layer is less than that of the IGBT region. [Prior art document] [Patent] [Patent Document 1] Japanese Unexamined Patent Publication No. 2018-73911 [Overview of the project] [Problems that the invention aims to solve]

[0003] The present invention provides a semiconductor device that increases the area of ​​the active region while suppressing reverse recovery loss. [Means for solving the problem]

[0004] In a first embodiment of the present invention, a semiconductor device is provided. The semiconductor device comprises a semiconductor substrate having a transistor portion and a diode portion, and a plurality of trench portions, wherein the transistor portion has an emitter region of a first conductivity type provided on the front surface of the semiconductor substrate, a base region of a second conductivity type provided on the semiconductor substrate, and a contact region of a second conductivity type provided on the front surface of the semiconductor substrate and having a higher doping concentration than the base region, the diode portion has an anode region of a second conductivity type provided on the front surface of the semiconductor substrate and having a lower doping concentration than the base region, the transistor portion has a main region on the front surface of the semiconductor substrate having the emitter region and the contact region and spaced apart from the diode portion, and a first boundary region provided between the main region and the diode portion and having the emitter region and the base region alternately provided on the front surface of the semiconductor substrate in the trench extension direction.

[0005] The main region may have the contact region and the emitter region arranged alternately in the trench stretching direction on the front surface of the semiconductor substrate.

[0006] A lifetime control region including a lifetime killer does not need to be provided on the front side of the semiconductor substrate.

[0007] The transistor portion has a second boundary region provided between the first boundary region and the diode portion, and the second boundary region may have the anode region on the front surface of the semiconductor substrate.

[0008] The transistor portion and the diode portion further have trench contact portions provided on the front surface of the semiconductor substrate, and the lower end of the trench contact portion may be shallower than the lower end of the emitter region.

[0009] The transistor portion and the diode portion further have trench contact portions provided on the front surface of the semiconductor substrate, and the lower end of the trench contact portion may be the same depth as the lower end of the emitter region.

[0010] The transistor and diode portions may further have a second conductivity type plug region provided at the bottom of the trench contact portion, which has a higher doping concentration than the base region.

[0011] The plug area does not need to be provided in the first boundary area.

[0012] The transistor portion has a second boundary region provided between the first boundary region and the diode portion, the main region and the first boundary region have a plug region of a second conductivity type provided at the bottom of the trench contact portion and having a higher doping concentration than the base region, and the diode portion and the second boundary region may be selectively provided with the plug region provided at the bottom of the trench contact portion and having a higher doping concentration than the base region.

[0013] The transistor portion has a second boundary region provided between the first boundary region and the diode portion, the main region is provided at the bottom of the trench contact portion and has a plug region of a second conductivity type with a higher doping concentration than the base region, and the diode portion and the second boundary region may be selectively provided with the plug region at the bottom of the trench contact portion with a higher doping concentration than the base region.

[0014] The transistor portion may further include a storage region of a first conductivity type provided on the semiconductor substrate.

[0015] The storage region does not need to be provided below the anode region.

[0016] The storage region is provided in both the transistor portion and the diode portion, and the storage region provided below the anode region may have a lower doping concentration than the storage region provided below the base region.

[0017] The transistor portion further comprises a collector region of a second conductivity type provided on the back surface of the semiconductor substrate, and the diode portion may further comprise a first cathode region of a first conductivity type provided on the back surface of the semiconductor substrate, and a second cathode region of a second conductivity type provided on the back surface of the semiconductor substrate, having a smaller area than the first cathode region.

[0018] Note that the above summary of the invention does not enumerate all the features of the present invention. Also, sub-combinations of these feature groups can also be inventions.

Brief Description of the Drawings

[0019] [Figure 1A] An example of a top view of the semiconductor device 100 according to Example 1 is shown. [Figure 1B] It is a diagram showing an example of the a-a' cross-section in FIG. 1A. [Figure 1C] It is a diagram showing an example of the b-b' cross-section in FIG. 1A. [Figure 1D] An example of a bottom view of the semiconductor device 100 is shown. [Figure 1E] Another example of a bottom view of the semiconductor device 100 is shown. [Figure 2] An example of a top view of the semiconductor device 1100 according to the comparative example is shown. [Figure 3A] It is a diagram showing a modified example of the a-a' cross-section in FIG. 1A. [Figure 3B] It is a diagram showing a modified example of the b-b' cross-section in FIG. 1A. <00ented. [Figure 4] It is a diagram showing a modified example of the b-b' cross-section in FIG. 1A. [Figure 5] An example of a top view of the semiconductor device 200 according to Example 2 is shown. [Figure 6A] An example of a top view of the semiconductor device 300 according to Example 3 is shown. [Figure 6B] It is a diagram showing an example of the d-d' cross-section in FIG. 6A. [Figure 6C] It is a diagram showing an example of the e-e' cross-section in FIG. 6A. [Figure 7A] It is a diagram showing a modified example of the d-d' cross-section in FIG. 6A. [Figure 7B] It is a diagram showing a modified example of the e-e' cross-section in FIG. 6A. [Figure 8A] It is a diagram showing a modified example of the d-d' cross-section in FIG. 6A. [Figure 8B] It is a diagram showing a modified example of the e-e' cross-section in FIG. 6A. [Figure 9] An example of a top view of the semiconductor device 400 according to Example 4 is shown. [Modes for carrying out the invention]

[0020] The present invention will be described below through embodiments of the invention, but these embodiments are not intended to limit the invention as defined in the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0021] In this specification, one side of a semiconductor substrate parallel to its depth direction is referred to as "top," and the other side as "bottom." Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as the top surface, and the other surface as the bottom surface. The directions of "top," "bottom," "front," and "back" are not limited to the direction of gravity or the direction of attachment to the substrate, etc., when mounting a semiconductor device.

[0022] In this specification, technical matters may be described using the orthogonal coordinate axes of the X, Y, and Z axes. In this specification, the plane parallel to the front surface of the semiconductor substrate is defined as the XY plane, and the depth direction of the semiconductor substrate is defined as the Z axis. In this specification, when viewing the semiconductor substrate in the Z axis direction... Top view It is called that.

[0023] In each embodiment, an example is shown where the first conductivity type is N-type and the second conductivity type is P-type, but the first conductivity type may be P-type and the second conductivity type may be N-type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment will have opposite polarities.

[0024] In this specification, layers or regions prefixed with N or P indicate that electrons or holes are the majority carriers, respectively. Furthermore, the + and - signs attached to N and P indicate higher and lower doping concentrations, respectively, compared to layers or regions without these signs, with ++ indicating a higher doping concentration than + and -- indicating a lower doping concentration than -.

[0025] In this specification, doping concentration refers to the concentration of the donor or accepted dopant. Therefore, its unit is / cm³. 3 In this specification, the doping concentration may be defined as the difference in concentrations between the donor and acceptor (i.e., the net doping concentration). In this case, the doping concentration can be measured by the SR method. Alternatively, the chemical concentrations of the donor and acceptor may be defined as the doping concentration. In this case, the doping concentration can be measured by the SIMS method. Unless otherwise specified, any of the above may be used as the doping concentration. Unless otherwise specified, the peak value of the doping concentration distribution in the doping region may be defined as the doping concentration in that doping region.

[0026] Furthermore, in this specification, dose refers to the number of ions per unit area implanted into the wafer during ion implantation. Therefore, its unit is / cm². 2 The doping dose in a semiconductor region can be expressed as the integrated concentration obtained by integrating the doping concentration over the depth of that semiconductor region. The unit of this integrated concentration is / cm². 2 Therefore, the dose and the integrated concentration can be treated as the same thing. The integrated concentration may also be the integral value up to the full width at half maximum, and if it overlaps with the spectrum of other semiconductor regions, it may be derived by removing the influence of those semiconductor regions.

[0027] Therefore, in this specification, high or low doping concentration can be interpreted as high or low dose. That is, if the doping concentration in one region is higher than the doping concentration in another region, it can be understood that the dose in that region is higher than the dose in the other region.

[0028] Figure 1A shows an example of a top view of a semiconductor device 100 according to Embodiment 1. The semiconductor device 100 comprises a semiconductor substrate having a transistor section 70 including a transistor element such as an IGBT, and a diode section 80 including a diode element such as a freewheeling diode (FWD). For example, the semiconductor device 100 is a reverse conducting IGBT (RC-IGBT).

[0029] In this specification, when simply referred to as a "top view," it means viewing from the front side of the semiconductor substrate. In this example, the orientation of the arrangement of the transistor section 70 and the diode section 80 in the top view is referred to as the X-axis, the direction perpendicular to the X-axis on the front surface of the semiconductor substrate is referred to as the Y-axis, and the direction perpendicular to the front surface of the semiconductor substrate is referred to as the Z-axis.

[0030] The transistor section 70 and the diode section 80 may each have an elongated length in the extension direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section described later.

[0031] The transistor section 70 is the region obtained by projecting the collector region 22, which is provided on the back side of the semiconductor substrate, onto the front side of the semiconductor substrate 10. In this example, the collector region 22 is of type P+. The transistor section 70 includes transistors such as IGBTs.

[0032] The transistor section 70 has a gate trench section 40 periodically arranged on the front side of the semiconductor substrate, which includes an N-type emitter region 12, a P-type base region 14, a gate conductive portion, and a gate insulating film.

[0033] The diode section 80 is the region obtained by projecting the cathode region 82, which is provided on the back side of the semiconductor substrate 10, onto the front side of the semiconductor substrate 10. In this example, the cathode region 82 is of type N+. The diode section 80 includes a diode such as a freewheel diode (FWD) provided adjacent to the transistor section 70 on the front side of the semiconductor substrate 10. On the back side of the semiconductor substrate 10, a P+ type collector region may be provided in areas other than the cathode region.

[0034] The semiconductor substrate may be a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate such as gallium nitride. In this example, the semiconductor substrate is a silicon substrate.

[0035] The semiconductor device 100 in this example includes a gate trench 40, a dummy trench 30, an emitter region 12, a base region 14, a contact region 15, a well region 17, and an anode region 84, all located on the front side of the semiconductor substrate. The gate trench 40 and the dummy trench 30 are examples of trenches.

[0036] Furthermore, the semiconductor device 100 in this example includes a gate metal layer 50 and an emitter electrode 52 provided above the front surface of the semiconductor substrate. An interlayer insulating film is provided between the emitter electrode 52 and the gate metal layer 50 and the front surface of the semiconductor substrate, but this is omitted in Figure 1A. Contact holes 54, 55, and 56 are provided in the interlayer insulating film in this example, penetrating the interlayer insulating film. In Figure 1A, each contact hole is hatched with diagonal lines.

[0037] The emitter electrode 52 is positioned above the gate trench 40, dummy trench 30, emitter region 12, base region 14, contact region 15, well region 17, and anode region 84. The emitter electrode 52 is electrically connected to the emitter region 12, base region 14, contact region 15, and anode region 84 on the front surface of the semiconductor substrate through the contact hole 54.

[0038] The emitter electrode 52 and the gate metal layer 50 are formed from a metal-containing material. At least a portion of the emitter electrode 52 may be formed from aluminum or an alloy mainly composed of aluminum (e.g., aluminum-silicon alloy, aluminum-silicon-copper alloy, etc.). At least a portion of the gate metal layer 50 may be formed from aluminum or an alloy mainly composed of aluminum (e.g., aluminum-silicon alloy, aluminum-silicon-copper alloy, etc.).

[0039] The emitter electrode 52 and the gate metal layer 50 may have a barrier metal formed of titanium or a titanium compound in the layer below a region formed of aluminum or the like. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.

[0040] The contact hole 55 connects the gate conductive portion within the gate trench portion 40 of the transistor portion 70 to the gate metal layer 50. A plug made of tungsten or the like may be provided inside the contact hole 55 via a barrier metal.

[0041] The contact hole 56 connects the dummy conductive part in the dummy trench 30 provided in the transistor section 70 and the diode section 80 to the emitter electrode 52. A plug made of tungsten or the like may be provided inside the contact hole 56 via a barrier metal.

[0042] The connection portion 25 electrically connects the front-side electrode, such as the emitter electrode 52 or the gate metal layer 50, to the semiconductor substrate. In one example, the connection portion 25 is provided in the region between the gate metal layer 50 and the gate conductive portion, including the inside of the contact hole 55. The connection portion 25 is also provided in the region between the emitter electrode 52 and the dummy conductive portion, including the inside of the contact hole 56.

[0043] The connecting portion 25 is made of a conductive material such as polysilicon doped with metals such as tungsten or impurities. The connecting portion 25 may also have a barrier metal such as titanium nitride. In this case, the connecting portion 25 is polysilicon (N+) doped with N-type impurities. The connecting portion 25 is provided above the front surface of the semiconductor substrate via an insulating film such as an oxide film.

[0044] The gate trenches 40 are arranged at predetermined intervals along a predetermined alignment direction (in this example, the X-axis direction). The gate trenches 40 in this example may have two extended portions 39 that extend along an extension direction (in this example, the Y-axis direction) parallel to the front surface of the semiconductor substrate and perpendicular to the alignment direction, and a connecting portion 41 that connects the two extended portions 39.

[0045] It is preferable that at least a portion of the connection portion 41 is formed in a curved shape. By connecting the ends of the two extended portions 39 of the gate trench portion 40, electric field concentration at the ends of the extended portions 39 can be mitigated. At the connection portion 41 of the gate trench portion 40, the gate metal layer 50 may be connected to the gate conductive portion.

[0046] The dummy trench portion 30 is a trench portion in which a dummy conductive portion provided inside is electrically connected to the emitter electrode 52. The dummy trench portion 30, like the gate trench portion 40, is arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). The dummy trench portion 30 in this example, like the gate trench portion 40, may have a U-shape on the front surface of the semiconductor substrate. That is, the dummy trench portion 30 may have two extended portions 29 that extend along the stretching direction and a connecting portion 31 that connects the two extended portions 29.

[0047] The transistor section 70 in this example has a structure in which one gate trench section 40 and two dummy trench sections 30 are repeatedly arranged. That is, the transistor section 70 in this example has gate trench sections 40 and dummy trench sections 30 in a ratio of 1:2. For example, in the transistor section 70, two extended sections 29 are provided between adjacent extended sections 39 in the arrangement direction.

[0048] However, the ratio of the gate trench portion 40 to the dummy trench portion 30 is not limited to this example. The ratio of the gate trench portion 40 to the dummy trench portion 30 may be 1:1 or 2:3. Furthermore, the transistor portion 70 may be a so-called full-gate structure in which the dummy trench portion 30 is omitted and the entire structure is made up of gate trench portions 40.

[0049] The well region 17 is located on the front side of the semiconductor substrate, closer to the drift region 18, which will be described later. The well region 17 is an example of a well region located on the edge side of the semiconductor device 100. The well region 17 is, for example, of type P++. The well region 17 is located within a predetermined range from the edge of the active region on the side where the gate metal layer 50 is provided.

[0050] The diffusion depth of the well region 17 may be greater than the depth of the gate trench portion 40 and the dummy trench portion 30. A portion of the gate trench portion 40 and the dummy trench portion 30 on the gate metal layer 50 side is provided in the well region 17. The bottom of the extending end of the gate trench portion 40 and the dummy trench portion 30 may be covered by the well region 17.

[0051] The contact holes 54 are provided above the emitter region 12 and the contact region 15 in the transistor section 70. The contact holes 54 are also provided above the anode region 84 in the diode section 80. None of the contact holes 54 are provided above the well regions 17 at both ends in the Y-axis direction. Thus, one or more contact holes 54 are provided in the interlayer insulating film. The contact holes 54 in this example may be provided in an extended direction.

[0052] The mesa portions 71 and 81 are mesa portions provided adjacent to the trench portions in a plane parallel to the front surface of the semiconductor substrate. The mesa portion is a portion of the semiconductor substrate sandwiched between two adjacent trench portions, and may be a portion from the front surface of the semiconductor substrate to the depth of the deepest bottom of each trench portion. The extended portions of each trench portion may be regarded as one trench portion. That is, the region sandwiched between two extended portions may be regarded as a mesa portion.

[0053] In the transistor portion 70, the mesa portion 71 is provided adjacent to at least one of the dummy trench portion 30 or the gate trench portion 40. The mesa portion 71 has a well region 17, an emitter region 12, a base region 14, and a contact region 15 on the front surface of the semiconductor substrate.

[0054] The base region 14 is a region provided on the front surface side of the semiconductor substrate in the transistor portion 70. The anode region 84 is a region provided on the front surface side of the semiconductor substrate in the diode portion 80.

[0055] The doping concentration of the anode region 84 is lower than that of the base region 14. As an example, the base region 14 is of P+ type and the anode region 84 is of P- type. The doping concentration of the anode region 84 is 2.0E12 cm -3 above and 8.0E12 cm -3 below, and the doping concentration of the base region 14 is 2.0E13 cm -3 above and 3.0E13 cm -3 below. Here, E means the power of 10. For example, 1E16 cm -3 means 1×10 16 cm -3 In this example, by reducing the doping concentration of the anode region 84, the hole injection during reverse recovery can be suppressed.

[0056] The emitter region 12 has the same conductivity type as the drift region 18, but with a higher doping concentration than the drift region 18. In this example, the emitter region 12 is N+ type. An example of a dopant for the emitter region 12 is arsenic (As). The emitter region 12 is provided on the front surface of the mesa portion 71, in contact with the gate trench portion 40. The emitter region 12 may extend in the X-axis direction from one of the two trench portions flanking the mesa portion 71 to the other.

[0057] Furthermore, the emitter region 12 may or may not be in contact with the dummy trench portion 30. In this example, the emitter region 12 is in contact with the dummy trench portion 30. The emitter region 12 is not provided in the mesa portion 81.

[0058] The contact region 15 has the same conductivity type as the base region 14, but with a higher doping concentration than the base region 14. In this example, the contact region 15 is of type P++. In this example, the contact region 15 is provided on the front surface of the mesa portion 71. The contact region 15 may be provided in the X-axis direction from one of the two trench portions flanking the mesa portion 71 to the other. The contact region 15 may or may not be in contact with the gate trench portion 40. Also, the contact region 15 may or may not be in contact with the dummy trench portion 30. In this example, the contact region 15 is in contact with both the dummy trench portion 30 and the gate trench portion 40.

[0059] The transistor section 70 in this example has a main region 72 spaced apart from the diode section 80, a first boundary region 73 provided between the main region 72 and the diode section, and a second boundary region 74 provided between the first boundary region 73 and the diode section 80.

[0060] In the mesa portion 71 of the main region 72, the emitter region 12 and the contact region 15 are alternately provided in the stretching direction on the front surface of the semiconductor substrate. In the mesa portion 71 of the first boundary region 73, the emitter region 12 and the base region 14 are alternately provided in the stretching direction on the front surface of the semiconductor substrate. In the mesa portion 71 of the second boundary region 74, the anode region 84 is provided on the front surface of the semiconductor substrate. The mesa portion 71 of the second boundary region 74 does not have an emitter region 12 or a contact region 15.

[0061] The mesa portion 81 is provided in the diode portion 80 in the region sandwiched between adjacent dummy trench portions 30. In this example, the anode region 84 is provided in the mesa portion 81 on the front surface of the semiconductor substrate. In other words, in this example, the front surface structure of the second boundary region 74 is the same as the front surface structure of the diode portion 80.

[0062] Thus, in this example, a first boundary region 73 and a second boundary region 74 are provided between the main region 72, which operates as a transistor, and the diode region 80. By providing an anode region 84 with a low doping concentration in the second boundary region 74, hole injection during reverse recovery can be suppressed.

[0063] On the other hand, by providing a base region 14 with a lower doping concentration than the contact region 15 in the first boundary region 73, hole injection during reverse recovery can be suppressed, and by providing an emitter region 12, the area of ​​the active region can be increased in addition to the main region 72. For example, if the length of the first boundary region 73 is W1 and the length of the second boundary region 74 is W2 in the arrangement direction, the total length W1+W2 of the first boundary region 73 and the second boundary region 74 is 68 μm to 72 μm, and the length W1 of the first boundary region 73 is 34 μm to 36 μm.

[0064] Figure 1B shows an example of the a-a' cross section in Figure 1A. Figure 1C shows an example of the b-b' cross section in Figure 1A. The a-a' and b-b' cross sections are XZ planes passing through the contact region 15. The a-a' cross section mainly shows the XZ plane from the main region 72 to the first boundary region 73, and the b-b' cross section mainly shows the XZ plane from the first boundary region 73 to the diode portion 80.

[0065] The semiconductor device 100 in this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in cross-sections a-a' and b-b'. The emitter electrode 52 is provided above the semiconductor substrate 10 and the interlayer insulating film 38.

[0066] The drift region 18 is a region provided on the semiconductor substrate 10. In this example, the drift region 18 is N-type. The drift region 18 may be a region remaining on the semiconductor substrate 10 without other doping regions being formed. That is, the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.

[0067] The buffer region 20 is a region located below the drift region 18. In this example, the buffer region 20 has the same conductivity type as the drift region 18, and is N-type as an example. The doping concentration of the buffer region 20 is higher than that of the drift region 18. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower surface of the base region 14 from reaching the collector region 22 and the cathode region 82.

[0068] The collector region 22 is a region in the transistor section 70 located below the buffer region 20, with a different conductivity type than the drift region 18. The cathode region 82 is a region in the diode section 80 located below the buffer region 20, with the same conductivity type as the drift region 18. The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor section 70 and the diode section 80.

[0069] The collector electrode 24 is provided on the back surface 23 of the semiconductor substrate 10. The collector electrode 24 is formed from a conductive material such as metal, or by laminating conductive materials.

[0070] The base region 14 is a region of a different conductivity type than the drift region 18, located above the drift region 18 in the mesa portion 71 of the main region 72 and the first boundary region 73. In this example, the base region 14 is of type P+. The base region 14 is provided in contact with the gate trench portion 40. The base region 14 may be provided in contact with the dummy trench portion 30.

[0071] The anode region 84 is a region of a different conductivity type than the drift region 18, located above the drift region 18 in the mesa portion 71 of the second boundary region 74 and the mesa portion 81 of the diode portion 80. In this example, the anode region 84 is P-type. The anode region 84 is located in contact with the dummy trench portion 30.

[0072] The emitter region 12 is provided between the base region 14 and the front surface 21. In this example, the emitter region 12 is provided in the mesa portion 71 of the main region 72 and the first boundary region 73, but not in the mesa portion 71 and mesa portion 81 of the second boundary region 74. The emitter region 12 is provided in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30.

[0073] When the diode section 80 conducts, an electron current flows from the cathode region 82 to the anode region 84. When the electron current reaches the anode region 84, conductivity modulation occurs, and a hole current flows from the anode region 84. In addition, the electron current diffused from the cathode region 82 promotes hole injection from the contact region 15 of the transistor section 70, increasing the hole density of the semiconductor substrate 10. As a result, the time it takes for holes to disappear when the diode section 80 is turned off becomes longer, so the reverse recovery peak current increases and the reverse recovery loss increases.

[0074] One known technique for suppressing such hole currents is to provide a lifetime control region containing a lifetime killer on the front surface of the semiconductor substrate. A lifetime killer is, for example, an electron beam injected into the entire semiconductor substrate, or helium, electron beams, or protons injected to a predetermined depth. The lifetime control region is a crystal defect formed inside the semiconductor substrate by the injection of the lifetime killer. The lifetime control region promotes the recombination and annihilation of electrons and holes that occur when the diode conducts, thereby reducing reverse recovery losses.

[0075] In this example, a lifetime control region including a lifetime killer is not provided on the front surface 21 of the semiconductor substrate 10. In this example, by lowering the doping concentration of the anode region 84, hole injection during reverse recovery can be suppressed even without a lifetime control region.

[0076] The trench contact portion 60 electrically connects the emitter electrode 52 to the semiconductor substrate. The trench contact portion 60 is provided continuously with the contact hole 54. In this example, the trench contact portion 60 is provided in both the mesa portion 71 and the mesa portion 81.

[0077] The trench contact portion 60 has a conductive material that fills the contact hole 54. The trench contact portion 60 is provided between two adjacent trench portions among a plurality of trench portions. In this example, the bottom of the trench contact portion 60 is covered by the plug region 19. The bottom of the trench contact portion 60 is the lower end of the trench contact portion 60 and a part of the side wall connected to the lower end. The trench contact portion 60 may have the same material as the emitter electrode 52.

[0078] Furthermore, a barrier metal made of titanium or a titanium compound may be provided inside the trench contact portion 60 and the contact hole 54. In addition, a plug made of tungsten or the like may be provided inside the trench contact portion 60 and the contact hole 54 via the barrier metal.

[0079] The lower end of the trench contact portion 60 is shallower than the lower end of the emitter region 12. By providing the trench contact portion 60, the resistance of the base region 14 is reduced, making it easier to extract minority carriers (e.g., holes). As a result, even if the base region 14 has a lower doping concentration than the contact region 15 in the first boundary region 73, the fracture tolerance, such as the latch-up tolerance caused by minority carriers, can be improved.

[0080] For example, the distance between the lower end of the emitter region 12 and the front surface 21 is 0.4 μm to 0.5 μm, and the distance D between the lower end of the trench contact portion 60 and the front surface 21 is 0.3 μm to 0.4 μm.

[0081] The lower end of the trench contact portion 60 may be shallower than or the same depth as the lower end of the emitter region 12. For example, the distance between the lower end of the emitter region 12 and the front surface 21 is 0.4 μm to 0.5 μm, and the distance D between the lower end of the trench contact portion 60 and the front surface 21 is 0.3 μm to 0.5 μm.

[0082] For example, the trench contact portion 60 is formed by etching the interlayer insulating film 38. The trench contact portion 60 has a substantially planar bottom surface. In this example, the trench contact portion 60 has a tapered shape with inclined side walls. However, the side walls of the trench contact portion 60 may be provided substantially perpendicular to the front surface 21.

[0083] The plug region 19 is provided at the bottom of the trench contact portion 60 in both the mesa portion 71 and the mesa portion 81. The plug region 19 has the same conductivity type as the base region 14 and the anode region 84, but has a higher doping concentration than the base region 14 and the anode region 84. In this example, the plug region 19 is of type P++.

[0084] For example, the plug region 19 is formed by ion implantation of boron (B) or boron fluoride (BF2) from the lower end of the trench contact portion 60. The plug region 19 may have the same doping concentration as the contact region 15. In this example, the doping concentration of the plug region 19 is 1E15cm². -3 Above, 1E16cm -3 The following applies: The plug region 19 suppresses latch-up by pulling out minority carriers.

[0085] The plug region 19 diffuses from the lower end of the trench contact portion 60 and covers at least a portion of the side wall of the trench contact portion 60. The lower end of the plug region 19 may be the same depth as or shallower than the lower end of the contact region 15. This suppresses the influence of the plug region 19 on the gate threshold due to its contribution to the base region 14.

[0086] Furthermore, in this example, by also providing a plug region 19 in the diode section 80, the low doping concentration in the anode region 84 can be compensated for, and an ohmic junction can be ensured.

[0087] The storage region 16 is a region located below the main region 72 and the first boundary region 73. As shown in Figure 1B, two or more storage regions 16 may be provided in the drift region 18. In this example, the storage region 16 has the same conductivity type as the drift region 18, and is N-type as an example. The storage region 16 does not need to be located below the anode region 84, i.e., in the second boundary region 74 and the diode section 80.

[0088] Furthermore, the accumulation region 16 is provided in contact with the gate trench portion 40. The accumulation region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration in the accumulation region 16 is higher than the doping concentration in the drift region 18. The doping concentration in the accumulation region 16 is 1E12cm -3 Above, 1E14cm -3 The following is possible: By providing a storage region 16, the carrier injection promotion effect (IE effect) can be enhanced, and the on-voltage of the transistor section 70 can be reduced.

[0089] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the front surface 21. Each trench extends from the front surface 21 to the drift region 18. In regions where at least one of the emitter region 12, base region 14, contact region 15, and storage region 16 is provided, each trench penetrates these regions as well and reaches the drift region 18. The statement that a trench penetrates a doping region is not limited to cases where the doping region is formed before the trenches are formed. Cases where doping regions are formed between the trenches after the trenches have been formed are also included in cases where the trenches penetrate a doping region.

[0090] The gate trench portion 40 has a gate trench provided on the front surface 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided covering the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor of the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench, on the inside of the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front surface 21 by an interlayer insulating film 38.

[0091] The gate conductive portion 44 includes a region in the depth direction of the semiconductor substrate 10 that faces an adjacent base region 14 on the mesa portion 71 side, with the gate insulating film 42 in between. When a predetermined voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is created on the surface layer of the interface in contact with the gate trench within the base region 14.

[0092] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the front surface 21 side. The dummy insulating film 32 is provided covering the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 is covered on the front surface 21 by an interlayer insulating film 38.

[0093] The interlayer insulating film 38 is provided on the front surface 21. An emitter electrode 52 is provided above the interlayer insulating film 38. The interlayer insulating film 38 is provided with one or more contact holes 54 for electrically connecting the emitter electrode 52 and the semiconductor substrate 10. Contact holes 55 and 56 may also be provided through the interlayer insulating film 38.

[0094] Figure 1D shows an example of a bottom view of the semiconductor device 100. Here, only the active region is shown on the back surface 23 of the semiconductor substrate 10, and the edge region is omitted. The collector electrode 24 provided on the back surface 23 of the semiconductor substrate 10 is also omitted.

[0095] The collector region 22 is a region in the transistor section 70 located below the buffer region 20, with a different conductivity type than the drift region 18. The cathode region 82 is a region in the diode section 80 located below the buffer region 20, with the same conductivity type as the drift region 18. The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor section 70 and the diode section 80. In the extension direction, the collector region 22 may be provided between the end of the active region and the end of the cathode region 82.

[0096] Figure 1E shows another example of a bottom view of the semiconductor device 100. Explanations common to Figure 1D are omitted here. The cathode region of this example has a first cathode region 82 of a first conductivity type corresponding to the cathode region 82 in Figure 1D, and a second cathode region 83 of a second conductivity type having a smaller area than the first cathode region 82.

[0097] As an example, the second cathode region 83 is a region evenly distributed within a part of the first cathode region 82. In this example, the second cathode region 83 may be provided extending in the direction of arrangement. In the direction of extension, the first cathode region 82 is longer than the second cathode region 83. The second cathode region 83 may have the same doping concentration as the collector region 22. The second cathode region 83 may be in contact with the collector region 22 at its end in the direction of arrangement. The second cathode region 83 suppresses surge voltage during reverse recovery and improves the characteristics of the diode section 80.

[0098] Figure 2 shows an example of a top view of a semiconductor device 1100 related to a comparative example. Here, elements common to the semiconductor device 100 shown in Figure 1A are given the same reference numerals, and their explanations are omitted.

[0099] The semiconductor device 1100 has a first boundary region 173 and a second boundary region 174 provided between the main region 72 of the transistor section 70 and the diode section 80. The first boundary region 173 is the region that includes the mesa section 71 closest to the main region 72, and on the front surface 21 of the semiconductor substrate 10, the contact region 15 extends in the stretching direction. The second boundary region 174 is the region provided between the first boundary region 173 and the diode section 80, and similar to the diode section 80, an anode region 84 is provided on the front surface 21 of the semiconductor substrate 10.

[0100] Similar to semiconductor device 100, semiconductor device 1100 suppresses reverse recovery loss by providing an anode region 84 with a low doping concentration in the diode section 80. Therefore, in semiconductor device 1100, hole injection from the main region 72 during reverse recovery is suppressed by also providing an anode region 84 with a low doping concentration in the second boundary region 174. In addition, latch-up is suppressed by providing a contact region 15 in the first boundary region 173. The sum of the widths of the first boundary region 173 and the second boundary region 174 in the array direction is approximately equal to the sum of the widths W1 + W2 of the first boundary region 73 and the second boundary region 74 in semiconductor device 100.

[0101] However, in semiconductor device 1100, the first boundary region 173 and the second boundary region 174 become inactive regions, thus reducing the area of ​​the active region. In contrast, semiconductor device 100 can reduce the inactive region by providing a base region 14 with a lower doping concentration than the contact region 15 in the first boundary region 73, thereby suppressing hole injection during reverse recovery, and by providing an emitter region 12.

[0102] Figure 3A shows a modified example of the a-a' section in Figure 1A. Figure 3B shows a modified example of the b-b' section in Figure 1A. Here, elements common to Figures 1B and 1C are given the same reference numerals and their explanations are omitted.

[0103] In this modified example, the plug region 19 is not provided at the lower end of the trench contact portion 60 located in the first boundary region 73. In other words, in the first boundary region 73, the bottom and side walls of the trench contact portion 60 are covered by the emitter region 12 or the base region 14.

[0104] In this way, by providing plug regions 19 in regions other than the first boundary region 73, and omitting the plug regions 19 in the first boundary region 73, it is possible to promote hole extraction while further suppressing hole injection during reverse recovery.

[0105] Figure 4 shows a modified example of the b-b' section in Figure 1A. Here, elements common to both Figure 1A and Figure 1C are given the same reference numerals, and their explanations are omitted.

[0106] In this modified example, in the second boundary region 74 and the diode section 80, a storage region 86 of the first conductivity type is provided below the anode region 84. The storage region 86 in this example has the same conductivity type as the drift region 18, and is N-type as an example. Similar to the storage region 16, two or more storage regions 86 may be provided in the drift region 18. The doping concentration of the storage region 86 is lower than the doping concentration of the storage region 16. The doping concentration of the storage region 86 is 1E11cm -3 Above, 1E12cm -3 The following is acceptable:

[0107] Thus, in this modified example, the semiconductor device 100 has a storage region 86 with a low doping concentration below the anode region 84, thereby providing a storage region throughout the entire transistor section 70 and diode section 80. As a result, in this modified example, the IE effect can be enhanced while maintaining a balance with the anode region 84 with a low doping concentration, thereby reducing the on-voltage of the transistor section 70.

[0108] Furthermore, as shown in Figures 3A and 3B, even if a plug region 19 is not provided in the first boundary region 73, a storage region 86 may be provided in the second boundary region 74 and the diode section 80.

[0109] Figure 5 shows an example of a top view of the semiconductor device 200 according to Embodiment 2. Here, elements common to Figure 1A are given the same reference numerals, and their descriptions are omitted.

[0110] In this example, in a top view of the semiconductor substrate 10, the length L0 in the extension direction of the emitter region 12 provided in the main region 72 is greater than the length L1 in the extension direction of the emitter region 12 provided in the first boundary region 73. small .

[0111] In other words, in this example, in a top view of the semiconductor substrate 10, the area ratio of the emitter region 12 in the first boundary region 73 is larger than the area ratio of the emitter region 12 in the main region 72. Also, in a top view of the semiconductor substrate 10, the area ratio of the base region 14 in the first boundary region 73 is smaller than the area ratio of the contact region 15 in the main region 72.

[0112] Thus, in the first boundary region 73, the area ratio of the emitter region 12 is increased, Base area 14 By reducing the area ratio, the area of ​​the active region can be further increased, and hole injection during reverse recovery can be suppressed.

[0113] Furthermore, the semiconductor device 200 does not necessarily need to have a plug region 19 in the first boundary region 73, as in Figures 3A and 3B. Also, the semiconductor device 200 may have a storage region 86 in the second boundary region 74 and the diode section 80, as in Figure 4.

[0114] Figure 6A shows an example of a top view of the semiconductor device 300 according to Embodiment 3. Here, elements common to Figure 1A are given the same reference numerals and their descriptions are omitted. Figure 6B shows an example of the d-d' cross section in Figure 6A. The d-d' cross section is the XZ plane passing through the contact region 15, similar to the b-b' cross section in Figure 1C. Figure 6C shows an example of the e-e' cross section in Figure 6A. The e-e' cross section is the XZ plane passing through the emitter region 12.

[0115] In Figure 6A, the plug region 19 is highlighted in the diode section 80 and the second boundary region 74 to clarify its placement. The width of the plug region 19 in the X-axis direction may be the same as the width of the contact hole 54 in the X-axis direction.

[0116] In this example, plug regions 19 are selectively provided in the diode section 80 and the second boundary region 74 in the direction of extension of the contact hole 54 (Y-axis direction). On the other hand, in the main region 72 and the first boundary region 73, the plug regions 19 are provided so as to cover the entire bottom of the contact hole 54.

[0117] In this way, by reducing the area of ​​the plug region 19 in the region where the anode region 84 is provided, hole injection during reverse recovery can be suppressed. The plug region 19 of the second boundary region 74 may also be selectively provided in the extension direction.

[0118] Furthermore, the semiconductor device 300 does not necessarily need to have a plug region 19 in the first boundary region 73, as in Figures 3A and 3B. Also, the semiconductor device 300 may have a storage region 86 in the second boundary region 74 and the diode section 80, as in Figure 4.

[0119] Furthermore, the location where the plug region 19 is selectively provided is not limited to the XZ plane passing through the contact region 15, but may also be the XZ plane passing through the emitter region 12, or it may be provided on the XZ plane passing through both the contact region 15 and the emitter region 12.

[0120] Thus, even if the plug region 19 is selectively provided in the diode region 80 and the second boundary region 74 in the extension direction (Y-axis direction) of the contact hole 54, the same effect as in Figure 1A can be obtained.

[0121] Figure 7A shows a modified example of the d-d' section in Figure 6A. The d-d' section is the XZ plane passing through the contact region 15, similar to the b-b' section in Figure 1C. Figure 7B shows a modified example of the e-e' section in Figure 6A. The e-e' section is the XZ plane passing through the emitter region 12.

[0122] In this example, plug regions 19 are selectively provided in the diode section 80 and the second boundary region 74 in the direction of extension of the contact hole 54 (Y-axis direction). Plug regions 19 are not provided in the first boundary region 73. In the main region 72 (not shown), plug regions 19 are provided so as to completely cover the bottom of the contact hole 54.

[0123] In this modified example, similar to Figures 3A and 3B, the plug region 19 is not provided at the lower end of the trench contact portion 60 located in the first boundary region 73. In other words, in the first boundary region 73, the bottom and side walls of the trench contact portion 60 are covered by the emitter region 12 or the base region 14.

[0124] In this way, by providing plug regions 19 in regions other than the first boundary region 73, and omitting the plug regions 19 in the first boundary region 73, it is possible to promote hole extraction while further suppressing hole injection during reverse recovery.

[0125] Furthermore, the same effect as in Figure 1A can be obtained by selectively providing the plug region 19 in the diode region 80 and the second boundary region 74 in the extension direction (Y-axis direction) of the contact hole 54.

[0126] Figure 8A shows a modified example of the d-d' section in Figure 6A. The d-d' section is the XZ plane passing through the contact region 15, similar to the b-b' section in Figure 1C. Figure 8B shows a modified example of the e-e' section in Figure 6A. The e-e' section is the XZ plane passing through the emitter region 12.

[0127] In this modified example, similar to Figure 4, a storage region 86 of the first conductivity type is provided below the anode region 84 in the second boundary region 74 and the diode region 80, which differs from Figures 7A and 7B. The storage region 86 in this example has the same conductivity type as the drift region 18, and is N-type as an example. Similar to the storage region 16, two or more storage regions 86 may be provided in the drift region 18. The doping concentration of the storage region 86 is lower than the doping concentration of the storage region 16. The doping concentration of the storage region 86 is 1E11cm -3 Above, 1E12cm -3 The following is acceptable:

[0128] As shown in this modified example, even if a storage region 86 of the first conductivity type is provided below the anode region 84 in the second boundary region 74 and the diode region 80, the same effects as in Figures 7A and 7B can be obtained.

[0129] Figure 9 shows an example of a top view of a semiconductor device 400 according to Embodiment 4. Here, elements common to Figure 1A are given the same reference numerals and their descriptions are omitted. In this example, the plug region 19 is highlighted in the diode section 80 and the second boundary region 74 for the purpose of clarifying the arrangement of the plug region 19. The width of the plug region 19 in the X-axis direction may be the same as the width of the contact hole 54 in the X-axis direction.

[0130] In this example, in a top view of the semiconductor substrate 10, the length L0 in the extension direction of the emitter region 12 provided in the main region 72 is greater than the length L1 in the extension direction of the emitter region 12 provided in the first boundary region 73. small Furthermore, plug regions 19 are selectively provided in the diode region 80 and the second boundary region 74 in the direction of extension of the contact hole 54 (Y-axis direction).

[0131] In other words, in this example, in a top view of the semiconductor substrate 10, the area ratio of the emitter region 12 in the first boundary region 73 is larger than the area ratio of the emitter region 12 in the main region 72. Also, in a top view of the semiconductor substrate 10, the area ratio of the base region 14 in the first boundary region 73 is smaller than the area ratio of the contact region 15 in the main region 72.

[0132] Thus, in the first boundary region 73, the area ratio of the emitter region 12 is increased, Base area 14 By reducing the area ratio, the area of ​​the active region can be further increased, and hole injection during reverse recovery can be suppressed.

[0133] Furthermore, by reducing the area of ​​the plug region 19 in the region where the anode region 84 is provided, hole injection during reverse recovery can be suppressed.

[0134] Furthermore, the semiconductor device 400, as in Figures 6B and 6C, has a plug region 19 in the first boundary region 73. set up Often, as in Figures 7A and 7B, it is not necessary to provide a plug area 19 in the first boundary area 73.

[0135] Furthermore, the semiconductor device 400 may be provided with a storage region 86 in the second boundary region 74 and the diode portion 80.

[0136] Furthermore, the location where the plug region 19 is selectively provided is not limited to the XZ plane passing through the contact region 15, but may also be the XZ plane passing through the emitter region 12, or it may be provided on the XZ plane passing through both the contact region 15 and the emitter region 12.

[0137] Even if the plug region 19 is selectively provided in the diode region 80 and the second boundary region 74 in the extension direction (Y-axis direction) of the contact hole 54, the same effect as in Figure 1A can be obtained.

[0138] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0139] It should be noted that the execution order of operations, procedures, steps, and stages in the apparatus, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be implemented in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, it does not mean that it is essential to perform the operations in that order. [Explanation of Symbols]

[0140] 10...Semiconductor substrate, 12...Emitter region, 14...Base region, 15...Contact region, 16...Storage region, 17...Well region, 18...Drift region, 19...Plug region, 20...Buffer region, 21...Front surface, 22...Collector region, 23...Back surface, 24...Collector electrode, 25...Connection portion, 29...Extended portion, 30...Dummy trench portion, 31...Connection portion, 32...Dummy insulating film, 34...Dummy conductive portion, 38...Interlayer insulating film, 39...Extended portion, 40...Gate trench portion, 41...Connection portion, 42...Gate insulating film, 44...Gate conductive portion, 50... Gate metal layer, 52...Emitter electrode, 54...Contact hole, 55...Contact hole, 56...Contact hole, 60...Trench contact area, 70...Transistor area, 71...Mesa area, 72...Main region, 73...First boundary region, 74...Second boundary region, 80...Diode area, 81...Mesa area, 82...Cathode region, 83...Second cathode region, 84...Anode region, 86...Storage region, 100...Semiconductor device, 173...First boundary region, 174...Second boundary region, 200...Semiconductor device, 300...Semiconductor device, 400...Semiconductor device, 1100...Semiconductor device

Claims

1. The semiconductor substrate has a transistor section and a diode section, and is provided with a plurality of trench sections. The aforementioned transistor section is A first conductivity type emitter region provided on the front surface of the semiconductor substrate, A second conductivity type base region provided on the semiconductor substrate, A second conductivity type contact region is provided on the front surface of the semiconductor substrate and has a doping concentration higher than that of the base region. It has, The diode portion is provided on the front surface of the semiconductor substrate and has a second conductivity type anode region with a lower doping concentration than the base region. The aforementioned transistor section is On the front surface of the semiconductor substrate, a main region having the emitter region and the contact region, and spaced apart from the diode portion, A first boundary region is provided between the main region and the diode portion, and on the front surface of the semiconductor substrate, the emitter region and the base region are alternately provided in the trench extension direction. It has, In the first boundary region, the emitter region is comprised of two trenches flanking the mesa. A semiconductor device that extends from one side to the other in the direction of the trench arrangement.

2. The main region has the contact region and the emitter region arranged alternately in the trench stretching direction on the front surface of the semiconductor substrate. The semiconductor device according to claim 1.

3. The semiconductor substrate does not have a lifetime control region including a lifetime killer on its front side. The semiconductor device according to claim 1.

4. The transistor section has a second boundary region provided between the first boundary region and the diode section. The second boundary region has the anode region on the front surface of the semiconductor substrate. The semiconductor device according to any one of claims 1 to 3.

5. The transistor section and the diode section further have trench contact sections provided on the front surface of the semiconductor substrate. The lower end of the trench contact portion is shallower than the lower end of the emitter region. The semiconductor device according to any one of claims 1 to 4.

6. A semiconductor substrate having a transistor section and a diode section, and provided with a plurality of trench sections, The aforementioned transistor section is A first conductivity type emitter region provided on the front surface of the semiconductor substrate, A second conductivity type base region provided on the semiconductor substrate, A second conductivity type contact region is provided on the front surface of the semiconductor substrate and has a doping concentration higher than that of the base region. It has, The diode portion is provided on the front surface of the semiconductor substrate and has a second conductivity type anode region with a lower doping concentration than the base region. The aforementioned transistor section is On the front surface of the semiconductor substrate, a main region having the emitter region and the contact region, and spaced apart from the diode portion, A first boundary region is provided between the main region and the diode portion, and on the front surface of the semiconductor substrate, the emitter region and the base region are alternately provided in the trench extension direction. It has, The transistor section and the diode section further have trench contact sections provided on the front surface of the semiconductor substrate. The lower end of the trench contact portion is the same depth as the lower end of the emitter region. Semiconductor equipment.

7. The transistor and diode portions are provided at the bottom of the trench contact portion and further have a second conductivity type plug region having a higher doping concentration than the base region. The semiconductor device according to claim 6.

8. A semiconductor substrate having a transistor section and a diode section, and provided with a plurality of trench sections, The aforementioned transistor section is A first conductivity type emitter region provided on the front surface of the semiconductor substrate, A second conductivity type base region provided on the semiconductor substrate, A second conductivity type contact region is provided on the front surface of the semiconductor substrate and has a doping concentration higher than that of the base region. It has, The diode portion is provided on the front surface of the semiconductor substrate and has a second conductivity type anode region with a lower doping concentration than the base region. The aforementioned transistor section is On the front surface of the semiconductor substrate, a main region having the emitter region and the contact region, and spaced apart from the diode portion, A first boundary region is provided between the main region and the diode portion, and on the front surface of the semiconductor substrate, the emitter region and the base region are alternately provided in the trench extension direction. It has, The transistor section and the diode section further have trench contact sections provided on the front surface of the semiconductor substrate. The lower end of the trench contact portion is shallower than the lower end of the emitter region. The transistor and diode portions are provided at the bottom of the trench contact portion and further have a second conductivity type plug region with a higher doping concentration than the base region. A semiconductor device in which the plug region is not provided in the first boundary region.

9. The transistor section has a second boundary region provided between the first boundary region and the diode section. The main region and the first boundary region are provided at the bottom of the trench contact portion and have a second conductivity type plug region with a higher doping concentration than the base region. The diode portion and the second boundary region are provided at the bottom of the trench contact portion, and the plug region, which has a higher doping concentration than the base region, is selectively provided. The semiconductor device according to claim 5 or 6.

10. The transistor section has a second boundary region provided between the first boundary region and the diode section. The main region is provided at the bottom of the trench contact portion and has a second conductivity type plug region with a higher doping concentration than the base region. The diode portion and the second boundary region are provided at the bottom of the trench contact portion, and the plug region, which has a higher doping concentration than the base region, is selectively provided. The semiconductor device according to claim 5 or 6.

11. The transistor portion further comprises a storage region of a first conductivity type provided on the semiconductor substrate. The semiconductor device according to any one of claims 1 to 10.

12. A semiconductor substrate having a transistor section and a diode section, and provided with a plurality of trench sections, The aforementioned transistor section is A first conductivity type emitter region provided on the front surface of the semiconductor substrate, A second conductivity type base region provided on the semiconductor substrate, A second conductivity type contact region is provided on the front surface of the semiconductor substrate and has a doping concentration higher than that of the base region. It has, The diode portion is provided on the front surface of the semiconductor substrate and has a second conductivity type anode region with a lower doping concentration than the base region. The aforementioned transistor section is On the front surface of the semiconductor substrate, a main region having the emitter region and the contact region, and spaced apart from the diode portion, A first boundary region is provided between the main region and the diode portion, and on the front surface of the semiconductor substrate, the emitter region and the base region are alternately provided in the trench extension direction. It has, The transistor portion further comprises a storage region of a first conductivity type provided on the semiconductor substrate, A semiconductor device in which the storage region is not provided below the anode region.

13. A semiconductor substrate having a transistor section and a diode section, and provided with a plurality of trench sections, The aforementioned transistor section is A first conductivity type emitter region provided on the front surface of the semiconductor substrate, A second conductivity type base region provided on the semiconductor substrate, A second conductivity type contact region is provided on the front surface of the semiconductor substrate and has a doping concentration higher than that of the base region. It has, The diode portion is provided on the front surface of the semiconductor substrate and has a second conductivity type anode region with a lower doping concentration than the base region. The aforementioned transistor section is On the front surface of the semiconductor substrate, a main region having the emitter region and the contact region, and spaced apart from the diode portion, A first boundary region is provided between the main region and the diode portion, and on the front surface of the semiconductor substrate, the emitter region and the base region are alternately provided in the trench extension direction. It has, The transistor portion further comprises a storage region of a first conductivity type provided on the semiconductor substrate, The storage region is provided in both the transistor portion and the diode portion, and the storage region provided below the anode region has a lower doping concentration than the storage region provided below the base region.

14. The transistor section further comprises a second conductivity type collector region provided on the back surface of the semiconductor substrate, The aforementioned diode section is A first cathode region of a first conductivity type provided on the back surface of the semiconductor substrate, A second cathode region of a second conductivity type is provided on the back surface of the semiconductor substrate and has a smaller area than the first cathode region. It further possesses The semiconductor device according to any one of claims 1 to 13.

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